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Signed-off-by: Naina Mehta Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index c24c537f62b1..11979b026d21 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -51,6 +51,7 @@ properties: - qcom,sdm845-sdhci - qcom,sdx55-sdhci - qcom,sdx65-sdhci + - qcom,sdx75-sdhci - qcom,sm6115-sdhci - qcom,sm6125-sdhci - qcom,sm6350-sdhci From patchwork Thu May 23 12:03:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naina Mehta X-Patchwork-Id: 798831 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4266013B5B3; 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Also add pins required for SDHCI. Signed-off-by: Naina Mehta --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 89 +++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index da1704061d58..16f3a2400d7f 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -538,6 +539,54 @@ #hwlock-cells = <1>; }; + sdhc: mmc@8804000 { + compatible = "qcom,sdx75-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x08804000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + iommus = <&apps_smmu 0x00a0 0x0>; + qcom,dll-config = <0x0007442c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + interconnects = <&system_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_SDCC_1>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + bus-width = <4>; + dma-coherent; + + /* Forbid SDR104/SDR50 - broken hw! */ + sdhci-caps-mask = <0x3 0>; + + status = "disabled"; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + usb: usb@a6f8800 { compatible = "qcom,sdx75-dwc3", "qcom,dwc3"; reg = <0x0 0x0a6f8800 0x0 0x400>; @@ -683,6 +732,46 @@ drive-strength = <2>; bias-pull-down; }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; apps_smmu: iommu@15000000 { From patchwork Thu May 23 12:03:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naina Mehta X-Patchwork-Id: 798598 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9B8F13D25A; Thu, 23 May 2024 12:04:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716465876; cv=none; b=bcUD+BUdE+yVDQ40RyS3X4DygkeO8ncUcyTl1B4Vvbs4m/T6oQH5YuOdMJ3BpsRv54LrxOKMcE0+RiV9DVLbgvW3b1+3WWo6+/w/AoVV9tcRFv2/XgNcFJyLDBt/hDJFrzaTQVP9HFX9gjJ8tmOnZ6ZxoUulnBs+9JRLMtO94WM= ARC-Message-Signature: i=1; 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Also add the required regulators. Signed-off-by: Naina Mehta --- arch/arm64/boot/dts/qcom/sdx75-idp.dts | 45 ++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75-idp.dts b/arch/arm64/boot/dts/qcom/sdx75-idp.dts index f76e72fb2072..fde16308c7e2 100644 --- a/arch/arm64/boot/dts/qcom/sdx75-idp.dts +++ b/arch/arm64/boot/dts/qcom/sdx75-idp.dts @@ -41,6 +41,29 @@ vin-supply = <&vph_ext>; }; + + reg_2v952_vcc: regulator-2v952-vcc { + compatible = "regulator-gpio"; + regulator-name = "2v952_vcc"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3600000>; + enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; + states = <1650000 0>, <3600000 1>; + startup-delay-us = <5000>; + enable-active-high; + regulator-boot-on; + + vin-supply = <&vph_ext>; + }; + + reg_2v95_vdd: regulator-2v95-vdd { + compatible = "regulator-fixed"; + regulator-name = "2v95_vdd"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + vin-supply = <®_2v952_vcc>; + }; }; &apps_rsc { @@ -259,8 +282,30 @@ status = "okay"; }; +&sdhc { + cd-gpios = <&tlmm 103 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_2v95_vdd>; + vqmmc-supply = <®_2v952_vcc>; + bus-width = <4>; + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc1_default &sd_cd>; + pinctrl-1 = <&sdc1_sleep &sd_cd>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <110 6>; + + sd_cd: sd-cd-state { + pins = "gpio103"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; &uart1 {