From patchwork Wed Jun 14 12:39:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105496 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp271340qgd; Wed, 14 Jun 2017 05:40:56 -0700 (PDT) X-Received: by 10.84.238.136 with SMTP id v8mr462691plk.249.1497444056791; Wed, 14 Jun 2017 05:40:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497444056; cv=none; d=google.com; s=arc-20160816; b=pekGlvzs+af3H7jRrA1bL7Uowgsu3GGFE0eu0BwkYC/lKIHDx+23JM+zwAI/D2o+IO azZ7VHCOV3uyD6hkMuurCslBRShlHvhvgA9TdRTDd4PiW7DBxWIHligmAD3UsTQwSczW GmhqCVI0/TaI1foRlduKaff4vPWLXjRPGXiF4t9VUSih8eWVcqt2/913/W/qcBOOqCR8 tXITnX15OejOh/oD60cFMnHZ8ttZfsxjmlQkaxhnQmCRjrszA3mgNDL3Go5NYsc9SWzx M5fvMDLG51o3ESFKnr4Z9Kz7rBXKsgEyjb0Nz1s7sr/j/YzGq1rBbI7ctHk4m8h36LKn qNpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=zmNRh7A8FVH3OZ1Rp2cBdJzAZ8cqDyrGmqjyhCmwtyo=; b=H3VaFocjkS9z9NRxhOyiANhEIUi+FwaRhPR5Z7cr0mIk8Oz0imoStY782m77XCzQZ8 tbCBYedWOTKgNF/3x8z38T248hrQaQaqSf+Ui/JqRg4Q6n6i9vHlv1gnbsK1NVVaz9Wh mYgT2XM5hO/e7z1gJppjsfktntzJhZ+fVO2pwZNW2LVPkmsBbupcahT9qHGOpvUmrepS lSEhd2bLhGFjllwvQZnTnvwZliti+lBGllM5lV7PnWiL7U3Lk1lsZhgrgeED284RF9rl U7XlVnrVfzOmtswoDc4cY2BYMBIQb4vaVZ33+KAuS2nLAD9cEK1VeqQo3CMZCo7/jp2i CRhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=P9arqJ1A; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y14si421657pgq.414.2017.06.14.05.40.56; Wed, 14 Jun 2017 05:40:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=P9arqJ1A; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752376AbdFNMky (ORCPT + 25 others); Wed, 14 Jun 2017 08:40:54 -0400 Received: from mail-wr0-f170.google.com ([209.85.128.170]:36051 "EHLO mail-wr0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751771AbdFNMkx (ORCPT ); Wed, 14 Jun 2017 08:40:53 -0400 Received: by mail-wr0-f170.google.com with SMTP id 36so66261901wry.3 for ; Wed, 14 Jun 2017 05:40:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zmNRh7A8FVH3OZ1Rp2cBdJzAZ8cqDyrGmqjyhCmwtyo=; b=P9arqJ1Ap9nF5meEzzfhjpaKTbxK1/C48obxwbfHdiyaT7AYIJrNkUhcyOAYC7v7id D5CzLrH11iFy8vOwXix4VgsX33riNUYvhhPX+mJhfHAZOq9NG+Xh0r1HXzXpCD1SMBCw D2ksi2fKIiSzWvTvPbeTBlr2xO7HiZDfcGIFY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zmNRh7A8FVH3OZ1Rp2cBdJzAZ8cqDyrGmqjyhCmwtyo=; b=rVarmxkChG0Zw/lJ+PCHgoSQGtXOBIMwzZcHkd9OFI4piInopFHaJ1sddQb+IA3Vjt ieuwavKFQpSlIVfx55ne7eGgVa83XW/+cUR3NWtAKqKd+1K8PPZDcoVEuGfqOQ6ohhbt qa3M9u8+AOR4Jr+E++NB+8v/+ZT4lPjoiTDSI/phGgGnicS8etPSdiJBAZZP//0/xF8I PkS9PX4BTTTjiAbmG59SAY2nO5oHirw360Z1JirKFMvOUQLLQWnt2VSOnwWGXS2Euh6N txut6OxAI84wVEZmMw27KlJa3xfnqpDk3DQcSJJRkFHkwoTT2YadPaDFYvlaaktHILoR 0ZLw== X-Gm-Message-State: AKS2vOyFcx7cFxEQjw4Iqhbv/q7bT3h7Fl04qhqeAhjMAAtkoJ2qzggl eMvXWNC0oSpzldnf X-Received: by 10.28.147.202 with SMTP id v193mr959021wmd.37.1497444051629; Wed, 14 Jun 2017 05:40:51 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:19a:b336:54d7:46e9]) by smtp.gmail.com with ESMTPSA id 80sm1457015wmg.17.2017.06.14.05.40.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 05:40:51 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Linus Walleij , Jonas Jensen Subject: [PATCH 02/23] clocksource/drivers/fttmr010: Fix the clock handling Date: Wed, 14 Jun 2017 14:39:23 +0200 Message-Id: <1497443984-12371-2-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Linus Walleij We need to also prepare and enable the clock we are using to get the right reference count and avoid it being shut off. Tested-by: Jonas Jensen Signed-off-by: Linus Walleij Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-fttmr010.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index b4a6f1e..58ce017 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -238,12 +238,18 @@ static int __init fttmr010_timer_of_init(struct device_node *np) * and using EXTCLK is not supported in the driver. */ struct clk *clk; + int ret; clk = of_clk_get_by_name(np, "PCLK"); if (IS_ERR(clk)) { - pr_err("could not get PCLK"); + pr_err("could not get PCLK\n"); return PTR_ERR(clk); } + ret = clk_prepare_enable(clk); + if (ret) { + pr_err("failed to enable PCLK\n"); + return ret; + } tick_rate = clk_get_rate(clk); return fttmr010_timer_common_init(np); From patchwork Wed Jun 14 12:39:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105514 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp273332qgd; Wed, 14 Jun 2017 05:45:58 -0700 (PDT) X-Received: by 10.98.59.92 with SMTP id i89mr443914pfa.122.1497444358715; Wed, 14 Jun 2017 05:45:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497444358; cv=none; d=google.com; s=arc-20160816; b=AjquC8Si/8DLAkFt0JlKGWOTs2l7PEyG29Rz23jTGdJZ3mInZHCOkDACosAukclfrr cThvA077gX+/uUknhYEdXQhpVX+esX6WiVnwHBKdvbEMxikiNHvzkc5CQhES2S4AYsL+ yR/zGWhRKRLrQwoVTTMytP6M/nTJ3V6ynEUf2sp/jRG/w5LVZWa7fj66zXuY1RwWHVXR dr8j3Ik0/LfC2xZk39FkvivrzLrVE7IMu853U3e/vbQQ15nru5ExqR8F/er78lCKB+NC UhOZxJEmfZL2XRpYFC0sub5kY3vscS+RBvA0hkQdB2cBaHcDY2V5HB63cN6Gj4mxC3a8 JBaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=EMWfj+zc8yvxTO8bOruXEzQzOIUzdGwn9o3wAn7fIhU=; b=KpmEmaxh/VUwAe3erVA5tfLmZPmMB5t0lS2IUK0vVWz9hCkknjxELSGK5zN0hon1n2 2mvt1vgtjYp7Of1qSaFVGbrdphdQKh1NucQgNLefmsQkSSgjtl4Q0ZfhpHsGnO3a0bxS C8UPET29TW8PDnn/0bLFA4eXKgJZiIGJd8YoecQHHAb991fO/FzLMXHVR+hM0Ep0TPkX g5o3uIkrGXrPo4G4zOM1WTeNHy40XjYzOwBhBIRidMT+FtObtyN2hgwYJe/kF/pYIq9w 2FS9cG6Dq6tJrXp1RM9vM9TC2wuxWf1cZrpAud9N9jeGlnUPHtkTwr3k16fbUej8h2WQ HUjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=dEjs7uw4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Subject: [PATCH 03/23] clocksource/drivers/fttmr010: Merge FTTMR010 DT bindings Date: Wed, 14 Jun 2017 14:39:24 +0200 Message-Id: <1497443984-12371-3-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Linus Walleij This merges the Moxa and FTTMR010 device tree bindings into the Faraday binding document to avoid confusion. The FTTMR010 is the IP block used by these SoCs, in vanilla or modified variant. The Aspeed variant is modified such that it is no longer fully register-compatible with FTTMR010 so for this reason it is not listed with two compatible strings, instead just one. Cc: Joel Stanley Tested-by: Jonas Jensen Signed-off-by: Linus Walleij Acked-by: Rob Herring Acked-by: Joel Stanley Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/faraday,fttmr010.txt | 4 +++- .../devicetree/bindings/timer/moxa,moxart-timer.txt | 19 ------------------- 2 files changed, 3 insertions(+), 20 deletions(-) delete mode 100644 Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt b/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt index b73ca6c..6e18bd6 100644 --- a/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt +++ b/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt @@ -7,7 +7,9 @@ Required properties: - compatible : Must be one of "faraday,fttmr010" - "cortina,gemini-timer" + "cortina,gemini-timer", "faraday,fttmr010" + "moxa,moxart-timer", "faraday,fttmr010" + "aspeed,ast2400-timer" - reg : Should contain registers location and length - interrupts : Should contain the three timer interrupts usually with flags for falling edge diff --git a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt deleted file mode 100644 index e207c11..0000000 --- a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt +++ /dev/null @@ -1,19 +0,0 @@ -MOXA ART timer - -Required properties: - -- compatible : Must be one of: - - "moxa,moxart-timer" - - "aspeed,ast2400-timer" -- reg : Should contain registers location and length -- interrupts : Should contain the timer interrupt number -- clocks : Should contain phandle for the clock that drives the counter - -Example: - - timer: timer@98400000 { - compatible = "moxa,moxart-timer"; - reg = <0x98400000 0x42>; - interrupts = <19 1>; - clocks = <&coreclk>; - }; From patchwork Wed Jun 14 12:39:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105515 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp273555qgd; Wed, 14 Jun 2017 05:46:36 -0700 (PDT) X-Received: by 10.99.95.147 with SMTP id t141mr101788pgb.263.1497444396396; Wed, 14 Jun 2017 05:46:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497444396; cv=none; d=google.com; s=arc-20160816; b=Yc7K139rqeQQKwo6pnI3GJwosVZPzhXJD1EdEtXA9dWxveR+AaaMoukqtVg8YDwnYI +YTEmnn47nk3RPzXl+ZmZjXyIoXzI7dklhrrGKV4KAI9J745mLwHJ2YKFdMRMdlh1O1Z 7XTK8a6Jge+GP6Pi1yA600jhnR5kx9COwp3vqO1ZYhLXxZzd6OUK84iLAVVlKwBo2V3M EtSr3+ZGyKfvJeupgfuzxdZQM9AClfKCCWhkQx9Xsl1hstIWA5FdhOc3PTx2K57SCerb SFW8YIEGCqXNM9DotWyUDZw4J/FOP5+c8buYQstxcI/aC/71jVH7C8rE7/Hj86OyXrxw UmZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=1xTO4zD5ALxVAtgfB46mDqibTY7cA5Bg9fMA4t03wFY=; b=kXMt0LadEbVTSsJndjP4c6G6BKsQajcUicflNBwxV7niWq13VrX6mSizs68Qk/m+sV lZtMzYGOEIg1AwvOU2H+dshWYx9q7l6olsPIg9ejFsEMso61Z9OTz8Zpzd1q9LMlB5Nh IIikX/GxRToI1aQDAUs0D1bU/TIe/ioaRGbQ037P0IDYTiITBeCBN5aC5PLcjtpFepRL Tl1X+nmu1J0kLLZJO2m5J/BfkJlLsCH1tIYJGXQXUcvshimyQnouZp5G/0I5OhSx5njN yHzbBIMGh1lzBnGQDrjp/M649mw8EZWF0a7Kj9Q8CWQvqcLXAr8P84DhbeJS3lG8Zshn j5Fg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=hpdfkHip; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n1si633731pld.62.2017.06.14.05.46.36; Wed, 14 Jun 2017 05:46:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=hpdfkHip; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752676AbdFNMqG (ORCPT + 25 others); Wed, 14 Jun 2017 08:46:06 -0400 Received: from mail-wr0-f178.google.com ([209.85.128.178]:35692 "EHLO mail-wr0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752447AbdFNMlB (ORCPT ); Wed, 14 Jun 2017 08:41:01 -0400 Received: by mail-wr0-f178.google.com with SMTP id q97so188222318wrb.2 for ; Wed, 14 Jun 2017 05:41:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1xTO4zD5ALxVAtgfB46mDqibTY7cA5Bg9fMA4t03wFY=; b=hpdfkHipXW3T5R9LkXhJ9THgke0nhqWyj3imbn/kf8JTKZpyEBdUNKpHOPEPIfbhKo CpsoJPD9xy2coV0VJuShuj4SCrllUI0W+IcXkoCIRc+iPtZIgwEM3vmMk85Evv0q5pxB QdYgqhrgu7PiUa9jV0aJ+fzK6lQxRBV2+330I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1xTO4zD5ALxVAtgfB46mDqibTY7cA5Bg9fMA4t03wFY=; b=fuDQIYUwZJDorhphCkZo6haE6zl9nhf1n/sIkF4iTH92Ab3dFPSNv1P3jqNqx7aKWO gcSvFMicsCkyf0zuaW59Y0O9Eh9SIyQk8ZDRfFMZuQB5sAoZ5Fyk2mSmlxhfVKwsKvKC 3Tp57j94wlnhZYdJxcLFj1UFJZwA5DAGL+s2SoWsxcOG9sDzqQTB2/DufT6V1bsQfFci owFq6vXxXYSMZ3o0taXHfLL3HPivhwtQ74DuDKwkIFP3OcUQ5j/1e/JVFuxpZ7d84BI7 BZ+I0CVtcfkrGk2Aq43858UzUDM36sR81qNmWSrkflOykfy2QU89PGW/wG6y5IkjnBzp rmRg== X-Gm-Message-State: AKS2vOxseCu0Yxl+jG96I+ivXhArHLEvLxC/K3GnjzrNK43Su8aDQr2w TsnKVw2+//SI+PeE X-Received: by 10.223.179.86 with SMTP id k22mr385811wrd.5.1497444060270; Wed, 14 Jun 2017 05:41:00 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:19a:b336:54d7:46e9]) by smtp.gmail.com with ESMTPSA id 80sm1457015wmg.17.2017.06.14.05.40.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 05:40:59 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Linus Walleij , Joel Stanley , Jonas Jensen Subject: [PATCH 04/23] clocksource/drivers/fttmr010: Drop Gemini specifics Date: Wed, 14 Jun 2017 14:39:25 +0200 Message-Id: <1497443984-12371-4-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Linus Walleij The Gemini now has a proper clock driver and a proper PCLK assigned in its device tree. Drop the Gemini-specific hacks to look up the system speed and rely on the clock framework like everyone else. Cc: Joel Stanley Tested-by: Jonas Jensen Signed-off-by: Linus Walleij Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-fttmr010.c | 103 ++++++++--------------------------- 1 file changed, 22 insertions(+), 81 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index 58ce017..db097db 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -11,8 +11,6 @@ #include #include #include -#include -#include #include #include #include @@ -179,9 +177,28 @@ static struct irqaction fttmr010_timer_irq = { .handler = fttmr010_timer_interrupt, }; -static int __init fttmr010_timer_common_init(struct device_node *np) +static int __init fttmr010_timer_init(struct device_node *np) { int irq; + struct clk *clk; + int ret; + + /* + * These implementations require a clock reference. + * FIXME: we currently only support clocking using PCLK + * and using EXTCLK is not supported in the driver. + */ + clk = of_clk_get_by_name(np, "PCLK"); + if (IS_ERR(clk)) { + pr_err("could not get PCLK\n"); + return PTR_ERR(clk); + } + ret = clk_prepare_enable(clk); + if (ret) { + pr_err("failed to enable PCLK\n"); + return ret; + } + tick_rate = clk_get_rate(clk); base = of_iomap(np, 0); if (!base) { @@ -229,81 +246,5 @@ static int __init fttmr010_timer_common_init(struct device_node *np) return 0; } - -static int __init fttmr010_timer_of_init(struct device_node *np) -{ - /* - * These implementations require a clock reference. - * FIXME: we currently only support clocking using PCLK - * and using EXTCLK is not supported in the driver. - */ - struct clk *clk; - int ret; - - clk = of_clk_get_by_name(np, "PCLK"); - if (IS_ERR(clk)) { - pr_err("could not get PCLK\n"); - return PTR_ERR(clk); - } - ret = clk_prepare_enable(clk); - if (ret) { - pr_err("failed to enable PCLK\n"); - return ret; - } - tick_rate = clk_get_rate(clk); - - return fttmr010_timer_common_init(np); -} -CLOCKSOURCE_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_of_init); - -/* - * Gemini-specific: relevant registers in the global syscon - */ -#define GLOBAL_STATUS 0x04 -#define CPU_AHB_RATIO_MASK (0x3 << 18) -#define CPU_AHB_1_1 (0x0 << 18) -#define CPU_AHB_3_2 (0x1 << 18) -#define CPU_AHB_24_13 (0x2 << 18) -#define CPU_AHB_2_1 (0x3 << 18) -#define REG_TO_AHB_SPEED(reg) ((((reg) >> 15) & 0x7) * 10 + 130) - -static int __init gemini_timer_of_init(struct device_node *np) -{ - static struct regmap *map; - int ret; - u32 val; - - map = syscon_regmap_lookup_by_phandle(np, "syscon"); - if (IS_ERR(map)) { - pr_err("Can't get regmap for syscon handle\n"); - return -ENODEV; - } - ret = regmap_read(map, GLOBAL_STATUS, &val); - if (ret) { - pr_err("Can't read syscon status register\n"); - return -ENXIO; - } - - tick_rate = REG_TO_AHB_SPEED(val) * 1000000; - pr_info("Bus: %dMHz ", tick_rate / 1000000); - - tick_rate /= 6; /* APB bus run AHB*(1/6) */ - - switch (val & CPU_AHB_RATIO_MASK) { - case CPU_AHB_1_1: - pr_cont("(1/1)\n"); - break; - case CPU_AHB_3_2: - pr_cont("(3/2)\n"); - break; - case CPU_AHB_24_13: - pr_cont("(24/13)\n"); - break; - case CPU_AHB_2_1: - pr_cont("(2/1)\n"); - break; - } - - return fttmr010_timer_common_init(np); -} -CLOCKSOURCE_OF_DECLARE(gemini, "cortina,gemini-timer", gemini_timer_of_init); +CLOCKSOURCE_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init); +CLOCKSOURCE_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init); From patchwork Wed Jun 14 12:39:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105497 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp271546qgd; Wed, 14 Jun 2017 05:41:25 -0700 (PDT) X-Received: by 10.84.217.86 with SMTP id e22mr504127plj.294.1497444085780; Wed, 14 Jun 2017 05:41:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497444085; cv=none; d=google.com; s=arc-20160816; b=CZMFPztsXtxbWkUAglaT/S0hRJPPTOsb45tFJHFekFdMr/lHBo4VVD1JwD3aN6nrER y1RNreO9+iWdsbBLKFmEcqw+3/NWBU46ljWd+mRvHcv5C/PTUINGpzROFXkpMmQiUthi eodztOEl/msBzgFd62PDA6WrRSli/rNPvVzmiDrhnNnqlfF7fi8yVdafb3s/htmnaw9x kNj0NYo8cl0FU86llMEGA44vw5SXOGEq52JSscR1X61gl5RWJAfNWH84Vr8xx4NuYK+M 2quYNqKsfsEGavIX4ezWtkt/K8qNeKFXKlPGQRaMAycKT1SmzA9L+zTA6Toxp/0J1zKO pe+g== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id 89si625331plc.277.2017.06.14.05.41.25; Wed, 14 Jun 2017 05:41:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=ULQs028k; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752518AbdFNMlG (ORCPT + 25 others); Wed, 14 Jun 2017 08:41:06 -0400 Received: from mail-wr0-f171.google.com ([209.85.128.171]:35717 "EHLO mail-wr0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752394AbdFNMlD (ORCPT ); Wed, 14 Jun 2017 08:41:03 -0400 Received: by mail-wr0-f171.google.com with SMTP id q97so188223527wrb.2 for ; Wed, 14 Jun 2017 05:41:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cvEfStQjch/lC7vl/dWjDPjvCYU1AknIn1uFt0zQE4E=; b=ULQs028klUgQLy0xFHXG9iYvTYJhPvOAu3twHk4V4KgxRFf1eMpbi4eI2bTE2fTN33 c/0q0/ISWgAYyp5qDhSl9Rd/TZmZvqiNMnDD/++sRftQ5z8RwF7TjaCOlX7QCfg05vL7 Yhxv2P0imlVbHpayyJrYS4VG0rAe7T8CZF4OY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cvEfStQjch/lC7vl/dWjDPjvCYU1AknIn1uFt0zQE4E=; b=VJIxUF3mHQEfDtgLw4+CSN+7Sq6egzc8Ma/qsNAAqDmYeSzh/txUj+R5Atc4Nuo9VR 4m1RJEOhWYOvJ6nbik3QaWReWU/OpWHRbXZyTo//vD6iVIlygE6sou8JT3WLXhyeKQX8 Xo8Qvwge1AZdUBkcTbWhWf6L8XZfYuO9fRDdMBLQhnLVyFbTZAVHKT9TyIHKP7Ww1dOo 0XUEq4Ujn/pBEjdH/6POPWGP+0ILHm/be0UlJLxDdUAMg2akkvEoW9xbYaASDs7iei1x zxq6Wq4xc/pzMA3XzUJpQ9te+X/jkEY4AxVti7Q+SRZuZUbbFwAOvYOr6WQyOSbeM5D+ vHDA== X-Gm-Message-State: AKS2vOwlXwVIub2eymRFxKy9ryM/pU0AzUWG0QvkNbK7PGxPcQso9ZR+ 29qY9GBE05xgA81d X-Received: by 10.28.214.211 with SMTP id n202mr932004wmg.105.1497444061884; Wed, 14 Jun 2017 05:41:01 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:19a:b336:54d7:46e9]) by smtp.gmail.com with ESMTPSA id 80sm1457015wmg.17.2017.06.14.05.41.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 05:41:01 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Linus Walleij , Joel Stanley , Jonas Jensen Subject: [PATCH 05/23] clocksource/drivers/fttmr010: Use state container Date: Wed, 14 Jun 2017 14:39:26 +0200 Message-Id: <1497443984-12371-5-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Linus Walleij This converts the Faraday FTTMR010 to use the state container design pattern. Take some care to handle the state container and free:ing of resources as has been done in the Moxa driver. Cc: Joel Stanley Tested-by: Jonas Jensen Signed-off-by: Linus Walleij Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-fttmr010.c | 190 +++++++++++++++++++++-------------- 1 file changed, 116 insertions(+), 74 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index db097db..9ad3148 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -15,6 +15,7 @@ #include #include #include +#include /* * Register definitions for the timers @@ -62,23 +63,35 @@ #define TIMER_3_INT_OVERFLOW (1 << 8) #define TIMER_INT_ALL_MASK 0x1ff -static unsigned int tick_rate; -static void __iomem *base; +struct fttmr010 { + void __iomem *base; + unsigned int tick_rate; + struct clock_event_device clkevt; +}; + +/* A local singleton used by sched_clock, which is stateless */ +static struct fttmr010 *local_fttmr; + +static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt) +{ + return container_of(evt, struct fttmr010, clkevt); +} static u64 notrace fttmr010_read_sched_clock(void) { - return readl(base + TIMER3_COUNT); + return readl(local_fttmr->base + TIMER3_COUNT); } static int fttmr010_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { + struct fttmr010 *fttmr010 = to_fttmr010(evt); u32 cr; /* Setup the match register */ - cr = readl(base + TIMER1_COUNT); - writel(cr + cycles, base + TIMER1_MATCH1); - if (readl(base + TIMER1_COUNT) - cr > cycles) + cr = readl(fttmr010->base + TIMER1_COUNT); + writel(cr + cycles, fttmr010->base + TIMER1_MATCH1); + if (readl(fttmr010->base + TIMER1_COUNT) - cr > cycles) return -ETIME; return 0; @@ -86,99 +99,90 @@ static int fttmr010_timer_set_next_event(unsigned long cycles, static int fttmr010_timer_shutdown(struct clock_event_device *evt) { + struct fttmr010 *fttmr010 = to_fttmr010(evt); + u32 cr; + + /* Stop timer and interrupt. */ + cr = readl(fttmr010->base + TIMER_CR); + cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); + writel(cr, fttmr010->base + TIMER_CR); + + return 0; +} + +static int fttmr010_timer_set_oneshot(struct clock_event_device *evt) +{ + struct fttmr010 *fttmr010 = to_fttmr010(evt); u32 cr; - /* - * Disable also for oneshot: the set_next() call will arm the timer - * instead. - */ /* Stop timer and interrupt. */ - cr = readl(base + TIMER_CR); + cr = readl(fttmr010->base + TIMER_CR); cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); - writel(cr, base + TIMER_CR); + writel(cr, fttmr010->base + TIMER_CR); /* Setup counter start from 0 */ - writel(0, base + TIMER1_COUNT); - writel(0, base + TIMER1_LOAD); + writel(0, fttmr010->base + TIMER1_COUNT); + writel(0, fttmr010->base + TIMER1_LOAD); - /* enable interrupt */ - cr = readl(base + TIMER_INTR_MASK); + /* Enable interrupt */ + cr = readl(fttmr010->base + TIMER_INTR_MASK); cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2); cr |= TIMER_1_INT_MATCH1; - writel(cr, base + TIMER_INTR_MASK); + writel(cr, fttmr010->base + TIMER_INTR_MASK); - /* start the timer */ - cr = readl(base + TIMER_CR); + /* Start the timer */ + cr = readl(fttmr010->base + TIMER_CR); cr |= TIMER_1_CR_ENABLE; - writel(cr, base + TIMER_CR); + writel(cr, fttmr010->base + TIMER_CR); return 0; } static int fttmr010_timer_set_periodic(struct clock_event_device *evt) { - u32 period = DIV_ROUND_CLOSEST(tick_rate, HZ); + struct fttmr010 *fttmr010 = to_fttmr010(evt); + u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ); u32 cr; /* Stop timer and interrupt */ - cr = readl(base + TIMER_CR); + cr = readl(fttmr010->base + TIMER_CR); cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); - writel(cr, base + TIMER_CR); + writel(cr, fttmr010->base + TIMER_CR); /* Setup timer to fire at 1/HT intervals. */ cr = 0xffffffff - (period - 1); - writel(cr, base + TIMER1_COUNT); - writel(cr, base + TIMER1_LOAD); + writel(cr, fttmr010->base + TIMER1_COUNT); + writel(cr, fttmr010->base + TIMER1_LOAD); /* enable interrupt on overflow */ - cr = readl(base + TIMER_INTR_MASK); + cr = readl(fttmr010->base + TIMER_INTR_MASK); cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2); cr |= TIMER_1_INT_OVERFLOW; - writel(cr, base + TIMER_INTR_MASK); + writel(cr, fttmr010->base + TIMER_INTR_MASK); /* Start the timer */ - cr = readl(base + TIMER_CR); + cr = readl(fttmr010->base + TIMER_CR); cr |= TIMER_1_CR_ENABLE; cr |= TIMER_1_CR_INT; - writel(cr, base + TIMER_CR); + writel(cr, fttmr010->base + TIMER_CR); return 0; } -/* Use TIMER1 as clock event */ -static struct clock_event_device fttmr010_clockevent = { - .name = "TIMER1", - /* Reasonably fast and accurate clock event */ - .rating = 300, - .shift = 32, - .features = CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = fttmr010_timer_set_next_event, - .set_state_shutdown = fttmr010_timer_shutdown, - .set_state_periodic = fttmr010_timer_set_periodic, - .set_state_oneshot = fttmr010_timer_shutdown, - .tick_resume = fttmr010_timer_shutdown, -}; - /* * IRQ handler for the timer */ static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id) { - struct clock_event_device *evt = &fttmr010_clockevent; + struct clock_event_device *evt = dev_id; evt->event_handler(evt); return IRQ_HANDLED; } -static struct irqaction fttmr010_timer_irq = { - .name = "Faraday FTTMR010 Timer Tick", - .flags = IRQF_TIMER, - .handler = fttmr010_timer_interrupt, -}; - static int __init fttmr010_timer_init(struct device_node *np) { + struct fttmr010 *fttmr010; int irq; struct clk *clk; int ret; @@ -198,53 +202,91 @@ static int __init fttmr010_timer_init(struct device_node *np) pr_err("failed to enable PCLK\n"); return ret; } - tick_rate = clk_get_rate(clk); - base = of_iomap(np, 0); - if (!base) { + fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL); + if (!fttmr010) { + ret = -ENOMEM; + goto out_disable_clock; + } + fttmr010->tick_rate = clk_get_rate(clk); + + fttmr010->base = of_iomap(np, 0); + if (!fttmr010->base) { pr_err("Can't remap registers"); - return -ENXIO; + ret = -ENXIO; + goto out_free; } /* IRQ for timer 1 */ irq = irq_of_parse_and_map(np, 0); if (irq <= 0) { pr_err("Can't parse IRQ"); - return -EINVAL; + ret = -EINVAL; + goto out_unmap; } /* * Reset the interrupt mask and status */ - writel(TIMER_INT_ALL_MASK, base + TIMER_INTR_MASK); - writel(0, base + TIMER_INTR_STATE); - writel(TIMER_DEFAULT_FLAGS, base + TIMER_CR); + writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK); + writel(0, fttmr010->base + TIMER_INTR_STATE); + writel(TIMER_DEFAULT_FLAGS, fttmr010->base + TIMER_CR); /* * Setup free-running clocksource timer (interrupts * disabled.) */ - writel(0, base + TIMER3_COUNT); - writel(0, base + TIMER3_LOAD); - writel(0, base + TIMER3_MATCH1); - writel(0, base + TIMER3_MATCH2); - clocksource_mmio_init(base + TIMER3_COUNT, - "fttmr010_clocksource", tick_rate, + local_fttmr = fttmr010; + writel(0, fttmr010->base + TIMER3_COUNT); + writel(0, fttmr010->base + TIMER3_LOAD); + writel(0, fttmr010->base + TIMER3_MATCH1); + writel(0, fttmr010->base + TIMER3_MATCH2); + clocksource_mmio_init(fttmr010->base + TIMER3_COUNT, + "FTTMR010-TIMER3", + fttmr010->tick_rate, 300, 32, clocksource_mmio_readl_up); - sched_clock_register(fttmr010_read_sched_clock, 32, tick_rate); + sched_clock_register(fttmr010_read_sched_clock, 32, + fttmr010->tick_rate); /* - * Setup clockevent timer (interrupt-driven.) + * Setup clockevent timer (interrupt-driven) on timer 1. */ - writel(0, base + TIMER1_COUNT); - writel(0, base + TIMER1_LOAD); - writel(0, base + TIMER1_MATCH1); - writel(0, base + TIMER1_MATCH2); - setup_irq(irq, &fttmr010_timer_irq); - fttmr010_clockevent.cpumask = cpumask_of(0); - clockevents_config_and_register(&fttmr010_clockevent, tick_rate, + writel(0, fttmr010->base + TIMER1_COUNT); + writel(0, fttmr010->base + TIMER1_LOAD); + writel(0, fttmr010->base + TIMER1_MATCH1); + writel(0, fttmr010->base + TIMER1_MATCH2); + ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER, + "FTTMR010-TIMER1", &fttmr010->clkevt); + if (ret) { + pr_err("FTTMR010-TIMER1 no IRQ\n"); + goto out_unmap; + } + + fttmr010->clkevt.name = "FTTMR010-TIMER1"; + /* Reasonably fast and accurate clock event */ + fttmr010->clkevt.rating = 300; + fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT; + fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event; + fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown; + fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic; + fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot; + fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown; + fttmr010->clkevt.cpumask = cpumask_of(0); + fttmr010->clkevt.irq = irq; + clockevents_config_and_register(&fttmr010->clkevt, + fttmr010->tick_rate, 1, 0xffffffff); return 0; + +out_unmap: + iounmap(fttmr010->base); +out_free: + kfree(fttmr010); +out_disable_clock: + clk_disable_unprepare(clk); + + return ret; } CLOCKSOURCE_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init); CLOCKSOURCE_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init); From patchwork Wed Jun 14 12:39:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105513 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp273102qgd; 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[209.132.180.67]) by mx.google.com with ESMTP id a7si651899plt.37.2017.06.14.05.45.20; Wed, 14 Jun 2017 05:45:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=HjFWDoAo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752710AbdFNMpS (ORCPT + 25 others); Wed, 14 Jun 2017 08:45:18 -0400 Received: from mail-wr0-f175.google.com ([209.85.128.175]:36229 "EHLO mail-wr0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752519AbdFNMlJ (ORCPT ); Wed, 14 Jun 2017 08:41:09 -0400 Received: by mail-wr0-f175.google.com with SMTP id 36so66270377wry.3 for ; Wed, 14 Jun 2017 05:41:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qoIdSuizDl/eUbdd32DNfabFLp2i25L6mzzJrzAyNJw=; b=HjFWDoAocLzTjTe1hfLqlaLBeF9jXRhjyNomrTCTqtPXGmdL/ulVYb8oRRPYw9DwSW BdMg5GL0XIWceI/n0+BpeXDIRpWsNxrmGyFmSDk1e3+Nk7V5834JE2gJNza9U/SGiFBE +1rbhMOQY1chOi5F60VTScFxKWqRwqUIyg2JA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qoIdSuizDl/eUbdd32DNfabFLp2i25L6mzzJrzAyNJw=; b=AgWKgA9HaWB/h9ZfOmEjZpaUOJfOpqnBZMXlOi3n7Fo/o2VWEEiRUtd2M+W9LaVs3z A8mebgKTsDgp2P29P2FbefwnCV8zj1S9PDN99NDofNGfCMnzWFtC8DMU5bbsyhghA4mz RztE0Gl+h4CdNREQw/Flbn1+vGMgcWAejbFtqnWwahxJLOmzlodtSEhCS+TJEcgHgL0u KGt2HsHAPfmFI/IM8TEITwG3fv9WwcECrpUOCxUC0whBRDfkO2Keccf900n8PkpwHj9h TbYpYDb3OEQSqypLD2YECCfxoGB7g+sU2jFLBedVl4rXdgvi+HxOXyU424Cy6UaeC9A5 Vxbg== X-Gm-Message-State: AKS2vOxri4oIx/5CkkffPLuPKvbTKzkcw2K8RrFkJIE1kdiiSAG8ctAQ 4yw5hisOyOpnddN2 X-Received: by 10.28.130.196 with SMTP id e187mr985005wmd.24.1497444063183; Wed, 14 Jun 2017 05:41:03 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:19a:b336:54d7:46e9]) by smtp.gmail.com with ESMTPSA id 80sm1457015wmg.17.2017.06.14.05.41.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 05:41:02 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Linus Walleij , Joel Stanley , Jonas Jensen Subject: [PATCH 06/23] clocksource/drivers/fttmr010: Switch to use bitops Date: Wed, 14 Jun 2017 14:39:27 +0200 Message-Id: <1497443984-12371-6-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Linus Walleij This switches the drivers to use the bitops BIT() macro to define bits. Cc: Joel Stanley Tested-by: Jonas Jensen Signed-off-by: Linus Walleij Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-fttmr010.c | 43 ++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 21 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index 9ad3148..9df14cf 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -16,6 +16,7 @@ #include #include #include +#include /* * Register definitions for the timers @@ -36,31 +37,31 @@ #define TIMER_INTR_STATE (0x34) #define TIMER_INTR_MASK (0x38) -#define TIMER_1_CR_ENABLE (1 << 0) -#define TIMER_1_CR_CLOCK (1 << 1) -#define TIMER_1_CR_INT (1 << 2) -#define TIMER_2_CR_ENABLE (1 << 3) -#define TIMER_2_CR_CLOCK (1 << 4) -#define TIMER_2_CR_INT (1 << 5) -#define TIMER_3_CR_ENABLE (1 << 6) -#define TIMER_3_CR_CLOCK (1 << 7) -#define TIMER_3_CR_INT (1 << 8) -#define TIMER_1_CR_UPDOWN (1 << 9) -#define TIMER_2_CR_UPDOWN (1 << 10) -#define TIMER_3_CR_UPDOWN (1 << 11) +#define TIMER_1_CR_ENABLE BIT(0) +#define TIMER_1_CR_CLOCK BIT(1) +#define TIMER_1_CR_INT BIT(2) +#define TIMER_2_CR_ENABLE BIT(3) +#define TIMER_2_CR_CLOCK BIT(4) +#define TIMER_2_CR_INT BIT(5) +#define TIMER_3_CR_ENABLE BIT(6) +#define TIMER_3_CR_CLOCK BIT(7) +#define TIMER_3_CR_INT BIT(8) +#define TIMER_1_CR_UPDOWN BIT(9) +#define TIMER_2_CR_UPDOWN BIT(10) +#define TIMER_3_CR_UPDOWN BIT(11) #define TIMER_DEFAULT_FLAGS (TIMER_1_CR_UPDOWN | \ TIMER_3_CR_ENABLE | \ TIMER_3_CR_UPDOWN) -#define TIMER_1_INT_MATCH1 (1 << 0) -#define TIMER_1_INT_MATCH2 (1 << 1) -#define TIMER_1_INT_OVERFLOW (1 << 2) -#define TIMER_2_INT_MATCH1 (1 << 3) -#define TIMER_2_INT_MATCH2 (1 << 4) -#define TIMER_2_INT_OVERFLOW (1 << 5) -#define TIMER_3_INT_MATCH1 (1 << 6) -#define TIMER_3_INT_MATCH2 (1 << 7) -#define TIMER_3_INT_OVERFLOW (1 << 8) +#define TIMER_1_INT_MATCH1 BIT(0) +#define TIMER_1_INT_MATCH2 BIT(1) +#define TIMER_1_INT_OVERFLOW BIT(2) +#define TIMER_2_INT_MATCH1 BIT(3) +#define TIMER_2_INT_MATCH2 BIT(4) +#define TIMER_2_INT_OVERFLOW BIT(5) +#define TIMER_3_INT_MATCH1 BIT(6) +#define TIMER_3_INT_MATCH2 BIT(7) +#define TIMER_3_INT_OVERFLOW BIT(8) #define TIMER_INT_ALL_MASK 0x1ff struct fttmr010 { From patchwork Wed Jun 14 12:39:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105512 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp272939qgd; Wed, 14 Jun 2017 05:44:57 -0700 (PDT) X-Received: by 10.84.198.129 with SMTP id p1mr481789pld.225.1497444297224; Wed, 14 Jun 2017 05:44:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497444297; cv=none; d=google.com; s=arc-20160816; b=gsgM4s4ZuX9AdTV1697Zu7ZQW8XU4qRbXg9MeKqg5IxJldpvStyvndbVFYjQ2ZuC+/ qK3RpvgrCESe/rSm/Cw47fVJVRNZfE6E/1yuas95TVJIAQZo/+uOCXDgpQHpSoBdoy/M R2Q3q8qUF1rXaA+8viZC/vEPUJ4uySMzhgUvheb93ekUc33CaO8cEXn89+UflV5Jq/FP 1qc+mjoLj4xLVuWPFvBFKSmu8EVRZO/bJz7pCML8Ezdyu8OztErKORbUvuE9blUCE2AJ /PB4nkF9ac0iweuKMSGP56D2DaQM7bXoOx0Q0uyf1S9gaDAjOzfCufjR6qV/WOPoK9c0 IBMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=96rWRNhAOakG06Tcjr9z/8cHNjzfaP5jpoVml7JywlQ=; b=ibFCx6MJ1J1IwYUvXGvYwMY7JQ258PLai2CpSaLyvpc9IUmzqNodseq3rdRDPIvo4C U23lQahIFBkVS8oPGIt65tL/T+WeI2ZePR2VwKfSdnOqaNo1qbdGAtD1VmKBuJRcze3u Sj2dgkHKJlRISQlvM0MVBsP2GyIsTHjI5SeYZCKJ9zaidIi0sNhGD8Bo1cmOcSwBp8l/ SDmlwHo+V91rG+0OyWlhdfzOxI2b9CCL+s+u2P6bkLU21rUK9OokzU942fRRuh5m6WWQ Xu3m+10+3eY+5a/UQKag/JQ7vdsk7Esawf/1Hrpx1Cb+WfzuLfSdYJyJ+83gWtyE8nXR MVug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=I9yuzBmA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a7si651899plt.37.2017.06.14.05.44.56; Wed, 14 Jun 2017 05:44:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=I9yuzBmA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752753AbdFNMoy (ORCPT + 25 others); Wed, 14 Jun 2017 08:44:54 -0400 Received: from mail-wr0-f180.google.com ([209.85.128.180]:35753 "EHLO mail-wr0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752530AbdFNMlL (ORCPT ); Wed, 14 Jun 2017 08:41:11 -0400 Received: by mail-wr0-f180.google.com with SMTP id q97so188225316wrb.2 for ; Wed, 14 Jun 2017 05:41:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=96rWRNhAOakG06Tcjr9z/8cHNjzfaP5jpoVml7JywlQ=; b=I9yuzBmAhGp3dmQ+VxnWpuLNUA8OrJk6M/ufYo1Y1ctjDjsdqmMkKAvMQQf9g0PNRC D3DeYBkBDSM2B9kD2JRNZm/nMHpJSkQKJhwO5XMiHSiwI8FaBoscIJ2HS4BTQ80KtYEL rPFsEqrfG8U0tIOXvCJu7CcyJNhHJdSgo09BY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=96rWRNhAOakG06Tcjr9z/8cHNjzfaP5jpoVml7JywlQ=; b=XQAzT6ERWl5qZ54Qn4Z0GMmQI8goZ7MwFLtiNuS4aBqCJcLDjqnOK1OzzGL3G+Y10D nWyLOZLtBYysfpKoPkvcXIkFqNnctWLOy4iPFAhO9kUgkyBcwbEENo576p6TMJSDE9sB 7UlInd8Kqv5kpo3Atw/HVQlRbDqQk3LvR0kWyhJEYQWJtPcHblxbur9BbTgtVJo5Lp11 PgSIcGTZdHJvlSJpnZfKl/xBGQq/mD3Du++YjbtvwEQfQUjDsv7c6hK2iI2MqHLCkhf2 0zk8Pt+QXRzdcyX/Vwe0k/zlw4QfvTC3t9U2szkHRQkqY4ysgPgvzP8nWxKq0hjJ61pJ h6fg== X-Gm-Message-State: AKS2vOxaNx5FUOxv6+nOxCAMFZ/GkUw3cuUxzQ2amIIftoLJltgHHWeg suZ7yHwSQwKjPjlg X-Received: by 10.223.129.183 with SMTP id 52mr355508wra.71.1497444064492; Wed, 14 Jun 2017 05:41:04 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:19a:b336:54d7:46e9]) by smtp.gmail.com with ESMTPSA id 80sm1457015wmg.17.2017.06.14.05.41.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 05:41:03 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Linus Walleij , Joel Stanley , Jonas Jensen Subject: [PATCH 07/23] clocksource/drivers/fttmr010: Switch to use TIMER2 src Date: Wed, 14 Jun 2017 14:39:28 +0200 Message-Id: <1497443984-12371-7-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Linus Walleij This switches the clocksource to TIMER2 like the Moxart driver does. Mainly to make it more similar to the Moxart/Aspeed driver but also because it seems more neat to use the timers in order: use timer 1, then timer 2. Cc: Joel Stanley Tested-by: Jonas Jensen Signed-off-by: Linus Walleij Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-fttmr010.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index 9df14cf..2d915d1 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -49,9 +49,6 @@ #define TIMER_1_CR_UPDOWN BIT(9) #define TIMER_2_CR_UPDOWN BIT(10) #define TIMER_3_CR_UPDOWN BIT(11) -#define TIMER_DEFAULT_FLAGS (TIMER_1_CR_UPDOWN | \ - TIMER_3_CR_ENABLE | \ - TIMER_3_CR_UPDOWN) #define TIMER_1_INT_MATCH1 BIT(0) #define TIMER_1_INT_MATCH2 BIT(1) @@ -80,7 +77,7 @@ static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt) static u64 notrace fttmr010_read_sched_clock(void) { - return readl(local_fttmr->base + TIMER3_COUNT); + return readl(local_fttmr->base + TIMER2_COUNT); } static int fttmr010_timer_set_next_event(unsigned long cycles, @@ -230,19 +227,21 @@ static int __init fttmr010_timer_init(struct device_node *np) */ writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK); writel(0, fttmr010->base + TIMER_INTR_STATE); - writel(TIMER_DEFAULT_FLAGS, fttmr010->base + TIMER_CR); + /* Enable timer 1 count up, timer 2 count up */ + writel((TIMER_1_CR_UPDOWN | TIMER_2_CR_ENABLE | TIMER_2_CR_UPDOWN), + fttmr010->base + TIMER_CR); /* * Setup free-running clocksource timer (interrupts * disabled.) */ local_fttmr = fttmr010; - writel(0, fttmr010->base + TIMER3_COUNT); - writel(0, fttmr010->base + TIMER3_LOAD); - writel(0, fttmr010->base + TIMER3_MATCH1); - writel(0, fttmr010->base + TIMER3_MATCH2); - clocksource_mmio_init(fttmr010->base + TIMER3_COUNT, - "FTTMR010-TIMER3", + writel(0, fttmr010->base + TIMER2_COUNT); + writel(0, fttmr010->base + TIMER2_LOAD); + writel(0, fttmr010->base + TIMER2_MATCH1); + writel(0, fttmr010->base + TIMER2_MATCH2); + clocksource_mmio_init(fttmr010->base + TIMER2_COUNT, + "FTTMR010-TIMER2", fttmr010->tick_rate, 300, 32, clocksource_mmio_readl_up); sched_clock_register(fttmr010_read_sched_clock, 32, From patchwork Wed Jun 14 12:39:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105498 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp271555qgd; Wed, 14 Jun 2017 05:41:26 -0700 (PDT) X-Received: by 10.101.85.199 with SMTP id k7mr447218pgs.172.1497444086556; Wed, 14 Jun 2017 05:41:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497444086; cv=none; d=google.com; s=arc-20160816; b=ldrvV2vRl4Un7TuVp4PykDHT2HM21/wVE9XFtO7ijy7TfQtDrSl+vxfzSyVGwxNs3X f/WfsUH+NIlKjXnrTAMtmrdENzSBW37f8XU1xIu1ut09LKESwDzF3GVn4TU2zs6cEJPN FcT3QcWPSQNOXf54CjLoa5bWFT8zKPXbXXUEg0b4Qko0r3uuVYLx5SJD88XCpTFUtTx/ AD8VvwuI8rP4xE6u+LRDqLtUr0StQlPvLU0QcHQvBddlZ6xmxaJ4CUqbiBwFeqSjorq0 tQTczL9wLNOjMoN3jlUYVGK4VFmBTb8NDgxDqi4s+t+8OIn2J3DCw3FBCWS0efJPZ5JK Uc+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=EMFrbM7U7g/gi4LdtGhB2DNi+5bXm13VPGgYeyWm0co=; b=Gv2Vn4AQpQ4b2M9sveXmUmLX8tjzOG5MfLkTGveC1AlZ2HYe74POx5auoq6L6ljSU5 IA+ZY71jsc3EC5eDrZUPZsePzgpZ6bsQ2aHg/JeIeLtUy/JD5vAaJ3DNHw1MpauyRhtO Pjy9DYsTedCsvHri9eWk2cclSdkoeom+82XfCYzkgG9sjhXM6tgnLvXje0VMa5mHrmJG doWPZgQb2DiKoaFwLaX01fK443qz+g2+oq/iPRCXsKwFkTAi9aCqWH6sTCO9nXaHVo1O WLsmdBY4QbPoiGCs+OC6sZMzZXKXR4TKIvT5WA7W5JKqK92fC6rfVruaDyG0q5bNCbP8 wuUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=UI7bCnfz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Subject: [PATCH 08/23] clocksource/drivers/fttmr010: Merge Moxa into FTTMR010 Date: Wed, 14 Jun 2017 14:39:29 +0200 Message-Id: <1497443984-12371-8-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Linus Walleij This merges the Moxa Art timer driver into the Faraday FTTMR010 driver and replaces all Kconfig symbols to use the Faraday driver instead. We are now so similar that the drivers can be merged by just adding a few lines to the Faraday timer. Differences: - The Faraday driver explicitly sets the counter to count upwards for the clocksource, removing the need for the clocksource core to invert the value. - The Faraday driver also handles sched_clock() On the Aspeed, the counter can only count downwards, so support the timers in downward-counting mode as well, and flag the Aspeed to use this mode. This mode was tested on the Gemini so I have high hopes that it'll work fine on the Aspeed as well. After this we have one driver for all three SoCs and a generic Faraday FTTMR010 timer driver, which is nice. Cc: Joel Stanley Cc: Jonas Jensen Signed-off-by: Linus Walleij Reviewed-by: Joel Stanley Tested-by: Joel Stanley Signed-off-by: Daniel Lezcano --- arch/arm/mach-aspeed/Kconfig | 2 +- arch/arm/mach-moxart/Kconfig | 2 +- drivers/clocksource/Kconfig | 7 - drivers/clocksource/Makefile | 1 - drivers/clocksource/moxart_timer.c | 256 ----------------------------------- drivers/clocksource/timer-fttmr010.c | 143 ++++++++++++++----- 6 files changed, 108 insertions(+), 303 deletions(-) delete mode 100644 drivers/clocksource/moxart_timer.c -- 2.7.4 diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig index f3f8c5c..2d5570e 100644 --- a/arch/arm/mach-aspeed/Kconfig +++ b/arch/arm/mach-aspeed/Kconfig @@ -4,7 +4,7 @@ menuconfig ARCH_ASPEED select SRAM select WATCHDOG select ASPEED_WATCHDOG - select MOXART_TIMER + select FTTMR010_TIMER select MFD_SYSCON select PINCTRL help diff --git a/arch/arm/mach-moxart/Kconfig b/arch/arm/mach-moxart/Kconfig index 70db2ab..a4a91f9 100644 --- a/arch/arm/mach-moxart/Kconfig +++ b/arch/arm/mach-moxart/Kconfig @@ -4,7 +4,7 @@ menuconfig ARCH_MOXART select CPU_FA526 select ARM_DMA_MEM_BUFFERABLE select FARADAY_FTINTC010 - select MOXART_TIMER + select FTTMR010_TIMER select GPIOLIB select PHYLIB if NETDEVICES help diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 545d541..1b22ade 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -188,13 +188,6 @@ config ATLAS7_TIMER help Enables support for the Atlas7 timer. -config MOXART_TIMER - bool "Moxart timer driver" if COMPILE_TEST - depends on GENERIC_CLOCKEVENTS - select CLKSRC_MMIO - help - Enables support for the Moxart timer. - config MXS_TIMER bool "Mxs timer driver" if COMPILE_TEST depends on GENERIC_CLOCKEVENTS diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 2b5b56a..cf0c30b 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -26,7 +26,6 @@ obj-$(CONFIG_ORION_TIMER) += time-orion.o obj-$(CONFIG_BCM2835_TIMER) += bcm2835_timer.o obj-$(CONFIG_CLPS711X_TIMER) += clps711x-timer.o obj-$(CONFIG_ATLAS7_TIMER) += timer-atlas7.o -obj-$(CONFIG_MOXART_TIMER) += moxart_timer.o obj-$(CONFIG_MXS_TIMER) += mxs_timer.o obj-$(CONFIG_CLKSRC_PXA) += pxa_timer.o obj-$(CONFIG_PRIMA2_TIMER) += timer-prima2.o diff --git a/drivers/clocksource/moxart_timer.c b/drivers/clocksource/moxart_timer.c deleted file mode 100644 index 7f34306..0000000 --- a/drivers/clocksource/moxart_timer.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * MOXA ART SoCs timer handling. - * - * Copyright (C) 2013 Jonas Jensen - * - * Jonas Jensen - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define TIMER1_BASE 0x00 -#define TIMER2_BASE 0x10 -#define TIMER3_BASE 0x20 - -#define REG_COUNT 0x0 /* writable */ -#define REG_LOAD 0x4 -#define REG_MATCH1 0x8 -#define REG_MATCH2 0xC - -#define TIMER_CR 0x30 -#define TIMER_INTR_STATE 0x34 -#define TIMER_INTR_MASK 0x38 - -/* - * Moxart TIMER_CR flags: - * - * MOXART_CR_*_CLOCK 0: PCLK, 1: EXT1CLK - * MOXART_CR_*_INT overflow interrupt enable bit - */ -#define MOXART_CR_1_ENABLE BIT(0) -#define MOXART_CR_1_CLOCK BIT(1) -#define MOXART_CR_1_INT BIT(2) -#define MOXART_CR_2_ENABLE BIT(3) -#define MOXART_CR_2_CLOCK BIT(4) -#define MOXART_CR_2_INT BIT(5) -#define MOXART_CR_3_ENABLE BIT(6) -#define MOXART_CR_3_CLOCK BIT(7) -#define MOXART_CR_3_INT BIT(8) -#define MOXART_CR_COUNT_UP BIT(9) - -#define MOXART_TIMER1_ENABLE (MOXART_CR_2_ENABLE | MOXART_CR_1_ENABLE) -#define MOXART_TIMER1_DISABLE (MOXART_CR_2_ENABLE) - -/* - * The ASpeed variant of the IP block has a different layout - * for the control register - */ -#define ASPEED_CR_1_ENABLE BIT(0) -#define ASPEED_CR_1_CLOCK BIT(1) -#define ASPEED_CR_1_INT BIT(2) -#define ASPEED_CR_2_ENABLE BIT(4) -#define ASPEED_CR_2_CLOCK BIT(5) -#define ASPEED_CR_2_INT BIT(6) -#define ASPEED_CR_3_ENABLE BIT(8) -#define ASPEED_CR_3_CLOCK BIT(9) -#define ASPEED_CR_3_INT BIT(10) - -#define ASPEED_TIMER1_ENABLE (ASPEED_CR_2_ENABLE | ASPEED_CR_1_ENABLE) -#define ASPEED_TIMER1_DISABLE (ASPEED_CR_2_ENABLE) - -struct moxart_timer { - void __iomem *base; - unsigned int t1_disable_val; - unsigned int t1_enable_val; - unsigned int count_per_tick; - struct clock_event_device clkevt; -}; - -static inline struct moxart_timer *to_moxart(struct clock_event_device *evt) -{ - return container_of(evt, struct moxart_timer, clkevt); -} - -static inline void moxart_disable(struct clock_event_device *evt) -{ - struct moxart_timer *timer = to_moxart(evt); - - writel(timer->t1_disable_val, timer->base + TIMER_CR); -} - -static inline void moxart_enable(struct clock_event_device *evt) -{ - struct moxart_timer *timer = to_moxart(evt); - - writel(timer->t1_enable_val, timer->base + TIMER_CR); -} - -static int moxart_shutdown(struct clock_event_device *evt) -{ - moxart_disable(evt); - return 0; -} - -static int moxart_set_oneshot(struct clock_event_device *evt) -{ - moxart_disable(evt); - writel(~0, to_moxart(evt)->base + TIMER1_BASE + REG_LOAD); - return 0; -} - -static int moxart_set_periodic(struct clock_event_device *evt) -{ - struct moxart_timer *timer = to_moxart(evt); - - moxart_disable(evt); - writel(timer->count_per_tick, timer->base + TIMER1_BASE + REG_LOAD); - writel(0, timer->base + TIMER1_BASE + REG_MATCH1); - moxart_enable(evt); - return 0; -} - -static int moxart_clkevt_next_event(unsigned long cycles, - struct clock_event_device *evt) -{ - struct moxart_timer *timer = to_moxart(evt); - u32 u; - - moxart_disable(evt); - - u = readl(timer->base + TIMER1_BASE + REG_COUNT) - cycles; - writel(u, timer->base + TIMER1_BASE + REG_MATCH1); - - moxart_enable(evt); - - return 0; -} - -static irqreturn_t moxart_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = dev_id; - evt->event_handler(evt); - return IRQ_HANDLED; -} - -static int __init moxart_timer_init(struct device_node *node) -{ - int ret, irq; - unsigned long pclk; - struct clk *clk; - struct moxart_timer *timer; - - timer = kzalloc(sizeof(*timer), GFP_KERNEL); - if (!timer) - return -ENOMEM; - - timer->base = of_iomap(node, 0); - if (!timer->base) { - pr_err("%s: of_iomap failed\n", node->full_name); - ret = -ENXIO; - goto out_free; - } - - irq = irq_of_parse_and_map(node, 0); - if (irq <= 0) { - pr_err("%s: irq_of_parse_and_map failed\n", node->full_name); - ret = -EINVAL; - goto out_unmap; - } - - clk = of_clk_get(node, 0); - if (IS_ERR(clk)) { - pr_err("%s: of_clk_get failed\n", node->full_name); - ret = PTR_ERR(clk); - goto out_unmap; - } - - pclk = clk_get_rate(clk); - - if (of_device_is_compatible(node, "moxa,moxart-timer")) { - timer->t1_enable_val = MOXART_TIMER1_ENABLE; - timer->t1_disable_val = MOXART_TIMER1_DISABLE; - } else if (of_device_is_compatible(node, "aspeed,ast2400-timer")) { - timer->t1_enable_val = ASPEED_TIMER1_ENABLE; - timer->t1_disable_val = ASPEED_TIMER1_DISABLE; - } else { - pr_err("%s: unknown platform\n", node->full_name); - ret = -EINVAL; - goto out_unmap; - } - - timer->count_per_tick = DIV_ROUND_CLOSEST(pclk, HZ); - - timer->clkevt.name = node->name; - timer->clkevt.rating = 200; - timer->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_ONESHOT; - timer->clkevt.set_state_shutdown = moxart_shutdown; - timer->clkevt.set_state_periodic = moxart_set_periodic; - timer->clkevt.set_state_oneshot = moxart_set_oneshot; - timer->clkevt.tick_resume = moxart_set_oneshot; - timer->clkevt.set_next_event = moxart_clkevt_next_event; - timer->clkevt.cpumask = cpumask_of(0); - timer->clkevt.irq = irq; - - ret = clocksource_mmio_init(timer->base + TIMER2_BASE + REG_COUNT, - "moxart_timer", pclk, 200, 32, - clocksource_mmio_readl_down); - if (ret) { - pr_err("%s: clocksource_mmio_init failed\n", node->full_name); - goto out_unmap; - } - - ret = request_irq(irq, moxart_timer_interrupt, IRQF_TIMER, - node->name, &timer->clkevt); - if (ret) { - pr_err("%s: setup_irq failed\n", node->full_name); - goto out_unmap; - } - - /* Clear match registers */ - writel(0, timer->base + TIMER1_BASE + REG_MATCH1); - writel(0, timer->base + TIMER1_BASE + REG_MATCH2); - writel(0, timer->base + TIMER2_BASE + REG_MATCH1); - writel(0, timer->base + TIMER2_BASE + REG_MATCH2); - - /* - * Start timer 2 rolling as our main wall clock source, keep timer 1 - * disabled - */ - writel(0, timer->base + TIMER_CR); - writel(~0, timer->base + TIMER2_BASE + REG_LOAD); - writel(timer->t1_disable_val, timer->base + TIMER_CR); - - /* - * documentation is not publicly available: - * min_delta / max_delta obtained by trial-and-error, - * max_delta 0xfffffffe should be ok because count - * register size is u32 - */ - clockevents_config_and_register(&timer->clkevt, pclk, 0x4, 0xfffffffe); - - return 0; - -out_unmap: - iounmap(timer->base); -out_free: - kfree(timer); - return ret; -} -CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init); -CLOCKSOURCE_OF_DECLARE(aspeed, "aspeed,ast2400-timer", moxart_timer_init); diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index 2d915d1..f880150 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -50,6 +50,20 @@ #define TIMER_2_CR_UPDOWN BIT(10) #define TIMER_3_CR_UPDOWN BIT(11) +/* + * The Aspeed AST2400 moves bits around in the control register + * and lacks bits for setting the timer to count upwards. + */ +#define TIMER_1_CR_ASPEED_ENABLE BIT(0) +#define TIMER_1_CR_ASPEED_CLOCK BIT(1) +#define TIMER_1_CR_ASPEED_INT BIT(2) +#define TIMER_2_CR_ASPEED_ENABLE BIT(4) +#define TIMER_2_CR_ASPEED_CLOCK BIT(5) +#define TIMER_2_CR_ASPEED_INT BIT(6) +#define TIMER_3_CR_ASPEED_ENABLE BIT(8) +#define TIMER_3_CR_ASPEED_CLOCK BIT(9) +#define TIMER_3_CR_ASPEED_INT BIT(10) + #define TIMER_1_INT_MATCH1 BIT(0) #define TIMER_1_INT_MATCH2 BIT(1) #define TIMER_1_INT_OVERFLOW BIT(2) @@ -64,6 +78,8 @@ struct fttmr010 { void __iomem *base; unsigned int tick_rate; + bool count_down; + u32 t1_enable_val; struct clock_event_device clkevt; }; @@ -77,6 +93,8 @@ static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt) static u64 notrace fttmr010_read_sched_clock(void) { + if (local_fttmr->count_down) + return ~readl(local_fttmr->base + TIMER2_COUNT); return readl(local_fttmr->base + TIMER2_COUNT); } @@ -86,11 +104,23 @@ static int fttmr010_timer_set_next_event(unsigned long cycles, struct fttmr010 *fttmr010 = to_fttmr010(evt); u32 cr; - /* Setup the match register */ + /* Stop */ + cr = readl(fttmr010->base + TIMER_CR); + cr &= ~fttmr010->t1_enable_val; + writel(cr, fttmr010->base + TIMER_CR); + + /* Setup the match register forward/backward in time */ cr = readl(fttmr010->base + TIMER1_COUNT); - writel(cr + cycles, fttmr010->base + TIMER1_MATCH1); - if (readl(fttmr010->base + TIMER1_COUNT) - cr > cycles) - return -ETIME; + if (fttmr010->count_down) + cr -= cycles; + else + cr += cycles; + writel(cr, fttmr010->base + TIMER1_MATCH1); + + /* Start */ + cr = readl(fttmr010->base + TIMER_CR); + cr |= fttmr010->t1_enable_val; + writel(cr, fttmr010->base + TIMER_CR); return 0; } @@ -100,9 +130,9 @@ static int fttmr010_timer_shutdown(struct clock_event_device *evt) struct fttmr010 *fttmr010 = to_fttmr010(evt); u32 cr; - /* Stop timer and interrupt. */ + /* Stop */ cr = readl(fttmr010->base + TIMER_CR); - cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); + cr &= ~fttmr010->t1_enable_val; writel(cr, fttmr010->base + TIMER_CR); return 0; @@ -113,14 +143,17 @@ static int fttmr010_timer_set_oneshot(struct clock_event_device *evt) struct fttmr010 *fttmr010 = to_fttmr010(evt); u32 cr; - /* Stop timer and interrupt. */ + /* Stop */ cr = readl(fttmr010->base + TIMER_CR); - cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); + cr &= ~fttmr010->t1_enable_val; writel(cr, fttmr010->base + TIMER_CR); - /* Setup counter start from 0 */ + /* Setup counter start from 0 or ~0 */ writel(0, fttmr010->base + TIMER1_COUNT); - writel(0, fttmr010->base + TIMER1_LOAD); + if (fttmr010->count_down) + writel(~0, fttmr010->base + TIMER1_LOAD); + else + writel(0, fttmr010->base + TIMER1_LOAD); /* Enable interrupt */ cr = readl(fttmr010->base + TIMER_INTR_MASK); @@ -128,11 +161,6 @@ static int fttmr010_timer_set_oneshot(struct clock_event_device *evt) cr |= TIMER_1_INT_MATCH1; writel(cr, fttmr010->base + TIMER_INTR_MASK); - /* Start the timer */ - cr = readl(fttmr010->base + TIMER_CR); - cr |= TIMER_1_CR_ENABLE; - writel(cr, fttmr010->base + TIMER_CR); - return 0; } @@ -142,26 +170,30 @@ static int fttmr010_timer_set_periodic(struct clock_event_device *evt) u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ); u32 cr; - /* Stop timer and interrupt */ + /* Stop */ cr = readl(fttmr010->base + TIMER_CR); - cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); + cr &= ~fttmr010->t1_enable_val; writel(cr, fttmr010->base + TIMER_CR); - /* Setup timer to fire at 1/HT intervals. */ - cr = 0xffffffff - (period - 1); - writel(cr, fttmr010->base + TIMER1_COUNT); - writel(cr, fttmr010->base + TIMER1_LOAD); - - /* enable interrupt on overflow */ - cr = readl(fttmr010->base + TIMER_INTR_MASK); - cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2); - cr |= TIMER_1_INT_OVERFLOW; - writel(cr, fttmr010->base + TIMER_INTR_MASK); + /* Setup timer to fire at 1/HZ intervals. */ + if (fttmr010->count_down) { + writel(period, fttmr010->base + TIMER1_LOAD); + writel(0, fttmr010->base + TIMER1_MATCH1); + } else { + cr = 0xffffffff - (period - 1); + writel(cr, fttmr010->base + TIMER1_COUNT); + writel(cr, fttmr010->base + TIMER1_LOAD); + + /* Enable interrupt on overflow */ + cr = readl(fttmr010->base + TIMER_INTR_MASK); + cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2); + cr |= TIMER_1_INT_OVERFLOW; + writel(cr, fttmr010->base + TIMER_INTR_MASK); + } /* Start the timer */ cr = readl(fttmr010->base + TIMER_CR); - cr |= TIMER_1_CR_ENABLE; - cr |= TIMER_1_CR_INT; + cr |= fttmr010->t1_enable_val; writel(cr, fttmr010->base + TIMER_CR); return 0; @@ -181,9 +213,11 @@ static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id) static int __init fttmr010_timer_init(struct device_node *np) { struct fttmr010 *fttmr010; + bool is_ast2400; int irq; struct clk *clk; int ret; + u32 val; /* * These implementations require a clock reference. @@ -223,13 +257,37 @@ static int __init fttmr010_timer_init(struct device_node *np) } /* + * The Aspeed AST2400 moves bits around in the control register, + * otherwise it works the same. + */ + is_ast2400 = of_device_is_compatible(np, "aspeed,ast2400-timer"); + if (is_ast2400) { + fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE | + TIMER_1_CR_ASPEED_INT; + /* Downward not available */ + fttmr010->count_down = true; + } else { + fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT; + } + + /* * Reset the interrupt mask and status */ writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK); writel(0, fttmr010->base + TIMER_INTR_STATE); - /* Enable timer 1 count up, timer 2 count up */ - writel((TIMER_1_CR_UPDOWN | TIMER_2_CR_ENABLE | TIMER_2_CR_UPDOWN), - fttmr010->base + TIMER_CR); + + /* + * Enable timer 1 count up, timer 2 count up, except on Aspeed, + * where everything just counts down. + */ + if (is_ast2400) + val = TIMER_2_CR_ASPEED_ENABLE; + else { + val = TIMER_2_CR_ENABLE; + if (!fttmr010->count_down) + val |= TIMER_1_CR_UPDOWN | TIMER_2_CR_UPDOWN; + } + writel(val, fttmr010->base + TIMER_CR); /* * Setup free-running clocksource timer (interrupts @@ -237,13 +295,22 @@ static int __init fttmr010_timer_init(struct device_node *np) */ local_fttmr = fttmr010; writel(0, fttmr010->base + TIMER2_COUNT); - writel(0, fttmr010->base + TIMER2_LOAD); writel(0, fttmr010->base + TIMER2_MATCH1); writel(0, fttmr010->base + TIMER2_MATCH2); - clocksource_mmio_init(fttmr010->base + TIMER2_COUNT, - "FTTMR010-TIMER2", - fttmr010->tick_rate, - 300, 32, clocksource_mmio_readl_up); + + if (fttmr010->count_down) { + writel(~0, fttmr010->base + TIMER2_LOAD); + clocksource_mmio_init(fttmr010->base + TIMER2_COUNT, + "FTTMR010-TIMER2", + fttmr010->tick_rate, + 300, 32, clocksource_mmio_readl_down); + } else { + writel(0, fttmr010->base + TIMER2_LOAD); + clocksource_mmio_init(fttmr010->base + TIMER2_COUNT, + "FTTMR010-TIMER2", + fttmr010->tick_rate, + 300, 32, clocksource_mmio_readl_up); + } sched_clock_register(fttmr010_read_sched_clock, 32, fttmr010->tick_rate); @@ -290,3 +357,5 @@ static int __init fttmr010_timer_init(struct device_node *np) } CLOCKSOURCE_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init); CLOCKSOURCE_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init); +CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init); +CLOCKSOURCE_OF_DECLARE(aspeed, "aspeed,ast2400-timer", fttmr010_timer_init); From patchwork Wed Jun 14 12:39:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105501 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp271613qgd; Wed, 14 Jun 2017 05:41:36 -0700 (PDT) X-Received: by 10.84.128.1 with SMTP id 1mr517132pla.244.1497444096743; Wed, 14 Jun 2017 05:41:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497444096; cv=none; d=google.com; s=arc-20160816; b=aRdaZ1l/wb/PSVVEqUH6B2bkEDYkdanwTB3e69kpJvK9FotduiPSiNIW3tJT6HwVN5 PLC8O5S/wRleGy9xf2aLzgtlI5WbGaSn+n9qengiCdzQ4vGnNMsAGJ134pKKYpMwNGOC Oo67Q0U5hqMpsTDXfQ8JoGM+JRpZVBRO30u8wzc48C6GICDZ9F+OdfGHKqyCo+/vix9X X52oZgE8Zk9HHfPedHqH7LX7s0xcmLJAVPMD+zit8IorswiO2E56cnmrK5BO//p97Cs3 qBR+OspawOpgcfCnkwSCbyIuVBoFXTSMOfnmCzZkopq+XDFOvostNcVShXkchwArAVw3 oj7Q== ARC-Message-Signature: i=1; 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Subject: [PATCH 09/23] clocksource/drivers/fttmr010: Add AST2500 compatible string Date: Wed, 14 Jun 2017 14:39:30 +0200 Message-Id: <1497443984-12371-9-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Also clean up space-before-tab issues in the documentation. Signed-off-by: Andrew Jeffery Acked-by: Joel Stanley Acked-by: Rob Herring Reviewed-by: Linus Walleij Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/timer/faraday,fttmr010.txt | 2 ++ drivers/clocksource/timer-fttmr010.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt b/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt index 6e18bd6..1957922 100644 --- a/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt +++ b/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt @@ -10,6 +10,8 @@ Required properties: "cortina,gemini-timer", "faraday,fttmr010" "moxa,moxart-timer", "faraday,fttmr010" "aspeed,ast2400-timer" + "aspeed,ast2500-timer" + - reg : Should contain registers location and length - interrupts : Should contain the three timer interrupts usually with flags for falling edge diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index f880150..68982ad 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -358,4 +358,5 @@ static int __init fttmr010_timer_init(struct device_node *np) CLOCKSOURCE_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init); CLOCKSOURCE_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init); CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init); -CLOCKSOURCE_OF_DECLARE(aspeed, "aspeed,ast2400-timer", fttmr010_timer_init); +CLOCKSOURCE_OF_DECLARE(ast2400, "aspeed,ast2400-timer", fttmr010_timer_init); +CLOCKSOURCE_OF_DECLARE(ast2500, "aspeed,ast2500-timer", fttmr010_timer_init); From patchwork Wed Jun 14 12:39:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105499 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp271559qgd; Wed, 14 Jun 2017 05:41:27 -0700 (PDT) X-Received: by 10.99.165.78 with SMTP id r14mr455825pgu.74.1497444086940; Wed, 14 Jun 2017 05:41:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497444086; cv=none; d=google.com; s=arc-20160816; b=jTsg6X5lv0EkmjBSK2c3nHY8SCfV9vj2IOm0hlRPHKT4ZA6AT7n8qmHEfM36UOpu1c IcmjQ2zzmDPDrRvHhOeqJoo2kyzY1jvXNBIVKG40Q4dYK4flAiNqyToAoAFc2la2J9nt xJwJFJUILDzaCKeKY1MD3W0EnYaNdPNYFYOQeougekQLNanJNe5qTJiYrNH+AfhzeiMv QXr5ORteqruZ9DkqBVTme1/ED9wUaK2C4dkzBsc5C6oGgDyrUDp/oPV9TPUWkjBLNuHb mBq8cEuqJgm8qsr2tsNmFfLr8zTLaAaidq+wEeduBH+C6w3jQ8NnnNBicNEgVESxVEEg e0hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=1NkE8kTzSalcDktEXa0trOW/GkwI1yE0VMBPFi90YFo=; b=vTtEx0zNpeve95XmUcJfTPLkqM9ZBHaGohFeQoucekpQ7i4AI2oUpzJwwDmtWmhqfe Py9R3PebAapIkPNI4hRaSuMRj7TS4Xgci1R0GEZtaF28oBUnzI/e4D2G3RICjzP6zSkh 1WiYDo4urDMFgVrvShVd1bHSyLAG8TYOkrrLDSLg+q99pijjrjUlgFISdb16AgQe221f wX8Mdg+OORb6qmmHS3/Lmw8QEId21kAAQgB+KtJcIF6tmNEfqbFEt9XJKipP2TTS6RTb MqxfmU/chpKvt87rW5gI9FTHTzRZH+i0Wl2fUovhlgRSpSF8LSCjf0eb1RnB1l/n8fPT no8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=XGV0ouFt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 89si625331plc.277.2017.06.14.05.41.26; Wed, 14 Jun 2017 05:41:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=XGV0ouFt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752582AbdFNMlX (ORCPT + 25 others); Wed, 14 Jun 2017 08:41:23 -0400 Received: from mail-wr0-f181.google.com ([209.85.128.181]:36398 "EHLO mail-wr0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752548AbdFNMlV (ORCPT ); Wed, 14 Jun 2017 08:41:21 -0400 Received: by mail-wr0-f181.google.com with SMTP id 36so66278262wry.3 for ; Wed, 14 Jun 2017 05:41:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1NkE8kTzSalcDktEXa0trOW/GkwI1yE0VMBPFi90YFo=; b=XGV0ouFtpLtCQZfsErY82bGjjYUWSPF/HS/s2TZQSwWMEHOaHlbrAYg9Wqn4Nu01Bx Bzd6Iq/SdehNbsskMtkrG+AO6R9fhqV9HS/Sze8sITVHdN5mrJ5NGQ0m2saQp4udqyhE gnVTvvhS8ojTCEOmdwuOeHVNXbYW6PmYbe2rU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1NkE8kTzSalcDktEXa0trOW/GkwI1yE0VMBPFi90YFo=; b=rfNx1qdq8ZMBMGlvgaYNyNC0uEpWQyLeDzV0hj1wd774lYRVCxLd9j7lrNWyJ666TF wXXWeyIhfcUYx7lmf6YcPBgBpcW85bCAjfmRXZtlFCO8ugoRiEauaM5GV6ARjnmeqtf8 B9NgAoDIEf4uPZa3tWWiTzLVHROqC9IsD9z1RR0n5i+0yJIcuO1oqPOxH+zOuAuJJ3Gz yQT7ocH8UpPIRj401QJ1DN9OxPnxhuozFc3R5DKDEy8BWMJiPrvdCmwDSEOsYaaCEIaZ sF3xHwZBWT7UKdwJzI21s6nhEebCL4hOoMCHWhQBB8taj63vPyFAdvJns05yyZD3BTUH cq7g== X-Gm-Message-State: AKS2vOxl2jSSfBKMgMTDp4kLWIUtZlD+J76XeI3qJXVl5jFC6cBSjstC hr4Vd7suGcTCyxDN X-Received: by 10.28.143.16 with SMTP id r16mr963000wmd.50.1497444075157; Wed, 14 Jun 2017 05:41:15 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:19a:b336:54d7:46e9]) by smtp.gmail.com with ESMTPSA id 80sm1457015wmg.17.2017.06.14.05.41.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 05:41:14 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Joel Stanley , Andrew Jeffery Subject: [PATCH 10/23] clocksource/drivers/fttmr010: Fix aspeed-2500 initialization Date: Wed, 14 Jun 2017 14:39:31 +0200 Message-Id: <1497443984-12371-10-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The recent changes made the fttmr010 to be more generic and support different timers with a very few differences like moxart or aspeed. The aspeed timer uses a countdown and there is a test against the aspeed2400 compatible string to set a flag. With the previous patch, we added the aspeed2500 compatible string but without taking care of setting the countdown flag. Fix this by specifiying a init function and pass the aspeed flag to a common init function. Reviewed-by: Linus Walleij Tested-by: Andrew Jeffery Reviewed-by: Andrew Jeffery Acked-by: Joel Stanley Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-fttmr010.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index 68982ad..d96190e 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -210,10 +210,9 @@ static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static int __init fttmr010_timer_init(struct device_node *np) +static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed) { struct fttmr010 *fttmr010; - bool is_ast2400; int irq; struct clk *clk; int ret; @@ -260,8 +259,7 @@ static int __init fttmr010_timer_init(struct device_node *np) * The Aspeed AST2400 moves bits around in the control register, * otherwise it works the same. */ - is_ast2400 = of_device_is_compatible(np, "aspeed,ast2400-timer"); - if (is_ast2400) { + if (is_aspeed) { fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE | TIMER_1_CR_ASPEED_INT; /* Downward not available */ @@ -280,7 +278,7 @@ static int __init fttmr010_timer_init(struct device_node *np) * Enable timer 1 count up, timer 2 count up, except on Aspeed, * where everything just counts down. */ - if (is_ast2400) + if (is_aspeed) val = TIMER_2_CR_ASPEED_ENABLE; else { val = TIMER_2_CR_ENABLE; @@ -355,8 +353,19 @@ static int __init fttmr010_timer_init(struct device_node *np) return ret; } + +static __init int aspeed_timer_init(struct device_node *np) +{ + return fttmr010_common_init(np, true); +} + +static __init int fttmr010_timer_init(struct device_node *np) +{ + return fttmr010_common_init(np, false); +} + CLOCKSOURCE_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init); CLOCKSOURCE_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init); CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init); -CLOCKSOURCE_OF_DECLARE(ast2400, "aspeed,ast2400-timer", fttmr010_timer_init); -CLOCKSOURCE_OF_DECLARE(ast2500, "aspeed,ast2500-timer", fttmr010_timer_init); +CLOCKSOURCE_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init); +CLOCKSOURCE_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init); From patchwork Wed Jun 14 12:39:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105500 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp271610qgd; Wed, 14 Jun 2017 05:41:36 -0700 (PDT) X-Received: by 10.99.152.70 with SMTP id l6mr436728pgo.136.1497444096354; Wed, 14 Jun 2017 05:41:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497444096; cv=none; d=google.com; s=arc-20160816; b=G7q+i7RuOgjI31uLD0TcWPqY04vAJBPGk5h7vvoNtbOVYrgPuDBTU4B8Dl29eWr2dX w2jBbKZnLzkQ1zViOtLnUPAlR0eoBB+PrUAYvw/zbgrrWT/FN1Nqo8G51TKbN0qo0Q3k 1KRxM4H1DBo+jHkOflQU25U/yj7LqKeJwVcz9ap/wnYC7pP6saZCdYQB/ccbi6r8kxJE X7wONNwQ2i3OrN2mt+1HTIBRkFcRhYWLM4X90jw/T+DitQ7uTpgsvxHTdbWlxeit4It4 Rwbl8jMMqteZBeEdssspbaUPmQohbsHo5ghut9EiQJzlCMz8JNF/fPMoxZUmqKA+kksX Pcrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=IYYe+4T7iSNenj0XXrLlcpDihhgG1Sfu5EPTqBGTbAQ=; b=A94LwUkDltQ9uxv6CKOxj/g12AwvXiNa6Oem3TWVXKvjtjT5XdeOzA9wGZoRwzRg14 VQVJyxhZmPqIzwR1PXm05Ijj+Pf0akCUqKxllRHEWeq9Em7x7HxYsosHrb2A6vt/pN7W PRQNPVZTza4y0eKRN58C758pWuMlw11cBEdF1BspPjtyuzeflP3n4SPB7ZTFYKInlEK7 Yu+j6tuP6UnT6UxplczGOoSbjBJNfjggjLfMEOW7OLKjgfLU9ZhxLn++T/K6/c7cD/u9 BjwbsmL/nhGqsLtmFKtLxWtfq0Hm+CajMU/EDa2S9+QCtaq3yZsQCkHizQ5o9Lx9tnC8 vzfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=hJlFCTvF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Subject: [PATCH 11/23] Revert "clockevents: Add a clkevt-of mechanism like clksrc-of" Date: Wed, 14 Jun 2017 14:39:32 +0200 Message-Id: <1497443984-12371-11-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org After discussing it, this feature is dropped as it is not considered adequate: https://patchwork.kernel.org/patch/9639317/ There is no user of this macro yet, so there is no impact on the drivers. This reverts commit 376bc27150f180d9f5eddec6a14117780177589d. Cc: Mark Rutland Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 7 ----- drivers/clocksource/Makefile | 1 - drivers/clocksource/clkevt-probe.c | 56 -------------------------------------- include/asm-generic/vmlinux.lds.h | 2 -- include/linux/clockchips.h | 9 ------ 5 files changed, 75 deletions(-) delete mode 100644 drivers/clocksource/clkevt-probe.c -- 2.7.4 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 1b22ade..623fcc6 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -5,10 +5,6 @@ config CLKSRC_OF bool select CLKSRC_PROBE -config CLKEVT_OF - bool - select CLKEVT_PROBE - config CLKSRC_ACPI bool select CLKSRC_PROBE @@ -16,9 +12,6 @@ config CLKSRC_ACPI config CLKSRC_PROBE bool -config CLKEVT_PROBE - bool - config CLKSRC_I8253 bool diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index cf0c30b..cad713c 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -1,5 +1,4 @@ obj-$(CONFIG_CLKSRC_PROBE) += clksrc-probe.o -obj-$(CONFIG_CLKEVT_PROBE) += clkevt-probe.o obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o diff --git a/drivers/clocksource/clkevt-probe.c b/drivers/clocksource/clkevt-probe.c deleted file mode 100644 index eb89b50..0000000 --- a/drivers/clocksource/clkevt-probe.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2016, Linaro Ltd. All rights reserved. - * Daniel Lezcano - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include - -extern struct of_device_id __clkevt_of_table[]; - -static const struct of_device_id __clkevt_of_table_sentinel - __used __section(__clkevt_of_table_end); - -int __init clockevent_probe(void) -{ - struct device_node *np; - const struct of_device_id *match; - of_init_fn_1_ret init_func; - int ret, clockevents = 0; - - for_each_matching_node_and_match(np, __clkevt_of_table, &match) { - if (!of_device_is_available(np)) - continue; - - init_func = match->data; - - ret = init_func(np); - if (ret) { - pr_warn("Failed to initialize '%s' (%d)\n", - np->name, ret); - continue; - } - - clockevents++; - } - - if (!clockevents) { - pr_crit("%s: no matching clockevent found\n", __func__); - return -ENODEV; - } - - return 0; -} diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h index 314a0b9..401d324 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -173,7 +173,6 @@ KEEP(*(__##name##_of_table_end)) #define CLKSRC_OF_TABLES() OF_TABLE(CONFIG_CLKSRC_OF, clksrc) -#define CLKEVT_OF_TABLES() OF_TABLE(CONFIG_CLKEVT_OF, clkevt) #define IRQCHIP_OF_MATCH_TABLE() OF_TABLE(CONFIG_IRQCHIP, irqchip) #define CLK_OF_TABLES() OF_TABLE(CONFIG_COMMON_CLK, clk) #define IOMMU_OF_TABLES() OF_TABLE(CONFIG_OF_IOMMU, iommu) @@ -558,7 +557,6 @@ CLK_OF_TABLES() \ RESERVEDMEM_OF_TABLES() \ CLKSRC_OF_TABLES() \ - CLKEVT_OF_TABLES() \ IOMMU_OF_TABLES() \ CPU_METHOD_OF_TABLES() \ CPUIDLE_METHOD_OF_TABLES() \ diff --git a/include/linux/clockchips.h b/include/linux/clockchips.h index acc9ce0..a116926 100644 --- a/include/linux/clockchips.h +++ b/include/linux/clockchips.h @@ -223,13 +223,4 @@ static inline void tick_setup_hrtimer_broadcast(void) { } #endif /* !CONFIG_GENERIC_CLOCKEVENTS */ -#define CLOCKEVENT_OF_DECLARE(name, compat, fn) \ - OF_DECLARE_1_RET(clkevt, name, compat, fn) - -#ifdef CONFIG_CLKEVT_PROBE -extern int clockevent_probe(void); -#else -static inline int clockevent_probe(void) { return 0; } -#endif - #endif /* _LINUX_CLOCKCHIPS_H */ From patchwork Wed Jun 14 12:39:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105510 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp272819qgd; Wed, 14 Jun 2017 05:44:41 -0700 (PDT) X-Received: by 10.99.106.66 with SMTP id f63mr450112pgc.150.1497444281330; Wed, 14 Jun 2017 05:44:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497444281; cv=none; d=google.com; s=arc-20160816; b=ORC6XoFbNZWF3wnLh6fZh11ky7lcYUiSneg/M0M9eA20oWWY24rcS2fRYGpimJPvOA cqS1CvHYXwtfGTaxAujcKYtruaBc4V9slAFWf6Sk4cSY0oqh0A+mlhhy5ia1Vq2RCZU2 P6DU4Q2iODv0jdU1I6H70FVr1DMjMUa/UJvZ6TABb8am67Un22wcccwN0RH0l6xSU6AW /x/WqYRGHfAL9+YcJm/g5SaaCxmFfskLi0DfqBb3VouCXr4bx8MIrv0EWOwTLgl0k9bR xh28bUZPDG68409BjndV4mSb/5CSojA5H9xZObYb8cRs1QI1gXFLAuMaBijgO5Zm3Ezu OMdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=NixKQgbIh5/vu+7UsXgg2wsHN3g45dGyYlWpC1EDYnQ=; b=Z9buqwiH+o1O+GchE21/PEm7d9HHVVKzDzge/vSztmCUNE3gNHpmurud5l3aMLY8k4 FCNgHItF1f06OjVOf/4+Z7bwwvHTj6oAiCXwck+ivEVWLX3utLW8g1dbnhVNRJbG1U91 VL+f+0P5+3Zltu7D2vff08z5mgp34c9NjUqVl3XCh2z5vYF7EhZo+ZNNvB3miWAnW0WN kzsgRhZvbQ/0ukco11LE+oOJizLhgxclYi/qpgilclTJiArRVULWrWez+S7d31/jLGP9 HqgjoqGJsGjj8ElpF0ej56ONw3PtxoY/ddTDzM5TKDkGRFSJn235YxsGBxBadov9jeRy ru1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=NWS5uL02; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Subject: [PATCH 14/23] clocksource/drivers: Rename CLOCKSOURCE_ACPI_DECLARE to TIMER_ACPI_DECLARE Date: Wed, 14 Jun 2017 14:39:35 +0200 Message-Id: <1497443984-12371-14-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The macro name is now renamed to 'TIMER_ACPI_DECLARE' for consistency with the CLOCKSOURCE_OF_DECLARE => TIMER_OF_DECLARE change. Signed-off-by: Daniel Lezcano Reviewed-by: Linus Walleij --- drivers/clocksource/arm_arch_timer.c | 2 +- include/linux/clocksource.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index bc60cd7..a89d41c 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -1516,5 +1516,5 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table) return arch_timer_common_init(); } -CLOCKSOURCE_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init); +TIMER_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init); #endif diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h index 010bb9f..e43f37f 100644 --- a/include/linux/clocksource.h +++ b/include/linux/clocksource.h @@ -258,7 +258,7 @@ extern void timer_probe(void); static inline void timer_probe(void) {} #endif -#define CLOCKSOURCE_ACPI_DECLARE(name, table_id, fn) \ +#define TIMER_ACPI_DECLARE(name, table_id, fn) \ ACPI_DECLARE_PROBE_ENTRY(clksrc, name, table_id, 0, NULL, 0, fn) #endif /* _LINUX_CLOCKSOURCE_H */ From patchwork Wed Jun 14 12:39:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105502 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp271918qgd; Wed, 14 Jun 2017 05:42:21 -0700 (PDT) X-Received: by 10.99.3.202 with SMTP id 193mr430992pgd.222.1497444141834; Wed, 14 Jun 2017 05:42:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497444141; cv=none; d=google.com; s=arc-20160816; b=tBTKf1NqISrT0bOissuLcPJC+FiHJrDZnljIIqe/TlhFXVJUaWqwTJUg3YRQV1s6SB G2Y6EJ7JR6f48gStK+KrsOf+oZlNgAqBHHUGZJu2sPv3kOxie/a3b+DaBPqumV49aguj vwVF+USJeQFK1KFQeY1IDRiQhFQ5CaSi7J5WLAbGFUhb7nnE+mk6y2Uk57bf8ot+U/s9 imS4U+4Lm0aVat3pBRsnPVMy3wT/5VgeMnVFSnCWqrFDx7v4Fr6g0dB7Yqs+oNGJV8JO qqoxm4P0W857clft3DJXSp9p2zyekHnoTsGn56nNr4dIJ0d89iJKZEAzjLwqkQmM8Xh1 mTtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=CTBj6VugFqP/r+4YmbJX4NBIGU5AR1cVccm3RV9PHp0=; b=s0w+sNlSlC1mHG0mnOi75c/YzUfNnD2bwlJwTOglmKqawO2vVGiXU0kH3B5b4vU6kL hG4gGz9SmWzppJ+Qls/rBv5aYm//1IdC4Af5sJgh3gRk3elZ5dxjP1i4NyB/EtL+Rd9A rmeBXTyyM5LCrUv8q2MO8OWzTazzmhlZGUXVQvPnVIlQPIyFP3ore7Y6naJhEqk1oKDS dxaaqTGiQEwA7kVDTXjAgJsH5K4wdTjg/e4AprivBn8rIaC4M0I27lojUpnzl3fzduQ8 NCJzZwNT1HOzDVBKZ+oaEZtMLloDjzmyZXNNyM7quTBzGe89vG0Qz0vHM7/sExCd3OYe TUdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=hMSCd2rS; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Subject: [PATCH 15/23] clocksource/drivers: Rename clksrc table to timer Date: Wed, 14 Jun 2017 14:39:36 +0200 Message-Id: <1497443984-12371-15-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The table name is now renamed to 'timer' for consistency with the CLOCKSOURCE_OF_DECLARE => TIMER_OF_DECLARE change. Signed-off-by: Daniel Lezcano Reviewed-by: Linus Walleij --- drivers/clocksource/clksrc-probe.c | 18 +++++++++--------- include/asm-generic/vmlinux.lds.h | 7 ++++--- include/linux/clocksource.h | 4 ++-- 3 files changed, 15 insertions(+), 14 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/clksrc-probe.c b/drivers/clocksource/clksrc-probe.c index 5d549c2..da81e5d 100644 --- a/drivers/clocksource/clksrc-probe.c +++ b/drivers/clocksource/clksrc-probe.c @@ -19,20 +19,20 @@ #include #include -extern struct of_device_id __clksrc_of_table[]; +extern struct of_device_id __timer_of_table[]; -static const struct of_device_id __clksrc_of_table_sentinel - __used __section(__clksrc_of_table_end); +static const struct of_device_id __timer_of_table_sentinel + __used __section(__timer_of_table_end); void __init timer_probe(void) { struct device_node *np; const struct of_device_id *match; of_init_fn_1_ret init_func_ret; - unsigned clocksources = 0; + unsigned timers = 0; int ret; - for_each_matching_node_and_match(np, __clksrc_of_table, &match) { + for_each_matching_node_and_match(np, __timer_of_table, &match) { if (!of_device_is_available(np)) continue; @@ -45,11 +45,11 @@ void __init timer_probe(void) continue; } - clocksources++; + timers++; } - clocksources += acpi_probe_device_table(clksrc); + timers += acpi_probe_device_table(timer); - if (!clocksources) - pr_crit("%s: no matching clocksources found\n", __func__); + if (!timers) + pr_crit("%s: no matching timers found\n", __func__); } diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h index 401d324..c6a4ef50 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -172,7 +172,7 @@ KEEP(*(__##name##_of_table)) \ KEEP(*(__##name##_of_table_end)) -#define CLKSRC_OF_TABLES() OF_TABLE(CONFIG_CLKSRC_OF, clksrc) +#define TIMER_OF_TABLES() OF_TABLE(CONFIG_CLKSRC_OF, timer) #define IRQCHIP_OF_MATCH_TABLE() OF_TABLE(CONFIG_IRQCHIP, irqchip) #define CLK_OF_TABLES() OF_TABLE(CONFIG_COMMON_CLK, clk) #define IOMMU_OF_TABLES() OF_TABLE(CONFIG_OF_IOMMU, iommu) @@ -556,14 +556,15 @@ MEM_DISCARD(init.rodata) \ CLK_OF_TABLES() \ RESERVEDMEM_OF_TABLES() \ - CLKSRC_OF_TABLES() \ + TIMER_OF_TABLES() \ IOMMU_OF_TABLES() \ CPU_METHOD_OF_TABLES() \ CPUIDLE_METHOD_OF_TABLES() \ KERNEL_DTB() \ IRQCHIP_OF_MATCH_TABLE() \ ACPI_PROBE_TABLE(irqchip) \ - ACPI_PROBE_TABLE(clksrc) \ + ACPI_PROBE_TABLE(timer) \ + ACPI_PROBE_TABLE(iort) \ EARLYCON_TABLE() #define INIT_TEXT \ diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h index e43f37f..7cd38b2 100644 --- a/include/linux/clocksource.h +++ b/include/linux/clocksource.h @@ -250,7 +250,7 @@ extern int clocksource_mmio_init(void __iomem *, const char *, extern int clocksource_i8253_init(void); #define TIMER_OF_DECLARE(name, compat, fn) \ - OF_DECLARE_1_RET(clksrc, name, compat, fn) + OF_DECLARE_1_RET(timer, name, compat, fn) #ifdef CONFIG_CLKSRC_PROBE extern void timer_probe(void); @@ -259,6 +259,6 @@ static inline void timer_probe(void) {} #endif #define TIMER_ACPI_DECLARE(name, table_id, fn) \ - ACPI_DECLARE_PROBE_ENTRY(clksrc, name, table_id, 0, NULL, 0, fn) + ACPI_DECLARE_PROBE_ENTRY(timer, name, table_id, 0, NULL, 0, fn) #endif /* _LINUX_CLOCKSOURCE_H */ From patchwork Wed Jun 14 12:39:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105511 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp272823qgd; Wed, 14 Jun 2017 05:44:41 -0700 (PDT) X-Received: by 10.99.2.142 with SMTP id 136mr436140pgc.264.1497444281694; Wed, 14 Jun 2017 05:44:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497444281; cv=none; d=google.com; s=arc-20160816; b=awjJeR1VxitGpLouFBod7AI5HnDHvxr64XHv5hJC1OXQWTuMkGZIa3DJyAb+/nQIoo b+lGcwsj+EH7b6Aaxmh1Y0KbFUPoz/Xaql5uOOKzneUpIp8AqUyaR3t4OS2+TLnNx4AN eWPyL+QZGuBEPYuTbaqzEmpisOFDneSquwMfVwmtiooexl0qmUMWuj3gQAwf04UIfpop ptnNU9C86ROEgPiUrKO1kZ97eVRQ8ahiITpctJJqzqFUBotLesYAXMhbSkPIe9Pw5X81 UJLzoODsg38FGYi6acXVxq9ej33HMF58Me1LPAmWSKliYpiQv5tu5C1CZ686urNip3HW u1HA== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id f5si598790pfb.416.2017.06.14.05.44.41; Wed, 14 Jun 2017 05:44:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=GPHfob2H; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752757AbdFNMoQ (ORCPT + 25 others); Wed, 14 Jun 2017 08:44:16 -0400 Received: from mail-wr0-f173.google.com ([209.85.128.173]:33202 "EHLO mail-wr0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752641AbdFNMmQ (ORCPT ); Wed, 14 Jun 2017 08:42:16 -0400 Received: by mail-wr0-f173.google.com with SMTP id v104so175917782wrb.0 for ; Wed, 14 Jun 2017 05:42:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EnA76xRu7pgJeVO6/1/WJvWizjAQBDNAd/In4lApfOY=; b=GPHfob2HakzeoxRSYI8ZWzZ3UQdNhatIqgVMWCb0QV1lzJDx/7Q++FC/z9AzxYT0J9 BYBr94cR8qHj7YScyJU1Qk0pNkx8PMQLX5/PkVMNM/nAJFupB/BgMa2HYOYmfwu7/RS0 pA/oCqTmZkmg47MuMf8jOOlIeM5RDu+X1mfiI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EnA76xRu7pgJeVO6/1/WJvWizjAQBDNAd/In4lApfOY=; b=BI0fEzYJdMZp8o5M0FaYX+UDg1J/YcBw01e860p/ZPTbrJqjZmkjm+Ohk5WY4tSG9m fz4EJVuahkGFT1LL6rn5w/VZY80e6z3yaio8/4lt6i65ZRXHHTv72dak5ScT0PEu6BUx dP8VmfHXlvU34I48o7Y3Hq2/rY/meYFhvIKbAW5SL2uCiRAFVldhCuvuCy6WeCmkBCsE u8VpFY2QZPHX+1eokqYZ13/WHR+YidIKLQkcISPSM0rUJsQdEZAXIXWfFVdwYEIJVs3F AlH13y9Gw2DuuGdGW7di3d8PzA2FdwcT+nhQBlmFV2bDrSR6ehOp98PGFjvwwjWAl6Iw 5ZWw== X-Gm-Message-State: AKS2vOzDbDxeRDozxNBmTQBYUUVlEuUgAc32LNFpZgVNTo4Ac+lPoml+ Dz4F7V/Kbo7hx2lv X-Received: by 10.28.126.133 with SMTP id z127mr9750139wmc.46.1497444129000; Wed, 14 Jun 2017 05:42:09 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:19a:b336:54d7:46e9]) by smtp.gmail.com with ESMTPSA id 80sm1457015wmg.17.2017.06.14.05.42.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 05:42:08 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org Subject: [PATCH 17/23] clocksource/drivers: Rename CLKSRC_ACPI to TIMER_ACPI Date: Wed, 14 Jun 2017 14:39:38 +0200 Message-Id: <1497443984-12371-17-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The config option name is now renamed to 'TIMER_ACPI' for consistency with the CLOCKSOURCE_OF_DECLARE => TIMER_OF_DECLARE change. Signed-off-by: Daniel Lezcano Reviewed-by: Linus Walleij --- drivers/clocksource/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 90f062e..4ba230d 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -5,7 +5,7 @@ config TIMER_OF bool select TIMER_PROBE -config CLKSRC_ACPI +config TIMER_ACPI bool select TIMER_PROBE @@ -310,7 +310,7 @@ config ARC_TIMERS_64BIT config ARM_ARCH_TIMER bool select TIMER_OF if OF - select CLKSRC_ACPI if ACPI + select TIMER_ACPI if ACPI config ARM_ARCH_TIMER_EVTSTREAM bool "Enable ARM architected timer event stream generation by default" From patchwork Wed Jun 14 12:39:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105509 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp272657qgd; Wed, 14 Jun 2017 05:44:13 -0700 (PDT) X-Received: by 10.84.239.23 with SMTP id w23mr503572plk.73.1497444253002; Wed, 14 Jun 2017 05:44:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497444252; cv=none; d=google.com; s=arc-20160816; b=Kqla+zoKtYYY26bQSOHPuZIJIBG7zIi8/bGm18JR/0dHgqqqCGkspC3Z4qUPwXNfVm 3x+1OWLE5hMO4U5WT9dOYIcDBl5LM+igqEgdp4irDgsnwd/i6pcXIrxyBGzGJmSiIaqn FhiGZlwkOXO+wuy/GF92LEd3+WActCjPugichJAGx7P/X04CSleAwSKJ8PE5BKzxQ6N2 +/30V3PqQCVzWOShavDSWySL8OTx7XBc97sek+DwWPZUcv/GkUvASRsXKqRTghn/iSkv j15FzVdK0wICSdtsxspfzvYUtfP7uGNsoeKa9oq/sGi8Pk8uMOQ7a/T8xg8W6331ux5z Xsgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=ANWbkGW8HLJDmwyDOEb8Tf0vPFF0kvlr95Ip6PymI58=; b=j7zElijAKmZH+7e1+A+LvdVb0Z1SEgkG6A9gEYcjQ2uXYpMoDsB5OdrtoJmnof8tHj xZ4pozC5hDmK90Mfsd9ViB9gOah/IenV9w2Vana5DBwinCO06nKeRCq/hLpGX+h8rF9N F66EyAOxuCKCdtIGkUMBwHSbPQFMwGE9q1lCUsaMLdJV/eo4pE6IRMrgkjg4Vdoar0r1 nuuCCTt+j2blLgSDjVvQJ/qc1tbdDExw9WyAuJDtL4jwFUKiGp43h1q95nYl0xPFXoUK siwUIuQTkh/PGP7oPjBkfC3uH0XR7C6TzW2+iHKPga+zpdaWFc0O+SjdI6fUhwy31EpB ZRug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=EJ8Glsbj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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In order to prevent conflicts for the next merge window, a temporary alias has been added which will be removed later. Cc: Arnd Bergman Signed-off-by: Daniel Lezcano --- include/linux/clocksource.h | 3 +++ 1 file changed, 3 insertions(+) -- 2.7.4 diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h index c48ceef..d92bd83 100644 --- a/include/linux/clocksource.h +++ b/include/linux/clocksource.h @@ -252,6 +252,9 @@ extern int clocksource_i8253_init(void); #define TIMER_OF_DECLARE(name, compat, fn) \ OF_DECLARE_1_RET(timer, name, compat, fn) +#define CLOCKSOURCE_OF_DECLARE(name, compat, fn) \ + TIMER_OF_DECLARE(name, compat, fn) + #ifdef CONFIG_TIMER_PROBE extern void timer_probe(void); #else From patchwork Wed Jun 14 12:39:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105504 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp272028qgd; Wed, 14 Jun 2017 05:42:37 -0700 (PDT) X-Received: by 10.99.115.79 with SMTP id d15mr439096pgn.140.1497444156977; Wed, 14 Jun 2017 05:42:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497444156; cv=none; d=google.com; s=arc-20160816; b=CuG5puXeU7YdtA+QwfM0Nn7zLtp8QGvU1P5uXr8jnPMpwdU35xBtjdnphkBLjYsNg3 5+U5MtbQ38YJskaurBWG10b53hCH4cpRzPv9RazS6N8NFuRl/2zg1tpWWqUXK/f9KS5w 6H8X+lMNYZbHrWV2+gy3DKX42hNJ1BXTMCh4rrU9hCouUW48USZqZPGNLWOKaVrGE8xr rwfif8sYtW0ZiX6xdHalTgjiczN5PGVlG5w63eeZPUcjLgKODRljlNrvIIbwjz/0NYEm JEdJv3ET0egIn5bsgCkQf7ubLwOOPo8f/yu/kYJPS9uVxsOT8Y1a4TCNtI62oK3NXz2Y SIIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=b/9MO8ZqLbbdZKGCC9VZ6jGcYCWTa/tTnTNxXzkeAaI=; b=C7sFGIlsQ6vtRo7Drmsj2kgKWyue3qHWm4pYNjDax50593QE1X+RtkJnBJE1R3Ew/W Tvf+NYLgkUD5LzDd1/vhdYb9Wks9Um2doBa4qycHSd0Dz27l25d/p0U3dhnQ2LhDMt17 A9kq9uJm7+ArXcYPeDK8FZjNhbjaZTD9dElAFznK4JPWe2Rw0y56lsKVMY3youfeOqiF FXBxaD79qT/s61tJaVxQl/yAu+QPyZIvWSwHTBwrw3IArveagrRPREdJrvf7kfgqqCpZ RHWqjpmCmLv76Pl8UW9CmJA6BQWPRQUgRbxyPM21ZjrkFWXNMkrQZaXi2nzReypI5Opf /TmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=jW54Wi4+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d15si617600plj.367.2017.06.14.05.42.36; Wed, 14 Jun 2017 05:42:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=jW54Wi4+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752746AbdFNMmY (ORCPT + 25 others); Wed, 14 Jun 2017 08:42:24 -0400 Received: from mail-wr0-f178.google.com ([209.85.128.178]:35709 "EHLO mail-wr0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752667AbdFNMmS (ORCPT ); Wed, 14 Jun 2017 08:42:18 -0400 Received: by mail-wr0-f178.google.com with SMTP id q97so188269034wrb.2 for ; Wed, 14 Jun 2017 05:42:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b/9MO8ZqLbbdZKGCC9VZ6jGcYCWTa/tTnTNxXzkeAaI=; b=jW54Wi4+0CrBoymDUMcjYU0wPD+dmo3E3fOvIsj2ydqFOogrZANL9ZeV1XnUG/Yx0M MwAIFdwEqwVpARSWhS7lCS6lKe9P//1/mHwW9a189quSqGl9QgMJwsoA5DtOphyLZsoY Ce45jdGFbmaY93DB8NKUjVmalN7WJwGJGoUfY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b/9MO8ZqLbbdZKGCC9VZ6jGcYCWTa/tTnTNxXzkeAaI=; b=k4P851hoE3SOCQN8GKbkYgh4r5EMw+/g/zBr1oNbvXcHNAMCnLHqayjCNPhinQQE02 0NXpruaZdP13Yk6UYsXj4eR43o8NTXtfnkggcMSvctiQ+hl0Lt/QaEHjKYMBxJX9ZmYe PRkUcRuRW9S+cMcgCtiLsj+wtJ9BkmJr1eamfGxRyxGRs354bEeWKEv658oXSbdltpgX od386Tz2rztYPNECaSGhjyEICkbvRIPlrqfZVstweH9TRtA6iKXYEVZEFVxEIO2Eh9q0 xYsLStKfVGdIrs0iTih1+uPKeXokysB6T9nezoULhgoHw8Wm3HejP3En9H/oVhoQrRPs 9UnQ== X-Gm-Message-State: AKS2vOwLi4AEkf/+hxThWyOvSFollG3xIQg0Vkbi0/iZQC1G4AKGdMfC 5mU75zje1CyoLeUR X-Received: by 10.223.171.77 with SMTP id r13mr357516wrc.83.1497444132035; Wed, 14 Jun 2017 05:42:12 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:19a:b336:54d7:46e9]) by smtp.gmail.com with ESMTPSA id 80sm1457015wmg.17.2017.06.14.05.42.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 05:42:11 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Linus Walleij , Andrew Jeffery , Joel Stanley , Jonas Jensen Subject: [PATCH 19/23] clocksource/drivers/fttmr010: Optimize sched_clock() Date: Wed, 14 Jun 2017 14:39:40 +0200 Message-Id: <1497443984-12371-19-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Linus Walleij The sched_clock() call should be really fast so we want to avoid an extra if() clause on the read path if possible. Implement two sched_clock_read() functions, one if the timer counts up and one if it counts down. Incidentally this also mirrors how clocksource_mmio_init() works and make things simple and easy to understand. Suggested-by: Daniel Lezcano Cc: Andrew Jeffery Cc: Joel Stanley Cc: Jonas Jensen Signed-off-by: Linus Walleij Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-fttmr010.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index a21020c..b56d7bd 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -91,13 +91,16 @@ static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt) return container_of(evt, struct fttmr010, clkevt); } -static u64 notrace fttmr010_read_sched_clock(void) +static u64 notrace fttmr010_read_sched_clock_up(void) { - if (local_fttmr->count_down) - return ~readl(local_fttmr->base + TIMER2_COUNT); return readl(local_fttmr->base + TIMER2_COUNT); } +static u64 notrace fttmr010_read_sched_clock_down(void) +{ + return ~readl(local_fttmr->base + TIMER2_COUNT); +} + static int fttmr010_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { @@ -302,15 +305,17 @@ static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed) "FTTMR010-TIMER2", fttmr010->tick_rate, 300, 32, clocksource_mmio_readl_down); + sched_clock_register(fttmr010_read_sched_clock_down, 32, + fttmr010->tick_rate); } else { writel(0, fttmr010->base + TIMER2_LOAD); clocksource_mmio_init(fttmr010->base + TIMER2_COUNT, "FTTMR010-TIMER2", fttmr010->tick_rate, 300, 32, clocksource_mmio_readl_up); + sched_clock_register(fttmr010_read_sched_clock_up, 32, + fttmr010->tick_rate); } - sched_clock_register(fttmr010_read_sched_clock, 32, - fttmr010->tick_rate); /* * Setup clockevent timer (interrupt-driven) on timer 1. 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[209.132.180.67]) by mx.google.com with ESMTP id r6si629373plj.223.2017.06.14.05.42.21; Wed, 14 Jun 2017 05:42:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=UniCp7k1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752673AbdFNMmS (ORCPT + 25 others); Wed, 14 Jun 2017 08:42:18 -0400 Received: from mail-wr0-f176.google.com ([209.85.128.176]:35732 "EHLO mail-wr0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752320AbdFNMmO (ORCPT ); Wed, 14 Jun 2017 08:42:14 -0400 Received: by mail-wr0-f176.google.com with SMTP id q97so188269949wrb.2 for ; Wed, 14 Jun 2017 05:42:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=K1xWgYiNDJXhWeMiZ86uYArKySkZl5+SdjrhjZsMJno=; b=UniCp7k1RYWgSkHGYipOr3pgIYqTvkhQ8yFCsjdMUzwlhisskAy17nvlZbGLNgMHtR SzTxdImPEYQ2lCR2DQJ6PEZLkBOjmUHHmudZMW66fFhmRcejdJ7E5fCvYnv3zi9poaz5 BUCuWP0thfEwLpdBufqLLVkaLVyh7Y06SAPD0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=K1xWgYiNDJXhWeMiZ86uYArKySkZl5+SdjrhjZsMJno=; b=gRPVNeDby+RWhjDI49N7VQGZ6BN6WOvynUxgt4DhTYm6tsgKNrPfHb/2bqep/ShysU 7DmJfznv3TGjbRqGfAK5PINM+/vhMj7WWo1h/V9/8e2K0EB+i9uVSb55TpGTXvZU+4vZ U1MaZHb/vBbwCxFCkwy/di3IpEgwwA/Wg6XmdM1MpBNAFWhc2PdLdt+wpXCrdBomOdNp i1cr8CbKv+1Wu3/mHmGBu0Qtu5JlTT+gMlqldQPZSvEPWtwZlFihna8oOBEXOsOBqGMw fnrW5rNC80jy85QFpA4fi8BHlTZN2FyH95MUtJ1BH+xZNW47sw6SL37zKyIF73ByAX9D XCrg== X-Gm-Message-State: AKS2vOzwvbLm4jxrJbJUuyy6W2J+6sbtJ/zV/aFWGU9WJcyGixvsAeKW /5auPNrvPEyKSd8E X-Received: by 10.223.179.86 with SMTP id k22mr389732wrd.5.1497444133367; Wed, 14 Jun 2017 05:42:13 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:19a:b336:54d7:46e9]) by smtp.gmail.com with ESMTPSA id 80sm1457015wmg.17.2017.06.14.05.42.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 05:42:12 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Alexandre Belloni , Nicolas Ferre , linux-arm-kernel@lists.infradead.org (moderated list:ATMEL Timer Count...) Subject: [PATCH 20/23] clocksource/drivers/tcb_clksrc: Save timer context on suspend/resume Date: Wed, 14 Jun 2017 14:39:41 +0200 Message-Id: <1497443984-12371-20-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alexandre Belloni On sama5d2, power to the core may be cut while entering suspend mode. It is necessary to save and restore the TCB registers. Signed-off-by: Alexandre Belloni Signed-off-by: Daniel Lezcano --- drivers/clocksource/tcb_clksrc.c | 51 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c index d4ca996..828729c 100644 --- a/drivers/clocksource/tcb_clksrc.c +++ b/drivers/clocksource/tcb_clksrc.c @@ -9,6 +9,7 @@ #include #include #include +#include #include @@ -40,6 +41,14 @@ */ static void __iomem *tcaddr; +static struct +{ + u32 cmr; + u32 imr; + u32 rc; + bool clken; +} tcb_cache[3]; +static u32 bmr_cache; static u64 tc_get_cycles(struct clocksource *cs) { @@ -61,12 +70,54 @@ static u64 tc_get_cycles32(struct clocksource *cs) return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV)); } +void tc_clksrc_suspend(struct clocksource *cs) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) { + tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR)); + tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR)); + tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC)); + tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) & + ATMEL_TC_CLKSTA); + } + + bmr_cache = readl(tcaddr + ATMEL_TC_BMR); +} + +void tc_clksrc_resume(struct clocksource *cs) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) { + /* Restore registers for the channel, RA and RB are not used */ + writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR)); + writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC)); + writel(0, tcaddr + ATMEL_TC_REG(i, RA)); + writel(0, tcaddr + ATMEL_TC_REG(i, RB)); + /* Disable all the interrupts */ + writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR)); + /* Reenable interrupts that were enabled before suspending */ + writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER)); + /* Start the clock if it was used */ + if (tcb_cache[i].clken) + writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR)); + } + + /* Dual channel, chain channels */ + writel(bmr_cache, tcaddr + ATMEL_TC_BMR); + /* Finally, trigger all the channels*/ + writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR); +} + static struct clocksource clksrc = { .name = "tcb_clksrc", .rating = 200, .read = tc_get_cycles, .mask = CLOCKSOURCE_MASK(32), .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .suspend = tc_clksrc_suspend, + .resume = tc_clksrc_resume, }; #ifdef CONFIG_GENERIC_CLOCKEVENTS From patchwork Wed Jun 14 12:39:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105506 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp272099qgd; Wed, 14 Jun 2017 05:42:49 -0700 (PDT) X-Received: by 10.99.106.66 with SMTP id f63mr443174pgc.150.1497444168950; Wed, 14 Jun 2017 05:42:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497444168; cv=none; d=google.com; s=arc-20160816; b=L/YgJOnzfxYbJ+b8FDh9E4BAbZphovPdyHRIqMl2/cDZ0veh/lGOhvOjf/oMJTHRTx TsCQT53UQ/6FYmQGFL7TTgSPiiWrUpNQoH5C2ziZyofgGsg/tFS3DJafStcHlOO2wOZZ 3GaDl0mhaONnqShft0uVIsOUShjtYtWbLAg8ouocajouM6udGkjsUddTIY5nt5ZRok7u 3VWOSHM+szKVrSLzIR77gPlozGwMZxr9NBYvqEIYigEjIariiL1Hkz81l3LvedGfCQcB UmUb0TSv3rFYj5mi3oC6GPqfwV6DQheqTsjEsNpakyFy5EL9D07Uy44imkg/GEOJCA/b ARng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=kO3i/55MFiacvbcrJreAhG49SCOWb5JhLIVbkuWAjmE=; b=uw+mzFV4Z7rYbF05wvzwA1we68pbLJP8l39ituoJme4GoOLbF61QFetWtypfskXgFQ X0HuSqsEWOLAcjiP3m0zjVvpXTxYnDnl3MCmLHXZPpDN40xmLFs+Gggc9fHHIYvW2HNC bPNr4IOOnt1Qe2dBUmB0qBcicr0C7szIUBGsUSTS884tLW8b3mIhBkgJZkzFK6XK+nfT Ds4weo1Q9rrD71s4osQv/1RBpsG2mCfEUOkCHG0p4asXrMoKMeGGuMG85h8sxdaVhpQK 4YkpR78Zz6QVKLcI3M0hQhKECmKmmrABLgenfNlFSkX+AdaUa1YjohilJcVTI5yw56UG j/Zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=Wnci2PeV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e12si600533pfb.358.2017.06.14.05.42.48; Wed, 14 Jun 2017 05:42:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=Wnci2PeV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752720AbdFNMmW (ORCPT + 25 others); Wed, 14 Jun 2017 08:42:22 -0400 Received: from mail-wr0-f169.google.com ([209.85.128.169]:35780 "EHLO mail-wr0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752660AbdFNMmS (ORCPT ); Wed, 14 Jun 2017 08:42:18 -0400 Received: by mail-wr0-f169.google.com with SMTP id q97so188272123wrb.2 for ; Wed, 14 Jun 2017 05:42:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kO3i/55MFiacvbcrJreAhG49SCOWb5JhLIVbkuWAjmE=; b=Wnci2PeVfPqRGiiOw7eJRaetXW+BHZgS1qAovPfD55So4c8xJbWxzcr9at4Yd9rGX2 wJxZG2WAWbFE4cXunxEyXv2ydL/pyTIOrHK7fjTV8b9yQ3x4juKtg6vaa4z+ykzOAaYv wRe7OAUg5y3PGHGniFy6BkoXHUaFswGh1NrVQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kO3i/55MFiacvbcrJreAhG49SCOWb5JhLIVbkuWAjmE=; b=SrGtotKoKacPu3vh1XIcMzprYEmCSR4K3CLaDDKoG0MGNcszWvpXzy3SJG5G0opF/n F1wOkzJtJORaP3BVgy0q+YnLdgwaWFXErDL7AYZMnF78iVebBefOU06w6/ViXvCJ9h12 9QcElOWhdVWly5cmauPBED4tG0i9Wln1iqD7yMyWmTNuzpQrkzHJsbdFh1pucPeT+otG OuRPyih8p+H/mwdrb0FYwnV8IctBUhUmJM3sF+MUCAq25WE58NZbvo0tq24TbDx1bHNu wG9AzMmc9TCkWJ5C+X8bc/rPevkLHibRxBTaYcLXk4Fkkci/5XwdYX9rX4/xBLTRbk7D xBmA== X-Gm-Message-State: AKS2vOwEQQbDJXqA4WmCGjItIwO5hhOwzulgHxDyIIEc0nfdAyy+AbBZ svVDAhXhnkxJnI/pQxNZ+OMS X-Received: by 10.223.162.215 with SMTP id t23mr344661wra.193.1497444136545; Wed, 14 Jun 2017 05:42:16 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:19a:b336:54d7:46e9]) by smtp.gmail.com with ESMTPSA id 80sm1457015wmg.17.2017.06.14.05.42.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 05:42:15 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org Subject: [PATCH 21/23] clocksource/drivers: Add timer-of common init routine Date: Wed, 14 Jun 2017 14:39:42 +0200 Message-Id: <1497443984-12371-21-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The different drivers are all using the same pattern when initializing. 1. Get the base address 2. Get the irq number 3. Get the clock 4. Prepare and enable the clock 5. Get the rate 6. Request an interrupt Instead of repeating again and again these steps in all the drivers, let's provide a common init routine to give the opportunity to factor all of them out. We can expect a significant kernel size improvement when the common routine will be used in all the drivers. Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 1 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-of.c | 172 +++++++++++++++++++++++++++++++++++++++++ drivers/clocksource/timer-of.h | 69 +++++++++++++++++ 4 files changed, 243 insertions(+) create mode 100644 drivers/clocksource/timer-of.c create mode 100644 drivers/clocksource/timer-of.h -- 2.7.4 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 4ba230d..4be163b 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -3,6 +3,7 @@ menu "Clock Source drivers" config TIMER_OF bool + depends on GENERIC_CLOCKEVENTS select TIMER_PROBE config TIMER_ACPI diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index ec55921..72bfd00 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -1,3 +1,4 @@ +obj-$(CONFIG_TIMER_OF) += timer-of.o obj-$(CONFIG_TIMER_PROBE) += timer-probe.o obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o diff --git a/drivers/clocksource/timer-of.c b/drivers/clocksource/timer-of.c new file mode 100644 index 0000000..be1dbee --- /dev/null +++ b/drivers/clocksource/timer-of.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2017, Linaro Ltd. All rights reserved. + * + * Author: Daniel Lezcano + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#include +#include +#include +#include +#include +#include + +#include "timer-of.h" + +static __init void timer_irq_exit(struct of_timer_irq *of_irq) +{ + struct timer_of *to = container_of(of_irq, struct timer_of, of_irq); + + struct clock_event_device *clkevt = &to->clkevt; + + of_irq->percpu ? free_percpu_irq(of_irq->irq, clkevt) : + free_irq(of_irq->irq, clkevt); +} + +static __init int timer_irq_init(struct device_node *np, + struct of_timer_irq *of_irq) +{ + int ret; + struct timer_of *to = container_of(of_irq, struct timer_of, of_irq); + struct clock_event_device *clkevt = &to->clkevt; + + of_irq->irq = of_irq->name ? of_irq_get_byname(np, of_irq->name): + irq_of_parse_and_map(np, of_irq->index); + if (!of_irq->irq) { + pr_err("Failed to map interrupt for %s\n", np->full_name); + return -EINVAL; + } + + ret = of_irq->percpu ? + request_percpu_irq(of_irq->irq, of_irq->handler, + np->full_name, clkevt) : + request_irq(of_irq->irq, of_irq->handler, + of_irq->flags ? of_irq->flags : IRQF_TIMER, + np->full_name, clkevt); + if (ret) { + pr_err("Failed to request irq %d for %s\n", of_irq->irq, + np->full_name); + return ret; + } + + clkevt->irq = of_irq->irq; + + return 0; +} + +static __init void timer_clk_exit(struct of_timer_clk *of_clk) +{ + of_clk->rate = 0; + clk_disable_unprepare(of_clk->clk); + clk_put(of_clk->clk); +} + +static __init int timer_clk_init(struct device_node *np, + struct of_timer_clk *of_clk) +{ + int ret; + + of_clk->clk = of_clk->name ? of_clk_get_by_name(np, of_clk->name) : + of_clk_get(np, of_clk->index); + if (IS_ERR(of_clk->clk)) { + pr_err("Failed to get clock for %s\n", np->full_name); + return PTR_ERR(of_clk->clk); + } + + ret = clk_prepare_enable(of_clk->clk); + if (ret) { + pr_err("Failed for enable clock for %s\n", np->full_name); + goto out_clk_put; + } + + of_clk->rate = clk_get_rate(of_clk->clk); + if (!of_clk->rate) { + ret = -EINVAL; + pr_err("Failed to get clock rate for %s\n", np->full_name); + goto out_clk_disable; + } + + of_clk->period = DIV_ROUND_UP(of_clk->rate, HZ); +out: + return ret; + +out_clk_disable: + clk_disable_unprepare(of_clk->clk); +out_clk_put: + clk_put(of_clk->clk); + + goto out; +} + +static __init void timer_base_exit(struct of_timer_base *of_base) +{ + iounmap(of_base->base); +} + +static __init int timer_base_init(struct device_node *np, + struct of_timer_base *of_base) +{ + const char *name = of_base->name ? of_base->name : np->full_name; + + of_base->base = of_io_request_and_map(np, of_base->index, name); + if (of_base->base) { + pr_err("Failed to iomap (%s)\n", name); + return -ENXIO; + } + + return 0; +} + +int __init timer_of_init(struct device_node *np, struct timer_of *to) +{ + int ret; + int flags = 0; + + if (to->flags & TIMER_OF_BASE) { + ret = timer_base_init(np, &to->of_base); + if (ret) + goto out_fail; + flags |= TIMER_OF_BASE; + } + + if (to->flags & TIMER_OF_CLOCK) { + ret = timer_clk_init(np, &to->of_clk); + if (ret) + goto out_fail; + flags |= TIMER_OF_CLOCK; + } + + if (to->flags & TIMER_OF_IRQ) { + ret = timer_irq_init(np, &to->of_irq); + if (ret) + goto out_fail; + flags |= TIMER_OF_IRQ; + } + + if (!to->clkevt.name) + to->clkevt.name = np->name; +out: + return ret; + +out_fail: + if (flags & TIMER_OF_IRQ) + timer_irq_exit(&to->of_irq); + + if (flags & TIMER_OF_CLOCK) + timer_clk_exit(&to->of_clk); + + if (flags & TIMER_OF_BASE) + timer_base_exit(&to->of_base); + goto out; +} diff --git a/drivers/clocksource/timer-of.h b/drivers/clocksource/timer-of.h new file mode 100644 index 0000000..e0d7272 --- /dev/null +++ b/drivers/clocksource/timer-of.h @@ -0,0 +1,69 @@ +#ifndef __TIMER_OF_H__ +#define __TIMER_OF_H__ + +#include + +#define TIMER_OF_BASE 0x1 +#define TIMER_OF_CLOCK 0x2 +#define TIMER_OF_IRQ 0x4 + +struct of_timer_irq { + int irq; + int index; + int percpu; + const char *name; + unsigned long flags; + irq_handler_t handler; +}; + +struct of_timer_base { + void __iomem *base; + const char *name; + int index; +}; + +struct of_timer_clk { + struct clk *clk; + const char *name; + int index; + unsigned long rate; + unsigned long period; +}; + +struct timer_of { + unsigned int flags; + struct clock_event_device clkevt; + struct of_timer_base of_base; + struct of_timer_irq of_irq; + struct of_timer_clk of_clk; + void *private_data; +}; + +static inline struct timer_of *to_timer_of(struct clock_event_device *clkevt) +{ + return container_of(clkevt, struct timer_of, clkevt); +} + +static inline void __iomem *timer_of_base(struct timer_of *to) +{ + return to->of_base.base; +} + +static inline int timer_of_irq(struct timer_of *to) +{ + return to->of_irq.irq; +} + +static inline unsigned long timer_of_rate(struct timer_of *to) +{ + return to->of_clk.rate; +} + +static inline unsigned long timer_of_period(struct timer_of *to) +{ + return to->of_clk.period; +} + +extern int __init timer_of_init(struct device_node *np, + struct timer_of *to); +#endif From patchwork Wed Jun 14 12:39:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105508 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp272570qgd; Wed, 14 Jun 2017 05:43:57 -0700 (PDT) X-Received: by 10.84.233.137 with SMTP id l9mr480088plk.215.1497444237077; Wed, 14 Jun 2017 05:43:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497444237; cv=none; d=google.com; s=arc-20160816; b=URBTF6aU9b7+ubij87U+qWaag673bnJsDh/1qejNsBrZmo6KGY0LvxsVvzP+rU9hFW EKKC2TJJJuwUyHOXGMwBy/8lTRfz/vQGMmM/Dx9d/DqXWX25U70JPyjhwczzLnrTLPP8 5TuJu7GUK3cDKopX57kVyMVNrqzahEemKDjej67Ek3YIH0sLGK+65fIQl03Y8Na80Xeu UBMbuDAox9W5eKQ0f0lbBPp3T2Nvk738D2ipcG9vP7m2ThXOkb/q4dAAFvLvT3zwXIb8 lUNBxUd9ySQ6wJN20AT+pd8Kj/EjEHDaEXwbtwaAgOGfAhBVG/JgbqpMBgWd0UysJSZY +Jmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=L1JOCtRxcezaRjvRMc9tbguUKmcVE4v2HTgpdejmP+o=; b=wqvInTUS8EKaEKOQpIGBLXubZJuL0Pqtkt5ZWqfyrd5/2sEopkY05DtHD+sZaYMqpv W0RFqASKOIk88dYnxITaulT3M2Xt76yxe7XMT4MCb5+A/X3CmOYo48f5Jjzm4+TE1/6u fNKkAI044KIXKHBN49Q+jx6QAFKAC8pbTV93+WG81ulzEyVornddmXFlCCdJDs3MfSlx IdcdRTgzNCxy1V6u7oNEi84LBtvcJSGiJ3ZhQT/E4DMKQQLN3fAAG7w8HJ8m4oJMGrpf NeVZRqhF8M1K6z0bMX4AFVuGG9nlk2ddMFC/G4ueiPMyAnhhPpK1DeVzTAngrMJRB0gz 4VmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=cdIylV+q; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p25si422624pge.487.2017.06.14.05.43.56; Wed, 14 Jun 2017 05:43:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=cdIylV+q; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752790AbdFNMnj (ORCPT + 25 others); Wed, 14 Jun 2017 08:43:39 -0400 Received: from mail-wr0-f170.google.com ([209.85.128.170]:34572 "EHLO mail-wr0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752167AbdFNMmT (ORCPT ); Wed, 14 Jun 2017 08:42:19 -0400 Received: by mail-wr0-f170.google.com with SMTP id 77so40897783wrb.1 for ; Wed, 14 Jun 2017 05:42:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=L1JOCtRxcezaRjvRMc9tbguUKmcVE4v2HTgpdejmP+o=; b=cdIylV+qWmlQj4zBJDHRlY85+CZgUOhb4MOWWoYLUyu/BttZySsWkp/CGkLYu63GjF GIvYu0S02DNGL6WSs/PyjBRyVUbQ19mHTZoo7G4b8ky90V+DSIJGaoyAJSSdcjI5uKmL t7XJavL9Z+RTwCCAjFNSvpi61qAjcolWuu3zs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=L1JOCtRxcezaRjvRMc9tbguUKmcVE4v2HTgpdejmP+o=; b=rewmecGw4wIKN+wL2CosT238CzAHlwRd/CrydoYi4T9YYZAyLit4Oa3jJs2GUufkCv TCy5TvPGf2p1KOmzN/wU/WJHNcxgrdnjgZdrDQgOHIh4plzFLc+Nowq7MRTQNmAPGqUf 3DbiO2Crzqec2O+tHOLDgyUuQdS4zxrZWydLRFBRuUIbEe91DdAKxCFI7vhUhPcSkPA1 tdJFzI1b1+0RDDKH82WImHAU/235sO+EWUUFLJK41m9RWspMwWYMZQF3lIDQIUx2sXfh cNJtAZTZUlPF8dgjm6S96UUv75+7tbo9UKgb0moaQPI8L4WxotnVwgFfQzTIJFo30f52 WslQ== X-Gm-Message-State: AKS2vOxMhCu3Pzg3FzsMzeJKBzPJ1BXN5NbzZiJuJuPpfY69W7OCvJWX ppZ81aHDa7DJPb5d X-Received: by 10.223.133.99 with SMTP id 90mr414949wrh.44.1497444138043; Wed, 14 Jun 2017 05:42:18 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:19a:b336:54d7:46e9]) by smtp.gmail.com with ESMTPSA id 80sm1457015wmg.17.2017.06.14.05.42.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 05:42:17 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Linus Walleij , Andrew Jeffery , Joel Stanley , Jonas Jensen Subject: [PATCH 22/23] clocksource/drivers/fttmr010: Implement delay timer Date: Wed, 14 Jun 2017 14:39:43 +0200 Message-Id: <1497443984-12371-22-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Linus Walleij This timer is often used on the ARM architecture, so as with so many siblings, we can implement delay timers, removing the need for the system to calibrate jiffys at boot, and potentially handling CPU frequency scaling on targets. We cannot just protect the Kconfig with a "depends on ARM" because it is already known that different architectures are using Faraday IP blocks, so it is better to make things open-ended and use Result on boot dmesg: Switching to timer-based delay loop, resolution 40n Calibrating delay loop (skipped), value calculated using timer frequency.. 50.00 BogoMIPS (lpj=250000) This is accurately the timer frequency, 250MHz on the APB bus. Cc: Andrew Jeffery Cc: Joel Stanley Cc: Jonas Jensen Signed-off-by: Linus Walleij Tested-by: Jonas Jensen Tested-by: Andrew Jeffery Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-fttmr010.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index b56d7bd..0093704 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -17,6 +17,7 @@ #include #include #include +#include /* * Register definitions for the timers @@ -81,9 +82,15 @@ struct fttmr010 { bool count_down; u32 t1_enable_val; struct clock_event_device clkevt; +#ifdef CONFIG_ARM + struct delay_timer delay_timer; +#endif }; -/* A local singleton used by sched_clock, which is stateless */ +/* + * A local singleton used by sched_clock and delay timer reads, which are + * fast and stateless + */ static struct fttmr010 *local_fttmr; static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt) @@ -101,6 +108,20 @@ static u64 notrace fttmr010_read_sched_clock_down(void) return ~readl(local_fttmr->base + TIMER2_COUNT); } +#ifdef CONFIG_ARM + +static unsigned long fttmr010_read_current_timer_up(void) +{ + return readl(local_fttmr->base + TIMER2_COUNT); +} + +static unsigned long fttmr010_read_current_timer_down(void) +{ + return ~readl(local_fttmr->base + TIMER2_COUNT); +} + +#endif + static int fttmr010_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { @@ -347,6 +368,18 @@ static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed) fttmr010->tick_rate, 1, 0xffffffff); +#ifdef CONFIG_ARM + /* Also use this timer for delays */ + if (fttmr010->count_down) + fttmr010->delay_timer.read_current_timer = + fttmr010_read_current_timer_down; + else + fttmr010->delay_timer.read_current_timer = + fttmr010_read_current_timer_up; + fttmr010->delay_timer.freq = fttmr010->tick_rate; + register_current_timer_delay(&fttmr010->delay_timer); +#endif + return 0; out_unmap: From patchwork Wed Jun 14 12:39:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 105507 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp272260qgd; Wed, 14 Jun 2017 05:43:11 -0700 (PDT) X-Received: by 10.99.50.135 with SMTP id y129mr447789pgy.238.1497444191661; Wed, 14 Jun 2017 05:43:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497444191; cv=none; d=google.com; s=arc-20160816; b=zPlz/gcpt4MQwdDQ6DwxZ4kdNe8bsAg0wZELSqeTPHFpTjNHsCxMYRnCy1jLNVaSp5 697EsbPNYP3Pu4n9rBMQhNWMz9MQQv80m9YhYm8eP1wlv25oAFPlRMoXFNcMey8b3i/g 1Qh7CKVP6aH5ACPkUVsdOWD+jljjawXK+E/Gl0/G4NxNV5mgDvhYKhph5lMfpKoEVSvv uUTsCVX8aId2jDMI52g4xD5uVIL5sdER61JSXR83xNMCQKl/WrG8SfgKZrKCYRNvazO5 PQ/T271gigyhgWMot/uzUzxCAT/6S71rkFS29uCyNV2UsuUiqjL8JEWBWtpuzkVClRxU KOhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=5HcXZc9cRWP5d9tLjGDE2UH9sb7Kd1xHLfGjUubEA0w=; b=oibtrf3+67AUmPrAYUO/ghBAyQCeSU7ZsNMNUsvNgokGL2jB2Sqt4wrUXhWSK3wY7j EJxIEzhE7duB2MA6N7Utla30zwI0WO4bLnBpZ9tU2Vf+FC8LIDeBLW6ujhF+CeyJQHXd 8V1l1tm0M9srP3RcNy5FVfmcYghmkiO5WrzGct6I99s313B7nfMIV6SwO5nHf+eDFmEi Y+T6Qib0TU7MYHh7cUY4X/xQ0aBYCNnaAbH2JcJSX2JUiJmyv18i3zXg7ua3/XICdrzj sByGJXDiy+9csvff+l8+WU2PJt5MOdMxcWNZLqYi3KkRroI95bIcmuLvJmhviQ8CqSgy Mmvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=iBaG5aap; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g92si631080plg.54.2017.06.14.05.43.11; Wed, 14 Jun 2017 05:43:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=iBaG5aap; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752774AbdFNMnD (ORCPT + 25 others); Wed, 14 Jun 2017 08:43:03 -0400 Received: from mail-wr0-f176.google.com ([209.85.128.176]:33333 "EHLO mail-wr0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752693AbdFNMmV (ORCPT ); Wed, 14 Jun 2017 08:42:21 -0400 Received: by mail-wr0-f176.google.com with SMTP id v104so175923440wrb.0 for ; Wed, 14 Jun 2017 05:42:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5HcXZc9cRWP5d9tLjGDE2UH9sb7Kd1xHLfGjUubEA0w=; b=iBaG5aaphW8fkdSbktxTHK/71jDSisc16hiymvnNfnPXSFPLMSbO2JOYkfwWI+btXW +K6FCYM9mOR2AtvrgVmqxWFFl+zHwCGwzwk+GYJXWy7erFetB7bJDXIzmyNA5iAHddXw cGXMPbY2zhkB1txGSAqeT7ngIdPXHsWVNOHmM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5HcXZc9cRWP5d9tLjGDE2UH9sb7Kd1xHLfGjUubEA0w=; b=FUk1n7TzRGI2Flqtl6BUotO5636E6SJdQWvhytM7LzaDwklrAeK6BFhAcq9N79yfnd bhBljYLrwDi8KaShCEDpqW85Q4Omcd1AKZK4zhgLfFsRfv3fWaeGKM1a5ifqc6kNmEN5 663cVhzxxcqB0Osoraf9kx4Y3dzE4zfGlRPg9sy2qdALYUsCll04ntoB9PW6MUaIEZdV I5Sh5tT8WjqyfQyeCeYGPR87U2KJg8P/A9ZXa5U47Oz+f0vgVcVWdSCKWOCFdvG1JJVD G4Oo9dcqSMrjCsHK0k7z1Yc0GMtXmrIfucMSn+PsO2duIWVTzvFHKXl9u1AKECNZ/1cT pMnw== X-Gm-Message-State: AKS2vOyqT+SI6+iDfStPFrrMhwI0/WGvfKhXteHVEYbKQQnJD0FUvMJR 9t3gXJkUruHktu5lTRK06Ivz X-Received: by 10.28.45.5 with SMTP id t5mr8532538wmt.50.1497444139377; Wed, 14 Jun 2017 05:42:19 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:19a:b336:54d7:46e9]) by smtp.gmail.com with ESMTPSA id 80sm1457015wmg.17.2017.06.14.05.42.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 05:42:18 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Linus Walleij , Andrew Jeffery , Joel Stanley , Jonas Jensen Subject: [PATCH 23/23] clocksource/drivers/fttmr010: Factor out clock read code Date: Wed, 14 Jun 2017 14:39:44 +0200 Message-Id: <1497443984-12371-23-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Linus Walleij The sched_clock() and delay timer callbacks can just call each other and we can save an #ifdef. Suggested-by: Daniel Lezcano Cc: Andrew Jeffery Cc: Joel Stanley Cc: Jonas Jensen Signed-off-by: Linus Walleij Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-fttmr010.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index 0093704..66dd909 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -98,30 +98,26 @@ static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt) return container_of(evt, struct fttmr010, clkevt); } -static u64 notrace fttmr010_read_sched_clock_up(void) +static unsigned long fttmr010_read_current_timer_up(void) { return readl(local_fttmr->base + TIMER2_COUNT); } -static u64 notrace fttmr010_read_sched_clock_down(void) +static unsigned long fttmr010_read_current_timer_down(void) { return ~readl(local_fttmr->base + TIMER2_COUNT); } -#ifdef CONFIG_ARM - -static unsigned long fttmr010_read_current_timer_up(void) +static u64 notrace fttmr010_read_sched_clock_up(void) { - return readl(local_fttmr->base + TIMER2_COUNT); + return fttmr010_read_current_timer_up(); } -static unsigned long fttmr010_read_current_timer_down(void) +static u64 notrace fttmr010_read_sched_clock_down(void) { - return ~readl(local_fttmr->base + TIMER2_COUNT); + return fttmr010_read_current_timer_down(); } -#endif - static int fttmr010_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) {