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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF0002636D.mail.protection.outlook.com (10.167.241.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7611.14 via Frontend Transport; Sun, 19 May 2024 12:41:25 +0000 Received: from SITE-L-T34-2.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Sun, 19 May 2024 07:41:23 -0500 From: Mario Limonciello To: , , CC: , , "Mario Limonciello" , Andy Shevchenko , Hans de Goede , Kieran Levin Subject: [PATCH] pinctrl: amd: Set up affinity for GPIO lines when enabling interrupt Date: Sun, 19 May 2024 07:41:09 -0500 Message-ID: <20240519124109.1523-1-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636D:EE_|MW4PR12MB6801:EE_ X-MS-Office365-Filtering-Correlation-Id: d9754e95-e617-4c6b-d08a-08dc7800ff4b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(1800799015)(376005)(82310400017)(36860700004); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2024 12:41:25.7634 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9754e95-e617-4c6b-d08a-08dc7800ff4b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6801 When a touchpad's attention interrupt is triggered on a different CPU than the GPIO controller interrupt multiple CPUs wake up the system and can cause higher power consumption than necessary for operating the touchpad. Waking up the additional CPUs is especially unnecessary as the irq_ack() callback for pinctrl-amd doesn't do anything. To solve this save the affinity of the GPIO controller interrupt when it's set up and assign that affinity to the GPIO line IRQ. Cc: Andy Shevchenko Cc: Hans de Goede Reported-by: Kieran Levin Link: https://bugzilla.kernel.org/show_bug.cgi?id=218169 Signed-off-by: Mario Limonciello --- drivers/pinctrl/pinctrl-amd.c | 18 ++++++++++++++++++ drivers/pinctrl/pinctrl-amd.h | 1 + 2 files changed, 19 insertions(+) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 7f66ec73199a..0f126caa8dfc 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -561,6 +561,21 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) return ret; } +static int amd_gpio_set_affinity(struct irq_data *data, const struct cpumask *dest, + bool force) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct amd_gpio *gpio_dev = gpiochip_get_data(gc); + + /* + * The affinity is explicitly set to the GPIO controller as amd_irq_ack() + * doesn't do anything and pinning to a different CPU is a needless wakeup. + */ + irq_data_update_effective_affinity(data, gpio_dev->base_affinity); + + return 0; +} + static void amd_irq_ack(struct irq_data *d) { /* @@ -580,6 +595,7 @@ static const struct irq_chip amd_gpio_irqchip = { .irq_set_wake = amd_gpio_irq_set_wake, .irq_eoi = amd_gpio_irq_eoi, .irq_set_type = amd_gpio_irq_set_type, + .irq_set_affinity = amd_gpio_set_affinity, /* * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event * also generates an IRQ. We need the IRQ so the irq_handler can clear @@ -1163,6 +1179,8 @@ static int amd_gpio_probe(struct platform_device *pdev) if (ret) goto out2; + gpio_dev->base_affinity = irq_get_affinity_mask(gpio_dev->irq); + platform_set_drvdata(pdev, gpio_dev); acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev); diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h index cf59089f2776..1a97c7570374 100644 --- a/drivers/pinctrl/pinctrl-amd.h +++ b/drivers/pinctrl/pinctrl-amd.h @@ -106,6 +106,7 @@ struct amd_gpio { struct platform_device *pdev; u32 *saved_regs; int irq; + const struct cpumask *base_affinity; }; /* KERNCZ configuration*/