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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 01/43] target/hppa: Move cpu_get_tb_cpu_state out of line Date: Wed, 15 May 2024 11:40:01 +0200 Message-Id: <20240515094043.82850-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 43 ++----------------------------------------- target/hppa/cpu.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 41 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index fb2e4c4a98..61f1353133 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -314,47 +314,8 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); #define TB_FLAG_PRIV_SHIFT 8 #define TB_FLAG_UNALIGN 0x400 -static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - uint32_t flags = env->psw_n * PSW_N; - - /* TB lookup assumes that PC contains the complete virtual address. - If we leave space+offset separate, we'll get ITLB misses to an - incomplete virtual address. This also means that we must separate - out current cpu privilege from the low bits of IAOQ_F. */ -#ifdef CONFIG_USER_ONLY - *pc = env->iaoq_f & -4; - *cs_base = env->iaoq_b & -4; - flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#else - /* ??? E, T, H, L, B bits need to be here, when implemented. */ - flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); - flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; - - *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), - env->iaoq_f & -4); - *cs_base = env->iasq_f; - - /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero - low 32-bits of CS_BASE. This will succeed for all direct branches, - which is the primary case we care about -- using goto_tb within a page. - Failure is indicated by a zero difference. */ - if (env->iasq_f == env->iasq_b) { - target_long diff = env->iaoq_b - env->iaoq_f; - if (diff == (int32_t)diff) { - *cs_base |= (uint32_t)diff; - } - } - if ((env->sr[4] == env->sr[5]) - & (env->sr[4] == env->sr[6]) - & (env->sr[4] == env->sr[7])) { - flags |= TB_FLAG_SR_SAME; - } -#endif - - *pflags = flags; -} +void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags); target_ulong cpu_hppa_get_psw(CPUHPPAState *env); void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 393a81988d..582036b31e 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -43,6 +43,48 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) return cpu->env.iaoq_f; } +void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags = env->psw_n * PSW_N; + + /* TB lookup assumes that PC contains the complete virtual address. + If we leave space+offset separate, we'll get ITLB misses to an + incomplete virtual address. This also means that we must separate + out current cpu privilege from the low bits of IAOQ_F. */ +#ifdef CONFIG_USER_ONLY + *pc = env->iaoq_f & -4; + *cs_base = env->iaoq_b & -4; + flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#else + /* ??? E, T, H, L, B bits need to be here, when implemented. */ + flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); + flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; + + *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), + env->iaoq_f & -4); + *cs_base = env->iasq_f; + + /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero + low 32-bits of CS_BASE. This will succeed for all direct branches, + which is the primary case we care about -- using goto_tb within a page. + Failure is indicated by a zero difference. */ + if (env->iasq_f == env->iasq_b) { + target_long diff = env->iaoq_b - env->iaoq_f; + if (diff == (int32_t)diff) { + *cs_base |= (uint32_t)diff; + } + } + if ((env->sr[4] == env->sr[5]) + & (env->sr[4] == env->sr[6]) + & (env->sr[4] == env->sr[7])) { + flags |= TB_FLAG_SR_SAME; + } +#endif + + *pflags = flags; +} + static void hppa_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { From patchwork Wed May 15 09:40:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796919 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2890375wra; Wed, 15 May 2024 02:42:38 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVeS9nuMnhJv/8K+ZRnOdesJvM7FRBIFnddZ/Jfxxq3I+H5NGSLp9F+lJPFI0wKv0K4lqYVIbeEfBov2AunxLva X-Google-Smtp-Source: AGHT+IHpkYaDW2DcURJTiUGq8jkuqbLX/W15TU8+N6p2bcsJbmNqkXpdLkwREhAY/m9BFoDqhJjg X-Received: by 2002:a05:6102:b0d:b0:47e:f719:cbd2 with SMTP id ada2fe7eead31-48077db4ab1mr15757880137.7.1715766158240; Wed, 15 May 2024 02:42:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766158; cv=none; d=google.com; s=arc-20160816; b=j8C3fYH0UPxHFcQ9oLfC0W0lNTG9cY9BZOTUPSqFdfM1uKIPGEYnSphRxxIzTGeJOy DQOEuhUXH95H8Ck4m8m35RsxYOvSoRAznbEWkkF2DZq5jRX0aH0VdobqaFDHUykyFrp4 9wqJSbed6XekZBpbKO0SGUC0rdHAgK79VN0xnsGpIes5Lv418+ocIVKpFcrsn6FFMQSk ZWNBwMIzGbPriR4s8OByNL0BecIs9xjRBrucNxhGc6am/cEkRc7NSfieyCB+Ba+AYzwj aGeaw6NPxCwhkx66Z2v5Y2sQ2GG8kxO21MZRFAZvTcKTl1MD4SsLLM6+ozuswSMdPH75 B9tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=uUppVIcVxulNFKmt5JKoE50UNp9B197FkQ2pGAAJJ2A=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=pqijuIstQiusXQhMBbKRHeIeZOnM2wfjtAGjCsQKyGUB1rUP3051lgnfeZpgLgP5Lf 3XanJfN0lk8XWACXxzq1ev0yLe6ULslgDItZg+1uWi+VvwXeTwq4xfngLpcPmG3OCxTb UIdIaMRNRphg8ujmq4BRPnM08Ire8Ck6Hv7leltczqsn8MA8/UrnwDvY3tpJxGHwY3as LTGa00zw6foro5JM4o+3RRu0nByK2BMTAP+n5qaoauzimcwNVf++IBy7uiwgyQGCyezg cEBIuGQZDD2Z+6ui1IgoRwgFeu4c+pdPwImSHjYZxYhWEFLtLERdJxuDvMECFaIUXf9X MCpg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fR4FSPp2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 02/43] target/hppa: Use hppa_form_gva_psw in hppa_cpu_get_pc Date: Wed, 15 May 2024 11:40:02 +0200 Message-Id: <20240515094043.82850-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This function is for log_pc(), which needs to produce a similar result to cpu_get_tb_cpu_state(). Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 582036b31e..be8c558014 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -38,9 +38,10 @@ static void hppa_cpu_set_pc(CPUState *cs, vaddr value) static vaddr hppa_cpu_get_pc(CPUState *cs) { - HPPACPU *cpu = HPPA_CPU(cs); + CPUHPPAState *env = cpu_env(cs); - return cpu->env.iaoq_f; + return hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), + env->iaoq_f & -4); } void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, @@ -61,8 +62,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; - *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), - env->iaoq_f & -4); + *pc = hppa_cpu_get_pc(env_cpu(env)); *cs_base = env->iasq_f; /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero From patchwork Wed May 15 09:40:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796909 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2889931wra; Wed, 15 May 2024 02:41:21 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWTd4sVDYW/TOqSYDJAuYoIG1nIr9JewmM+Bed19bTZG0YR2nDz8v6SkqKbzp35BZxXWChX/cSZZa/YnwC1mPMx X-Google-Smtp-Source: AGHT+IEQkhoCpgtHKPJK2kYbhA329QBkLXD/Trgfx4NtBbGIgEDVTQMTNAHEzr2NIrEpUgc2V1kh X-Received: by 2002:a05:620a:2145:b0:792:8e98:d03f with SMTP id af79cd13be357-792c75f4511mr1625043185a.52.1715766081206; Wed, 15 May 2024 02:41:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766081; cv=none; d=google.com; s=arc-20160816; b=CnIYA9kVN/cqpG9uaMZgrUMeWaq7r8RJuB6QOgwV51xSbZVbHz7wNQRqt5dhnsePcY vUtGcnk/6vYiSus7wJkLndR0j9caUzyNQxXcAQAvompWOrPNMUUDnubGP59fSt7mfVr+ GZjtrHQTJBB/cAHVTmJu3reZBaJA8lQksmnrN8TYUCRtDNbaV+80TRo2tJ4GIRouhRuB v/0Vp/mdecbEg0ZqNmlCVOGxRJVemJDpvOZSh3SRvHoBJ82B5ny5hRLiwCwlOWoPHJOm MKBxDRArxCm3oO0CR3lv7CedVJpWPOSIEVkeu5yRV96O5iBhLAtlDN8udy9nXYDD9t47 AV4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9BrG3Zn76z7rLtlJmzfLPoC6MrTK5dndaUipWNrjLnI=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=w9B6nG9XoIPGhg4YSV7WxYDBoLjG2Vs6i8zzH3vtEgOn3eRMdurWyu1r80fwzLWwI/ tJRH2PXnZf1HW+7dBshLhSwM93sqMvDuuTMA2p3sn+tZo4ND3Pwr2cRNdp+swd1wEhav 4eg/oIU7U/LUAs3d47tSFBrvnZ+Hh50xDzeLYYLtFzeI8Cdc+vob0mPoGE49m9EUeORY nVqRs2SVmUeSnH2INNz1D2MAZR1ebYVP3k2VUuWwMHqmDEeE+5mgQf9kDK0ApTk958g9 5hHiwuDX/CIO3nVzYx4uktywqHPoqi+rdJ1jZq+DWuwyV8JxZyOQ7/sFUZjnzuoYh5Jh Gl4w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vOH3ASc2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 03/43] target/hppa: Move constant destination check into use_goto_tb Date: Wed, 15 May 2024 11:40:03 +0200 Message-Id: <20240515094043.82850-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22e; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Share this check between gen_goto_tb and hppa_tr_translate_insn. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6d45611888..398803981c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -662,9 +662,10 @@ static bool gen_illegal(DisasContext *ctx) } while (0) #endif -static bool use_goto_tb(DisasContext *ctx, uint64_t dest) +static bool use_goto_tb(DisasContext *ctx, uint64_t bofs, uint64_t nofs) { - return translator_use_goto_tb(&ctx->base, dest); + return (bofs != -1 && nofs != -1 && + translator_use_goto_tb(&ctx->base, bofs)); } /* If the next insn is to be nullified, and it's on the same page, @@ -678,16 +679,16 @@ static bool use_nullify_skip(DisasContext *ctx) } static void gen_goto_tb(DisasContext *ctx, int which, - uint64_t f, uint64_t b) + uint64_t b, uint64_t n) { - if (f != -1 && b != -1 && use_goto_tb(ctx, f)) { + if (use_goto_tb(ctx, b, n)) { tcg_gen_goto_tb(which); - copy_iaoq_entry(ctx, cpu_iaoq_f, f, NULL); - copy_iaoq_entry(ctx, cpu_iaoq_b, b, NULL); + copy_iaoq_entry(ctx, cpu_iaoq_f, b, NULL); + copy_iaoq_entry(ctx, cpu_iaoq_b, n, NULL); tcg_gen_exit_tb(ctx->base.tb, which); } else { - copy_iaoq_entry(ctx, cpu_iaoq_f, f, cpu_iaoq_b); - copy_iaoq_entry(ctx, cpu_iaoq_b, b, ctx->iaoq_n_var); + copy_iaoq_entry(ctx, cpu_iaoq_f, b, cpu_iaoq_b); + copy_iaoq_entry(ctx, cpu_iaoq_b, n, ctx->iaoq_n_var); tcg_gen_lookup_and_goto_ptr(); } } @@ -4744,8 +4745,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) /* Advance the insn queue. Note that this check also detects a priority change within the instruction queue. */ if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) { - if (ctx->iaoq_b != -1 && ctx->iaoq_n != -1 - && use_goto_tb(ctx, ctx->iaoq_b) + if (use_goto_tb(ctx, ctx->iaoq_b, ctx->iaoq_n) && (ctx->null_cond.c == TCG_COND_NEVER || ctx->null_cond.c == TCG_COND_ALWAYS)) { nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); From patchwork Wed May 15 09:40:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796947 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2892340wra; Wed, 15 May 2024 02:48:55 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWoEtcbLScTtnHNNR8n7OWVfAOXLaAGq/CVOSgwbLv0lYdIgICbXpnjHF76X716XElZSiheAJrjbpTsb61SDPnJ X-Google-Smtp-Source: AGHT+IFJrrHfgIrUl5s93BG8hxhaRHHSzPcBoSwT/8bUMPdJeYz7k19mJ9uVsJ3fNYJ1fnQ3g+Fx X-Received: by 2002:a81:ae43:0:b0:61a:d372:8767 with SMTP id 00721157ae682-622afff0e8amr145758267b3.51.1715766535266; Wed, 15 May 2024 02:48:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766535; cv=none; d=google.com; s=arc-20160816; b=zKoijMB12Tx68vtVxRYnI+DPJKAGimkFyHEiQarfEk+yQ+e3DMAXmaqhy7ZtxHh2/P GK2NbcRwSnh0aMrKAcWrcYtJ3QOgtwJdhNYRLB2fQbBtBITbkHsUPwq4fUIUE+PEklk6 Nqm8tzYfsipZsiRkXBK31xLt19TEKwtfNfVZjk1Phy136IWfDDXjNQTmKyTlHTQ7mlDe NWTwYTHVs1DSrDlcA0XcKUCIMe2LwZ/DG9JhnRszQMg4p3NlrcE8gbZ7KJ/Xkm9+ASzi aTMPh/olZCssuR/cCNwZnteUsGVHzQdbW8dzXlj2w2Ds60+cHfzHwQRh1NcHkD0jN95q GNfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=oC+Q8BvM2mb+Wj5yO6tGqI0fDdQydJH7QvUSzYQl9rE=; fh=3//KcqJEsa04kIBt5Nb/DJuP+2GuH1NwDRxnSl44zdw=; b=P198ndvFAN8wKQehExOoUj+7IolR21ejrVEVMZbVsuQV3xXzk1nHUnXfOBneutAXua Ms6ErzhPsJkUR0NgyLNe+4dG6+O8Ur7kqZQ9I/IYihYYHB6lqmieZJYvrRZL3KiBIUE/ daMoMr3zA0ipFmxuoR/muNvxrLjhLRoOhKxRT5jrfsOyoE7b7sA5O4qdXmNu5tCpR4J1 L2/LIMPsKh5+rTqALq561g4BClEAqDMYrArpMMheMszBvDpauYdT/YMBs5qEVqn9cYpH /qFP6JYAYSQo7VIyjRduZtgcTPUST3bQkcGfMCI5Ohz/AhkWzZIheV+JW26MyPErR5RD w4qA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kEsGhl7g; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 04/43] target/hppa: Pass displacement to do_dbranch Date: Wed, 15 May 2024 11:40:04 +0200 Message-Id: <20240515094043.82850-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass a displacement instead of an absolute value. In trans_be, remove the user-only do_dbranch case. The branch we are attempting to optimize is to the zero page, which is perforce on a different page than the code currently executing, which means that we will *not* use a goto_tb. Use a plain indirect branch instead, which is what we got out of the attempted direct branch anyway. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 33 +++++++++------------------------ 1 file changed, 9 insertions(+), 24 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 398803981c..4c42b518c5 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1766,9 +1766,11 @@ static bool do_fop_dedd(DisasContext *ctx, unsigned rt, /* Emit an unconditional branch to a direct target, which may or may not have already had nullification handled. */ -static bool do_dbranch(DisasContext *ctx, uint64_t dest, +static bool do_dbranch(DisasContext *ctx, int64_t disp, unsigned link, bool is_n) { + uint64_t dest = iaoq_dest(ctx, disp); + if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { if (link != 0) { copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); @@ -1815,10 +1817,7 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, /* Handle TRUE and NEVER as direct branches. */ if (c == TCG_COND_ALWAYS) { - return do_dbranch(ctx, dest, 0, is_n && disp >= 0); - } - if (c == TCG_COND_NEVER) { - return do_dbranch(ctx, ctx->iaoq_n, 0, is_n && disp < 0); + return do_dbranch(ctx, disp, 0, is_n && disp >= 0); } taken = gen_new_label(); @@ -3914,22 +3913,6 @@ static bool trans_be(DisasContext *ctx, arg_be *a) { TCGv_i64 tmp; -#ifdef CONFIG_USER_ONLY - /* ??? It seems like there should be a good way of using - "be disp(sr2, r0)", the canonical gateway entry mechanism - to our advantage. But that appears to be inconvenient to - manage along side branch delay slots. Therefore we handle - entry into the gateway page via absolute address. */ - /* Since we don't implement spaces, just branch. Do notice the special - case of "be disp(*,r0)" using a direct branch to disp, so that we can - goto_tb to the TB containing the syscall. */ - if (a->b == 0) { - return do_dbranch(ctx, a->disp, a->l, a->n); - } -#else - nullify_over(ctx); -#endif - tmp = tcg_temp_new_i64(); tcg_gen_addi_i64(tmp, load_gpr(ctx, a->b), a->disp); tmp = do_ibranch_priv(ctx, tmp); @@ -3939,6 +3922,8 @@ static bool trans_be(DisasContext *ctx, arg_be *a) #else TCGv_i64 new_spc = tcg_temp_new_i64(); + nullify_over(ctx); + load_spr(ctx, new_spc, a->sp); if (a->l) { copy_iaoq_entry(ctx, cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var); @@ -3968,7 +3953,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) static bool trans_bl(DisasContext *ctx, arg_bl *a) { - return do_dbranch(ctx, iaoq_dest(ctx, a->disp), a->l, a->n); + return do_dbranch(ctx, a->disp, a->l, a->n); } static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) @@ -4022,7 +4007,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) save_gpr(ctx, a->l, tmp); } - return do_dbranch(ctx, dest, 0, a->n); + return do_dbranch(ctx, dest - iaoq_dest(ctx, 0), 0, a->n); } static bool trans_blr(DisasContext *ctx, arg_blr *a) @@ -4035,7 +4020,7 @@ static bool trans_blr(DisasContext *ctx, arg_blr *a) return do_ibranch(ctx, tmp, a->l, a->n); } else { /* BLR R0,RX is a good way to load PC+8 into RX. */ - return do_dbranch(ctx, ctx->iaoq_f + 8, a->l, a->n); + return do_dbranch(ctx, 0, a->l, a->n); } } From patchwork Wed May 15 09:40:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796922 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2890851wra; Wed, 15 May 2024 02:44:04 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXweVMYE2lLHLjzQNWqe4OCRXXri+kUl+hpJ2yS86EFRcVO9ORWjEG9SksOfjw8EMh0+T6GS9bo5CZsDrDQ3gtl X-Google-Smtp-Source: AGHT+IGq8zpbD4SFai8QPUdbEaK+XhuKougIMKx3mjLDQUcQscjAexxJ/53anbeoCDLWICoGxx61 X-Received: by 2002:a05:6214:4381:b0:6a0:cb42:993d with SMTP id 6a1803df08f44-6a168167e0emr188969896d6.23.1715766243944; Wed, 15 May 2024 02:44:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766243; cv=none; d=google.com; s=arc-20160816; b=XOBTdOaIYISSNsGmsf9YVbzP1kDIGrlxlMDpBFLWeaCvPlgDOZiaj1P5p1dr2WknmO /bLB4VCp5r3ecEiDnyiQ+Cph/ga39FRekP87APzFUXM+LNfWVD9ouOlsVlVc2ClvqU+u SP7YSsRuY1zX//VBlIsGZJZA8mNKDj/R+RSL5DOgTBCqK1pYtkCasAkj3P/OSdfv+Kha dI/3Syq7S5vVLLsyMzGkojmziM+bg8VcZIy21YCFIUCY/btEHLV2USUQYvPElekXJbBb pjGw5WBHOGn5OaoB+gpJlq/uHtFB4vtESmkbZSRKkDS4EX+Sorsklhy93HhYSkH4S4au vt7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=tWp6bdA1sBa5OoQyzeOLvPwfbI/UOT6XgwKsQG7+re4=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=szAZ4Tkzfyd8bJfOC/9ZvM3I8E/o5AlnVRvnXCKoF7vq87SDBoTw5/p7kmxTmlW2D3 KqH/Rvq0qyRr6GUp2v2NLLhmLtkHe31yhyDDtgSGVSXSUDvofQoGHXODyhc4bewfJhBv A9xC0NlCojDZytG1k+SxS7zmXE4fbpfswAb8MeFSLCWHrejM2aFD431EPGNrtbXAMl5f Awem4X1Z5leO49/J37jcFQ3HH1KIOF/GzR3SpJhFoChAOCjX3r48ECP+KZ+YXg3mQrXK Qyk82jzyTBZgYxvBIGxUvz6NSfKoNnVKTzTVDD69AF4BEwW2r3ybo98+c3zqqNiyS7MQ B6BA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nApT73Mf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 05/43] target/hppa: Allow prior nullification in do_ibranch Date: Wed, 15 May 2024 11:40:05 +0200 Message-Id: <20240515094043.82850-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Simplify the function by not attempting a conditional move on the branch destination -- just use nullify_over normally. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 73 +++++++++++------------------------------ 1 file changed, 20 insertions(+), 53 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 4c42b518c5..140dfb747a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1871,17 +1871,15 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, unsigned link, bool is_n) { - TCGv_i64 a0, a1, next, tmp; - TCGCond c; + TCGv_i64 next; - assert(ctx->null_lab == NULL); + if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { + next = tcg_temp_new_i64(); + tcg_gen_mov_i64(next, dest); - if (ctx->null_cond.c == TCG_COND_NEVER) { if (link != 0) { copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); } - next = tcg_temp_new_i64(); - tcg_gen_mov_i64(next, dest); if (is_n) { if (use_nullify_skip(ctx)) { copy_iaoq_entry(ctx, cpu_iaoq_f, -1, next); @@ -1895,60 +1893,29 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, } ctx->iaoq_n = -1; ctx->iaoq_n_var = next; - } else if (is_n && use_nullify_skip(ctx)) { - /* The (conditional) branch, B, nullifies the next insn, N, - and we're allowed to skip execution N (no single-step or - tracepoint in effect). Since the goto_ptr that we must use - for the indirect branch consumes no special resources, we - can (conditionally) skip B and continue execution. */ - /* The use_nullify_skip test implies we have a known control path. */ - tcg_debug_assert(ctx->iaoq_b != -1); - tcg_debug_assert(ctx->iaoq_n != -1); + return true; + } - /* We do have to handle the non-local temporary, DEST, before - branching. Since IOAQ_F is not really live at this point, we - can simply store DEST optimistically. Similarly with IAOQ_B. */ + nullify_over(ctx); + + if (is_n && use_nullify_skip(ctx)) { copy_iaoq_entry(ctx, cpu_iaoq_f, -1, dest); next = tcg_temp_new_i64(); tcg_gen_addi_i64(next, dest, 4); copy_iaoq_entry(ctx, cpu_iaoq_b, -1, next); - - nullify_over(ctx); - if (link != 0) { - copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); - } - tcg_gen_lookup_and_goto_ptr(); - return nullify_end(ctx); + nullify_set(ctx, 0); } else { - c = ctx->null_cond.c; - a0 = ctx->null_cond.a0; - a1 = ctx->null_cond.a1; - - tmp = tcg_temp_new_i64(); - next = tcg_temp_new_i64(); - - copy_iaoq_entry(ctx, tmp, ctx->iaoq_n, ctx->iaoq_n_var); - tcg_gen_movcond_i64(c, next, a0, a1, tmp, dest); - ctx->iaoq_n = -1; - ctx->iaoq_n_var = next; - - if (link != 0) { - tcg_gen_movcond_i64(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp); - } - - if (is_n) { - /* The branch nullifies the next insn, which means the state of N - after the branch is the inverse of the state of N that applied - to the branch. */ - tcg_gen_setcond_i64(tcg_invert_cond(c), cpu_psw_n, a0, a1); - cond_free(&ctx->null_cond); - ctx->null_cond = cond_make_n(); - ctx->psw_n_nonzero = true; - } else { - cond_free(&ctx->null_cond); - } + copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + copy_iaoq_entry(ctx, cpu_iaoq_b, -1, dest); + nullify_set(ctx, is_n); } - return true; + if (link != 0) { + copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); + } + + tcg_gen_lookup_and_goto_ptr(); + ctx->base.is_jmp = DISAS_NORETURN; + return nullify_end(ctx); } /* Implement From patchwork Wed May 15 09:40:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796910 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2889986wra; Wed, 15 May 2024 02:41:29 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVy0s5GUY1/2fjDaLBDon8SUWKNz4tdRp7IVZNw4uC56PT5gbCZ0i+ooNhmsngyQR+fd63VjcPogBoQmtIr6iIG X-Google-Smtp-Source: AGHT+IF8+AKS2W/mCh3+z865PgP9NFRa8toTypshN0g+yiVElZit7gsem0XuorNvs1DO/nTnuYhF X-Received: by 2002:a05:6214:5a04:b0:6a0:b462:cde9 with SMTP id 6a1803df08f44-6a1681806eamr191192376d6.24.1715766089119; Wed, 15 May 2024 02:41:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766089; cv=none; d=google.com; s=arc-20160816; b=F4IrOQF949zwYltZ4+w2S04AW22hHjYMwiR9rvy9bnYC37aP2auR8oy9659hsNBkpn 3pusZZvhVt1H3pwaty3afaZz/AE4EDAWx4HhKFW1AvQGW4XozJ/DYJK5IkU5jVQvRizK mGd0/+FmmLTyuM5DUDKyJrSg8UvfRvq4LxbgyzDf4PpU0RfWDaopXwwnLak5MTIbFhys imgmX1H6W/dVhNB4eBVjXR3GxMlE8R5v75bFiRK1yX2EtTQSOpPKfK39wrfw1EFrLZ9p J/5Z9RNRMoJxwfbLcMrJToyicM04noWpJXROAzNef5UAIw+icqes3F+SVbW0HFsxqNxK QJ7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LWUr8lq4r4FRgquzvOJs5lbd1cxSGRXEBJY5ElBtf/k=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=puyc5MitG00qdVICce8zpCIeOZElEEtoa89A92amG/nwDkujKe7xj58FzG7aKhUcHz SmvIro2l2eqQKlBoMhxOwSJUDYZEXeQtL7yvDToYQzQPLz1pCuXY28Ph+xBQM5/HRQEW t/GGfmALoHuP1/cOIQEYLGw9ZoRVQf7pZqKRXYLie95MC7O35mpijTHncqIbGVHihrsk 82SSfnkuOCWKzMkZayV3egqRbUSE3u66DOY0kmfmt05Bcy5H0wUb1tNvl9WNYqEyPcLm 7RcGwndxjYoVAiDOdSl4JZSZy2bLe0PIragcewjGksDAtgL/NebjHZBCtsVhqAmQa0bn H3jQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zrXmdVJs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 06/43] target/hppa: Use CF_BP_PAGE instead of cpu_breakpoint_test Date: Wed, 15 May 2024 11:40:06 +0200 Message-Id: <20240515094043.82850-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The generic tcg driver will have already checked for breakpoints. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 140dfb747a..d272be0e6e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -674,8 +674,9 @@ static bool use_goto_tb(DisasContext *ctx, uint64_t bofs, uint64_t nofs) executing a TB that merely branches to the next TB. */ static bool use_nullify_skip(DisasContext *ctx) { - return (((ctx->iaoq_b ^ ctx->iaoq_f) & TARGET_PAGE_MASK) == 0 - && !cpu_breakpoint_test(ctx->cs, ctx->iaoq_b, BP_ANY)); + return (!(tb_cflags(ctx->base.tb) & CF_BP_PAGE) + && ctx->iaoq_b != -1 + && is_same_page(&ctx->base, ctx->iaoq_b)); } static void gen_goto_tb(DisasContext *ctx, int which, From patchwork Wed May 15 09:40:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796927 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2890910wra; Wed, 15 May 2024 02:44:12 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVDjAVituvZtdVsbguukfTjhzgdoHzpmpqFaLQdjUoqmX1sPSb0uDR/KN6gZfgrL/zECPGq12DIyMugYFsqp/r5 X-Google-Smtp-Source: AGHT+IEfATFdVNvka5yM1sh8cXFATKzIYfANErU2zTlkaX0YbPhOhmqyQ+CAA6p/IddLU95DBUS5 X-Received: by 2002:ac8:570a:0:b0:43d:f943:624c with SMTP id d75a77b69052e-43dfda8cacemr181293001cf.6.1715766252071; Wed, 15 May 2024 02:44:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766252; cv=none; d=google.com; s=arc-20160816; b=Zi8gKSF8fOA0pS4elqQg9JfrTTxj6nfKZQpFLQa2z9s9iFkWPPhAzK6qDiQUGEpY+z Ue+ISOXgSvFvnU2h1xt2TVfqmAoOUfjntNS5GvgIU4tKLke8Ljk2ORm5r0bark0KYbVK qbwsL/D84JxT+eglVN0PhB8hycrD1pUhu8k4OrNGH0btULbUuSp9g/+JqUVR9xHduLeX xjGVkMm24wBu9L+gNfYB2ms3fByolPbU1rW7HGvy4mXQ0XxFaEY/yKk9bzpPwRY3l9ml IkyK8LLDFcoEGcVNPquk9nwhIkrSleOPFuFFZhfCHDROKJlRSl+kcYiTSynE36Zy+C9e djCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+6KGcMVwWSn7kVLgoZwm5idlDPcCsf80saUhPLfhVY8=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=QlRYvCoZe37vVJR23c45VWSGGHnmZXMv8qvCY/Qidnldw6PyVUWnhZJGljR81Mwsnr ib4tEnPGf0dpA5Yi26Z3JmvewOzWQYuqh2mIR7jD7YtHn1497UzMaRV1jxNbotKL03OK qjH6ET4rc4SSUW0aoQpNDr7ox+WkZHvthmRwXqpnjnxNMCxXqDDXN0MlBXi6iLS/4XJV B0u1TR580643izahWvacp0YZp5BsPlL4pIP7UHMpKseidAaYJvtZXWWp56dWI82zViMu YFrjDPR6H6hndz9aJf0FidRifOl0IVsKYYm3ihoOTeBeLbK3mAVzoh9eR6yo+8pA3Iws Gq3g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RaAIFog9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 07/43] target/hppa: Add install_iaq_entries Date: Wed, 15 May 2024 11:40:07 +0200 Message-Id: <20240515094043.82850-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instead of two separate cpu_iaoq_entry calls, use one call to update both IAQ_Front and IAQ_Back. Simplify with an argument combination that automatically handles a simple increment from Front to Back. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 64 +++++++++++++++++++++-------------------- 1 file changed, 33 insertions(+), 31 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d272be0e6e..08d5e2a4bc 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -617,6 +617,23 @@ static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, } } +static void install_iaq_entries(DisasContext *ctx, uint64_t bi, TCGv_i64 bv, + uint64_t ni, TCGv_i64 nv) +{ + copy_iaoq_entry(ctx, cpu_iaoq_f, bi, bv); + + /* Allow ni variable, with nv null, to indicate a trivial advance. */ + if (ni != -1 || nv) { + copy_iaoq_entry(ctx, cpu_iaoq_b, ni, nv); + } else if (bi != -1) { + copy_iaoq_entry(ctx, cpu_iaoq_b, bi + 4, NULL); + } else { + tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, 4); + tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, + gva_offset_mask(ctx->tb_flags)); + } +} + static inline uint64_t iaoq_dest(DisasContext *ctx, int64_t disp) { return ctx->iaoq_f + disp + 8; @@ -629,8 +646,7 @@ static void gen_excp_1(int exception) static void gen_excp(DisasContext *ctx, int exception) { - copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); - copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); + install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); nullify_save(ctx); gen_excp_1(exception); ctx->base.is_jmp = DISAS_NORETURN; @@ -684,12 +700,10 @@ static void gen_goto_tb(DisasContext *ctx, int which, { if (use_goto_tb(ctx, b, n)) { tcg_gen_goto_tb(which); - copy_iaoq_entry(ctx, cpu_iaoq_f, b, NULL); - copy_iaoq_entry(ctx, cpu_iaoq_b, n, NULL); + install_iaq_entries(ctx, b, NULL, n, NULL); tcg_gen_exit_tb(ctx->base.tb, which); } else { - copy_iaoq_entry(ctx, cpu_iaoq_f, b, cpu_iaoq_b); - copy_iaoq_entry(ctx, cpu_iaoq_b, n, ctx->iaoq_n_var); + install_iaq_entries(ctx, b, cpu_iaoq_b, n, ctx->iaoq_n_var); tcg_gen_lookup_and_goto_ptr(); } } @@ -1883,9 +1897,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, } if (is_n) { if (use_nullify_skip(ctx)) { - copy_iaoq_entry(ctx, cpu_iaoq_f, -1, next); - tcg_gen_addi_i64(next, next, 4); - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, next); + install_iaq_entries(ctx, -1, next, -1, NULL); nullify_set(ctx, 0); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; return true; @@ -1900,14 +1912,10 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, nullify_over(ctx); if (is_n && use_nullify_skip(ctx)) { - copy_iaoq_entry(ctx, cpu_iaoq_f, -1, dest); - next = tcg_temp_new_i64(); - tcg_gen_addi_i64(next, dest, 4); - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, next); + install_iaq_entries(ctx, -1, dest, -1, NULL); nullify_set(ctx, 0); } else { - copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, dest); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest); nullify_set(ctx, is_n); } if (link != 0) { @@ -1998,9 +2006,7 @@ static void do_page_zero(DisasContext *ctx) tcg_gen_st_i64(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])); tmp = tcg_temp_new_i64(); tcg_gen_ori_i64(tmp, cpu_gr[31], 3); - copy_iaoq_entry(ctx, cpu_iaoq_f, -1, tmp); - tcg_gen_addi_i64(tmp, tmp, 4); - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp); + install_iaq_entries(ctx, -1, tmp, -1, NULL); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; break; @@ -2744,8 +2750,8 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) nullify_over(ctx); /* Advance the instruction queue. */ - copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); - copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, + ctx->iaoq_n, ctx->iaoq_n_var); nullify_set(ctx, 0); /* Tell the qemu main loop to halt until this cpu has work. */ @@ -3898,18 +3904,15 @@ static bool trans_be(DisasContext *ctx, arg_be *a) tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_b); } if (a->n && use_nullify_skip(ctx)) { - copy_iaoq_entry(ctx, cpu_iaoq_f, -1, tmp); - tcg_gen_addi_i64(tmp, tmp, 4); - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp); + install_iaq_entries(ctx, -1, tmp, -1, NULL); tcg_gen_mov_i64(cpu_iasq_f, new_spc); tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f); nullify_set(ctx, 0); } else { - copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, tmp); if (ctx->iaoq_b == -1) { tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); } - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp); tcg_gen_mov_i64(cpu_iasq_b, new_spc); nullify_set(ctx, a->n); } @@ -4018,11 +4021,10 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a) nullify_over(ctx); dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); - copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest); if (ctx->iaoq_b == -1) { tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); } - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, dest); tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); if (a->l) { copy_iaoq_entry(ctx, cpu_gr[a->l], ctx->iaoq_n, ctx->iaoq_n_var); @@ -4721,8 +4723,8 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) case DISAS_IAQ_N_STALE: case DISAS_IAQ_N_STALE_EXIT: if (ctx->iaoq_f == -1) { - copy_iaoq_entry(ctx, cpu_iaoq_f, -1, cpu_iaoq_b); - copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); + install_iaq_entries(ctx, -1, cpu_iaoq_b, + ctx->iaoq_n, ctx->iaoq_n_var); #ifndef CONFIG_USER_ONLY tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); #endif @@ -4751,8 +4753,8 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) case DISAS_TOO_MANY: case DISAS_IAQ_N_STALE: case DISAS_IAQ_N_STALE_EXIT: - copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); - copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); + install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, + ctx->iaoq_b, cpu_iaoq_b); nullify_save(ctx); /* FALLTHRU */ case DISAS_IAQ_N_UPDATED: From patchwork Wed May 15 09:40:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796937 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2891934wra; Wed, 15 May 2024 02:47:37 -0700 (PDT) X-Forwarded-Encrypted: i=2; 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 08/43] target/hppa: Add install_link Date: Wed, 15 May 2024 11:40:08 +0200 Message-Id: <20240515094043.82850-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=richard.henderson@linaro.org; helo=mail-lf1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a common routine for writing the return address. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 55 ++++++++++++++++++++++++----------------- 1 file changed, 32 insertions(+), 23 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 08d5e2a4bc..220665d98e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -634,6 +634,24 @@ static void install_iaq_entries(DisasContext *ctx, uint64_t bi, TCGv_i64 bv, } } +static void install_link(DisasContext *ctx, unsigned link, bool with_sr0) +{ + tcg_debug_assert(ctx->null_cond.c == TCG_COND_NEVER); + if (!link) { + return; + } + if (ctx->iaoq_b == -1) { + tcg_gen_addi_i64(cpu_gr[link], cpu_iaoq_b, 4); + } else { + tcg_gen_movi_i64(cpu_gr[link], ctx->iaoq_b + 4); + } +#ifndef CONFIG_USER_ONLY + if (with_sr0) { + tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_b); + } +#endif +} + static inline uint64_t iaoq_dest(DisasContext *ctx, int64_t disp) { return ctx->iaoq_f + disp + 8; @@ -1787,9 +1805,7 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, uint64_t dest = iaoq_dest(ctx, disp); if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { - if (link != 0) { - copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); - } + install_link(ctx, link, false); ctx->iaoq_n = dest; if (is_n) { ctx->null_cond.c = TCG_COND_ALWAYS; @@ -1797,10 +1813,7 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, } else { nullify_over(ctx); - if (link != 0) { - copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); - } - + install_link(ctx, link, false); if (is_n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); gen_goto_tb(ctx, 0, dest, dest + 4); @@ -1892,9 +1905,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, next = tcg_temp_new_i64(); tcg_gen_mov_i64(next, dest); - if (link != 0) { - copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); - } + install_link(ctx, link, false); if (is_n) { if (use_nullify_skip(ctx)) { install_iaq_entries(ctx, -1, next, -1, NULL); @@ -1911,16 +1922,17 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, nullify_over(ctx); + next = tcg_temp_new_i64(); + tcg_gen_mov_i64(next, dest); + + install_link(ctx, link, false); if (is_n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, dest, -1, NULL); + install_iaq_entries(ctx, -1, next, -1, NULL); nullify_set(ctx, 0); } else { - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, next); nullify_set(ctx, is_n); } - if (link != 0) { - copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); - } tcg_gen_lookup_and_goto_ptr(); ctx->base.is_jmp = DISAS_NORETURN; @@ -3899,10 +3911,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) nullify_over(ctx); load_spr(ctx, new_spc, a->sp); - if (a->l) { - copy_iaoq_entry(ctx, cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var); - tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_b); - } + install_link(ctx, a->l, true); if (a->n && use_nullify_skip(ctx)) { install_iaq_entries(ctx, -1, tmp, -1, NULL); tcg_gen_mov_i64(cpu_iasq_f, new_spc); @@ -4019,16 +4028,16 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a) return do_ibranch(ctx, dest, a->l, a->n); #else nullify_over(ctx); - dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); + dest = tcg_temp_new_i64(); + tcg_gen_mov_i64(dest, load_gpr(ctx, a->b)); + dest = do_ibranch_priv(ctx, dest); + install_link(ctx, a->l, false); install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest); if (ctx->iaoq_b == -1) { tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); } tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); - if (a->l) { - copy_iaoq_entry(ctx, cpu_gr[a->l], ctx->iaoq_n, ctx->iaoq_n_var); - } nullify_set(ctx, a->n); tcg_gen_lookup_and_goto_ptr(); ctx->base.is_jmp = DISAS_NORETURN; From patchwork Wed May 15 09:40:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796943 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2892142wra; Wed, 15 May 2024 02:48:16 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU+ti045yxeKF8fm0F9uNkqgxv3Z7Ougu10CFZ63aOIHDS/+UF++xEVtvT94bjBXpSgYYvJZDiW1jz+yWL+f+W0 X-Google-Smtp-Source: AGHT+IGV24q0GQCFmUTnhKZWK3iq+9kT7jiUj0i0SShlx7CLbK9sM6CYdw2c95JH4pGmy2jmAHGg X-Received: by 2002:a05:6214:5681:b0:698:ecae:429c with SMTP id 6a1803df08f44-6a168240388mr214243776d6.56.1715766496108; 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 09/43] target/hppa: Delay computation of IAQ_Next Date: Wed, 15 May 2024 11:40:09 +0200 Message-Id: <20240515094043.82850-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We no longer have to allocate a temp and perform an addition before translation of the rest of the insn. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 220665d98e..9189e0350b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1807,6 +1807,7 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { install_link(ctx, link, false); ctx->iaoq_n = dest; + ctx->iaoq_n_var = NULL; if (is_n) { ctx->null_cond.c = TCG_COND_ALWAYS; } @@ -1863,11 +1864,6 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, ctx->null_lab = NULL; } nullify_set(ctx, n); - if (ctx->iaoq_n == -1) { - /* The temporary iaoq_n_var died at the branch above. - Regenerate it here instead of saving it. */ - tcg_gen_addi_i64(ctx->iaoq_n_var, cpu_iaoq_b, 4); - } gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); } @@ -4631,8 +4627,6 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->iaoq_f = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; ctx->iaoq_b = (diff ? ctx->iaoq_f + diff : -1); #endif - ctx->iaoq_n = -1; - ctx->iaoq_n_var = NULL; ctx->zero = tcg_constant_i64(0); @@ -4684,14 +4678,8 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) /* Set up the IA queue for the next insn. This will be overwritten by a branch. */ - if (ctx->iaoq_b == -1) { - ctx->iaoq_n = -1; - ctx->iaoq_n_var = tcg_temp_new_i64(); - tcg_gen_addi_i64(ctx->iaoq_n_var, cpu_iaoq_b, 4); - } else { - ctx->iaoq_n = ctx->iaoq_b + 4; - ctx->iaoq_n_var = NULL; - } + ctx->iaoq_n_var = NULL; + ctx->iaoq_n = ctx->iaoq_b == -1 ? -1 : ctx->iaoq_b + 4; if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) { ctx->null_cond.c = TCG_COND_NEVER; @@ -4742,7 +4730,13 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) ? DISAS_EXIT : DISAS_IAQ_N_UPDATED); } else if (ctx->iaoq_b == -1) { - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, ctx->iaoq_n_var); + if (ctx->iaoq_n_var) { + copy_iaoq_entry(ctx, cpu_iaoq_b, -1, ctx->iaoq_n_var); + } else { + tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_b, 4); + tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, + gva_offset_mask(ctx->tb_flags)); + } } break; From patchwork Wed May 15 09:40:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796940 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2891984wra; Wed, 15 May 2024 02:47:47 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUA8YGLEyZOCta+T11Y73l5dLwc6LTy1xYmlGJM/YotjuhcaPN0j59VdqhYtvsjM0/uYkbqL2RO3JPPGWUdpI+L X-Google-Smtp-Source: AGHT+IEMQMWk/JZCv1t3KQz+qhlQ7oO+RSl3pcEXUOxqaKlEVA1lKkYti5FO2vXsbn4JQ5MKlQIV X-Received: by 2002:a05:6102:3707:b0:47c:24fa:b627 with SMTP id ada2fe7eead31-48077de52e5mr16288587137.13.1715766467493; Wed, 15 May 2024 02:47:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766467; cv=none; d=google.com; s=arc-20160816; b=W4d7W9aUApLtq2Tql+3qrfHRfIFRz5hF2robh9cINRHf15ImafddXtgdZSbZNy1mzi MesxJ5TfCMmCAeDs27rJAxuVzkRDPB6Q5LzsgV96pUJfMmjCnQb3Pq0R2ScEVNj8U8AL q9yX9ZMfifrFxE4YmGG6JgnQ8dSNJp3jKPGwe8CLUaPrS1ePvqeSTphtAgRhgBLbBrbz qpcLk2okHOd9pJ1K5UutlqjCJm2Px7lclTiCjBZxoSgvxhwQAd8ZgYZtSjOMusMIUyt7 z90xVIw5ykf1DQwHwmpb8dqGXdFgU9Jh5hXbA6cZPc57En7uCSQTiLgZuEQkNEO3nsMn phQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8D/PMBczQIsrFLsR1lIqXJyOFdBm71SwgovD3vevRX4=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=yMVNnglYJ7PD6u6zugNyyPabhY1kxOm2mLg6TKIPAOHuZbOyL92kd1JV9O+QUe38Gi BMoEjZ4H3f3t+7M9IgXAsAWfsJsrhWrAm20UlkeQLaZ1KP5g5mwHcvHsahINRorBmMCV OC08wAcvCC93FheOVdYuD3sR6YwNBRTm4QZJj79sixgZDDfQ8SS5RooGTUSL2IVXyJZi IOtES/n9WZB9QqGPoEXhDaVXxRPy9QYUypk0/HNqLhUHcy/QtR1dHAdmlmnuoolVSY9n s44JXZi8yLJWp8FWzyME7CvAnop60Li2dyT+XYIQPvqCigbOjP6Tc70ZkSpBxjTUISNt 4Mjw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O6yVTTZh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 10/43] target/hppa: Skip nullified insns in unconditional dbranch path Date: Wed, 15 May 2024 11:40:10 +0200 Message-Id: <20240515094043.82850-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 9189e0350b..6c5efb0023 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1806,11 +1806,17 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { install_link(ctx, link, false); - ctx->iaoq_n = dest; - ctx->iaoq_n_var = NULL; if (is_n) { + if (use_nullify_skip(ctx)) { + nullify_set(ctx, 0); + gen_goto_tb(ctx, 0, dest, dest + 4); + ctx->base.is_jmp = DISAS_NORETURN; + return true; + } ctx->null_cond.c = TCG_COND_ALWAYS; } + ctx->iaoq_n = dest; + ctx->iaoq_n_var = NULL; } else { nullify_over(ctx); From patchwork Wed May 15 09:40:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796931 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2890994wra; Wed, 15 May 2024 02:44:30 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUkyOXkXidXYkh94UL1av8BMfSvonMlel/WbF6XpTr6UBkCk+07IVmzxwVJaqIRVMI3M1xGLNCzGZgBYV9nnXbR X-Google-Smtp-Source: AGHT+IEUza8HxjT3K7rL1pGzHxBfQYxpOFucXNrPf+9rNv0uJMullGBQxyfYWqy751zB/dHlBMtr X-Received: by 2002:a05:620a:1485:b0:792:bd32:bba7 with SMTP id af79cd13be357-792c7598891mr1507237085a.25.1715766270186; Wed, 15 May 2024 02:44:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766270; cv=none; d=google.com; s=arc-20160816; b=qe91G0ob+QsKPAi2FAkOI/oOf3wTfwcjxNGQtwxTDe/VjMVi+WSuu/8B4LeOb5lpHs G5y11uFkbr+n+8w3RT2P+KyJWZRuIXbHq9VSmziDgmV2wdDf8GKbKG4nfWsnig4tHtPY esR2I6sEMzskA/UJVnL+O8UcpHTn6yaxy6NGGI5xcJv+vYiHP1TXEW322WB7RpvgdSay aslRVSckYjV9dx6zykisVRDxDXxGoaZqcmJt1xwLizlZBI51TrS45fvi7IPammYOgEEE Stkn+8SxwYXXdRCPPmZcR575xjRGHcvEjYx5Fwp5a5g9dvEfOUEIiS2+PQ0zK8t97h9/ WVeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gMyHqhS5OxS8Cmc1XYDwE2yVlV/PBlI3c6TyUB0pUZg=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=iIU/7UjPls+l+QOJx42D7IiU7wkWaK1Wcj4jRsIeD8eiymDzr2hhGGlQ03dGJOvHQq DOw9D2wvDtPignqRtPq8zkZ6/30eeSLAGWK2kPlK6B/R9RTYm3qeg/J/505TIMKQhI38 9nORo72obKXGAbIcUL8zzo24uBwsOKHqzWyqUNvQOyszM80FLk3TA4I0PdBrKRij9Sh2 ZB6e5OBiHsiX1nf/EjJjRukMNUlNln7AcF3Ifv6dkNP0QHm/pMZnEfUqmcXHqCBkxiJc ROGtZeXOjZUvh5sbh9C3kxsHzvOrgTCX096JNgwmkXLmPHVeT2JZZr/cLf2KNuEnNp3e LBhQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ThxXjMjc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 11/43] target/hppa: Simplify TB end Date: Wed, 15 May 2024 11:40:11 +0200 Message-Id: <20240515094043.82850-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Minimize the amount of code in hppa_tr_translate_insn advancing the insn queue for the next insn. Move the goto_tb path to hppa_tr_tb_stop. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 109 +++++++++++++++++++++------------------- 1 file changed, 57 insertions(+), 52 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6c5efb0023..b79c44bd49 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4700,54 +4700,31 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) } } - /* Advance the insn queue. Note that this check also detects - a priority change within the instruction queue. */ - if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) { - if (use_goto_tb(ctx, ctx->iaoq_b, ctx->iaoq_n) - && (ctx->null_cond.c == TCG_COND_NEVER - || ctx->null_cond.c == TCG_COND_ALWAYS)) { - nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); - gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); - ctx->base.is_jmp = ret = DISAS_NORETURN; - } else { - ctx->base.is_jmp = ret = DISAS_IAQ_N_STALE; - } + /* If the TranslationBlock must end, do so. */ + ctx->base.pc_next += 4; + if (ret != DISAS_NEXT) { + return; } + /* Note this also detects a priority change. */ + if (ctx->iaoq_b != ctx->iaoq_f + 4) { + ctx->base.is_jmp = DISAS_IAQ_N_STALE; + return; + } + + /* + * Advance the insn queue. + * The only exit now is DISAS_TOO_MANY from the translator loop. + */ ctx->iaoq_f = ctx->iaoq_b; ctx->iaoq_b = ctx->iaoq_n; - ctx->base.pc_next += 4; - - switch (ret) { - case DISAS_NORETURN: - case DISAS_IAQ_N_UPDATED: - break; - - case DISAS_NEXT: - case DISAS_IAQ_N_STALE: - case DISAS_IAQ_N_STALE_EXIT: - if (ctx->iaoq_f == -1) { - install_iaq_entries(ctx, -1, cpu_iaoq_b, - ctx->iaoq_n, ctx->iaoq_n_var); -#ifndef CONFIG_USER_ONLY - tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); -#endif - nullify_save(ctx); - ctx->base.is_jmp = (ret == DISAS_IAQ_N_STALE_EXIT - ? DISAS_EXIT - : DISAS_IAQ_N_UPDATED); - } else if (ctx->iaoq_b == -1) { - if (ctx->iaoq_n_var) { - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, ctx->iaoq_n_var); - } else { - tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_b, 4); - tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, - gva_offset_mask(ctx->tb_flags)); - } + if (ctx->iaoq_b == -1) { + if (ctx->iaoq_n_var) { + copy_iaoq_entry(ctx, cpu_iaoq_b, -1, ctx->iaoq_n_var); + } else { + tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_b, 4); + tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, + gva_offset_mask(ctx->tb_flags)); } - break; - - default: - g_assert_not_reached(); } } @@ -4755,23 +4732,51 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); DisasJumpType is_jmp = ctx->base.is_jmp; + uint64_t fi, bi; + TCGv_i64 fv, bv; + TCGv_i64 fs; + + /* Assume the insn queue has not been advanced. */ + fi = ctx->iaoq_b; + fv = cpu_iaoq_b; + fs = fi == -1 ? cpu_iasq_b : NULL; + bi = ctx->iaoq_n; + bv = ctx->iaoq_n_var; switch (is_jmp) { case DISAS_NORETURN: break; case DISAS_TOO_MANY: - case DISAS_IAQ_N_STALE: - case DISAS_IAQ_N_STALE_EXIT: - install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, - ctx->iaoq_b, cpu_iaoq_b); - nullify_save(ctx); + /* The insn queue has not been advanced. */ + bi = fi; + bv = fv; + fi = ctx->iaoq_f; + fv = NULL; + fs = NULL; /* FALLTHRU */ - case DISAS_IAQ_N_UPDATED: - if (is_jmp != DISAS_IAQ_N_STALE_EXIT) { - tcg_gen_lookup_and_goto_ptr(); + case DISAS_IAQ_N_STALE: + if (use_goto_tb(ctx, fi, bi) + && (ctx->null_cond.c == TCG_COND_NEVER + || ctx->null_cond.c == TCG_COND_ALWAYS)) { + nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); + gen_goto_tb(ctx, 0, fi, bi); break; } /* FALLTHRU */ + case DISAS_IAQ_N_STALE_EXIT: + install_iaq_entries(ctx, fi, fv, bi, bv); + if (fs) { + tcg_gen_mov_i64(cpu_iasq_f, fs); + } + nullify_save(ctx); + if (is_jmp == DISAS_IAQ_N_STALE_EXIT) { + tcg_gen_exit_tb(NULL, 0); + break; + } + /* FALLTHRU */ + case DISAS_IAQ_N_UPDATED: + tcg_gen_lookup_and_goto_ptr(); + break; case DISAS_EXIT: tcg_gen_exit_tb(NULL, 0); break; From patchwork Wed May 15 09:40:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796935 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2891126wra; Wed, 15 May 2024 02:44:58 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXind896Wvecvce89qEH2GuVf5Ihx2NuxJvax2i7QZZPGVq32m9W8s521tnTUqKGVds1krGqs9wy61Wdwj0FUkP X-Google-Smtp-Source: AGHT+IELsiRgFTrdGhinBUVIimXp2oIguXEsGHlCFRNM6HXhQNkU5Vw1fqfhX2OVTkR5B6591Wvi X-Received: by 2002:ac8:5f93:0:b0:43a:b15d:bf69 with SMTP id d75a77b69052e-43dfdcd7283mr219667881cf.46.1715766298098; Wed, 15 May 2024 02:44:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766298; cv=none; d=google.com; s=arc-20160816; b=QMNaMd6YZgsxze9Dddu716mGt8XCEipEADcfSecbo+VoLcRp9KE5YLgEovdWIkSRmn EE/xKIy0+w1PuXdjnPOpKczRvCtH8SrQROGYiYj1clWvAEM7HRhhtgszLuMI9zqdHPky zMtmxzEE6hS+NFEm76WVfC1TbVksoyUKKFARxixjv9tqKU/NxKfm+XpR8/O0AxfREEuZ He5vDJPyCXWmaOWABfFV4HzNj2JBDWZmz5MjFRoGkDeleX6LZSnrXv4W4/+jT68HXhTC xFrFuakSVZn5Qy7a2fYZxzdsCb+PHAqkYwRqJNEQQ+AkuEKj/xHkZrIxM8xzdPPEnq2N BijA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ixJmGoyxJB9sbwoHJd6SpaODQZW3sNI1pPxi/MSBfJ0=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=hRrs5I9MkTwE5jv/pdat5CnqW0cItD34aOporOfuVqnIohYDV9C8mqVlDPpBEfceZw ovs4Z0HD4w18tRscPXkfm5GVaq5/1m6yOu6qg3yCmm0lAyTNBz4NRe5cr+lHKGNy3bxM y7UW5JaKSlLw1ZACuK7lr2xy2gAOpXBAcnIEg85E/nd1lm8mtoLep8/MMz+qrwmmUIJf 8nUfTRD52/BliyNk6Be2B76DBd0ocdeadS8dYomzA3FAv2diCVlNh8+/PVth+e/HeeUE bV3DVRhMRgDPTrnE6i+yp/BgfF6MG0FyI9JdMApFb+ygbgT2kZD7dprQEKLBYNT6to1X tmzg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IIEHO7W2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 12/43] target/hppa: Add IASQ entries to DisasContext Date: Wed, 15 May 2024 11:40:12 +0200 Message-Id: <20240515094043.82850-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add variable to track space changes to IAQ. So far, no such changes are introduced, but the new checks vs ctx->iasq_b may eliminate an unnecessary copy to cpu_iasq_f with e.g. BLR. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 39 ++++++++++++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b79c44bd49..b4e384baa3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -50,6 +50,13 @@ typedef struct DisasContext { uint64_t iaoq_b; uint64_t iaoq_n; TCGv_i64 iaoq_n_var; + /* + * Null when IASQ_Back unchanged from IASQ_Front, + * or cpu_iasq_b, when IASQ_Back has been changed. + */ + TCGv_i64 iasq_b; + /* Null when IASQ_Next unchanged from IASQ_Back, or set by branch. */ + TCGv_i64 iasq_n; DisasCond null_cond; TCGLabel *null_lab; @@ -3917,12 +3924,12 @@ static bool trans_be(DisasContext *ctx, arg_be *a) if (a->n && use_nullify_skip(ctx)) { install_iaq_entries(ctx, -1, tmp, -1, NULL); tcg_gen_mov_i64(cpu_iasq_f, new_spc); - tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f); + tcg_gen_mov_i64(cpu_iasq_b, new_spc); nullify_set(ctx, 0); } else { install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, tmp); - if (ctx->iaoq_b == -1) { - tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); + if (ctx->iasq_b) { + tcg_gen_mov_i64(cpu_iasq_f, ctx->iasq_b); } tcg_gen_mov_i64(cpu_iasq_b, new_spc); nullify_set(ctx, a->n); @@ -4036,8 +4043,8 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a) install_link(ctx, a->l, false); install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest); - if (ctx->iaoq_b == -1) { - tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); + if (ctx->iasq_b) { + tcg_gen_mov_i64(cpu_iasq_f, ctx->iasq_b); } tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); nullify_set(ctx, a->n); @@ -4618,6 +4625,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->mmu_idx = MMU_USER_IDX; ctx->iaoq_f = ctx->base.pc_first | ctx->privilege; ctx->iaoq_b = ctx->base.tb->cs_base | ctx->privilege; + ctx->iasq_b = NULL; ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; @@ -4632,6 +4640,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->iaoq_f = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; ctx->iaoq_b = (diff ? ctx->iaoq_f + diff : -1); + ctx->iasq_b = (diff ? NULL : cpu_iasq_b); #endif ctx->zero = tcg_constant_i64(0); @@ -4684,6 +4693,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) /* Set up the IA queue for the next insn. This will be overwritten by a branch. */ + ctx->iasq_n = NULL; ctx->iaoq_n_var = NULL; ctx->iaoq_n = ctx->iaoq_b == -1 ? -1 : ctx->iaoq_b + 4; @@ -4706,7 +4716,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) return; } /* Note this also detects a priority change. */ - if (ctx->iaoq_b != ctx->iaoq_f + 4) { + if (ctx->iaoq_b != ctx->iaoq_f + 4 || ctx->iasq_b) { ctx->base.is_jmp = DISAS_IAQ_N_STALE; return; } @@ -4726,6 +4736,10 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) gva_offset_mask(ctx->tb_flags)); } } + if (ctx->iasq_n) { + tcg_gen_mov_i64(cpu_iasq_b, ctx->iasq_n); + ctx->iasq_b = cpu_iasq_b; + } } static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) @@ -4734,14 +4748,15 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) DisasJumpType is_jmp = ctx->base.is_jmp; uint64_t fi, bi; TCGv_i64 fv, bv; - TCGv_i64 fs; + TCGv_i64 fs, bs; /* Assume the insn queue has not been advanced. */ fi = ctx->iaoq_b; fv = cpu_iaoq_b; - fs = fi == -1 ? cpu_iasq_b : NULL; + fs = ctx->iasq_b; bi = ctx->iaoq_n; bv = ctx->iaoq_n_var; + bs = ctx->iasq_n; switch (is_jmp) { case DISAS_NORETURN: @@ -4750,12 +4765,15 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) /* The insn queue has not been advanced. */ bi = fi; bv = fv; + bs = fs; fi = ctx->iaoq_f; fv = NULL; fs = NULL; /* FALLTHRU */ case DISAS_IAQ_N_STALE: - if (use_goto_tb(ctx, fi, bi) + if (fs == NULL + && bs == NULL + && use_goto_tb(ctx, fi, bi) && (ctx->null_cond.c == TCG_COND_NEVER || ctx->null_cond.c == TCG_COND_ALWAYS)) { nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); @@ -4768,6 +4786,9 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) if (fs) { tcg_gen_mov_i64(cpu_iasq_f, fs); } + if (bs) { + tcg_gen_mov_i64(cpu_iasq_b, bs); + } nullify_save(ctx); if (is_jmp == DISAS_IAQ_N_STALE_EXIT) { tcg_gen_exit_tb(NULL, 0); From patchwork Wed May 15 09:40:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796913 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2890064wra; Wed, 15 May 2024 02:41:42 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUUuY0hYtxtM5wAbq1OZfJIRGO/wD9ubvZrxh59FXkMKxba4xLMPfXz8z5YSw29OmA6W3wLnqfO5MsV7gqJ9BUK X-Google-Smtp-Source: AGHT+IG75Y00C0HphgYS3FQ6CNs87b8ZSVrmli9jToTsuHo9NlXeI4vGvnj2bTTXKCoGcR4kIepw X-Received: by 2002:a05:6214:4a8e:b0:6a0:cd5f:d8d1 with SMTP id 6a1803df08f44-6a16821471amr171831866d6.50.1715766102002; Wed, 15 May 2024 02:41:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766101; cv=none; d=google.com; s=arc-20160816; b=GS28bj3d9MDcbkYOBnkloP6mByq8+/ZOk/RobonH4OoYGldBjpK6Uq4q6MZB2EUpfz y7yWwx6F1/lND8ngyKbU/6P+yjZcEV6Jw5RmV6xjuJ7Oby6RV7HxSfNpvRUe4SAvuubV ceZuTZYUkvD0Q2vB1U6cQZDyku0lnlRDUHTLttsd+28dCGzXCvY4VT17R823w0tA04aO MKiahbdmdkXJCTTNjLURbXt2pfpM4rPqRhPUEsk/3ypDmS0JLHfM6svfmHe8Co4UAWz+ 0S0dVw27vp4rU4uyScGWaM+3TvKwbw2YxZHXMlJ7trrMIITel1wcw3n2EWJtpV0BqeSQ UUVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DMb5zREhSXLC82TThYEUSCGBhHh5HnCaaLKrwiRaSAU=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=bzhtTlYot+/0jSc2fQC/RODiFzp7qflMGOt60f6eNlmUVmjJ8yXnff9lwPRtaKqz5J Z+vaNhF6+q3ti7a9QmObPWXM2sHV3Bh3Y7NeTa5/rHYd6fm+qVr7/XVeTXvpLXNkah3U JK8joThDC1bXe4RUICBXBVo6NQsP74JdJW2oAs7R//IH5JyHsMctyzK2y48xZhGrbpNu J3Ze7hvHwSZU/NIeXugI3Z3AQYN0y3bEFSiBbAmkg/ivpWfmKTQMgu4lCXFTVAp0bpNf BXtNO4UgzofLdz+B/z/uIihlY1GMWMXa3nLUZljL8wPQbpZp1kaG9uMA/dhCRKE/sZ0z 0Jew==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WQ30g4ll; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 13/43] target/hppa: Add space arguments to install_iaq_entries Date: Wed, 15 May 2024 11:40:13 +0200 Message-Id: <20240515094043.82850-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move space assighments to a central location. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 58 +++++++++++++++++++---------------------- 1 file changed, 27 insertions(+), 31 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b4e384baa3..eed0f92db4 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -624,8 +624,9 @@ static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, } } -static void install_iaq_entries(DisasContext *ctx, uint64_t bi, TCGv_i64 bv, - uint64_t ni, TCGv_i64 nv) +static void install_iaq_entries(DisasContext *ctx, + uint64_t bi, TCGv_i64 bv, TCGv_i64 bs, + uint64_t ni, TCGv_i64 nv, TCGv_i64 ns) { copy_iaoq_entry(ctx, cpu_iaoq_f, bi, bv); @@ -639,6 +640,12 @@ static void install_iaq_entries(DisasContext *ctx, uint64_t bi, TCGv_i64 bv, tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, gva_offset_mask(ctx->tb_flags)); } + if (bs) { + tcg_gen_mov_i64(cpu_iasq_f, bs); + } + if (ns || bs) { + tcg_gen_mov_i64(cpu_iasq_b, ns ? ns : bs); + } } static void install_link(DisasContext *ctx, unsigned link, bool with_sr0) @@ -671,7 +678,8 @@ static void gen_excp_1(int exception) static void gen_excp(DisasContext *ctx, int exception) { - install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, NULL, + ctx->iaoq_b, cpu_iaoq_b, NULL); nullify_save(ctx); gen_excp_1(exception); ctx->base.is_jmp = DISAS_NORETURN; @@ -725,10 +733,11 @@ static void gen_goto_tb(DisasContext *ctx, int which, { if (use_goto_tb(ctx, b, n)) { tcg_gen_goto_tb(which); - install_iaq_entries(ctx, b, NULL, n, NULL); + install_iaq_entries(ctx, b, NULL, NULL, n, NULL, NULL); tcg_gen_exit_tb(ctx->base.tb, which); } else { - install_iaq_entries(ctx, b, cpu_iaoq_b, n, ctx->iaoq_n_var); + install_iaq_entries(ctx, b, cpu_iaoq_b, ctx->iasq_b, + n, ctx->iaoq_n_var, ctx->iasq_n); tcg_gen_lookup_and_goto_ptr(); } } @@ -1917,7 +1926,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, install_link(ctx, link, false); if (is_n) { if (use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, -1, NULL); + install_iaq_entries(ctx, -1, next, NULL, -1, NULL, NULL); nullify_set(ctx, 0); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; return true; @@ -1936,10 +1945,11 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, install_link(ctx, link, false); if (is_n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, -1, NULL); + install_iaq_entries(ctx, -1, next, NULL, -1, NULL, NULL); nullify_set(ctx, 0); } else { - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, next); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, + -1, next, NULL); nullify_set(ctx, is_n); } @@ -2027,7 +2037,7 @@ static void do_page_zero(DisasContext *ctx) tcg_gen_st_i64(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])); tmp = tcg_temp_new_i64(); tcg_gen_ori_i64(tmp, cpu_gr[31], 3); - install_iaq_entries(ctx, -1, tmp, -1, NULL); + install_iaq_entries(ctx, -1, tmp, NULL, -1, NULL, NULL); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; break; @@ -2771,8 +2781,8 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) nullify_over(ctx); /* Advance the instruction queue. */ - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, - ctx->iaoq_n, ctx->iaoq_n_var); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, + ctx->iaoq_n, ctx->iaoq_n_var, ctx->iasq_n); nullify_set(ctx, 0); /* Tell the qemu main loop to halt until this cpu has work. */ @@ -3922,16 +3932,11 @@ static bool trans_be(DisasContext *ctx, arg_be *a) load_spr(ctx, new_spc, a->sp); install_link(ctx, a->l, true); if (a->n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, tmp, -1, NULL); - tcg_gen_mov_i64(cpu_iasq_f, new_spc); - tcg_gen_mov_i64(cpu_iasq_b, new_spc); + install_iaq_entries(ctx, -1, tmp, new_spc, -1, NULL, new_spc); nullify_set(ctx, 0); } else { - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, tmp); - if (ctx->iasq_b) { - tcg_gen_mov_i64(cpu_iasq_f, ctx->iasq_b); - } - tcg_gen_mov_i64(cpu_iasq_b, new_spc); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, + -1, tmp, new_spc); nullify_set(ctx, a->n); } tcg_gen_lookup_and_goto_ptr(); @@ -4042,11 +4047,8 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a) dest = do_ibranch_priv(ctx, dest); install_link(ctx, a->l, false); - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest); - if (ctx->iasq_b) { - tcg_gen_mov_i64(cpu_iasq_f, ctx->iasq_b); - } - tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, + -1, dest, space_select(ctx, 0, dest)); nullify_set(ctx, a->n); tcg_gen_lookup_and_goto_ptr(); ctx->base.is_jmp = DISAS_NORETURN; @@ -4782,13 +4784,7 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) } /* FALLTHRU */ case DISAS_IAQ_N_STALE_EXIT: - install_iaq_entries(ctx, fi, fv, bi, bv); - if (fs) { - tcg_gen_mov_i64(cpu_iasq_f, fs); - } - if (bs) { - tcg_gen_mov_i64(cpu_iasq_b, bs); - } + install_iaq_entries(ctx, fi, fv, fs, bi, bv, bs); nullify_save(ctx); if (is_jmp == DISAS_IAQ_N_STALE_EXIT) { tcg_gen_exit_tb(NULL, 0); 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 14/43] target/hppa: Add space argument to do_ibranch Date: Wed, 15 May 2024 11:40:14 +0200 Message-Id: <20240515094043.82850-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This allows unification of BE, BLR, BV, BVE with a common helper. Since we can now track space with IAQ_Next, we can now let the TranslationBlock continue across the delay slot with BE, BVE. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 76 ++++++++++++++--------------------------- 1 file changed, 26 insertions(+), 50 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index eed0f92db4..1758c6e1d4 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1914,8 +1914,8 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, /* Emit an unconditional branch to an indirect target. This handles nullification of the branch itself. */ -static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, - unsigned link, bool is_n) +static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, TCGv_i64 dspc, + unsigned link, bool with_sr0, bool is_n) { TCGv_i64 next; @@ -1923,10 +1923,10 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, next = tcg_temp_new_i64(); tcg_gen_mov_i64(next, dest); - install_link(ctx, link, false); + install_link(ctx, link, with_sr0); if (is_n) { if (use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, NULL, -1, NULL, NULL); + install_iaq_entries(ctx, -1, next, dspc, -1, NULL, NULL); nullify_set(ctx, 0); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; return true; @@ -1935,6 +1935,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, } ctx->iaoq_n = -1; ctx->iaoq_n_var = next; + ctx->iasq_n = dspc; return true; } @@ -1943,13 +1944,13 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, next = tcg_temp_new_i64(); tcg_gen_mov_i64(next, dest); - install_link(ctx, link, false); + install_link(ctx, link, with_sr0); if (is_n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, NULL, -1, NULL, NULL); + install_iaq_entries(ctx, -1, next, dspc, -1, NULL, NULL); nullify_set(ctx, 0); } else { install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, - -1, next, NULL); + -1, next, dspc); nullify_set(ctx, is_n); } @@ -3916,33 +3917,18 @@ static bool trans_depi_sar(DisasContext *ctx, arg_depi_sar *a) static bool trans_be(DisasContext *ctx, arg_be *a) { - TCGv_i64 tmp; + TCGv_i64 dest = tcg_temp_new_i64(); + TCGv_i64 space = NULL; - tmp = tcg_temp_new_i64(); - tcg_gen_addi_i64(tmp, load_gpr(ctx, a->b), a->disp); - tmp = do_ibranch_priv(ctx, tmp); + tcg_gen_addi_i64(dest, load_gpr(ctx, a->b), a->disp); + dest = do_ibranch_priv(ctx, dest); -#ifdef CONFIG_USER_ONLY - return do_ibranch(ctx, tmp, a->l, a->n); -#else - TCGv_i64 new_spc = tcg_temp_new_i64(); - - nullify_over(ctx); - - load_spr(ctx, new_spc, a->sp); - install_link(ctx, a->l, true); - if (a->n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, tmp, new_spc, -1, NULL, new_spc); - nullify_set(ctx, 0); - } else { - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, - -1, tmp, new_spc); - nullify_set(ctx, a->n); - } - tcg_gen_lookup_and_goto_ptr(); - ctx->base.is_jmp = DISAS_NORETURN; - return nullify_end(ctx); +#ifndef CONFIG_USER_ONLY + space = tcg_temp_new_i64(); + load_spr(ctx, space, a->sp); #endif + + return do_ibranch(ctx, dest, space, a->l, true, a->n); } static bool trans_bl(DisasContext *ctx, arg_bl *a) @@ -4011,7 +3997,7 @@ static bool trans_blr(DisasContext *ctx, arg_blr *a) tcg_gen_shli_i64(tmp, load_gpr(ctx, a->x), 3); tcg_gen_addi_i64(tmp, tmp, ctx->iaoq_f + 8); /* The computation here never changes privilege level. */ - return do_ibranch(ctx, tmp, a->l, a->n); + return do_ibranch(ctx, tmp, NULL, a->l, false, a->n); } else { /* BLR R0,RX is a good way to load PC+8 into RX. */ return do_dbranch(ctx, 0, a->l, a->n); @@ -4030,30 +4016,20 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a) tcg_gen_add_i64(dest, dest, load_gpr(ctx, a->b)); } dest = do_ibranch_priv(ctx, dest); - return do_ibranch(ctx, dest, 0, a->n); + return do_ibranch(ctx, dest, NULL, 0, false, a->n); } static bool trans_bve(DisasContext *ctx, arg_bve *a) { - TCGv_i64 dest; + TCGv_i64 b = load_gpr(ctx, a->b); + TCGv_i64 dest = do_ibranch_priv(ctx, b); + TCGv_i64 space = NULL; -#ifdef CONFIG_USER_ONLY - dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); - return do_ibranch(ctx, dest, a->l, a->n); -#else - nullify_over(ctx); - dest = tcg_temp_new_i64(); - tcg_gen_mov_i64(dest, load_gpr(ctx, a->b)); - dest = do_ibranch_priv(ctx, dest); - - install_link(ctx, a->l, false); - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, - -1, dest, space_select(ctx, 0, dest)); - nullify_set(ctx, a->n); - tcg_gen_lookup_and_goto_ptr(); - ctx->base.is_jmp = DISAS_NORETURN; - return nullify_end(ctx); +#ifndef CONFIG_USER_ONLY + space = space_select(ctx, 0, b); #endif + + return do_ibranch(ctx, dest, space, a->l, false, a->n); } static bool trans_nopbts(DisasContext *ctx, arg_nopbts *a) From patchwork Wed May 15 09:40:15 2024 Content-Type: text/plain; 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 15/43] target/hppa: Use umax in do_ibranch_priv Date: Wed, 15 May 2024 11:40:15 +0200 Message-Id: <20240515094043.82850-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Using umax is clearer than the same operation using movcond. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 1758c6e1d4..e9ba792065 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1982,7 +1982,7 @@ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset) dest = tcg_temp_new_i64(); tcg_gen_andi_i64(dest, offset, -4); tcg_gen_ori_i64(dest, dest, ctx->privilege); - tcg_gen_movcond_i64(TCG_COND_GTU, dest, dest, offset, dest, offset); + tcg_gen_umax_i64(dest, dest, offset); break; } return dest; From patchwork Wed May 15 09:40:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796929 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2890932wra; Wed, 15 May 2024 02:44:19 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVF07kHvQB80dErgXAun5mQ8qKWrwxIWU+UJuRzbZrDj0Qo94PZixoTUUzGorx2NS/ULd4hj54Z0WafADRFDZpc X-Google-Smtp-Source: AGHT+IGG5NeJUUEdimitAm0TOkY0Xh3P/4oE04MZkn4iWUyr+lhM+f+dkesWAJenFKijKXU2vFbv X-Received: by 2002:a05:6214:2c01:b0:6a0:b4fd:c7b0 with SMTP id 6a1803df08f44-6a16816a4f2mr174574226d6.32.1715766258871; Wed, 15 May 2024 02:44:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766258; cv=none; d=google.com; s=arc-20160816; b=Diue3TVLUCsOFnLSudpdXon3th6XK5681cdKshLhRISVUhjVd2HuJTGCZBQNZDZeGG 8/rsFg/dSDVCPARPT3qVQVT08wD7lfZuZo3Ai/T9AefMEokZuQdDoHo4YDdyiHb2Kvm0 nyqQgJfDRXV8/98nN9LYjUE3LZCtTUkV9rdt0IyJC0e/QEKdlX1pTCN4Ew/cZOy8IW1e EpyePQ9aKGI0YKHiFEsabSTbitWX+7IizBE4TwtyMab09ugnYtl9L8j9cJtCjxQf/+Ee uI5ZyBuJJyLbyGzvoqfarsyTQ6WsywmamUhBogUs6VAtisWtFo1lrE45n6Yh8DbNbdG0 msKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YfJJCi+4YxuFZhkV51ZJx0iiIuxKudoNy6Mn9JaLA38=; fh=kQadAhxV42GJ3cd2VUw1RyURv/zJQGvmUdF7iLEVTtc=; b=jAZKsBqaAwhi7kjxNd0zauSu65uUsVPUfHQbHiMUO03XFGIbper2pkB/NJxYXyvKMl KiI3oSKy44F1vGIXq6Vwdu1/FTyG7q49Au1e/m7rl38EpaS1HuVKKTx/51Ec/KzrWfs4 PHqCrN4Q9iA79hbC17Y0RCP1cqYZM5q0KGcy30JDDCygsX6bC4gIIk+x20m0YjoQxIr9 9RPn6yjjxuttqhOIIqvOYa1bOeNU33j8yDGZw6cgFKwpRusQ7J1LYCLlErbzLRrVXZZt STebgDxtiOX+IJIYXviQ+siST8RAdZFtTYMKztKttqjG6oEWRQQmMsN0bD8/0PThv2Aq i8lA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=td2MOEQL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 16/43] target/hppa: Always make a copy in do_ibranch_priv Date: Wed, 15 May 2024 11:40:16 +0200 Message-Id: <20240515094043.82850-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This simplifies callers, which might otherwise have to make another copy. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e9ba792065..1ede4bd725 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1968,18 +1968,17 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, TCGv_i64 dspc, */ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset) { - TCGv_i64 dest; + TCGv_i64 dest = tcg_temp_new_i64(); switch (ctx->privilege) { case 0: /* Privilege 0 is maximum and is allowed to decrease. */ - return offset; + tcg_gen_mov_i64(dest, offset); + break; case 3: /* Privilege 3 is minimum and is never allowed to increase. */ - dest = tcg_temp_new_i64(); tcg_gen_ori_i64(dest, offset, 3); break; default: - dest = tcg_temp_new_i64(); tcg_gen_andi_i64(dest, offset, -4); tcg_gen_ori_i64(dest, dest, ctx->privilege); tcg_gen_umax_i64(dest, dest, offset); From patchwork Wed May 15 09:40:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796950 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2892599wra; Wed, 15 May 2024 02:49:48 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWSUjEOVbU+wD6B0Uw6ryrDiBkSjRdq77JgCu4VXUYpbdcplEOFPGX/fFlzsD9Pb+yPViFIllp0Ng69V+Jb3IOI X-Google-Smtp-Source: AGHT+IHd3iiR+buINVg8pfJPy4ZfTKT/P5cciOLpgaJZ24SnOE/O/D8IlRef6QZNn4V4y+E4suPE X-Received: by 2002:a05:620a:119b:b0:792:9b65:b2d6 with SMTP id af79cd13be357-792c6c3ad7emr2693689985a.5.1715766588637; Wed, 15 May 2024 02:49:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766588; cv=none; d=google.com; s=arc-20160816; b=kYiLwUu0jtd6t1MkmMzlujBEYolRmS5qxck5YbznnhxYxWiTl50RfmDfEi5uSESyw+ GQ6PwhPqjFjIidwHdkmefCJUon281eR8m2TvIowptksGHN/BjIKJMs7U8pKsHftiRzOj YJ5DKGWy6oAS0Aarra7GP/G991BUsT2tqOXncC7Z5364rCsm455NaLUTV7KYPWMsv8Rm fzGZ847HuVodMPGhcg5SSTp4pAZ1lCizAVVzHyzZ58ECSclRFSIlvdqPT7io0BQ1Nfr0 43Yf/INrD6vIjEXCxLfTvMXfDIBj7icWTcOtsF6H/+dgOim83niokjDVEilNRUCmqTq7 iroQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=x9vD3QA0hSAnzVhzL4fCLzND1tEPhJQEChXFiX7AsQA=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=yH5j4I8vEaQ3TLbibXvKK1JcTYv8IqolvMpOihSXfVrQZx3dvUJYscwrIXvqsvHJzW xM6VmCO2ZuwgJhfOamLbKGlaeI87GobdOj4WpDwM5tAUomQQpMbZfeEey0esqH0DT5RF f+OCA/ZFuQXbadvBRDNS4WUaLzZWYGVID4KGTSDLZ/jSoktCnnEJmpGoK2fPY3VzBz9Q UjhQ6QMWc5swZJawQH/YhXJZHHcN+mb08geT/Pc4XF8B8offbsSe1cy/gvXXLPsBoa/Y UU91FFtWTkMbdN8cxYUVPqbTAlZPyC2wtG8h01ds3P6QF7ND7D1E2bBvfEiruWLBEHnC g1Tg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xtZLFfLU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 17/43] target/hppa: Introduce and use DisasIAQE for branch management Date: Wed, 15 May 2024 11:40:17 +0200 Message-Id: <20240515094043.82850-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Wrap offset and space together in one structure, ensuring that they're copied together as required. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 378 +++++++++++++++++++++------------------- 1 file changed, 198 insertions(+), 180 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 1ede4bd725..e0e4db75ee 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -42,21 +42,23 @@ typedef struct DisasCond { TCGv_i64 a0, a1; } DisasCond; +typedef struct DisasIAQE { + /* IASQ; may be null for no change from TB. */ + TCGv_i64 space; + /* IAOQ base; may be null for immediate absolute address. */ + TCGv_i64 base; + /* IAOQ addend; absolute immedate address if base is null. */ + int64_t disp; +} DisasIAQE; + typedef struct DisasContext { DisasContextBase base; CPUState *cs; - uint64_t iaoq_f; - uint64_t iaoq_b; - uint64_t iaoq_n; - TCGv_i64 iaoq_n_var; - /* - * Null when IASQ_Back unchanged from IASQ_Front, - * or cpu_iasq_b, when IASQ_Back has been changed. - */ - TCGv_i64 iasq_b; - /* Null when IASQ_Next unchanged from IASQ_Back, or set by branch. */ - TCGv_i64 iasq_n; + /* IAQ_Front, IAQ_Back. */ + DisasIAQE iaq_f, iaq_b; + /* IAQ_Next, for jumps, otherwise null for simple advance. */ + DisasIAQE iaq_j, *iaq_n; DisasCond null_cond; TCGLabel *null_lab; @@ -602,49 +604,67 @@ static bool nullify_end(DisasContext *ctx) return true; } +static bool iaqe_variable(const DisasIAQE *e) +{ + return e->base || e->space; +} + +static DisasIAQE iaqe_incr(const DisasIAQE *e, int64_t disp) +{ + return (DisasIAQE){ + .space = e->space, + .base = e->base, + .disp = e->disp + disp, + }; +} + +static DisasIAQE iaqe_branchi(DisasContext *ctx, int64_t disp) +{ + return (DisasIAQE){ + .space = ctx->iaq_b.space, + .disp = ctx->iaq_f.disp + 8 + disp, + }; +} + +static DisasIAQE iaqe_next_absv(DisasContext *ctx, TCGv_i64 var) +{ + return (DisasIAQE){ + .space = ctx->iaq_b.space, + .base = var, + }; +} + static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, - uint64_t ival, TCGv_i64 vval) + const DisasIAQE *src) { uint64_t mask = gva_offset_mask(ctx->tb_flags); - if (ival != -1) { - tcg_gen_movi_i64(dest, ival & mask); - return; - } - tcg_debug_assert(vval != NULL); - - /* - * We know that the IAOQ is already properly masked. - * This optimization is primarily for "iaoq_f = iaoq_b". - */ - if (vval == cpu_iaoq_f || vval == cpu_iaoq_b) { - tcg_gen_mov_i64(dest, vval); + if (src->base == NULL) { + tcg_gen_movi_i64(dest, src->disp & mask); + } else if (src->disp == 0) { + tcg_gen_andi_i64(dest, src->base, mask); } else { - tcg_gen_andi_i64(dest, vval, mask); + tcg_gen_addi_i64(dest, src->base, src->disp); + tcg_gen_andi_i64(dest, dest, mask); } } -static void install_iaq_entries(DisasContext *ctx, - uint64_t bi, TCGv_i64 bv, TCGv_i64 bs, - uint64_t ni, TCGv_i64 nv, TCGv_i64 ns) +static void install_iaq_entries(DisasContext *ctx, const DisasIAQE *f, + const DisasIAQE *b) { - copy_iaoq_entry(ctx, cpu_iaoq_f, bi, bv); + DisasIAQE b_next; - /* Allow ni variable, with nv null, to indicate a trivial advance. */ - if (ni != -1 || nv) { - copy_iaoq_entry(ctx, cpu_iaoq_b, ni, nv); - } else if (bi != -1) { - copy_iaoq_entry(ctx, cpu_iaoq_b, bi + 4, NULL); - } else { - tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, 4); - tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, - gva_offset_mask(ctx->tb_flags)); + if (b == NULL) { + b_next = iaqe_incr(f, 4); + b = &b_next; } - if (bs) { - tcg_gen_mov_i64(cpu_iasq_f, bs); + copy_iaoq_entry(ctx, cpu_iaoq_f, f); + copy_iaoq_entry(ctx, cpu_iaoq_b, b); + if (f->space) { + tcg_gen_mov_i64(cpu_iasq_f, f->space); } - if (ns || bs) { - tcg_gen_mov_i64(cpu_iasq_b, ns ? ns : bs); + if (b->space || f->space) { + tcg_gen_mov_i64(cpu_iasq_b, b->space ? : f->space); } } @@ -654,10 +674,11 @@ static void install_link(DisasContext *ctx, unsigned link, bool with_sr0) if (!link) { return; } - if (ctx->iaoq_b == -1) { - tcg_gen_addi_i64(cpu_gr[link], cpu_iaoq_b, 4); + if (ctx->iaq_b.base) { + tcg_gen_addi_i64(cpu_gr[link], ctx->iaq_b.base, + ctx->iaq_b.disp + 4); } else { - tcg_gen_movi_i64(cpu_gr[link], ctx->iaoq_b + 4); + tcg_gen_movi_i64(cpu_gr[link], ctx->iaq_b.disp + 4); } #ifndef CONFIG_USER_ONLY if (with_sr0) { @@ -666,11 +687,6 @@ static void install_link(DisasContext *ctx, unsigned link, bool with_sr0) #endif } -static inline uint64_t iaoq_dest(DisasContext *ctx, int64_t disp) -{ - return ctx->iaoq_f + disp + 8; -} - static void gen_excp_1(int exception) { gen_helper_excp(tcg_env, tcg_constant_i32(exception)); @@ -678,8 +694,7 @@ static void gen_excp_1(int exception) static void gen_excp(DisasContext *ctx, int exception) { - install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, NULL, - ctx->iaoq_b, cpu_iaoq_b, NULL); + install_iaq_entries(ctx, &ctx->iaq_f, &ctx->iaq_b); nullify_save(ctx); gen_excp_1(exception); ctx->base.is_jmp = DISAS_NORETURN; @@ -711,10 +726,12 @@ static bool gen_illegal(DisasContext *ctx) } while (0) #endif -static bool use_goto_tb(DisasContext *ctx, uint64_t bofs, uint64_t nofs) +static bool use_goto_tb(DisasContext *ctx, const DisasIAQE *f, + const DisasIAQE *b) { - return (bofs != -1 && nofs != -1 && - translator_use_goto_tb(&ctx->base, bofs)); + return (!iaqe_variable(f) && + (b == NULL || !iaqe_variable(b)) && + translator_use_goto_tb(&ctx->base, f->disp)); } /* If the next insn is to be nullified, and it's on the same page, @@ -724,20 +741,19 @@ static bool use_goto_tb(DisasContext *ctx, uint64_t bofs, uint64_t nofs) static bool use_nullify_skip(DisasContext *ctx) { return (!(tb_cflags(ctx->base.tb) & CF_BP_PAGE) - && ctx->iaoq_b != -1 - && is_same_page(&ctx->base, ctx->iaoq_b)); + && !iaqe_variable(&ctx->iaq_b) + && is_same_page(&ctx->base, ctx->iaq_b.disp)); } static void gen_goto_tb(DisasContext *ctx, int which, - uint64_t b, uint64_t n) + const DisasIAQE *f, const DisasIAQE *b) { - if (use_goto_tb(ctx, b, n)) { + if (use_goto_tb(ctx, f, b)) { tcg_gen_goto_tb(which); - install_iaq_entries(ctx, b, NULL, NULL, n, NULL, NULL); + install_iaq_entries(ctx, f, b); tcg_gen_exit_tb(ctx->base.tb, which); } else { - install_iaq_entries(ctx, b, cpu_iaoq_b, ctx->iasq_b, - n, ctx->iaoq_n_var, ctx->iasq_n); + install_iaq_entries(ctx, f, b); tcg_gen_lookup_and_goto_ptr(); } } @@ -1818,37 +1834,35 @@ static bool do_fop_dedd(DisasContext *ctx, unsigned rt, static bool do_dbranch(DisasContext *ctx, int64_t disp, unsigned link, bool is_n) { - uint64_t dest = iaoq_dest(ctx, disp); + ctx->iaq_j = iaqe_branchi(ctx, disp); if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { install_link(ctx, link, false); if (is_n) { if (use_nullify_skip(ctx)) { nullify_set(ctx, 0); - gen_goto_tb(ctx, 0, dest, dest + 4); + gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); ctx->base.is_jmp = DISAS_NORETURN; return true; } ctx->null_cond.c = TCG_COND_ALWAYS; } - ctx->iaoq_n = dest; - ctx->iaoq_n_var = NULL; + ctx->iaq_n = &ctx->iaq_j; } else { nullify_over(ctx); install_link(ctx, link, false); if (is_n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); - gen_goto_tb(ctx, 0, dest, dest + 4); + gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); } else { nullify_set(ctx, is_n); - gen_goto_tb(ctx, 0, ctx->iaoq_b, dest); + gen_goto_tb(ctx, 0, &ctx->iaq_b, &ctx->iaq_j); } - nullify_end(ctx); nullify_set(ctx, 0); - gen_goto_tb(ctx, 1, ctx->iaoq_b, ctx->iaoq_n); + gen_goto_tb(ctx, 1, &ctx->iaq_b, NULL); ctx->base.is_jmp = DISAS_NORETURN; } return true; @@ -1859,7 +1873,7 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, DisasCond *cond) { - uint64_t dest = iaoq_dest(ctx, disp); + DisasIAQE next; TCGLabel *taken = NULL; TCGCond c = cond->c; bool n; @@ -1879,26 +1893,29 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, n = is_n && disp < 0; if (n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); - gen_goto_tb(ctx, 0, ctx->iaoq_n, ctx->iaoq_n + 4); + next = iaqe_incr(&ctx->iaq_b, 4); + gen_goto_tb(ctx, 0, &next, NULL); } else { if (!n && ctx->null_lab) { gen_set_label(ctx->null_lab); ctx->null_lab = NULL; } nullify_set(ctx, n); - gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); + gen_goto_tb(ctx, 0, &ctx->iaq_b, NULL); } gen_set_label(taken); /* Taken: Condition satisfied; nullify on forward branches. */ n = is_n && disp >= 0; + + next = iaqe_branchi(ctx, disp); if (n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); - gen_goto_tb(ctx, 1, dest, dest + 4); + gen_goto_tb(ctx, 1, &next, NULL); } else { nullify_set(ctx, n); - gen_goto_tb(ctx, 1, ctx->iaoq_b, dest); + gen_goto_tb(ctx, 1, &ctx->iaq_b, &next); } /* Not taken: the branch itself was nullified. */ @@ -1912,45 +1929,36 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, return true; } -/* Emit an unconditional branch to an indirect target. This handles - nullification of the branch itself. */ -static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, TCGv_i64 dspc, - unsigned link, bool with_sr0, bool is_n) +/* + * Emit an unconditional branch to an indirect target, in ctx->iaq_j. + * This handles nullification of the branch itself. + */ +static bool do_ibranch(DisasContext *ctx, unsigned link, + bool with_sr0, bool is_n) { - TCGv_i64 next; - if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { - next = tcg_temp_new_i64(); - tcg_gen_mov_i64(next, dest); - install_link(ctx, link, with_sr0); if (is_n) { if (use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, dspc, -1, NULL, NULL); + install_iaq_entries(ctx, &ctx->iaq_j, NULL); nullify_set(ctx, 0); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; return true; } ctx->null_cond.c = TCG_COND_ALWAYS; } - ctx->iaoq_n = -1; - ctx->iaoq_n_var = next; - ctx->iasq_n = dspc; + ctx->iaq_n = &ctx->iaq_j; return true; } nullify_over(ctx); - next = tcg_temp_new_i64(); - tcg_gen_mov_i64(next, dest); - install_link(ctx, link, with_sr0); if (is_n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, dspc, -1, NULL, NULL); + install_iaq_entries(ctx, &ctx->iaq_j, NULL); nullify_set(ctx, 0); } else { - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, - -1, next, dspc); + install_iaq_entries(ctx, &ctx->iaq_b, &ctx->iaq_j); nullify_set(ctx, is_n); } @@ -1997,8 +2005,6 @@ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset) aforementioned BE. */ static void do_page_zero(DisasContext *ctx) { - TCGv_i64 tmp; - /* If by some means we get here with PSW[N]=1, that implies that the B,GATE instruction would be skipped, and we'd fault on the next insn within the privileged page. */ @@ -2018,11 +2024,11 @@ static void do_page_zero(DisasContext *ctx) non-sequential instruction execution. Normally the PSW[B] bit detects this by disallowing the B,GATE instruction to execute under such conditions. */ - if (ctx->iaoq_b != ctx->iaoq_f + 4) { + if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp != ctx->iaq_f.disp + 4) { goto do_sigill; } - switch (ctx->iaoq_f & -4) { + switch (ctx->iaq_f.disp & -4) { case 0x00: /* Null pointer call */ gen_excp_1(EXCP_IMP); ctx->base.is_jmp = DISAS_NORETURN; @@ -2034,11 +2040,15 @@ static void do_page_zero(DisasContext *ctx) break; case 0xe0: /* SET_THREAD_POINTER */ - tcg_gen_st_i64(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])); - tmp = tcg_temp_new_i64(); - tcg_gen_ori_i64(tmp, cpu_gr[31], 3); - install_iaq_entries(ctx, -1, tmp, NULL, -1, NULL, NULL); - ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; + { + DisasIAQE next = { .base = tcg_temp_new_i64() }; + + tcg_gen_st_i64(cpu_gr[26], tcg_env, + offsetof(CPUHPPAState, cr[27])); + tcg_gen_ori_i64(next.base, cpu_gr[31], 3); + install_iaq_entries(ctx, &next, NULL); + ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; + } break; case 0x100: /* SYSCALL */ @@ -2077,11 +2087,12 @@ static bool trans_sync(DisasContext *ctx, arg_sync *a) static bool trans_mfia(DisasContext *ctx, arg_mfia *a) { - unsigned rt = a->t; - TCGv_i64 tmp = dest_gpr(ctx, rt); - tcg_gen_movi_i64(tmp, ctx->iaoq_f & ~3ULL); - save_gpr(ctx, rt, tmp); + TCGv_i64 dest = dest_gpr(ctx, a->t); + copy_iaoq_entry(ctx, dest, &ctx->iaq_f); + tcg_gen_andi_i64(dest, dest, -4); + + save_gpr(ctx, a->t, dest); cond_free(&ctx->null_cond); return true; } @@ -2781,8 +2792,7 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) nullify_over(ctx); /* Advance the instruction queue. */ - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, - ctx->iaoq_n, ctx->iaoq_n_var, ctx->iasq_n); + install_iaq_entries(ctx, &ctx->iaq_b, NULL); nullify_set(ctx, 0); /* Tell the qemu main loop to halt until this cpu has work. */ @@ -3916,18 +3926,18 @@ static bool trans_depi_sar(DisasContext *ctx, arg_depi_sar *a) static bool trans_be(DisasContext *ctx, arg_be *a) { - TCGv_i64 dest = tcg_temp_new_i64(); - TCGv_i64 space = NULL; - - tcg_gen_addi_i64(dest, load_gpr(ctx, a->b), a->disp); - dest = do_ibranch_priv(ctx, dest); - #ifndef CONFIG_USER_ONLY - space = tcg_temp_new_i64(); - load_spr(ctx, space, a->sp); + ctx->iaq_j.space = tcg_temp_new_i64(); + load_spr(ctx, ctx->iaq_j.space, a->sp); #endif - return do_ibranch(ctx, dest, space, a->l, true, a->n); + ctx->iaq_j.base = tcg_temp_new_i64(); + ctx->iaq_j.disp = 0; + + tcg_gen_addi_i64(ctx->iaq_j.base, load_gpr(ctx, a->b), a->disp); + ctx->iaq_j.base = do_ibranch_priv(ctx, ctx->iaq_j.base); + + return do_ibranch(ctx, a->l, true, a->n); } static bool trans_bl(DisasContext *ctx, arg_bl *a) @@ -3937,7 +3947,7 @@ static bool trans_bl(DisasContext *ctx, arg_bl *a) static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) { - uint64_t dest = iaoq_dest(ctx, a->disp); + int64_t disp = a->disp; nullify_over(ctx); @@ -3952,7 +3962,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) * b evil * in which instructions at evil would run with increased privs. */ - if (ctx->iaoq_b == -1 || ctx->iaoq_b != ctx->iaoq_f + 4) { + if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp != ctx->iaq_f.disp + 4) { return gen_illegal(ctx); } @@ -3970,10 +3980,11 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) } /* No change for non-gateway pages or for priv decrease. */ if (type >= 4 && type - 4 < ctx->privilege) { - dest = deposit64(dest, 0, 2, type - 4); + disp -= ctx->privilege; + disp += type - 4; } } else { - dest &= -4; /* priv = 0 */ + disp -= ctx->privilege; /* priv = 0 */ } #endif @@ -3986,17 +3997,23 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) save_gpr(ctx, a->l, tmp); } - return do_dbranch(ctx, dest - iaoq_dest(ctx, 0), 0, a->n); + return do_dbranch(ctx, disp, 0, a->n); } static bool trans_blr(DisasContext *ctx, arg_blr *a) { if (a->x) { - TCGv_i64 tmp = tcg_temp_new_i64(); - tcg_gen_shli_i64(tmp, load_gpr(ctx, a->x), 3); - tcg_gen_addi_i64(tmp, tmp, ctx->iaoq_f + 8); + DisasIAQE next = iaqe_incr(&ctx->iaq_f, 8); + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + /* The computation here never changes privilege level. */ - return do_ibranch(ctx, tmp, NULL, a->l, false, a->n); + copy_iaoq_entry(ctx, t0, &next); + tcg_gen_shli_i64(t1, load_gpr(ctx, a->x), 3); + tcg_gen_add_i64(t0, t0, t1); + + ctx->iaq_j = iaqe_next_absv(ctx, t0); + return do_ibranch(ctx, a->l, false, a->n); } else { /* BLR R0,RX is a good way to load PC+8 into RX. */ return do_dbranch(ctx, 0, a->l, a->n); @@ -4015,20 +4032,22 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a) tcg_gen_add_i64(dest, dest, load_gpr(ctx, a->b)); } dest = do_ibranch_priv(ctx, dest); - return do_ibranch(ctx, dest, NULL, 0, false, a->n); + ctx->iaq_j = iaqe_next_absv(ctx, dest); + + return do_ibranch(ctx, 0, false, a->n); } static bool trans_bve(DisasContext *ctx, arg_bve *a) { TCGv_i64 b = load_gpr(ctx, a->b); - TCGv_i64 dest = do_ibranch_priv(ctx, b); - TCGv_i64 space = NULL; #ifndef CONFIG_USER_ONLY - space = space_select(ctx, 0, b); + ctx->iaq_j.space = space_select(ctx, 0, b); #endif + ctx->iaq_j.base = do_ibranch_priv(ctx, b); + ctx->iaq_j.disp = 0; - return do_ibranch(ctx, dest, space, a->l, false, a->n); + return do_ibranch(ctx, a->l, false, a->n); } static bool trans_nopbts(DisasContext *ctx, arg_nopbts *a) @@ -4600,9 +4619,8 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #ifdef CONFIG_USER_ONLY ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX); ctx->mmu_idx = MMU_USER_IDX; - ctx->iaoq_f = ctx->base.pc_first | ctx->privilege; - ctx->iaoq_b = ctx->base.tb->cs_base | ctx->privilege; - ctx->iasq_b = NULL; + ctx->iaq_f.disp = ctx->base.pc_first | ctx->privilege; + ctx->iaq_b.disp = ctx->base.tb->cs_base | ctx->privilege; ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; @@ -4615,9 +4633,13 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) uint64_t iasq_f = cs_base & ~0xffffffffull; int32_t diff = cs_base; - ctx->iaoq_f = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; - ctx->iaoq_b = (diff ? ctx->iaoq_f + diff : -1); - ctx->iasq_b = (diff ? NULL : cpu_iasq_b); + ctx->iaq_f.disp = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; + if (diff) { + ctx->iaq_b.disp = ctx->iaq_f.disp + diff; + } else { + ctx->iaq_b.base = cpu_iaoq_b; + ctx->iaq_b.space = cpu_iasq_b; + } #endif ctx->zero = tcg_constant_i64(0); @@ -4645,7 +4667,10 @@ static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b, 0); + tcg_debug_assert(!iaqe_variable(&ctx->iaq_f)); + tcg_gen_insn_start(ctx->iaq_f.disp, + iaqe_variable(&ctx->iaq_b) ? -1 : ctx->iaq_b.disp, + 0); ctx->insn_start_updated = false; } @@ -4668,11 +4693,12 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) the page permissions for execute. */ uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next); - /* Set up the IA queue for the next insn. - This will be overwritten by a branch. */ - ctx->iasq_n = NULL; - ctx->iaoq_n_var = NULL; - ctx->iaoq_n = ctx->iaoq_b == -1 ? -1 : ctx->iaoq_b + 4; + /* + * Set up the IA queue for the next insn. + * This will be overwritten by a branch. + */ + ctx->iaq_n = NULL; + memset(&ctx->iaq_j, 0, sizeof(ctx->iaq_j)); if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) { ctx->null_cond.c = TCG_COND_NEVER; @@ -4693,7 +4719,8 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) return; } /* Note this also detects a priority change. */ - if (ctx->iaoq_b != ctx->iaoq_f + 4 || ctx->iasq_b) { + if (iaqe_variable(&ctx->iaq_b) + || ctx->iaq_b.disp != ctx->iaq_f.disp + 4) { ctx->base.is_jmp = DISAS_IAQ_N_STALE; return; } @@ -4702,20 +4729,25 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) * Advance the insn queue. * The only exit now is DISAS_TOO_MANY from the translator loop. */ - ctx->iaoq_f = ctx->iaoq_b; - ctx->iaoq_b = ctx->iaoq_n; - if (ctx->iaoq_b == -1) { - if (ctx->iaoq_n_var) { - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, ctx->iaoq_n_var); - } else { - tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_b, 4); - tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, - gva_offset_mask(ctx->tb_flags)); - } + ctx->iaq_f.disp = ctx->iaq_b.disp; + if (!ctx->iaq_n) { + ctx->iaq_b.disp += 4; + return; } - if (ctx->iasq_n) { - tcg_gen_mov_i64(cpu_iasq_b, ctx->iasq_n); - ctx->iasq_b = cpu_iasq_b; + /* + * If IAQ_Next is variable in any way, we need to copy into the + * IAQ_Back globals, in case the next insn raises an exception. + */ + if (ctx->iaq_n->base) { + copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaq_n); + ctx->iaq_b.base = cpu_iaoq_b; + ctx->iaq_b.disp = 0; + } else { + ctx->iaq_b.disp = ctx->iaq_n->disp; + } + if (ctx->iaq_n->space) { + tcg_gen_mov_i64(cpu_iasq_b, ctx->iaq_n->space); + ctx->iaq_b.space = cpu_iasq_b; } } @@ -4723,43 +4755,29 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); DisasJumpType is_jmp = ctx->base.is_jmp; - uint64_t fi, bi; - TCGv_i64 fv, bv; - TCGv_i64 fs, bs; - /* Assume the insn queue has not been advanced. */ - fi = ctx->iaoq_b; - fv = cpu_iaoq_b; - fs = ctx->iasq_b; - bi = ctx->iaoq_n; - bv = ctx->iaoq_n_var; - bs = ctx->iasq_n; + DisasIAQE *f = &ctx->iaq_b; + DisasIAQE *b = ctx->iaq_n; switch (is_jmp) { case DISAS_NORETURN: break; case DISAS_TOO_MANY: /* The insn queue has not been advanced. */ - bi = fi; - bv = fv; - bs = fs; - fi = ctx->iaoq_f; - fv = NULL; - fs = NULL; + f = &ctx->iaq_f; + b = &ctx->iaq_b; /* FALLTHRU */ case DISAS_IAQ_N_STALE: - if (fs == NULL - && bs == NULL - && use_goto_tb(ctx, fi, bi) + if (use_goto_tb(ctx, f, b) && (ctx->null_cond.c == TCG_COND_NEVER || ctx->null_cond.c == TCG_COND_ALWAYS)) { nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); - gen_goto_tb(ctx, 0, fi, bi); + gen_goto_tb(ctx, 0, f, b); break; } /* FALLTHRU */ case DISAS_IAQ_N_STALE_EXIT: - install_iaq_entries(ctx, fi, fv, fs, bi, bv, bs); + install_iaq_entries(ctx, f, b); nullify_save(ctx); if (is_jmp == DISAS_IAQ_N_STALE_EXIT) { tcg_gen_exit_tb(NULL, 0); @@ -4815,6 +4833,6 @@ static const TranslatorOps hppa_tr_ops = { void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc) { - DisasContext ctx; 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 18/43] target/hppa: Use displacements in DisasIAQE Date: Wed, 15 May 2024 11:40:18 +0200 Message-Id: <20240515094043.82850-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is a first step in enabling CF_PCREL, but for now we regenerate the absolute address before writeback. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 43 ++++++++++++++++++++++------------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e0e4db75ee..de077e7a57 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -45,9 +45,9 @@ typedef struct DisasCond { typedef struct DisasIAQE { /* IASQ; may be null for no change from TB. */ TCGv_i64 space; - /* IAOQ base; may be null for immediate absolute address. */ + /* IAOQ base; may be null for relative address. */ TCGv_i64 base; - /* IAOQ addend; absolute immedate address if base is null. */ + /* IAOQ addend; if base is null, relative to ctx->iaoq_first. */ int64_t disp; } DisasIAQE; @@ -60,6 +60,9 @@ typedef struct DisasContext { /* IAQ_Next, for jumps, otherwise null for simple advance. */ DisasIAQE iaq_j, *iaq_n; + /* IAOQ_Front at entry to TB. */ + uint64_t iaoq_first; + DisasCond null_cond; TCGLabel *null_lab; @@ -640,7 +643,7 @@ static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, uint64_t mask = gva_offset_mask(ctx->tb_flags); if (src->base == NULL) { - tcg_gen_movi_i64(dest, src->disp & mask); + tcg_gen_movi_i64(dest, (ctx->iaoq_first + src->disp) & mask); } else if (src->disp == 0) { tcg_gen_andi_i64(dest, src->base, mask); } else { @@ -674,12 +677,8 @@ static void install_link(DisasContext *ctx, unsigned link, bool with_sr0) if (!link) { return; } - if (ctx->iaq_b.base) { - tcg_gen_addi_i64(cpu_gr[link], ctx->iaq_b.base, - ctx->iaq_b.disp + 4); - } else { - tcg_gen_movi_i64(cpu_gr[link], ctx->iaq_b.disp + 4); - } + DisasIAQE next = iaqe_incr(&ctx->iaq_b, 4); + copy_iaoq_entry(ctx, cpu_gr[link], &next); #ifndef CONFIG_USER_ONLY if (with_sr0) { tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_b); @@ -731,7 +730,7 @@ static bool use_goto_tb(DisasContext *ctx, const DisasIAQE *f, { return (!iaqe_variable(f) && (b == NULL || !iaqe_variable(b)) && - translator_use_goto_tb(&ctx->base, f->disp)); + translator_use_goto_tb(&ctx->base, ctx->iaoq_first + f->disp)); } /* If the next insn is to be nullified, and it's on the same page, @@ -742,7 +741,8 @@ static bool use_nullify_skip(DisasContext *ctx) { return (!(tb_cflags(ctx->base.tb) & CF_BP_PAGE) && !iaqe_variable(&ctx->iaq_b) - && is_same_page(&ctx->base, ctx->iaq_b.disp)); + && (((ctx->iaoq_first + ctx->iaq_b.disp) ^ ctx->iaoq_first) + & TARGET_PAGE_MASK) == 0); } static void gen_goto_tb(DisasContext *ctx, int which, @@ -2005,6 +2005,8 @@ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset) aforementioned BE. */ static void do_page_zero(DisasContext *ctx) { + assert(ctx->iaq_f.disp == 0); + /* If by some means we get here with PSW[N]=1, that implies that the B,GATE instruction would be skipped, and we'd fault on the next insn within the privileged page. */ @@ -2024,11 +2026,11 @@ static void do_page_zero(DisasContext *ctx) non-sequential instruction execution. Normally the PSW[B] bit detects this by disallowing the B,GATE instruction to execute under such conditions. */ - if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp != ctx->iaq_f.disp + 4) { + if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp != 4) { goto do_sigill; } - switch (ctx->iaq_f.disp & -4) { + switch (ctx->base.pc_first) { case 0x00: /* Null pointer call */ gen_excp_1(EXCP_IMP); ctx->base.is_jmp = DISAS_NORETURN; @@ -4619,8 +4621,8 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #ifdef CONFIG_USER_ONLY ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX); ctx->mmu_idx = MMU_USER_IDX; - ctx->iaq_f.disp = ctx->base.pc_first | ctx->privilege; - ctx->iaq_b.disp = ctx->base.tb->cs_base | ctx->privilege; + ctx->iaoq_first = ctx->base.pc_first | ctx->privilege; + ctx->iaq_b.disp = ctx->base.tb->cs_base - ctx->base.pc_first; ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; @@ -4633,9 +4635,10 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) uint64_t iasq_f = cs_base & ~0xffffffffull; int32_t diff = cs_base; - ctx->iaq_f.disp = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; + ctx->iaoq_first = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; + if (diff) { - ctx->iaq_b.disp = ctx->iaq_f.disp + diff; + ctx->iaq_b.disp = diff; } else { ctx->iaq_b.base = cpu_iaoq_b; ctx->iaq_b.space = cpu_iasq_b; @@ -4668,9 +4671,9 @@ static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) DisasContext *ctx = container_of(dcbase, DisasContext, base); tcg_debug_assert(!iaqe_variable(&ctx->iaq_f)); - tcg_gen_insn_start(ctx->iaq_f.disp, - iaqe_variable(&ctx->iaq_b) ? -1 : ctx->iaq_b.disp, - 0); + tcg_gen_insn_start(ctx->iaoq_first + ctx->iaq_f.disp, + (iaqe_variable(&ctx->iaq_b) ? -1 : + ctx->iaoq_first + ctx->iaq_b.disp), 0); ctx->insn_start_updated = false; } From patchwork Wed May 15 09:40:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796912 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2890018wra; Wed, 15 May 2024 02:41:35 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVcFse7UWLSCzPbLjrKbtWyp4v/WDm9nECfzJ+rXHvg1FU9ns1LLUEVoP6NjKuTB6aAIQqGXmMXZm7YmLN/rCAZ X-Google-Smtp-Source: AGHT+IFDyhf5I0uHnGqBbMB82gdzuRn16ZbAG/UcAcL5rVFegpx3Lh4NBHmbhfBu/3NXqFG+eA6U X-Received: by 2002:ac8:7e95:0:b0:43a:8877:e372 with SMTP id d75a77b69052e-43dfdd1b465mr173864051cf.48.1715766094903; Wed, 15 May 2024 02:41:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766094; cv=none; d=google.com; s=arc-20160816; b=DsKATUeK7PB9Xka6V4MZJ7CQG5uNoL5rJhvINQ4j9yw/QXwgsi+tQNxjyb4b3sbpx+ fZr3Mgd9An0voBmQDdpJcUXDJhtsSkOSbJSVQR4qxxi53Rt36kmMsn4oI9CjyHG89GRl 2+UgyODzEHJsYaqLJZ3PShnUlXw+D2Dristwg8wQzAZJU57jpjo3IFn5dd2sVax7TXtp EsVH3rTRX0VB7TdayYtHQq88VEUYiqPHFVqdk37/rbq9yHvy4tCJug/701V1oFs1RX9V nBRvMMm99rjR2HSCDPRE97xRtqSGUNk5DqnCQvbHSuQ0QnM6CqQpfZmjcKAW0OuknRPL bDRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=l70NVTnTNxZE1g+5+378o7Svk1vAno2NTsB+Y4jn2m0=; fh=3//KcqJEsa04kIBt5Nb/DJuP+2GuH1NwDRxnSl44zdw=; b=e+4pRNzNfELzMjhR6V8N2UAoviRUDEy449rIRaW8hWoZC7FctwKpTmu/NUcLRd18Qw 5cK0YGKpuJMTLpkqz58LzgX72Ps+eVFQnDcIY5uYBEHFYNHGdi7HzOWdwSNYNYurBNmg J5O1uvROI+3XhxJhT5xdEcOJufYCO35THIl+11AyQoPd/rHz8SZBRyEnvHs4PYfXmNFY KATx4FCuqzoDk0KRVocEpLgCbGgK/jXeuVDY7zVVrqGJFpM3d5U6xkkwXZEDPhtE0ReU fKn8LZ7qccVB2STcQv3G5dZRh4J46ToKpTvbOe4CdnwgmGE/XV+DoVZFti9/iKoQA/Xb gsWA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rSMw25bD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 19/43] target/hppa: Rename cond_make_* helpers Date: Wed, 15 May 2024 11:40:19 +0200 Message-Id: <20240515094043.82850-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use 'v' for a variable that needs copying, 't' for a temp that doesn't need copying, and 'i' for an immediate, and use this naming for both arguments of the comparison. So: cond_make_tmp -> cond_make_tt cond_make_0_tmp -> cond_make_ti cond_make_0 -> cond_make_vi cond_make -> cond_make_vv Pass 0 explictly, rather than implicitly in the function name. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 52 ++++++++++++++++++++--------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index de077e7a57..07ba35001b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -345,32 +345,32 @@ static DisasCond cond_make_n(void) }; } -static DisasCond cond_make_tmp(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) +static DisasCond cond_make_tt(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) { assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS); return (DisasCond){ .c = c, .a0 = a0, .a1 = a1 }; } -static DisasCond cond_make_0_tmp(TCGCond c, TCGv_i64 a0) +static DisasCond cond_make_ti(TCGCond c, TCGv_i64 a0, uint64_t imm) { - return cond_make_tmp(c, a0, tcg_constant_i64(0)); + return cond_make_tt(c, a0, tcg_constant_i64(imm)); } -static DisasCond cond_make_0(TCGCond c, TCGv_i64 a0) +static DisasCond cond_make_vi(TCGCond c, TCGv_i64 a0, uint64_t imm) { TCGv_i64 tmp = tcg_temp_new_i64(); tcg_gen_mov_i64(tmp, a0); - return cond_make_0_tmp(c, tmp); + return cond_make_ti(c, tmp, imm); } -static DisasCond cond_make(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) +static DisasCond cond_make_vv(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) { TCGv_i64 t0 = tcg_temp_new_i64(); TCGv_i64 t1 = tcg_temp_new_i64(); tcg_gen_mov_i64(t0, a0); tcg_gen_mov_i64(t1, a1); - return cond_make_tmp(c, t0, t1); + return cond_make_tt(c, t0, t1); } static void cond_free(DisasCond *cond) @@ -789,7 +789,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, tcg_gen_ext32u_i64(tmp, res); res = tmp; } - cond = cond_make_0(TCG_COND_EQ, res); + cond = cond_make_vi(TCG_COND_EQ, res, 0); break; case 2: /* < / >= (N ^ V / !(N ^ V) */ tmp = tcg_temp_new_i64(); @@ -797,7 +797,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, if (!d) { tcg_gen_ext32s_i64(tmp, tmp); } - cond = cond_make_0_tmp(TCG_COND_LT, tmp); + cond = cond_make_ti(TCG_COND_LT, tmp, 0); break; case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */ /* @@ -819,10 +819,10 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, tcg_gen_sari_i64(tmp, tmp, 63); tcg_gen_and_i64(tmp, tmp, res); } - cond = cond_make_0_tmp(TCG_COND_EQ, tmp); + cond = cond_make_ti(TCG_COND_EQ, tmp, 0); break; case 4: /* NUV / UV (!UV / UV) */ - cond = cond_make_0(TCG_COND_EQ, uv); + cond = cond_make_vi(TCG_COND_EQ, uv, 0); break; case 5: /* ZNV / VNZ (!UV | Z / UV & !Z) */ tmp = tcg_temp_new_i64(); @@ -830,7 +830,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, if (!d) { tcg_gen_ext32u_i64(tmp, tmp); } - cond = cond_make_0_tmp(TCG_COND_EQ, tmp); + cond = cond_make_ti(TCG_COND_EQ, tmp, 0); break; case 6: /* SV / NSV (V / !V) */ if (!d) { @@ -838,12 +838,12 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, tcg_gen_ext32s_i64(tmp, sv); sv = tmp; } - cond = cond_make_0(TCG_COND_LT, sv); + cond = cond_make_ti(TCG_COND_LT, sv, 0); break; case 7: /* OD / EV */ tmp = tcg_temp_new_i64(); tcg_gen_andi_i64(tmp, res, 1); - cond = cond_make_0_tmp(TCG_COND_NE, tmp); + cond = cond_make_ti(TCG_COND_NE, tmp, 0); break; default: g_assert_not_reached(); @@ -905,9 +905,9 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d, tcg_gen_ext32s_i64(t1, in1); tcg_gen_ext32s_i64(t2, in2); } - return cond_make_tmp(tc, t1, t2); + return cond_make_tt(tc, t1, t2); } - return cond_make(tc, in1, in2); + return cond_make_vv(tc, in1, in2); } /* @@ -979,9 +979,9 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d, } else { tcg_gen_ext32s_i64(tmp, res); } - return cond_make_0_tmp(tc, tmp); + return cond_make_ti(tc, tmp, 0); } - return cond_make_0(tc, res); + return cond_make_vi(tc, res, 0); } /* Similar, but for shift/extract/deposit conditions. */ @@ -1040,7 +1040,7 @@ static DisasCond do_unit_zero_cond(unsigned cf, bool d, TCGv_i64 res) tcg_gen_andc_i64(tmp, tmp, res); tcg_gen_andi_i64(tmp, tmp, sgns); - return cond_make_0_tmp(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, tmp); + return cond_make_ti(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, tmp, 0); } static TCGv_i64 get_carry(DisasContext *ctx, bool d, @@ -1454,7 +1454,7 @@ static void do_unit_addsub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, } tcg_gen_andi_i64(cb, cb, test_cb); - cond = cond_make_0_tmp(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, cb); + cond = cond_make_ti(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, cb, 0); } if (is_tc) { @@ -3543,7 +3543,7 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) tcg_gen_shl_i64(tmp, tcg_r, tmp); } - cond = cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); + cond = cond_make_ti(a->c ? TCG_COND_GE : TCG_COND_LT, tmp, 0); return do_cbranch(ctx, a->disp, a->n, &cond); } @@ -3560,7 +3560,7 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) p = a->p | (a->d ? 0 : 32); tcg_gen_shli_i64(tmp, tcg_r, p); - cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); + cond = cond_make_ti(a->c ? TCG_COND_GE : TCG_COND_LT, tmp, 0); return do_cbranch(ctx, a->disp, a->n, &cond); } @@ -4364,7 +4364,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a) switch (a->c) { case 0: /* simple */ tcg_gen_andi_i64(t, t, 0x4000000); - ctx->null_cond = cond_make_0(TCG_COND_NE, t); + ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0); goto done; case 2: /* rej */ inv = true; @@ -4394,16 +4394,16 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a) if (inv) { TCGv_i64 c = tcg_constant_i64(mask); tcg_gen_or_i64(t, t, c); - ctx->null_cond = cond_make(TCG_COND_EQ, t, c); + ctx->null_cond = cond_make_tt(TCG_COND_EQ, t, c); } else { tcg_gen_andi_i64(t, t, mask); - ctx->null_cond = cond_make_0(TCG_COND_EQ, t); + ctx->null_cond = cond_make_ti(TCG_COND_EQ, t, 0); } } else { unsigned cbit = (a->y ^ 1) - 1; tcg_gen_extract_i64(t, t, 21 - cbit, 1); - ctx->null_cond = cond_make_0(TCG_COND_NE, t); + ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0); } done: From patchwork Wed May 15 09:40:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796917 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2890123wra; Wed, 15 May 2024 02:41:52 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUQWoGtGudRzJ4cjIKUNChJ/k/x29cyqOKs1OY0KeCRy04Et2THOrvasJYZOi4lgqsGj/tDZsdix28p3f8KLHoM X-Google-Smtp-Source: AGHT+IGdmQDr1csbTh3SEEhCXasdP5TlE9EyUvXE6HFQFffw9S5hl6wGxU8HTM+k0l8+nLZNR4G9 X-Received: by 2002:a05:6808:1925:b0:3c9:94bb:dde5 with SMTP id 5614622812f47-3c9970cde5amr20374800b6e.39.1715766112054; Wed, 15 May 2024 02:41:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766112; cv=none; d=google.com; s=arc-20160816; b=gPbO8ZBCk2w+6h0mQ+kBbyaaicHeJAETC2Pjz4nAjzZAMsGkD+z2OwQ/AJgs/Yi38n QNunCSLvGeUxx3IHdBuLxJTxJoaYKQMx3JGs1O1d0cak8Z2h2vuEqnG/IwUscvyFJB6x h4qGiWiw5oQjQZv3LjOIDQiTc06YLaqaUMIumASiNhzjHUiNLZeZQrwLT+MPMFikP1EW PQKuHyfQC18XH7V8qPxCjtd72unldbElm0m0NmVkEUPhuty52SMeXX1OabqX+wXdtqFc fgiYU/wAHpIhuOdD+DJJuTqDwKEgsS3aHGfGsBW47PRqFcqJQMUFlW2RDe2SrtoQhhOT SN5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hoUJ/XePo7kWT/3zZI4lYWlaHp1tQqpPfuSuynDreWc=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=qcV9gqqvkNYJXAGWSlFHVCppZmbLUV+VXgqQtqXYiKDCPlSvLMgLePrTKat7EwnfB3 HYc8YwRYJiI7qIMvojtSuM/ujHr77mCccb4bePNyK2X/eFIkhKu3uD6J1RWku0dBCffA vfnF6RfSYoxbByS187iqNUZldJvINqH0saUr8GaUHBJ8FNjKAYkK+02vjT0Dtwmr9S4q Y9/VqFkjIvvtIcn/ayj8jzzN3LKkpUl2SAZMU2wPGlOW2WaxYxtRbMvc6lgHg35C4xTZ gnAQE6AxyAXHYgirszIm7xPKdbl3v8lGoFOFwA5P80XR5fYwvAZlL8swGAP3DhCXG3wZ lxJA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oDwp6RQC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.40.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:40:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 20/43] target/hppa: Use TCG_COND_TST* in do_cond Date: Wed, 15 May 2024 11:40:20 +0200 Message-Id: <20240515094043.82850-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We can directly test bits of a 32-bit comparison without zero or sign-extending an intermediate result. We can directly test bit 0 for odd/even. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 64 ++++++++++++++++++----------------------- 1 file changed, 28 insertions(+), 36 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 07ba35001b..813f1571e9 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -776,28 +776,36 @@ static bool cond_need_cb(int c) static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, TCGv_i64 res, TCGv_i64 uv, TCGv_i64 sv) { + TCGCond sign_cond, zero_cond; + uint64_t sign_imm, zero_imm; DisasCond cond; TCGv_i64 tmp; + if (d) { + /* 64-bit condition. */ + sign_imm = 0; + sign_cond = TCG_COND_LT; + zero_imm = 0; + zero_cond = TCG_COND_EQ; + } else { + /* 32-bit condition. */ + sign_imm = 1ull << 31; + sign_cond = TCG_COND_TSTNE; + zero_imm = UINT32_MAX; + zero_cond = TCG_COND_TSTEQ; + } + switch (cf >> 1) { case 0: /* Never / TR (0 / 1) */ cond = cond_make_f(); break; case 1: /* = / <> (Z / !Z) */ - if (!d) { - tmp = tcg_temp_new_i64(); - tcg_gen_ext32u_i64(tmp, res); - res = tmp; - } - cond = cond_make_vi(TCG_COND_EQ, res, 0); + cond = cond_make_vi(zero_cond, res, zero_imm); break; case 2: /* < / >= (N ^ V / !(N ^ V) */ tmp = tcg_temp_new_i64(); tcg_gen_xor_i64(tmp, res, sv); - if (!d) { - tcg_gen_ext32s_i64(tmp, tmp); - } - cond = cond_make_ti(TCG_COND_LT, tmp, 0); + cond = cond_make_ti(sign_cond, tmp, sign_imm); break; case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */ /* @@ -805,21 +813,15 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, * (N ^ V) | Z * ((res < 0) ^ (sv < 0)) | !res * ((res ^ sv) < 0) | !res - * (~(res ^ sv) >= 0) | !res - * !(~(res ^ sv) >> 31) | !res - * !(~(res ^ sv) >> 31 & res) + * ((res ^ sv) < 0 ? 1 : !res) + * !((res ^ sv) < 0 ? 0 : res) */ tmp = tcg_temp_new_i64(); - tcg_gen_eqv_i64(tmp, res, sv); - if (!d) { - tcg_gen_sextract_i64(tmp, tmp, 31, 1); - tcg_gen_and_i64(tmp, tmp, res); - tcg_gen_ext32u_i64(tmp, tmp); - } else { - tcg_gen_sari_i64(tmp, tmp, 63); - tcg_gen_and_i64(tmp, tmp, res); - } - cond = cond_make_ti(TCG_COND_EQ, tmp, 0); + tcg_gen_xor_i64(tmp, res, sv); + tcg_gen_movcond_i64(sign_cond, tmp, + tmp, tcg_constant_i64(sign_imm), + ctx->zero, res); + cond = cond_make_ti(zero_cond, tmp, zero_imm); break; case 4: /* NUV / UV (!UV / UV) */ cond = cond_make_vi(TCG_COND_EQ, uv, 0); @@ -827,23 +829,13 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, case 5: /* ZNV / VNZ (!UV | Z / UV & !Z) */ tmp = tcg_temp_new_i64(); tcg_gen_movcond_i64(TCG_COND_EQ, tmp, uv, ctx->zero, ctx->zero, res); - if (!d) { - tcg_gen_ext32u_i64(tmp, tmp); - } - cond = cond_make_ti(TCG_COND_EQ, tmp, 0); + cond = cond_make_ti(zero_cond, tmp, zero_imm); break; case 6: /* SV / NSV (V / !V) */ - if (!d) { - tmp = tcg_temp_new_i64(); - tcg_gen_ext32s_i64(tmp, sv); - sv = tmp; - } - cond = cond_make_ti(TCG_COND_LT, sv, 0); + cond = cond_make_vi(sign_cond, sv, sign_imm); break; case 7: /* OD / EV */ - tmp = tcg_temp_new_i64(); - tcg_gen_andi_i64(tmp, res, 1); - cond = cond_make_ti(TCG_COND_NE, tmp, 0); + cond = cond_make_vi(TCG_COND_TSTNE, res, 1); break; default: g_assert_not_reached(); From patchwork Wed May 15 09:40:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796926 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2890911wra; Wed, 15 May 2024 02:44:12 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX8W6+W9JnTpjmD6U/6F8q02OLnE5qmsAl+R22qG3NR0yGYaYRHD//cRtEusOrlXJQz+Ueg+CkfJZVGXVCwLRbm X-Google-Smtp-Source: AGHT+IFDUainxPjdFFvGXaiQ115o4C8aT+Mu6gInAhKPS8erPANpVwsjJl4a0uI8OowOEMwz8nwa X-Received: by 2002:a05:6214:5c44:b0:6a0:d20e:5406 with SMTP id 6a1803df08f44-6a16814f5b6mr159451436d6.17.1715766252053; Wed, 15 May 2024 02:44:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766252; cv=none; d=google.com; s=arc-20160816; b=T7EXf0OTTKcRsMeO9aXRGd6uup0eBsE0AuSoAwbyFup+l5rBa0XUV6z/195L8KskyI lEZM96hWgd/as6H7PDWq7oWc/3QasebWXcjUhYXlWDg/uHWp3jxA1a4sCAlz/wGFv4xx BeJ058DyDmKVjBC9W4qMHz//d3k+5pkSUQx+wQ9qzyY9aUjtXpgCtbx1z3p56FpW4Ezs zHG0Dv/L36lHbTu9us7TpxWOyBNn8opHZ1PorrlmnypQkbPlomZoBJJhqNRAquqLwRwP 2w46xIE2r0A/axKH3Os96AFL13LYsSwANxXXmWz2f/5yjSZ0IbZ6WlOFN58p5Mcc1Ufn fEvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Bc9+7FT9ewR5kS1vQGkFjz332Ns1o4RnoFgiZ7ZrChg=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=SxzSemErJ//MgiCCyw/VVUr0F3s72XEyPirpuvh79TKM3MYl31rdYo7ULRnnBBXD8p xVquG/ZjCeIkT/rWOLo5t0a0QHIypQ3ESty9T7q/mxPjCbDoAs2cfzKh1RdnzUx5TjaL acRR27Xhex88H3hC4JUx8Z+iwLCSWMAD2EUAM+wqXkE1LDrj8Lh0IaguBnPKejLWdB/U GZK52FRcpwCD5sECnKJvs0WSkTvDDIya5efEBNYCA7ZV1sGkz40gVSa017AbDQyG5PAF 47DgNhZBn1wH3fFKSlxfSqRF2ekur9CI3SPPVvl4DNwEa35g6j+TP8oVmHX4XMOpa3wc Gedw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZxKitB7h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 21/43] target/hppa: Use TCG_COND_TST* in do_log_cond Date: Wed, 15 May 2024 11:40:21 +0200 Message-Id: <20240515094043.82850-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=richard.henderson@linaro.org; helo=mail-lf1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We can directly test bits of a 32-bit comparison without zero or sign-extending an intermediate result. We can directly test bit 0 for odd/even. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 78 ++++++++++++++--------------------------- 1 file changed, 27 insertions(+), 51 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 813f1571e9..62cc3c3117 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -915,65 +915,41 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d, TCGv_i64 res) { TCGCond tc; - bool ext_uns; + uint64_t imm; - switch (cf) { - case 0: /* never */ - case 9: /* undef, C */ - case 11: /* undef, C & !Z */ - case 12: /* undef, V */ - return cond_make_f(); - - case 1: /* true */ - case 8: /* undef, !C */ - case 10: /* undef, !C | Z */ - case 13: /* undef, !V */ - return cond_make_t(); - - case 2: /* == */ - tc = TCG_COND_EQ; - ext_uns = true; + switch (cf >> 1) { + case 0: /* never / always */ + case 4: /* undef, C */ + case 5: /* undef, C & !Z */ + case 6: /* undef, V */ + return cf & 1 ? cond_make_t() : cond_make_f(); + case 1: /* == / <> */ + tc = d ? TCG_COND_EQ : TCG_COND_TSTEQ; + imm = d ? 0 : UINT32_MAX; break; - case 3: /* <> */ - tc = TCG_COND_NE; - ext_uns = true; + case 2: /* < / >= */ + tc = d ? TCG_COND_LT : TCG_COND_TSTNE; + imm = d ? 0 : 1ull << 31; break; - case 4: /* < */ - tc = TCG_COND_LT; - ext_uns = false; + case 3: /* <= / > */ + tc = cf & 1 ? TCG_COND_GT : TCG_COND_LE; + if (!d) { + TCGv_i64 tmp = tcg_temp_new_i64(); + tcg_gen_ext32s_i64(tmp, res); + return cond_make_ti(tc, tmp, 0); + } + return cond_make_vi(tc, res, 0); + case 7: /* OD / EV */ + tc = TCG_COND_TSTNE; + imm = 1; break; - case 5: /* >= */ - tc = TCG_COND_GE; - ext_uns = false; - break; - case 6: /* <= */ - tc = TCG_COND_LE; - ext_uns = false; - break; - case 7: /* > */ - tc = TCG_COND_GT; - ext_uns = false; - break; - - case 14: /* OD */ - case 15: /* EV */ - return do_cond(ctx, cf, d, res, NULL, NULL); - default: g_assert_not_reached(); } - - if (!d) { - TCGv_i64 tmp = tcg_temp_new_i64(); - - if (ext_uns) { - tcg_gen_ext32u_i64(tmp, res); - } else { - tcg_gen_ext32s_i64(tmp, res); - } - return cond_make_ti(tc, tmp, 0); + if (cf & 1) { + tc = tcg_invert_cond(tc); } - return cond_make_vi(tc, res, 0); + return cond_make_vi(tc, res, imm); } /* Similar, but for shift/extract/deposit conditions. */ From patchwork Wed May 15 09:40:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796914 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2890074wra; Wed, 15 May 2024 02:41:45 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWCaqr7No34W6Axlq9hhGHnKtFhtCG2rHxcMYgPQKMy7I5YFljJUPaIgHEgoLEgj3jZNjrV5f0oLLtB8u4TjCKX X-Google-Smtp-Source: AGHT+IEsuKUKfpCE3/7e6cjHVCBrEV67O8DwuUNsxPnPIF3RvfpHP9rLqR9lEcx1gH1sgVWw1RUl X-Received: by 2002:a05:6808:19a9:b0:3c9:9473:4300 with SMTP id 5614622812f47-3c9970d1a4amr19765053b6e.48.1715766104820; Wed, 15 May 2024 02:41:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766104; cv=none; d=google.com; s=arc-20160816; b=ht8KXP6CFpDys9SI8efPFoseTbQ5cEBPzH1xGWj/SGKqe73d1hCldmFokaknIetQUY oKzLIIYe2IdAj/kFzvdTAIO7o8jhZ8Kb4oGKa3rmFrRlTfOL4h0+TUtXgWDey0LOMXGn ajudAIIM+6lFgqZy6jx7Yb1T6mYqbZVHkeaWDNkRLQccPYjPlNfwJNasqzeGE9Rs0S6z bVBDHlVJ9GEKxt6D+XQyl7HLzHJ1wreGjvqLdwT0WV4D78airMhz35eOcpFESyi11EGQ IA5sLL8kpLCgUxqt38sNAnK2uxt6SqLAShg/2MdEI7Ibil2mqWpUSeVANllnkyWf/kB0 EmRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xKJZYifPLAfMVMiut/051TBGFTmpS1Nu/DFU0w70ggM=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=nBPHnMm61K++rCxHXefsPc05p1YDDPx1gAW4zPapgfUtuLOjGqLtIiyN1sT3A0KF89 8dGIBZtWw1o7eGuexIhJ7ayMQvr4CQIpG0w8rYyzRQk30f54Na2hC5Ma5OcnuRCJAbbc FnNYxNm9WYi3WJN6OnhaGuP9co9jM4lLHPwRYQHLgvHR2O0fJw+U8N8dXtojacvmbuZq S577Q760X/siPWH9of30H1Wg97gLNwCe4ZaYSOZ8ei2d/jsuOHo1SaFHf0sJD9LFOgBN NxufpR1vYIcWYpXmLVyTXssJJEQH/iCwglOYPeHEPuQTiNQJzdlJI2aKc/KGO9GWj+K+ +e0w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WGpYO12G; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 22/43] target/hppa: Use TCG_COND_TST* in do_unit_zero_cond Date: Wed, 15 May 2024 11:40:22 +0200 Message-Id: <20240515094043.82850-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 62cc3c3117..b19d7c64fe 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1006,9 +1006,8 @@ static DisasCond do_unit_zero_cond(unsigned cf, bool d, TCGv_i64 res) tmp = tcg_temp_new_i64(); tcg_gen_subi_i64(tmp, res, ones); tcg_gen_andc_i64(tmp, tmp, res); - tcg_gen_andi_i64(tmp, tmp, sgns); - return cond_make_ti(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, tmp, 0); + return cond_make_ti(cf & 1 ? TCG_COND_TSTEQ : TCG_COND_TSTNE, tmp, sgns); } static TCGv_i64 get_carry(DisasContext *ctx, bool d, From patchwork Wed May 15 09:40:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796938 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2891977wra; Wed, 15 May 2024 02:47:46 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW6n/v/Rs71NRB1vYoltjCdoRmsCjPaWYk1Miv4EGjuKbsJx88lWyGT6KjzFllURvRsDvFnKLilUOmqavZ9MjK0 X-Google-Smtp-Source: AGHT+IGeQatrjpZurGlER4WN99srWlMsGZ8dhpfj2glK5RuyV+efC/qPgwKWh9Pxc3soJDdqDBtI X-Received: by 2002:a05:622a:1b17:b0:43b:15e1:1e87 with SMTP id d75a77b69052e-43dfdaab036mr240174811cf.11.1715766465824; Wed, 15 May 2024 02:47:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766465; cv=none; d=google.com; s=arc-20160816; b=xq7agS0CBhawAdivUwC8VcwPkxpnm+xFN5bPjwVvP7/HbCcqI+CdrpBD+Am5s3VfOw UoWohf8XZbEGu7FsW78mbPipUTSNUpdi181V1dW2j8VJnzmstarz7Vf5IEMRZC9mlr2Q m58rMi3iLz6KwqfOed4f2rkNPf7mxe5UncHd5bvfP8yfS4D4horSMkmn+LqVjjJ2C19Z q4Xmmso2J716upc7VfEXne+0IXBzdv+4NPPvi0LBmqJA52G0M6iPUUvIj5eV9oO94fvp dbwcx8Fg3xw8FGMDRh2GkYgk+OLNrHzHPf0tTTLI7FkQfqO9EOxlmX7inBo/LdPOxNKG 52HA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OSrjBrTs7BiOjRfXoLuD7sENLd2Ur3ZnScDSTPyxo90=; fh=3//KcqJEsa04kIBt5Nb/DJuP+2GuH1NwDRxnSl44zdw=; b=rDzbtPXjh/NyG3+P5ihfpQlmQKDwWVXNofoJwunOZIrW34NfHqRIbNxypBLRNkqcrW 7LOpIcvCDX+Q0MLCHA8oARK9yVVlPw7+jbV3wouJvXBMsDB7FORTYWhiJvHd6VEN6XPl LAXPjXnhJlD3qDJS67izynW+1sQBT74emUsolUUrvh/I8wg8D0eyPTPWmH9Frvx81eWV sxJ6uAG7aDRt1TKfSDnlo5ghn9CqwkHVWiVabZd425VqKmZqTu7GB+3PA2B37Vi4aJG9 CdwLraZJ0+NHa+8hMo81geOZqD39WtRgNYfmdJOKaqfkqPJ7TU3JuJxlN3VmGoAS7FW9 oZ8g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ryh3qnzH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 23/43] target/hppa: Use TCG_COND_TST* in do_unit_addsub Date: Wed, 15 May 2024 11:40:23 +0200 Message-Id: <20240515094043.82850-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b19d7c64fe..4e49bd2b67 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1420,8 +1420,8 @@ static void do_unit_addsub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, tcg_gen_shri_i64(cb, cb, 1); } - tcg_gen_andi_i64(cb, cb, test_cb); - cond = cond_make_ti(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, cb, 0); + cond = cond_make_ti(cf & 1 ? TCG_COND_TSTEQ : TCG_COND_TSTNE, + cb, test_cb); } if (is_tc) { From patchwork Wed May 15 09:40:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796946 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2892332wra; Wed, 15 May 2024 02:48:54 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXRmTiuwPHHowHTb5iNGolW6kyQtJMocn6WGkhRcpkP4jybDato3xTHMCgszSqI/i9hPx5SRQXTZ9WnNxiaDe83 X-Google-Smtp-Source: AGHT+IHHCtng5HgE8y63b/QmHPK/7Q7tBeueRM/mWl/H6J1Ef7gV0RheXDqNFt4FeQtV6FgZy4MR X-Received: by 2002:ad4:580f:0:b0:6a3:5b93:20b1 with SMTP id 6a1803df08f44-6a35b93218fmr2210036d6.53.1715766534358; Wed, 15 May 2024 02:48:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766534; cv=none; d=google.com; s=arc-20160816; b=ZyTbNRMED3g5FiLaMYdqN/p0VtT/12QWl5N3diOMT10/AET1iHatQCqf22S7WgcrS3 lIBoHzlfkGAsDVjt4+48TQGoMbI4VIVmVg/rV9iuxwLq+u+1lXCATNJxDLl3szbQQaJ5 vnzduXi1BmfHoog7CqJf8tklV+0Gae5bkJyzzGrByt3KMn4o1muwFTN/2rGsCXnYfPFo haYxl7r+t/3PjFb5Q0S2yicpWDp4+1rClWe6vGMiPlzsQzLzcDkSEGm/eP3f7qh4FswZ F+WB4O0mxpvaQdTJ2yZ5HycCuajpy/sUUt9ykxwTnaTC0Zk+vt4Rs+ODfj7kVcSNzFT6 YYrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4ut1tTRNwrZrLRbqcF7h53mi8stN5BjGNXrsWn90/1M=; fh=3//KcqJEsa04kIBt5Nb/DJuP+2GuH1NwDRxnSl44zdw=; b=z4gH9MsNtYrJDUfo/MYWn2gR12Idt0OGyxTTM8C+0oJiTa1dNKmO8gzzoaF+J18G8A ONQT42uFBoYwdFrRybaZIPVHsUoq5zOo39df8VcW4Ju+Z1ZztWOoAEoXjFgXc3vfs0vc z7DASRTG6ut2Gqrs1ZjJtrtkqIdaxgYC2cZYrFBKPc+VvXhQGfEY4vu3LbtaUJHjQam0 QDEWOFyeJRiMN8mWeBwK/+6SvISfKxgr+jf96zY8sxsidTX0xwN9L2EDE5a2U0TkBLdE GSs8yBu6rlBWLOvfVe/TKxX4pCSthMeiDKZLdrjhnMpHaxwqYQ6eYsb5L2A/R1LJWqMn LTXg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zC0nhpyL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 24/43] target/hppa: Use TCG_COND_TST* in trans_bb_imm Date: Wed, 15 May 2024 11:40:24 +0200 Message-Id: <20240515094043.82850-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 4e49bd2b67..af6be5100c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3516,18 +3516,12 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) { - TCGv_i64 tmp, tcg_r; DisasCond cond; - int p; + int p = a->p | (a->d ? 0 : 32); nullify_over(ctx); - - tmp = tcg_temp_new_i64(); - tcg_r = load_gpr(ctx, a->r); - p = a->p | (a->d ? 0 : 32); - tcg_gen_shli_i64(tmp, tcg_r, p); - - cond = cond_make_ti(a->c ? TCG_COND_GE : TCG_COND_LT, tmp, 0); + cond = cond_make_vi(a->c ? TCG_COND_TSTEQ : TCG_COND_TSTNE, + load_gpr(ctx, a->r), 1ull << (63 - p)); return do_cbranch(ctx, a->disp, a->n, &cond); } From patchwork Wed May 15 09:40:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796930 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2890977wra; Wed, 15 May 2024 02:44:28 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWigZuOOwrcnIIJSI3jw7X3ZAyKdR913/Q8tC56cWDJnH7vIpLSRXsS6LLVW9dhgYr25U2kzlHzbjiexFIljhif X-Google-Smtp-Source: AGHT+IGptasG4ylDe94ln5uj2NoQjRyzgZTkY/HiqUMtadIA5rpZUwcoQd65NydvUAITBsQrClkX X-Received: by 2002:a05:6214:4890:b0:6a0:cef9:d45e with SMTP id 6a1803df08f44-6a168211714mr172196576d6.50.1715766267834; Wed, 15 May 2024 02:44:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766267; cv=none; d=google.com; s=arc-20160816; b=BqP0IIgpDOIGekUZcdAV1SbZwHpz/Q+T0glfQeWf2sCBbGqYIsw2tpDs983MD2NVIE fxixOnrxGYKbVuW/tFBtb7t9XpC4h2EUm9ddX0RkGxCCFF/zxgWgIUPw5gFNnuOKixaA r2kUjymsObzOCWOlGR3ybaS0UYzTfe675bmvbyKTW1n8yxA79hBxt6KHnPAS+ThE/amJ CHdJRp+fYKc7rdq4dEh8X5Y1XPh5l5W4S9RfjgBfwn0uis/KdQRe+cPeQPX975Adcm1L flBZQOt2/4v/uP7RZb8PPb0pnIu9UlYW3dH9QTS7KRlS2yZqYoD4d3KfvRHneo45dLdU Z47Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=X4jRd3hxbjTiAu+s3YZQjoqjOWe8GR5Gzz4gHz0Aol8=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=Qu2rWdqWu/jGMSjtCcJAitnOVPeQHeX3AO9qt+migghJkMRg1LepuG06L52yfCNaR5 W96b9N1s30juw7EmumRTLgYzji6ZNrIQbCWf6NeMH1horfQSfXjRxDEHdbcKR2WNmDXm Dw2TKY83aBfl1nq8Kifh0iNMHPgvwd2S7x2ZoVOzavPdTrZ8cPvEyAiEaXxiIMqdy/vx C5eRXdvYwrLKn2d7n3RVM6Hm1/LJFnPNkGQ+YpOkRouhGobPtOmeXER0YmTLGL+p/A0v hx+syHXUJJWhcJk0mDsjS6rV2pNfLVTmtsAwOtj2jK0zXsYED/wJypAbKKgrQRz3Axqq rK7A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F5jg2kTG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 25/43] target/hppa: Use registerfields.h for FPSR Date: Wed, 15 May 2024 11:40:25 +0200 Message-Id: <20240515094043.82850-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Define all of the context dependent field definitions. Use FIELD_EX32 and FIELD_DP32 with named fields instead of extract32 and deposit32 with raw constants. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 25 +++++++++++++++++++++++++ target/hppa/fpu_helper.c | 26 +++++++++++++------------- target/hppa/translate.c | 18 ++++++++---------- 3 files changed, 46 insertions(+), 23 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 61f1353133..c37b4e12fb 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -24,6 +24,7 @@ #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" #include "qemu/interval-tree.h" +#include "hw/registerfields.h" #define MMU_ABS_W_IDX 6 #define MMU_ABS_IDX 7 @@ -152,6 +153,30 @@ #define CR_IPSW 22 #define CR_EIRR 23 +FIELD(FPSR, ENA_I, 0, 1) +FIELD(FPSR, ENA_U, 1, 1) +FIELD(FPSR, ENA_O, 2, 1) +FIELD(FPSR, ENA_Z, 3, 1) +FIELD(FPSR, ENA_V, 4, 1) +FIELD(FPSR, ENABLES, 0, 5) +FIELD(FPSR, D, 5, 1) +FIELD(FPSR, T, 6, 1) +FIELD(FPSR, RM, 9, 2) +FIELD(FPSR, CQ, 11, 11) +FIELD(FPSR, CQ0_6, 15, 7) +FIELD(FPSR, CQ0_4, 17, 5) +FIELD(FPSR, CQ0_2, 19, 3) +FIELD(FPSR, CQ0, 21, 1) +FIELD(FPSR, CA, 15, 7) +FIELD(FPSR, CA0, 21, 1) +FIELD(FPSR, C, 26, 1) +FIELD(FPSR, FLG_I, 27, 1) +FIELD(FPSR, FLG_U, 28, 1) +FIELD(FPSR, FLG_O, 29, 1) +FIELD(FPSR, FLG_Z, 30, 1) +FIELD(FPSR, FLG_V, 31, 1) +FIELD(FPSR, FLAGS, 27, 5) + typedef struct HPPATLBEntry { union { IntervalTreeNode itree; diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 576f283b04..deaed2b65d 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -30,7 +30,7 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) env->fr0_shadow = shadow; - switch (extract32(shadow, 9, 2)) { + switch (FIELD_EX32(shadow, FPSR, RM)) { default: rm = float_round_nearest_even; break; @@ -46,7 +46,7 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) } set_float_rounding_mode(rm, &env->fp_status); - d = extract32(shadow, 5, 1); + d = FIELD_EX32(shadow, FPSR, D); set_flush_to_zero(d, &env->fp_status); set_flush_inputs_to_zero(d, &env->fp_status); } @@ -57,7 +57,7 @@ void cpu_hppa_loaded_fr0(CPUHPPAState *env) } #define CONVERT_BIT(X, SRC, DST) \ - ((SRC) > (DST) \ + ((unsigned)(SRC) > (unsigned)(DST) \ ? (X) / ((SRC) / (DST)) & (DST) \ : ((X) & (SRC)) * ((DST) / (SRC))) @@ -73,12 +73,12 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra) } set_float_exception_flags(0, &env->fp_status); - hard_exp |= CONVERT_BIT(soft_exp, float_flag_inexact, 1u << 0); - hard_exp |= CONVERT_BIT(soft_exp, float_flag_underflow, 1u << 1); - hard_exp |= CONVERT_BIT(soft_exp, float_flag_overflow, 1u << 2); - hard_exp |= CONVERT_BIT(soft_exp, float_flag_divbyzero, 1u << 3); - hard_exp |= CONVERT_BIT(soft_exp, float_flag_invalid, 1u << 4); - shadow |= hard_exp << (32 - 5); + hard_exp |= CONVERT_BIT(soft_exp, float_flag_inexact, R_FPSR_ENA_I_MASK); + hard_exp |= CONVERT_BIT(soft_exp, float_flag_underflow, R_FPSR_ENA_U_MASK); + hard_exp |= CONVERT_BIT(soft_exp, float_flag_overflow, R_FPSR_ENA_O_MASK); + hard_exp |= CONVERT_BIT(soft_exp, float_flag_divbyzero, R_FPSR_ENA_Z_MASK); + hard_exp |= CONVERT_BIT(soft_exp, float_flag_invalid, R_FPSR_ENA_V_MASK); + shadow |= hard_exp << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT); env->fr0_shadow = shadow; env->fr[0] = (uint64_t)shadow << 32; @@ -378,15 +378,15 @@ static void update_fr0_cmp(CPUHPPAState *env, uint32_t y, if (y) { /* targeted comparison */ /* set fpsr[ca[y - 1]] to current compare */ - shadow = deposit32(shadow, 21 - (y - 1), 1, c); + shadow = deposit32(shadow, R_FPSR_CA0_SHIFT - (y - 1), 1, c); } else { /* queued comparison */ /* shift cq right by one place */ - shadow = deposit32(shadow, 11, 10, extract32(shadow, 12, 10)); + shadow = (shadow & ~R_FPSR_CQ_MASK) | ((shadow >> 1) & R_FPSR_CQ_MASK); /* move fpsr[c] to fpsr[cq[0]] */ - shadow = deposit32(shadow, 21, 1, extract32(shadow, 26, 1)); + shadow = FIELD_DP32(shadow, FPSR, CQ0, FIELD_EX32(shadow, FPSR, C)); /* set fpsr[c] to current compare */ - shadow = deposit32(shadow, 26, 1, c); + shadow = FIELD_DP32(shadow, FPSR, C, c); } env->fr0_shadow = shadow; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index af6be5100c..efd4398437 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4324,29 +4324,28 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a) switch (a->c) { case 0: /* simple */ - tcg_gen_andi_i64(t, t, 0x4000000); - ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0); - goto done; + mask = R_FPSR_C_MASK; + break; case 2: /* rej */ inv = true; /* fallthru */ case 1: /* acc */ - mask = 0x43ff800; + mask = R_FPSR_C_MASK | R_FPSR_CQ_MASK; break; case 6: /* rej8 */ inv = true; /* fallthru */ case 5: /* acc8 */ - mask = 0x43f8000; + mask = R_FPSR_C_MASK | R_FPSR_CQ0_6_MASK; break; case 9: /* acc6 */ - mask = 0x43e0000; + mask = R_FPSR_C_MASK | R_FPSR_CQ0_4_MASK; break; case 13: /* acc4 */ - mask = 0x4380000; + mask = R_FPSR_C_MASK | R_FPSR_CQ0_2_MASK; break; case 17: /* acc2 */ - mask = 0x4200000; + mask = R_FPSR_C_MASK | R_FPSR_CQ0_MASK; break; default: gen_illegal(ctx); @@ -4363,11 +4362,10 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a) } else { unsigned cbit = (a->y ^ 1) - 1; - tcg_gen_extract_i64(t, t, 21 - cbit, 1); + tcg_gen_extract_i64(t, t, R_FPSR_CA0_SHIFT - cbit, 1); ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0); } - done: return nullify_end(ctx); } From patchwork Wed May 15 09:40:26 2024 Content-Type: text/plain; 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 26/43] target/hppa: Use TCG_COND_TST* in trans_ftest Date: Wed, 15 May 2024 11:40:26 +0200 Message-Id: <20240515094043.82850-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index efd4398437..11d74bb2aa 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4311,6 +4311,8 @@ static bool trans_fcmp_d(DisasContext *ctx, arg_fclass2 *a) static bool trans_ftest(DisasContext *ctx, arg_ftest *a) { + TCGCond tc = TCG_COND_TSTNE; + uint32_t mask; TCGv_i64 t; nullify_over(ctx); @@ -4319,21 +4321,18 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a) tcg_gen_ld32u_i64(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow)); if (a->y == 1) { - int mask; - bool inv = false; - switch (a->c) { case 0: /* simple */ mask = R_FPSR_C_MASK; break; case 2: /* rej */ - inv = true; + tc = TCG_COND_TSTEQ; /* fallthru */ case 1: /* acc */ mask = R_FPSR_C_MASK | R_FPSR_CQ_MASK; break; case 6: /* rej8 */ - inv = true; + tc = TCG_COND_TSTEQ; /* fallthru */ case 5: /* acc8 */ mask = R_FPSR_C_MASK | R_FPSR_CQ0_6_MASK; @@ -4351,21 +4350,12 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a) gen_illegal(ctx); return true; } - if (inv) { - TCGv_i64 c = tcg_constant_i64(mask); - tcg_gen_or_i64(t, t, c); - ctx->null_cond = cond_make_tt(TCG_COND_EQ, t, c); - } else { - tcg_gen_andi_i64(t, t, mask); - ctx->null_cond = cond_make_ti(TCG_COND_EQ, t, 0); - } } else { unsigned cbit = (a->y ^ 1) - 1; - - tcg_gen_extract_i64(t, t, R_FPSR_CA0_SHIFT - cbit, 1); - ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0); + mask = R_FPSR_CA0_MASK >> cbit; } + ctx->null_cond = cond_make_ti(tc, t, mask); return nullify_end(ctx); } From patchwork Wed May 15 09:40:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796949 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2892412wra; Wed, 15 May 2024 02:49:09 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWjRZQ+P7J6FMuQIyagM7DaPfaQUoDHG+uoXicOZ3JrjOWVhWqmFeIhyktW+qHI+9OTAgHH8wP9JjubcqX9nm73 X-Google-Smtp-Source: AGHT+IEJ3x1t432Oh9CIghsz3Umwffenp2Hdq+8PAMUXVCXKW51iTZWll9wuaWTarxTtTP+MY/1L X-Received: by 2002:a05:620a:4d5:b0:790:99e1:7cd4 with SMTP id af79cd13be357-792c7577038mr1575782785a.5.1715766549197; Wed, 15 May 2024 02:49:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766549; cv=none; d=google.com; s=arc-20160816; b=rySqV4c97vPuGiw3YVMi9CAAwjoL34c2flez2OxE8TnrTl7VMgp/kKFKmcwhlRzj+I gfk6oOUKrkbHBtpxXizxGGZMy6jEDHTOuKX+d4bY3ZpYbcQ/aYlOpW0Jcrpzb9fgtpa1 uTYHjIn2UM4lKtbOs6r0IffJuPN9mahsBEh6c7uh+Cuq5jWOXt/9ubLw2zo4f/dcdbgE mTF3bx1Mm8mYM2Hp8YbKaSdEPodcYfWiBD3hgp/KkG3qK6Q3kOTRNqR0mIsuRckoG5HA UJc9INm4AUzVXA8BzuEw1Do3rHIskMjc9e1ubd+jr6+RuY2eqsmbN3hwAJoqMfEwZP0o BHpA== ARC-Message-Signature: i=1; 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 27/43] target/hppa: Remove cond_free Date: Wed, 15 May 2024 11:40:27 +0200 Message-Id: <20240515094043.82850-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that we do not need to free tcg temporaries, the only thing cond_free does is reset the condition to never. Instead, simply write a new condition over the old, which may be simply cond_make_f() for the never condition. The do_*_cond functions do the right thing with c or cf == 0, so there's no need for a special case anymore. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 102 +++++++++++----------------------------- 1 file changed, 27 insertions(+), 75 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 11d74bb2aa..81a75ddf95 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -373,21 +373,6 @@ static DisasCond cond_make_vv(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) return cond_make_tt(c, t0, t1); } -static void cond_free(DisasCond *cond) -{ - switch (cond->c) { - default: - cond->a0 = NULL; - cond->a1 = NULL; - /* fallthru */ - case TCG_COND_ALWAYS: - cond->c = TCG_COND_NEVER; - break; - case TCG_COND_NEVER: - break; - } -} - static TCGv_i64 load_gpr(DisasContext *ctx, unsigned reg) { if (reg == 0) { @@ -537,7 +522,7 @@ static void nullify_over(DisasContext *ctx) tcg_gen_brcond_i64(ctx->null_cond.c, ctx->null_cond.a0, ctx->null_cond.a1, ctx->null_lab); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); } } @@ -555,7 +540,7 @@ static void nullify_save(DisasContext *ctx) ctx->null_cond.a0, ctx->null_cond.a1); ctx->psw_n_nonzero = true; } - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); } /* Set a PSW[N] to X. The intention is that this is used immediately @@ -1166,7 +1151,6 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1, save_gpr(ctx, rt, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); ctx->null_cond = cond; } @@ -1263,7 +1247,6 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, save_gpr(ctx, rt, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); ctx->null_cond = cond; } @@ -1318,7 +1301,6 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_i64 in1, save_gpr(ctx, rt, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); ctx->null_cond = cond; } @@ -1333,10 +1315,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TCGv_i64 in1, save_gpr(ctx, rt, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (cf) { - ctx->null_cond = do_log_cond(ctx, cf, d, dest); - } + ctx->null_cond = do_log_cond(ctx, cf, d, dest); } static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a, @@ -1431,7 +1410,6 @@ static void do_unit_addsub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, } save_gpr(ctx, rt, dest); - cond_free(&ctx->null_cond); ctx->null_cond = cond; } @@ -1854,7 +1832,6 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, taken = gen_new_label(); tcg_gen_brcond_i64(c, cond->a0, cond->a1, taken); - cond_free(cond); /* Not taken: Condition not satisfied; nullify on backward branches. */ n = is_n && disp < 0; @@ -2036,7 +2013,7 @@ static void do_page_zero(DisasContext *ctx) static bool trans_nop(DisasContext *ctx, arg_nop *a) { - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2050,7 +2027,7 @@ static bool trans_sync(DisasContext *ctx, arg_sync *a) /* No point in nullifying the memory barrier. */ tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2062,7 +2039,7 @@ static bool trans_mfia(DisasContext *ctx, arg_mfia *a) tcg_gen_andi_i64(dest, dest, -4); save_gpr(ctx, a->t, dest); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2077,7 +2054,7 @@ static bool trans_mfsp(DisasContext *ctx, arg_mfsp *a) save_gpr(ctx, rt, t0); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2122,7 +2099,7 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a) save_gpr(ctx, rt, tmp); done: - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2162,7 +2139,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a) tcg_gen_andi_i64(tmp, reg, ctx->is_pa20 ? 63 : 31); save_or_nullify(ctx, cpu_sar, tmp); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2236,7 +2213,7 @@ static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a) tcg_gen_andi_i64(tmp, tmp, ctx->is_pa20 ? 63 : 31); save_or_nullify(ctx, cpu_sar, tmp); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2253,7 +2230,7 @@ static bool trans_ldsid(DisasContext *ctx, arg_ldsid *a) #endif save_gpr(ctx, a->t, dest); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2415,7 +2392,7 @@ static bool trans_nop_addrx(DisasContext *ctx, arg_ldst *a) tcg_gen_add_i64(dest, src1, src2); save_gpr(ctx, a->b, dest); } - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2657,7 +2634,7 @@ static bool trans_lci(DisasContext *ctx, arg_lci *a) since the entire address space is coherent. */ save_gpr(ctx, a->t, ctx->zero); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2734,7 +2711,7 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) unsigned rt = a->t; if (rt == 0) { /* NOP */ - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } if (r2 == 0) { /* COPY */ @@ -2745,7 +2722,7 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) } else { save_gpr(ctx, rt, cpu_gr[r1]); } - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } #ifndef CONFIG_USER_ONLY @@ -2810,11 +2787,7 @@ static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a) tcg_gen_xor_i64(dest, tcg_r1, tcg_r2); save_gpr(ctx, a->t, dest); - cond_free(&ctx->null_cond); - if (a->cf) { - ctx->null_cond = do_unit_zero_cond(a->cf, a->d, dest); - } - + ctx->null_cond = do_unit_zero_cond(a->cf, a->d, dest); return nullify_end(ctx); } @@ -2840,7 +2813,7 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc) tcg_gen_subi_i64(tmp, tmp, 1); } save_gpr(ctx, a->t, tmp); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -3366,7 +3339,7 @@ static bool trans_ldil(DisasContext *ctx, arg_ldil *a) tcg_gen_movi_i64(tcg_rt, a->i); save_gpr(ctx, a->t, tcg_rt); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -3377,7 +3350,7 @@ static bool trans_addil(DisasContext *ctx, arg_addil *a) tcg_gen_addi_i64(tcg_r1, tcg_rt, a->i); save_gpr(ctx, 1, tcg_r1); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -3393,7 +3366,7 @@ static bool trans_ldo(DisasContext *ctx, arg_ldo *a) tcg_gen_addi_i64(tcg_rt, cpu_gr[a->b], a->i); } save_gpr(ctx, a->t, tcg_rt); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -3619,10 +3592,7 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a) save_gpr(ctx, a->t, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); - } + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); return nullify_end(ctx); } @@ -3662,10 +3632,7 @@ static bool trans_shrp_imm(DisasContext *ctx, arg_shrp_imm *a) save_gpr(ctx, a->t, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); - } + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); return nullify_end(ctx); } @@ -3707,10 +3674,7 @@ static bool trans_extr_sar(DisasContext *ctx, arg_extr_sar *a) save_gpr(ctx, a->t, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); - } + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); return nullify_end(ctx); } @@ -3743,10 +3707,7 @@ static bool trans_extr_imm(DisasContext *ctx, arg_extr_imm *a) save_gpr(ctx, a->t, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); - } + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); return nullify_end(ctx); } @@ -3783,10 +3744,7 @@ static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a) save_gpr(ctx, a->t, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); - } + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); return nullify_end(ctx); } @@ -3819,10 +3777,7 @@ static bool trans_dep_imm(DisasContext *ctx, arg_dep_imm *a) save_gpr(ctx, a->t, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); - } + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); return nullify_end(ctx); } @@ -3856,10 +3811,7 @@ static bool do_dep_sar(DisasContext *ctx, unsigned rt, unsigned c, save_gpr(ctx, rt, dest); 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 28/43] target/hppa: Introduce DisasDelayException Date: Wed, 15 May 2024 11:40:28 +0200 Message-Id: <20240515094043.82850-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Allow an exception to be emitted at the end of the TranslationBlock, leaving only the conditional branch inline. Use it for simple exception instructions like break, which happen to be nullified. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 60 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 55 insertions(+), 5 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 81a75ddf95..706537ea59 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -51,6 +51,17 @@ typedef struct DisasIAQE { int64_t disp; } DisasIAQE; +typedef struct DisasDelayException { + struct DisasDelayException *next; + TCGLabel *lab; + uint32_t insn; + bool set_iir; + int8_t set_n; + uint8_t excp; + /* Saved state at parent insn. */ + DisasIAQE iaq_f, iaq_b; +} DisasDelayException; + typedef struct DisasContext { DisasContextBase base; CPUState *cs; @@ -66,6 +77,7 @@ typedef struct DisasContext { DisasCond null_cond; TCGLabel *null_lab; + DisasDelayException *delay_excp_list; TCGv_i64 zero; uint32_t insn; @@ -684,13 +696,38 @@ static void gen_excp(DisasContext *ctx, int exception) ctx->base.is_jmp = DISAS_NORETURN; } +static DisasDelayException *delay_excp(DisasContext *ctx, uint8_t excp) +{ + DisasDelayException *e = tcg_malloc(sizeof(DisasDelayException)); + + memset(e, 0, sizeof(*e)); + e->next = ctx->delay_excp_list; + ctx->delay_excp_list = e; + + e->lab = gen_new_label(); + e->insn = ctx->insn; + e->set_iir = true; + e->set_n = ctx->psw_n_nonzero ? 0 : -1; + e->excp = excp; + e->iaq_f = ctx->iaq_f; + e->iaq_b = ctx->iaq_b; + + return e; +} + static bool gen_excp_iir(DisasContext *ctx, int exc) { - nullify_over(ctx); - tcg_gen_st_i64(tcg_constant_i64(ctx->insn), - tcg_env, offsetof(CPUHPPAState, cr[CR_IIR])); - gen_excp(ctx, exc); - return nullify_end(ctx); + if (ctx->null_cond.c == TCG_COND_NEVER) { + tcg_gen_st_i64(tcg_constant_i64(ctx->insn), + tcg_env, offsetof(CPUHPPAState, cr[CR_IIR])); + gen_excp(ctx, exc); + } else { + DisasDelayException *e = delay_excp(ctx, exc); + tcg_gen_brcond_i64(tcg_invert_cond(ctx->null_cond.c), + ctx->null_cond.a0, ctx->null_cond.a1, e->lab); + ctx->null_cond = cond_make_f(); + } + return true; } static bool gen_illegal(DisasContext *ctx) @@ -4697,6 +4734,19 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) default: g_assert_not_reached(); } + + for (DisasDelayException *e = ctx->delay_excp_list; e ; e = e->next) { + gen_set_label(e->lab); + if (e->set_n >= 0) { + tcg_gen_movi_i64(cpu_psw_n, e->set_n); + } + if (e->set_iir) { + tcg_gen_st_i64(tcg_constant_i64(e->insn), tcg_env, + offsetof(CPUHPPAState, cr[CR_IIR])); + } + install_iaq_entries(ctx, &e->iaq_f, &e->iaq_b); + gen_excp_1(e->excp); + } } static void hppa_tr_disas_log(const DisasContextBase *dcbase, From patchwork Wed May 15 09:40:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796911 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2889990wra; Wed, 15 May 2024 02:41:29 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWH+9iN+65KBA+Kp2lsd2+x2awU4g38Qg91ozKaT2FoeumM28tfFBcxU1qpmOSpejVMqbEvDqVcUdp115k1yxue X-Google-Smtp-Source: AGHT+IEehhWUDPaD2GwsB6PTZg9DUsjk9EBHs8KaHtsbx/z5CS6ZYYYGvktXQP1lK8Pg59rGhp6L X-Received: by 2002:a05:620a:2704:b0:792:fa98:276 with SMTP id af79cd13be357-792fa980402mr101849885a.27.1715766089735; Wed, 15 May 2024 02:41:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766089; cv=none; d=google.com; s=arc-20160816; b=m2lsj8i2UH/odJoOtVIuZrxR0Lj+DZrfcRHwmtLlCd12juKMZz96bLxYGTSmTIjQ+Z czLKYJUCgKkGhkk8VKnQkMHSZII/B8fZj9/07nV5N7/r4xLKRBgfv/xl7cHtz7fUWr8W mlb5JlzuQ+MKenNtgG1E6yd5j+SwQxEL7yt93nGaRYzYv+SQnofbuNausMsVNq/W4RTC 7mZBXhadIOOxhgAeMkUD7k9jwqr2kmdYy6nU8qh2u0SoK9V50979yo7xcnG0NFWeEM8I iFpa8C+awZBN8JNU3xVq5wiN6Y6VI30KI6++yFOep+iOLPUOyOO/Nq3oG6+qsVX4a0Yq lnNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xIMB9DvpLVvL8O/ArHYL+McDtTeWMTKUufERzC06JL4=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=v5mlowlyRlRyVoHgcsByj91eKZfXEh1Igs9Rs883fKNmBOOTUflO3seXOLAyjVwotv q2FgFT7IzHZUAoYX/As8BU80N7JCaRnqffGb03kY7CLFST3iGPLzTq9/LwIgyfrXODgf Ei5rmbtNI+xbnukrvj0B6tNdAK5QV2US8avSq3DQ6k7kMDcVrO3S4rigAMhdbNYXM0O0 2LBYEBfDTi3SJy/MXxYhu8jIAXN5Udf0FiyHAgju102m4Qzkn2zg9P1AkMd6OkOC5/45 SN3Pq+11+8DUa6E5R48MtL33yrhOWIBjhlPFA0ZyXHP1r5rjUGcAUA754FW4l8mxYZij n71g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HP58Fpsp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 29/43] target/hppa: Use delay_excp for conditional traps Date: Wed, 15 May 2024 11:40:29 +0200 Message-Id: <20240515094043.82850-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/helper.h | 1 - target/hppa/int_helper.c | 2 +- target/hppa/op_helper.c | 7 ------- target/hppa/translate.c | 41 ++++++++++++++++++++++++++++++---------- 4 files changed, 32 insertions(+), 19 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 5900fd70bc..3d0d143aed 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -1,6 +1,5 @@ DEF_HELPER_2(excp, noreturn, env, int) DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tl) -DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tl) DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl) diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index a667ee380d..1aa3e88ef1 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -134,13 +134,13 @@ void hppa_cpu_do_interrupt(CPUState *cs) switch (i) { case EXCP_ILL: case EXCP_BREAK: + case EXCP_COND: case EXCP_PRIV_REG: case EXCP_PRIV_OPR: /* IIR set via translate.c. */ break; case EXCP_OVERFLOW: - case EXCP_COND: case EXCP_ASSIST: case EXCP_DTLB_MISS: case EXCP_NA_ITLB_MISS: diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 6cf49f33b7..a8b69fd481 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -49,13 +49,6 @@ void HELPER(tsv)(CPUHPPAState *env, target_ulong cond) } } -void HELPER(tcond)(CPUHPPAState *env, target_ulong cond) -{ - if (unlikely(cond)) { - hppa_dynamic_excp(env, EXCP_COND, GETPC()); - } -} - static void atomic_store_mask32(CPUHPPAState *env, target_ulong addr, uint32_t val, uint32_t mask, uintptr_t ra) { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 706537ea59..ae291124f2 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1117,6 +1117,25 @@ static TCGv_i64 do_sub_sv(DisasContext *ctx, TCGv_i64 res, return sv; } +static void gen_tc(DisasContext *ctx, DisasCond *cond) +{ + DisasDelayException *e; + + switch (cond->c) { + case TCG_COND_NEVER: + break; + case TCG_COND_ALWAYS: + gen_excp_iir(ctx, EXCP_COND); + break; + default: + e = delay_excp(ctx, EXCP_COND); + tcg_gen_brcond_i64(cond->c, cond->a0, cond->a1, e->lab); + /* In the non-trap path, the condition is known false. */ + *cond = cond_make_f(); + break; + } +} + static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1, TCGv_i64 in2, unsigned shift, bool is_l, bool is_tsv, bool is_tc, bool is_c, unsigned cf, bool d) @@ -1175,9 +1194,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1, /* Emit any conditional trap before any writeback. */ cond = do_cond(ctx, cf, d, dest, uv, sv); if (is_tc) { - tmp = tcg_temp_new_i64(); - tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); - gen_helper_tcond(tcg_env, tmp); + gen_tc(ctx, &cond); } /* Write back the result. */ @@ -1196,6 +1213,10 @@ static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_d_sh *a, { TCGv_i64 tcg_r1, tcg_r2; + if (unlikely(is_tc && a->cf == 1)) { + /* Unconditional trap on condition. */ + return gen_excp_iir(ctx, EXCP_COND); + } if (a->cf) { nullify_over(ctx); } @@ -1211,6 +1232,10 @@ static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a, { TCGv_i64 tcg_im, tcg_r2; + if (unlikely(is_tc && a->cf == 1)) { + /* Unconditional trap on condition. */ + return gen_excp_iir(ctx, EXCP_COND); + } if (a->cf) { nullify_over(ctx); } @@ -1225,7 +1250,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, TCGv_i64 in2, bool is_tsv, bool is_b, bool is_tc, unsigned cf, bool d) { - TCGv_i64 dest, sv, cb, cb_msb, tmp; + TCGv_i64 dest, sv, cb, cb_msb; unsigned c = cf >> 1; DisasCond cond; @@ -1273,9 +1298,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, /* Emit any conditional trap before any writeback. */ if (is_tc) { - tmp = tcg_temp_new_i64(); - tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); - gen_helper_tcond(tcg_env, tmp); + gen_tc(ctx, &cond); } /* Write back the result. */ @@ -1441,9 +1464,7 @@ static void do_unit_addsub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, } if (is_tc) { - TCGv_i64 tmp = tcg_temp_new_i64(); - tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); - gen_helper_tcond(tcg_env, tmp); + gen_tc(ctx, &cond); } save_gpr(ctx, rt, dest); From patchwork Wed May 15 09:40:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796951 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2892998wra; Wed, 15 May 2024 02:51:12 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXorjlmkaLdUgqky5jRncHgk6qpXQ9CZn2BdwTgt+TQyfZJ/mbJfjsh0QpMKGaHQZc7n0A6Rm2bAVO7TryGjmQX X-Google-Smtp-Source: AGHT+IEd1xKcoJofNpZ3O6ysYOvIENWr/Ox4WkC/QHGABX2DMsDDBpdWSb2xNwBx0V/nBYAaHS4p X-Received: by 2002:a05:620a:450f:b0:792:de9e:a462 with SMTP id af79cd13be357-792de9ea546mr1150139085a.68.1715766671774; Wed, 15 May 2024 02:51:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766671; cv=none; d=google.com; s=arc-20160816; b=X4uDkqHqz+8T43c1zfGVknJ1jE53j6//e1Bg/JJlrxiEgVcz2RSIUs6xs4H/zLR6Zz 3V30Z6WnWZk+tMpNHn1UyYYX+bDE5kN3defKvhrxqEExqT7d7TEif3fx4icu/pQpBkrc KNZAPuANMmML5XM7miWyIRKeQ+8H/WUs82B5FducPxBsdZggPhryr0Fg1KbDVSOjSQdI j//TK0nMOOnunM5xjhWoGiWeFBYzGvSQnrNsxEB+Dlc/rDfJ0M1eQs1Qxs2c9/xh2G1/ CJgkIZG97FyVSdAmFY3YPlUFyS/RWW1WkQ/7cgBwrQ+VWXdOvlexMgsFhYNJRxSayBh0 H3mg== ARC-Message-Signature: i=1; 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 30/43] target/hppa: Use delay_excp for conditional trap on overflow Date: Wed, 15 May 2024 11:40:30 +0200 Message-Id: <20240515094043.82850-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/helper.h | 1 - target/hppa/int_helper.c | 2 +- target/hppa/op_helper.c | 7 ------- target/hppa/translate.c | 21 +++++++++++++-------- 4 files changed, 14 insertions(+), 17 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 3d0d143aed..c12b48a04a 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -1,5 +1,4 @@ DEF_HELPER_2(excp, noreturn, env, int) -DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tl) DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl) diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 1aa3e88ef1..97e5f0b9a7 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -134,13 +134,13 @@ void hppa_cpu_do_interrupt(CPUState *cs) switch (i) { case EXCP_ILL: case EXCP_BREAK: + case EXCP_OVERFLOW: case EXCP_COND: case EXCP_PRIV_REG: case EXCP_PRIV_OPR: /* IIR set via translate.c. */ break; - case EXCP_OVERFLOW: case EXCP_ASSIST: case EXCP_DTLB_MISS: case EXCP_NA_ITLB_MISS: diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index a8b69fd481..66cad78a57 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -42,13 +42,6 @@ G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra) cpu_loop_exit_restore(cs, ra); } -void HELPER(tsv)(CPUHPPAState *env, target_ulong cond) -{ - if (unlikely((target_long)cond < 0)) { - hppa_dynamic_excp(env, EXCP_OVERFLOW, GETPC()); - } -} - static void atomic_store_mask32(CPUHPPAState *env, target_ulong addr, uint32_t val, uint32_t mask, uintptr_t ra) { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ae291124f2..16b25a9ede 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1136,6 +1136,17 @@ static void gen_tc(DisasContext *ctx, DisasCond *cond) } } +static void gen_tsv(DisasContext *ctx, TCGv_i64 *sv, bool d) +{ + DisasCond cond = do_cond(ctx, /* SV */ 12, d, NULL, NULL, *sv); + DisasDelayException *e = delay_excp(ctx, EXCP_OVERFLOW); + + tcg_gen_brcond_i64(cond.c, cond.a0, cond.a1, e->lab); + + /* In the non-trap path, V is known zero. */ + *sv = tcg_constant_i64(0); +} + static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1, TCGv_i64 in2, unsigned shift, bool is_l, bool is_tsv, bool is_tc, bool is_c, unsigned cf, bool d) @@ -1178,10 +1189,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1, if (is_tsv || cond_need_sv(c)) { sv = do_add_sv(ctx, dest, in1, in2, orig_in1, shift, d); if (is_tsv) { - if (!d) { - tcg_gen_ext32s_i64(sv, sv); - } - gen_helper_tsv(tcg_env, sv); + gen_tsv(ctx, &sv, d); } } @@ -1282,10 +1290,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, if (is_tsv || cond_need_sv(c)) { sv = do_sub_sv(ctx, dest, in1, in2); if (is_tsv) { - if (!d) { - tcg_gen_ext32s_i64(sv, sv); - } - gen_helper_tsv(tcg_env, sv); + gen_tsv(ctx, &sv, d); } } From patchwork Wed May 15 09:40:31 2024 Content-Type: text/plain; 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 31/43] linux-user/hppa: Force all code addresses to PRIV_USER Date: Wed, 15 May 2024 11:40:31 +0200 Message-Id: <20240515094043.82850-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The kernel does this along the return path to user mode. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- linux-user/hppa/target_cpu.h | 4 ++-- target/hppa/cpu.h | 3 +++ linux-user/elfload.c | 4 ++-- linux-user/hppa/cpu_loop.c | 14 +++++++------- linux-user/hppa/signal.c | 6 ++++-- target/hppa/cpu.c | 7 +++++-- target/hppa/gdbstub.c | 6 ++++++ target/hppa/translate.c | 4 ++-- 8 files changed, 31 insertions(+), 17 deletions(-) diff --git a/linux-user/hppa/target_cpu.h b/linux-user/hppa/target_cpu.h index aacf3e9e02..4b84422a90 100644 --- a/linux-user/hppa/target_cpu.h +++ b/linux-user/hppa/target_cpu.h @@ -28,8 +28,8 @@ static inline void cpu_clone_regs_child(CPUHPPAState *env, target_ulong newsp, /* Indicate child in return value. */ env->gr[28] = 0; /* Return from the syscall. */ - env->iaoq_f = env->gr[31]; - env->iaoq_b = env->gr[31] + 4; + env->iaoq_f = env->gr[31] | PRIV_USER; + env->iaoq_b = env->iaoq_f + 4; } static inline void cpu_clone_regs_parent(CPUHPPAState *env, unsigned flags) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c37b4e12fb..5a1e720bb6 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -42,6 +42,9 @@ #define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1) #define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX) +#define PRIV_KERNEL 0 +#define PRIV_USER 3 + #define TARGET_INSN_START_EXTRA_WORDS 2 /* No need to flush MMU_ABS*_IDX */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index b473cda6b4..c1e1511ff2 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1887,8 +1887,8 @@ static inline void init_thread(struct target_pt_regs *regs, static inline void init_thread(struct target_pt_regs *regs, struct image_info *infop) { - regs->iaoq[0] = infop->entry; - regs->iaoq[1] = infop->entry + 4; + regs->iaoq[0] = infop->entry | PRIV_USER; + regs->iaoq[1] = regs->iaoq[0] + 4; regs->gr[23] = 0; regs->gr[24] = infop->argv; regs->gr[25] = infop->argc; diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index d5232f37fe..bc093b8fe8 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -129,8 +129,8 @@ void cpu_loop(CPUHPPAState *env) default: env->gr[28] = ret; /* We arrived here by faking the gateway page. Return. */ - env->iaoq_f = env->gr[31]; - env->iaoq_b = env->gr[31] + 4; + env->iaoq_f = env->gr[31] | PRIV_USER; + env->iaoq_b = env->iaoq_f + 4; break; case -QEMU_ERESTARTSYS: case -QEMU_ESIGRETURN: @@ -140,8 +140,8 @@ void cpu_loop(CPUHPPAState *env) case EXCP_SYSCALL_LWS: env->gr[21] = hppa_lws(env); /* We arrived here by faking the gateway page. Return. */ - env->iaoq_f = env->gr[31]; - env->iaoq_b = env->gr[31] + 4; + env->iaoq_f = env->gr[31] | PRIV_USER; + env->iaoq_b = env->iaoq_f + 4; break; case EXCP_IMP: force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, env->iaoq_f); @@ -152,9 +152,9 @@ void cpu_loop(CPUHPPAState *env) case EXCP_PRIV_OPR: /* check for glibc ABORT_INSTRUCTION "iitlbp %r0,(%sr0, %r0)" */ if (env->cr[CR_IIR] == 0x04000000) { - force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->iaoq_f); + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->iaoq_f); } else { - force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->iaoq_f); + force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->iaoq_f); } break; case EXCP_PRIV_REG: @@ -170,7 +170,7 @@ void cpu_loop(CPUHPPAState *env) force_sig_fault(TARGET_SIGFPE, 0, env->iaoq_f); break; case EXCP_BREAK: - force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f & ~3); + force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f); break; case EXCP_DEBUG: force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f); diff --git a/linux-user/hppa/signal.c b/linux-user/hppa/signal.c index 682ba25922..f6f094c960 100644 --- a/linux-user/hppa/signal.c +++ b/linux-user/hppa/signal.c @@ -101,7 +101,9 @@ static void restore_sigcontext(CPUArchState *env, struct target_sigcontext *sc) cpu_hppa_loaded_fr0(env); __get_user(env->iaoq_f, &sc->sc_iaoq[0]); + env->iaoq_f |= PRIV_USER; __get_user(env->iaoq_b, &sc->sc_iaoq[1]); + env->iaoq_b |= PRIV_USER; __get_user(env->cr[CR_SAR], &sc->sc_sar); } @@ -162,8 +164,8 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, unlock_user(fdesc, haddr, 0); haddr = dest; } - env->iaoq_f = haddr; - env->iaoq_b = haddr + 4; + env->iaoq_f = haddr | PRIV_USER; + env->iaoq_b = env->iaoq_f + 4; env->psw_n = 0; return; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index be8c558014..a007de5521 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -32,6 +32,9 @@ static void hppa_cpu_set_pc(CPUState *cs, vaddr value) { HPPACPU *cpu = HPPA_CPU(cs); +#ifdef CONFIG_USER_ONLY + value |= PRIV_USER; +#endif cpu->env.iaoq_f = value; cpu->env.iaoq_b = value + 4; } @@ -93,8 +96,8 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); #ifdef CONFIG_USER_ONLY - cpu->env.iaoq_f = tb->pc; - cpu->env.iaoq_b = tb->cs_base; + cpu->env.iaoq_f = tb->pc | PRIV_USER; + cpu->env.iaoq_b = tb->cs_base | PRIV_USER; #else /* Recover the IAOQ values from the GVA + PRIV. */ uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index 4a965b38d7..0daa52f7af 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -163,12 +163,18 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->cr[CR_SAR] = val & (hppa_is_pa20(env) ? 63 : 31); break; case 33: +#ifdef CONFIG_USER_ONLY + val |= PRIV_USER; +#endif env->iaoq_f = val; break; case 34: env->iasq_f = (uint64_t)val << 32; break; case 35: +#ifdef CONFIG_USER_ONLY + val |= PRIV_USER; +#endif env->iaoq_b = val; break; case 36: diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 16b25a9ede..12359bafb6 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2054,7 +2054,7 @@ static void do_page_zero(DisasContext *ctx) tcg_gen_st_i64(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])); - tcg_gen_ori_i64(next.base, cpu_gr[31], 3); + tcg_gen_ori_i64(next.base, cpu_gr[31], PRIV_USER); install_iaq_entries(ctx, &next, NULL); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; } @@ -4583,7 +4583,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->is_pa20 = hppa_is_pa20(cpu_env(cs)); #ifdef CONFIG_USER_ONLY - ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX); + ctx->privilege = PRIV_USER; ctx->mmu_idx = MMU_USER_IDX; ctx->iaoq_first = ctx->base.pc_first | ctx->privilege; ctx->iaq_b.disp = ctx->base.tb->cs_base - ctx->base.pc_first; From patchwork Wed May 15 09:40:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796923 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2890852wra; Wed, 15 May 2024 02:44:04 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWXgb6A5BFhBLYiLb95reNG4fnuK8Y1V47ETueIZ77z21SOfCeODgjY8mFtpEajXxk82NVga1R+vpEa53EGiNSm X-Google-Smtp-Source: AGHT+IHjDAAL2WIyORByUQHhwnqTUcqbANqqUE9YJfGXQL5E9Sn2VqM+dwfQIt+sjBXG8tiC3kiF X-Received: by 2002:ac8:5a16:0:b0:43c:562f:e07b with SMTP id d75a77b69052e-43dfdac2d61mr209182411cf.7.1715766244096; Wed, 15 May 2024 02:44:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766244; cv=none; d=google.com; s=arc-20160816; b=LpGov1IMhj1AYw3jud+LaUzyzGhCx4bik78E2/tA9rtSA51jAa4YpOz5xOL9ELY3kK 94D6WwTSTOJ7MKih8W3aBGGIfn85X+/YqF86mRR/jsy2de/6ic3IhHpPN2CgtkDwV8uG CTKMxqMdjUZZqiQlz51X6lmGMkQW22UUwcQ5d6IGIgIc3YNKGXK2o5lmhe3No7IEXFUE YzHWCAyWC07Rwoycv68CpaPfZWyoKjWRm/HRiosxT1fzmCd3q5odNp24OXHZ6vyvtxkt Dusrh3cfgkYm7yyI8IJ+wQc85aaZXWFl8iT1VSDNzmSrNBliEKs3+JEQns7QVCuN2WA7 nA+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=CJ/OU2GzKkfi9eg8xXZcP2KYs11/NjQ23m2qkET+jGw=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=iLqV9/6B+lTGiT7WD5dMX5JwYMeTFDcHQXekwvmDILk+3fMe+zScbEp2Gpnf+0Xmlu n2v/tEgR6BcPC2ZN4ptMu7SCJ/dTFkMaPiX/Fi2FY+lMoKBHvGY9DBhIN1rVVtNXV/zY tX6djEE6Zm55i1XW1A6QbCICu5RCgNpuV8ev28/OK3Dht4cSUxGnqQIRdtNXePf1ENo5 AVm04Hnv0q15ltSssdQyGhNad6ZAdgGu2Qw8sSbXF1gT/GdnhLohHtYXp/Y9jJ30a2oB DrSBP7yKAClBAzKkv1x8VKAO0Lx6EBzMTRs0Etf3yRZf9xaTUq33d8cThSmYRo2WkXwn Cr5Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TTzYBRny; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 32/43] target/hppa: Store full iaoq_f and page offset of iaoq_b in TB Date: Wed, 15 May 2024 11:40:32 +0200 Message-Id: <20240515094043.82850-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In preparation for CF_PCREL. store the iaoq_f in 3 parts: high bits in cs_base, middle bits in pc, and low bits in priv. For iaoq_b, set a bit for either of space or page differing, else the page offset. Install iaq entries before goto_tb. The change to not record the full direct branch difference in TB means that we have to store at least iaoq_b before goto_tb. But since a later change to enable CF_PCREL will require both iaoq_f and iaoq_b to be updated before goto_tb, go ahead and update both fields now. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 ++ target/hppa/cpu.c | 72 ++++++++++++++++++----------------------- target/hppa/translate.c | 29 +++++++++-------- 3 files changed, 48 insertions(+), 55 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 5a1e720bb6..1232a4cef2 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -341,6 +341,8 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); #define TB_FLAG_SR_SAME PSW_I #define TB_FLAG_PRIV_SHIFT 8 #define TB_FLAG_UNALIGN 0x400 +#define CS_BASE_DIFFPAGE (1 << 12) +#define CS_BASE_DIFFSPACE (1 << 13) void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index a007de5521..003af63e20 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -48,36 +48,43 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) } void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) + uint64_t *pcsbase, uint32_t *pflags) { uint32_t flags = env->psw_n * PSW_N; + uint64_t cs_base = 0; + + /* + * TB lookup assumes that PC contains the complete virtual address. + * If we leave space+offset separate, we'll get ITLB misses to an + * incomplete virtual address. This also means that we must separate + * out current cpu privilege from the low bits of IAOQ_F. + */ + *pc = hppa_cpu_get_pc(env_cpu(env)); + flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; + + if (hppa_is_pa20(env)) { + cs_base = env->iaoq_f & MAKE_64BIT_MASK(32, 32); + } + + /* + * The only really interesting case is if IAQ_Back is on the same page + * as IAQ_Front, so that we can use goto_tb between the blocks. In all + * other cases, we'll be ending the TranslationBlock with one insn and + * not linking between them. + */ + if (env->iasq_f != env->iasq_b) { + cs_base |= CS_BASE_DIFFSPACE; + } else if ((env->iaoq_f ^ env->iaoq_b) & TARGET_PAGE_MASK) { + cs_base |= CS_BASE_DIFFPAGE; + } else { + cs_base |= env->iaoq_b & ~TARGET_PAGE_MASK; + } - /* TB lookup assumes that PC contains the complete virtual address. - If we leave space+offset separate, we'll get ITLB misses to an - incomplete virtual address. This also means that we must separate - out current cpu privilege from the low bits of IAOQ_F. */ #ifdef CONFIG_USER_ONLY - *pc = env->iaoq_f & -4; - *cs_base = env->iaoq_b & -4; flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; #else /* ??? E, T, H, L, B bits need to be here, when implemented. */ flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); - flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; - - *pc = hppa_cpu_get_pc(env_cpu(env)); - *cs_base = env->iasq_f; - - /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero - low 32-bits of CS_BASE. This will succeed for all direct branches, - which is the primary case we care about -- using goto_tb within a page. - Failure is indicated by a zero difference. */ - if (env->iasq_f == env->iasq_b) { - target_long diff = env->iaoq_b - env->iaoq_f; - if (diff == (int32_t)diff) { - *cs_base |= (uint32_t)diff; - } - } if ((env->sr[4] == env->sr[5]) & (env->sr[4] == env->sr[6]) & (env->sr[4] == env->sr[7])) { @@ -85,6 +92,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, } #endif + *pcsbase = cs_base; *pflags = flags; } @@ -93,25 +101,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, { HPPACPU *cpu = HPPA_CPU(cs); - tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); - -#ifdef CONFIG_USER_ONLY - cpu->env.iaoq_f = tb->pc | PRIV_USER; - cpu->env.iaoq_b = tb->cs_base | PRIV_USER; -#else - /* Recover the IAOQ values from the GVA + PRIV. */ - uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; - target_ulong cs_base = tb->cs_base; - target_ulong iasq_f = cs_base & ~0xffffffffull; - int32_t diff = cs_base; - - cpu->env.iasq_f = iasq_f; - cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv; - if (diff) { - cpu->env.iaoq_b = cpu->env.iaoq_f + diff; - } -#endif - + /* IAQ is always up-to-date before goto_tb. */ cpu->env.psw_n = (tb->flags & PSW_N) != 0; } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 12359bafb6..70df42f558 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -770,12 +770,11 @@ static bool use_nullify_skip(DisasContext *ctx) static void gen_goto_tb(DisasContext *ctx, int which, const DisasIAQE *f, const DisasIAQE *b) { + install_iaq_entries(ctx, f, b); if (use_goto_tb(ctx, f, b)) { tcg_gen_goto_tb(which); - install_iaq_entries(ctx, f, b); tcg_gen_exit_tb(ctx->base.tb, which); } else { - install_iaq_entries(ctx, f, b); tcg_gen_lookup_and_goto_ptr(); } } @@ -4576,6 +4575,7 @@ static bool trans_diag_unimp(DisasContext *ctx, arg_diag_unimp *a) static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); + uint64_t cs_base, iaoq_f, iaoq_b; int bound; ctx->cs = cs; @@ -4585,29 +4585,30 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #ifdef CONFIG_USER_ONLY ctx->privilege = PRIV_USER; ctx->mmu_idx = MMU_USER_IDX; - ctx->iaoq_first = ctx->base.pc_first | ctx->privilege; - ctx->iaq_b.disp = ctx->base.tb->cs_base - ctx->base.pc_first; ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; ctx->mmu_idx = (ctx->tb_flags & PSW_D ? PRIV_P_TO_MMU_IDX(ctx->privilege, ctx->tb_flags & PSW_P) : ctx->tb_flags & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX); +#endif /* Recover the IAOQ values from the GVA + PRIV. */ - uint64_t cs_base = ctx->base.tb->cs_base; - uint64_t iasq_f = cs_base & ~0xffffffffull; - int32_t diff = cs_base; + cs_base = ctx->base.tb->cs_base; + iaoq_f = cs_base & MAKE_64BIT_MASK(32, 32); + iaoq_f |= ctx->base.pc_first & MAKE_64BIT_MASK(2, 30); + iaoq_f |= ctx->privilege; + ctx->iaoq_first = iaoq_f; - ctx->iaoq_first = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; - - if (diff) { - ctx->iaq_b.disp = diff; - } else { - ctx->iaq_b.base = cpu_iaoq_b; + if (unlikely(cs_base & CS_BASE_DIFFSPACE)) { ctx->iaq_b.space = cpu_iasq_b; + ctx->iaq_b.base = cpu_iaoq_b; + } else if (unlikely(cs_base & CS_BASE_DIFFPAGE)) { + ctx->iaq_b.base = cpu_iaoq_b; + } else { + iaoq_b = (iaoq_f & TARGET_PAGE_MASK) | (cs_base & ~TARGET_PAGE_MASK); + ctx->iaq_b.disp = iaoq_b - iaoq_f; } -#endif ctx->zero = tcg_constant_i64(0); From patchwork Wed May 15 09:40:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796925 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2890895wra; Wed, 15 May 2024 02:44:10 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUcy3m5+rZL1/CpIW305d70QTwsYqHZTpNvFfSkQaSPMUAWsTDPiXuf4+CeuEdLV/sk8BCYW3Bc+Ms+WU6oQaVF X-Google-Smtp-Source: AGHT+IEKravjiqgbi9g8/de6Y2pwKYF6T74TkxLSHlHFRbbCTHRfDwxG9K9dRRUz0xQMkadJ9FgL X-Received: by 2002:a05:6808:181e:b0:3c7:366b:980a with SMTP id 5614622812f47-3c997037929mr20912600b6e.5.1715766250732; Wed, 15 May 2024 02:44:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766250; cv=none; d=google.com; s=arc-20160816; b=qW81XCZrljxbBBo+ZFel5+cUJOIWOzM3abik1zar4YkuvjrDMgQvXwNPa3JWY0BVQl sz6WNrHUhUUlIG40nLp41NajhNqR9kjxZZdBUWv+Er89rXYXd0GMQntDiGzyl8xaBKty C1ByiaPf+/WXSfebTDEv9+VT2VqxTZrdgMD0awdxujf4xzyYIah2LW+D/Gh3AUBht+Vc cxGF4JxnUl2TXlFLUMGnJljKWvyiDrHUh73wqsi04AMQU6ceaVk+thL3enPwL4IQ6QGS TqHOXex/E6nF3xhZtA+CdR0lVlcyIgxvV2dFOyCoL9tqL2Ig5XzPJgAVVaDcOcsiKiVd BZew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QR5yb7F9XGohps2L09MGmPdjKhQ67DsiVbKjELjIFUE=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=gdUalve6BGObM3h0W+ZmXG84OY0bLss7bvG/64GPyhHi4MOoEMBba0uK6YArUyfdRW tiVV106NGy8i8bzwvr1vhoZw4rFJ0GXdKJj65DI9V6ZoM1sOpT29pm22/of5SUOj5ZGf 9yGioKLlvzzYOoC7JdlxFEOZALgMnzq1juqTRh/Xl+RIAb2D/gC8smWqFva/qR5O2zfB s5siKAagn1oGKr65Vi4g57MMRBM2z3fnk5zPlYzaf4Mu1Fy1QeDUN4iIOa3bMwEylFZA zkvBNmQrc4No9Ygl69Twzxka14Kwhs4KpozrHYd3wA7Minf4W56MPrYvH2hr7OdWQ4Wa dxIA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lMsVruP+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 33/43] target/hppa: Do not mask in copy_iaoq_entry Date: Wed, 15 May 2024 11:40:33 +0200 Message-Id: <20240515094043.82850-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org As with loads and stores, code offsets are kept intact until the full gva is formed. In qemu, this is in cpu_get_tb_cpu_state. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 70df42f558..ab8dd161ad 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -637,15 +637,10 @@ static DisasIAQE iaqe_next_absv(DisasContext *ctx, TCGv_i64 var) static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, const DisasIAQE *src) { - uint64_t mask = gva_offset_mask(ctx->tb_flags); - if (src->base == NULL) { - tcg_gen_movi_i64(dest, (ctx->iaoq_first + src->disp) & mask); - } else if (src->disp == 0) { - tcg_gen_andi_i64(dest, src->base, mask); + tcg_gen_movi_i64(dest, ctx->iaoq_first + src->disp); } else { tcg_gen_addi_i64(dest, src->base, src->disp); - tcg_gen_andi_i64(dest, dest, mask); } } From patchwork Wed May 15 09:40:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796915 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2890090wra; Wed, 15 May 2024 02:41:48 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVKhB3jhBbRRSH1Kxt74pFGqTlNdaj7O5QsfP7gDW8r7xUaUnGBnqYZ/gQvx2BQtUWCJQHJ5nsulQurZa73UMiP X-Google-Smtp-Source: AGHT+IH37OMbje9jSS9Gh43C8nsVv0LFmeOQKshxB8JFUPhQEEuzNfcUJvKIk2x0HmkS5h3I88bf X-Received: by 2002:a05:622a:5b0f:b0:43e:9eb:d714 with SMTP id d75a77b69052e-43e09ebd9c1mr153787721cf.54.1715766107866; Wed, 15 May 2024 02:41:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766107; cv=none; d=google.com; s=arc-20160816; b=HEsIivYZXYlVQgFPQ4HW68zBPyVQ+YOJNsorh8nyIfAK5zWS9g0twYp/0M7fkzTv3D lmKrAskroPtW/40xWE6hgRcDgLiwalgHDwANahKcMAETGrqFfuFqkHg1KQG2w0UfFAla zG2Ny206qppAK1oZW3qPfQD4uiEw35IRxYUG0XYQ+02hidpFXE/7sLNxJCBrWIbpfdc7 qOhm92SUD3aql3BU9HIlmPySZnYWOkhvOQ84qQh8LWrpXnNKL1e8Q1IBe4185dlH9OB1 AT09YMoLUYbBhlNKeiis/EMxJeeB3gb7AVj6VDEtoCmBFqg4Vi0KaZtckHRNHamXRI4y zfog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hio8O4VlGrDNaYjRplJpmTel6P9cR/NqGITHgXJe1FA=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=ij/lInMn4pS6neAsF+9RvsqPRU8XGAaA5/EYvVmsw7WCIKko3kExbDx1zfoKb55edz EBi2tn5Tvja8i9VToCK7GmS/VHt9ZoyziJ94PWbACUjdOhJCNxs+dJXtA2fU1eaC8mWn 5qSANSdwCySistig2qKebJ9uauze6lroG7AmjEjNinTU729GvlLf2Nte3D8l1s2banl+ DEBlYs9Xt2e92yUm9UzCxT4ciImIXPd2yPyLEqjiLE/4dkUIbw+dqC7pfX54/MsATJxX 4JDRPy2sHteNa1uWxntqPvNCS0QH9DM70ixWMm+JtnGxMm0qvEG04Ugm8NKYOOGa7Vx8 b/uw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H9bT0aoq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 34/43] target/hppa: Improve hppa_cpu_dump_state Date: Wed, 15 May 2024 11:40:34 +0200 Message-Id: <20240515094043.82850-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Print both raw IAQ_Front and IAQ_Back as well as the GVAs. Print control registers in system mode. Print floating point registers if CPU_DUMP_FPU. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/helper.c | 60 +++++++++++++++++++++++++++++++++++++++----- 1 file changed, 54 insertions(+), 6 deletions(-) diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 9d217d051c..7d22c248fb 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -102,6 +102,19 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) { +#ifndef CONFIG_USER_ONLY + static const char cr_name[32][5] = { + "RC", "CR1", "CR2", "CR3", + "CR4", "CR5", "CR6", "CR7", + "PID1", "PID2", "CCR", "SAR", + "PID3", "PID4", "IVA", "EIEM", + "ITMR", "ISQF", "IOQF", "IIR", + "ISR", "IOR", "IPSW", "EIRR", + "TR0", "TR1", "TR2", "TR3", + "TR4", "TR5", "TR6", "TR7", + }; +#endif + CPUHPPAState *env = cpu_env(cs); target_ulong psw = cpu_hppa_get_psw(env); target_ulong psw_cb; @@ -117,11 +130,12 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) m = UINT32_MAX; } - qemu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx - " IIR %0*" PRIx64 "\n", + qemu_fprintf(f, "IA_F %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n" + "IA_B %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n", + env->iasq_f >> 32, w, m & env->iaoq_f, hppa_form_gva_psw(psw, env->iasq_f, env->iaoq_f), - hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b), - w, m & env->cr[CR_IIR]); + env->iasq_b >> 32, w, m & env->iaoq_b, + hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b)); psw_c[0] = (psw & PSW_W ? 'W' : '-'); psw_c[1] = (psw & PSW_E ? 'E' : '-'); @@ -154,12 +168,46 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) (i & 3) == 3 ? '\n' : ' '); } #ifndef CONFIG_USER_ONLY + for (i = 0; i < 32; i++) { + qemu_fprintf(f, "%-4s %0*" PRIx64 "%c", + cr_name[i], w, m & env->cr[i], + (i & 3) == 3 ? '\n' : ' '); + } + qemu_fprintf(f, "ISQB %0*" PRIx64 " IOQB %0*" PRIx64 "\n", + w, m & env->cr_back[0], w, m & env->cr_back[1]); for (i = 0; i < 8; i++) { qemu_fprintf(f, "SR%02d %08x%c", i, (uint32_t)(env->sr[i] >> 32), (i & 3) == 3 ? '\n' : ' '); } #endif - qemu_fprintf(f, "\n"); - /* ??? FR */ + if (flags & CPU_DUMP_FPU) { + static const char rm[4][4] = { "RN", "RZ", "R+", "R-" }; + char flg[6], ena[6]; + uint32_t fpsr = env->fr0_shadow; + + flg[0] = (fpsr & R_FPSR_FLG_V_MASK ? 'V' : '-'); + flg[1] = (fpsr & R_FPSR_FLG_Z_MASK ? 'Z' : '-'); + flg[2] = (fpsr & R_FPSR_FLG_O_MASK ? 'O' : '-'); + flg[3] = (fpsr & R_FPSR_FLG_U_MASK ? 'U' : '-'); + flg[4] = (fpsr & R_FPSR_FLG_I_MASK ? 'I' : '-'); + flg[5] = '\0'; + + ena[0] = (fpsr & R_FPSR_ENA_V_MASK ? 'V' : '-'); + ena[1] = (fpsr & R_FPSR_ENA_Z_MASK ? 'Z' : '-'); + ena[2] = (fpsr & R_FPSR_ENA_O_MASK ? 'O' : '-'); + ena[3] = (fpsr & R_FPSR_ENA_U_MASK ? 'U' : '-'); + ena[4] = (fpsr & R_FPSR_ENA_I_MASK ? 'I' : '-'); + ena[5] = '\0'; + + qemu_fprintf(f, "FPSR %08x flag %s enable %s %s\n", + fpsr, flg, ena, rm[FIELD_EX32(fpsr, FPSR, RM)]); + + for (i = 0; i < 32; i++) { + qemu_fprintf(f, "FR%02d %016" PRIx64 "%c", + i, env->fr[i], (i & 3) == 3 ? '\n' : ' '); + } + } + + qemu_fprintf(f, "\n"); } From patchwork Wed May 15 09:40:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796939 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2891976wra; Wed, 15 May 2024 02:47:46 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWK+8f+Hi1iv6YI+LPs8M+zAB16KRlPnfqBI8mG1aohN1jV6InXBPUJMEecCFzYvxAoQ85HmbxHEsjt3yM0P5jy X-Google-Smtp-Source: AGHT+IEfMXKr38PCDlkJm6sSmLX3XZn9fV1WYKw+2IwaGwZqXEK5ddB/uWF//8JUfQL7HiU2btIv X-Received: by 2002:a05:620a:5695:b0:790:9720:64f7 with SMTP id af79cd13be357-792c75af04cmr1757852985a.40.1715766465826; Wed, 15 May 2024 02:47:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766465; cv=none; d=google.com; s=arc-20160816; b=ai7H5yKcwDRBV4i0ucL+DxFgCao+Kcwtr/zIfjGg7ci7STVEWJH9MdswpvndH3F9A+ bzd/omg0bCH1DrD+JO2hrtAyrMAagGr7YF/l9w+bycSgW231zOou97c3785YhNeRoB6K uX9smHj8JrKZ8grTx9nrmdGzw6Dm9xR48C2YUnmQMALRp7nuQ4qOw2J5L5s23QUNOCqU S3w/4VTGMPbch0QedN1Usw3M+11QxTlx/tKpO9nlqf2mo7KTdDEsQLVD0c+P96V8XqzU NGehl4gyMwdfgfDNXKjwU8LlQDqfjo8NA9+vf/R2UkiauXgv+yC0VPpxBzsZr+y609LC d5Kw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TRr5iMjk/iKTg9QSCtlcsOfq6KzG2dbDyArDFZKIcHE=; fh=3//KcqJEsa04kIBt5Nb/DJuP+2GuH1NwDRxnSl44zdw=; b=BZfinlzRv64zWmmyB7Pm1mhrRpnPD36Nr7AQSP6Dy6RwHZu7FyD7LsFDPqHiIEc3TC N1QI6yCd1X1Led3X5UfJ3h6T67BlmNIlNlKe80vumX4Df6Oq9p/6McJYTegu/2UnM8RX /KNF9P6hOKRNEwEdmlK8SVazg4uougQwjJg/H464yx/xz7GX9Fw6ag7f6h7T8Dk4lCGB lbTtVUEzAhAQWd98N62IFRBQ1vTyMzmeUjEZCDDZeBq7PA8KljBHDuTnBTSyIm6bIvyV EJCWsBc2SG1m2hzC53PHMRz1Im08+gYBu1S6AwIEiFx5gXdnHi2L4a0rM5NvpZZdy1xw HkmQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jJII4ey5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 35/43] target/hppa: Split PSW X and B into their own field Date: Wed, 15 May 2024 11:40:35 +0200 Message-Id: <20240515094043.82850-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Generally, both of these bits are cleared at the end of each instruction. By separating these, we will be able to clear both with a single insn, instead of 2 or 3. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 3 ++- target/hppa/helper.c | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 1232a4cef2..f247ad56d7 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -208,7 +208,8 @@ typedef struct CPUArchState { uint64_t fr[32]; uint64_t sr[8]; /* stored shifted into place for gva */ - target_ulong psw; /* All psw bits except the following: */ + uint32_t psw; /* All psw bits except the following: */ + uint32_t psw_xb; /* X and B, in their normal positions */ target_ulong psw_n; /* boolean */ target_long psw_v; /* in most significant bit */ diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 7d22c248fb..b79ddd8184 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -54,7 +54,7 @@ target_ulong cpu_hppa_get_psw(CPUHPPAState *env) psw |= env->psw_n * PSW_N; psw |= (env->psw_v < 0) * PSW_V; - psw |= env->psw; + psw |= env->psw | env->psw_xb; return psw; } @@ -76,8 +76,8 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) } psw &= ~reserved; - env->psw = psw & (uint32_t)~(PSW_N | PSW_V | PSW_CB); - + env->psw = psw & (uint32_t)~(PSW_B | PSW_N | PSW_V | PSW_X | PSW_CB); + env->psw_xb = psw & (PSW_X | PSW_B); env->psw_n = (psw / PSW_N) & 1; env->psw_v = -((psw / PSW_V) & 1); From patchwork Wed May 15 09:40:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796934 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2891123wra; Wed, 15 May 2024 02:44:58 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVDiDLZ5y8tkr7wgT+49wh3bJX2BeFhXR0AEUMyZPgwM6/Bzy0eqDGbBPnVeFCXwJeNUCfBWvkoGYZopOSWKqJE X-Google-Smtp-Source: AGHT+IFj9Mq7dp+WDohysQm03Yqt5rAh8v4lcoKQUOc3VWiULxb01TgP+t4kLvDnOkzAv0nHwgwJ X-Received: by 2002:a05:620a:5a:b0:78a:6a01:d8d with SMTP id af79cd13be357-792c7610220mr1584026185a.65.1715766297704; Wed, 15 May 2024 02:44:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766297; cv=none; d=google.com; s=arc-20160816; b=XcMX7BSuioEpfF0wjLMTXzhHlzN/YN7JW9FpjRA5yJ7OlPr+SwIkJ4jIbKP2Bc/ibd 2/rUgL9RHhTEcQrca6xKkJuWrGyTLHbkRFDXMaQKYzLpB9moZZs7sA6+cSzn+Psh1S2m 8FnqUB5LY83TBvruORqjWul0kL4LIWMX2DR9MlHFXrXIrmI+6SL+2Q6hlFk4daBnH5h5 KumxPbIcVk3CzwtrhAqg/zeNhH5TmAUt//NclcSVCR0pzzT2BYuGtTfWoNMnvVWmX4ql /Fd2IkJYeB3y4L6gluvV3h4j27nZpVEiQmTmfVx5hmla6IS9iuM2OMZ6P8wihGY/Yfyu cPEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MTXjrqHLm9JH8e5dSGpKeq4vzWp/XOEH4I3ff7qowb0=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=RUj+6M2c4MxXPV8BZ1bAK68aPjej5vEFiMiCx3F1Izt3FtdnxG0p506x0ge4Ud6x5G UtKm3xDe0R4n2wEiXpjUiLaYbLen2RBsAaxUa0spI+Fvs2w1WkQag0wzHgZx/keDcfkb KjKgz59jM/MVhShcaheqNN+hdCxnih1ChnzjoCuW/YvA5Oov4Y6Rbi9FRX11rLgd/+YK gjEBYR6gg8x0e1YyGnuon4hhTsi8sAAojaES01NOfMPsF+tk7+GMGaJpiyrCz76/ovds yJPTOBWqcNSZw/l/YPmqQKSNc8dh9BeNjEgUlJgCa9DJcIVoU4mn/Xvp9/OeYjj2eClg x+ZQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a0YENjc8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 36/43] target/hppa: Manage PSW_X and PSW_B in translator Date: Wed, 15 May 2024 11:40:36 +0200 Message-Id: <20240515094043.82850-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org PSW_X is cleared after every instruction, and only set by RFI. PSW_B is cleared after every non-branch, or branch not taken, and only set by taken branches. We can clear both bits with a single store, at most once per TB. Taken branches set PSW_B, at most once per TB. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/cpu.c | 10 ++++++--- target/hppa/translate.c | 50 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+), 3 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 003af63e20..5f0df0697a 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -50,7 +50,7 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, uint64_t *pcsbase, uint32_t *pflags) { - uint32_t flags = env->psw_n * PSW_N; + uint32_t flags = 0; uint64_t cs_base = 0; /* @@ -80,11 +80,14 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, cs_base |= env->iaoq_b & ~TARGET_PAGE_MASK; } + /* ??? E, T, H, L bits need to be here, when implemented. */ + flags |= env->psw_n * PSW_N; + flags |= env->psw_xb; + flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); + #ifdef CONFIG_USER_ONLY flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; #else - /* ??? E, T, H, L, B bits need to be here, when implemented. */ - flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); if ((env->sr[4] == env->sr[5]) & (env->sr[4] == env->sr[6]) & (env->sr[4] == env->sr[7])) { @@ -103,6 +106,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, /* IAQ is always up-to-date before goto_tb. */ cpu->env.psw_n = (tb->flags & PSW_N) != 0; + cpu->env.psw_xb = tb->flags & (PSW_X | PSW_B); } static void hppa_restore_state_to_opc(CPUState *cs, diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ab8dd161ad..f7d54f4009 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -84,7 +84,9 @@ typedef struct DisasContext { uint32_t tb_flags; int mmu_idx; int privilege; + uint32_t psw_xb; bool psw_n_nonzero; + bool psw_b_next; bool is_pa20; bool insn_start_updated; @@ -263,6 +265,7 @@ static TCGv_i64 cpu_psw_n; static TCGv_i64 cpu_psw_v; static TCGv_i64 cpu_psw_cb; static TCGv_i64 cpu_psw_cb_msb; +static TCGv_i32 cpu_psw_xb; void hppa_translate_init(void) { @@ -315,6 +318,9 @@ void hppa_translate_init(void) *v->var = tcg_global_mem_new(tcg_env, v->ofs, v->name); } + cpu_psw_xb = tcg_global_mem_new_i32(tcg_env, + offsetof(CPUHPPAState, psw_xb), + "psw_xb"); cpu_iasq_f = tcg_global_mem_new_i64(tcg_env, offsetof(CPUHPPAState, iasq_f), "iasq_f"); @@ -509,6 +515,25 @@ static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg) #endif } +/* + * Write a value to psw_xb, bearing in mind the known value. + * To be used just before exiting the TB, so do not update the known value. + */ +static void store_psw_xb(DisasContext *ctx, uint32_t xb) +{ + tcg_debug_assert(xb == 0 || xb == PSW_B); + if (ctx->psw_xb != xb) { + tcg_gen_movi_i32(cpu_psw_xb, xb); + } +} + +/* Write a value to psw_xb, and update the known value. */ +static void set_psw_xb(DisasContext *ctx, uint32_t xb) +{ + store_psw_xb(ctx, xb); + ctx->psw_xb = xb; +} + /* Skip over the implementation of an insn that has been nullified. Use this when the insn is too complex for a conditional move. */ static void nullify_over(DisasContext *ctx) @@ -576,6 +601,8 @@ static bool nullify_end(DisasContext *ctx) /* For NEXT, NORETURN, STALE, we can easily continue (or exit). For UPDATED, we cannot update on the nullified path. */ assert(status != DISAS_IAQ_N_UPDATED); + /* Taken branches are handled manually. */ + assert(!ctx->psw_b_next); if (likely(null_lab == NULL)) { /* The current insn wasn't conditional or handled the condition @@ -1843,6 +1870,7 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, if (is_n) { if (use_nullify_skip(ctx)) { nullify_set(ctx, 0); + store_psw_xb(ctx, 0); gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); ctx->base.is_jmp = DISAS_NORETURN; return true; @@ -1850,20 +1878,24 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, ctx->null_cond.c = TCG_COND_ALWAYS; } ctx->iaq_n = &ctx->iaq_j; + ctx->psw_b_next = true; } else { nullify_over(ctx); install_link(ctx, link, false); if (is_n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); + store_psw_xb(ctx, 0); gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); } else { nullify_set(ctx, is_n); + store_psw_xb(ctx, PSW_B); gen_goto_tb(ctx, 0, &ctx->iaq_b, &ctx->iaq_j); } nullify_end(ctx); nullify_set(ctx, 0); + store_psw_xb(ctx, 0); gen_goto_tb(ctx, 1, &ctx->iaq_b, NULL); ctx->base.is_jmp = DISAS_NORETURN; } @@ -1894,6 +1926,7 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, n = is_n && disp < 0; if (n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); + store_psw_xb(ctx, 0); next = iaqe_incr(&ctx->iaq_b, 4); gen_goto_tb(ctx, 0, &next, NULL); } else { @@ -1902,6 +1935,7 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, ctx->null_lab = NULL; } nullify_set(ctx, n); + store_psw_xb(ctx, 0); gen_goto_tb(ctx, 0, &ctx->iaq_b, NULL); } @@ -1913,9 +1947,11 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, next = iaqe_branchi(ctx, disp); if (n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); + store_psw_xb(ctx, 0); gen_goto_tb(ctx, 1, &next, NULL); } else { nullify_set(ctx, n); + store_psw_xb(ctx, PSW_B); gen_goto_tb(ctx, 1, &ctx->iaq_b, &next); } @@ -1949,6 +1985,7 @@ static bool do_ibranch(DisasContext *ctx, unsigned link, ctx->null_cond.c = TCG_COND_ALWAYS; } ctx->iaq_n = &ctx->iaq_j; + ctx->psw_b_next = true; return true; } @@ -1958,9 +1995,11 @@ static bool do_ibranch(DisasContext *ctx, unsigned link, if (is_n && use_nullify_skip(ctx)) { install_iaq_entries(ctx, &ctx->iaq_j, NULL); nullify_set(ctx, 0); + store_psw_xb(ctx, 0); } else { install_iaq_entries(ctx, &ctx->iaq_b, &ctx->iaq_j); nullify_set(ctx, is_n); + store_psw_xb(ctx, PSW_B); } tcg_gen_lookup_and_goto_ptr(); @@ -2387,6 +2426,7 @@ static bool trans_halt(DisasContext *ctx, arg_halt *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY + set_psw_xb(ctx, 0); nullify_over(ctx); gen_helper_halt(tcg_env); ctx->base.is_jmp = DISAS_NORETURN; @@ -2398,6 +2438,7 @@ static bool trans_reset(DisasContext *ctx, arg_reset *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY + set_psw_xb(ctx, 0); nullify_over(ctx); gen_helper_reset(tcg_env); ctx->base.is_jmp = DISAS_NORETURN; @@ -2792,6 +2833,9 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) if ((rt == 10 || rt == 31) && r1 == rt && r2 == rt) { /* PAUSE */ /* No need to check for supervisor, as userland can only pause until the next timer interrupt. */ + + set_psw_xb(ctx, 0); + nullify_over(ctx); /* Advance the instruction queue. */ @@ -4576,6 +4620,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->cs = cs; ctx->tb_flags = ctx->base.tb->flags; ctx->is_pa20 = hppa_is_pa20(cpu_env(cs)); + ctx->psw_xb = ctx->tb_flags & (PSW_X | PSW_B); #ifdef CONFIG_USER_ONLY ctx->privilege = PRIV_USER; @@ -4662,6 +4707,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) */ ctx->iaq_n = NULL; memset(&ctx->iaq_j, 0, sizeof(ctx->iaq_j)); + ctx->psw_b_next = false; if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) { ctx->null_cond.c = TCG_COND_NEVER; @@ -4674,6 +4720,10 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) ret = ctx->base.is_jmp; assert(ctx->null_lab == NULL); } + + if (ret != DISAS_NORETURN) { + set_psw_xb(ctx, ctx->psw_b_next ? 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 37/43] target/hppa: Implement PSW_B Date: Wed, 15 May 2024 11:40:37 +0200 Message-Id: <20240515094043.82850-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org PSW_B causes B,GATE to trap as an illegal instruction, removing our previous sequential execution test that was merely an approximation. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 25 ++++++------------------- 1 file changed, 6 insertions(+), 19 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index f7d54f4009..f40ac92e98 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2062,11 +2062,8 @@ static void do_page_zero(DisasContext *ctx) g_assert_not_reached(); } - /* Check that we didn't arrive here via some means that allowed - non-sequential instruction execution. Normally the PSW[B] bit - detects this by disallowing the B,GATE instruction to execute - under such conditions. */ - if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp != 4) { + /* If PSW[B] is set, the B,GATE insn would trap. */ + if (ctx->psw_xb & PSW_B) { goto do_sigill; } @@ -3965,23 +3962,13 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) { int64_t disp = a->disp; - nullify_over(ctx); - - /* Make sure the caller hasn't done something weird with the queue. - * ??? This is not quite the same as the PSW[B] bit, which would be - * expensive to track. Real hardware will trap for - * b gateway - * b gateway+4 (in delay slot of first branch) - * However, checking for a non-sequential instruction queue *will* - * diagnose the security hole - * b gateway - * b evil - * in which instructions at evil would run with increased privs. - */ - if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp != ctx->iaq_f.disp + 4) { + /* Trap if PSW[B] is set. */ + if (ctx->psw_xb & PSW_B) { return gen_illegal(ctx); } + nullify_over(ctx); + #ifndef CONFIG_USER_ONLY if (ctx->tb_flags & PSW_C) { int type = hppa_artype_for_page(cpu_env(ctx->cs), ctx->base.pc_next); From patchwork Wed May 15 09:40:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796921 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2890506wra; Wed, 15 May 2024 02:42:56 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW1lILcp1yRXgDk6NYdWJrWTfWnZOlqudEvNx+mtWV6NV/kebYw24mETAEXfsFhZsJduav+L26SRiEUecMDIe7e X-Google-Smtp-Source: AGHT+IGxd8scdKKu9JHLB816PVdh5MT3O7uIooDC8JuUnqyvOuMmRP6qbp1h6IhPpfN8xylk5S2K X-Received: by 2002:a05:622a:28a:b0:43a:fa0d:92e6 with SMTP id d75a77b69052e-43dfdaab24emr166496581cf.4.1715766176323; Wed, 15 May 2024 02:42:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766176; cv=none; d=google.com; s=arc-20160816; b=sE5kew2P7M/2XQcfamLVVCPnsW7WcpPrWDIYNp6AmdCLtfXI1piztCMZ1mqbaZYX12 +GY+7awRCHerUo5lwX3YPClZzJkku4T2j9rFonYCwnCxcqynipQOEnRZcYAFcTxFvCSV LclV7HrrMAGdi8MaY+3gDFJ1KB6AAV0076ZH1X57OBQ/Ztpps44gi1fhCFRoNiVdVRID zx1sbmKTEUtjeJnplg9kXwA9iSPYwFe6I0smyc5qQAZCAffc27MgwmdpeFDg0CiqK1xD bSlWxv9S8YPvwlKj8V1SrxuXp9bkpxx4C5mEbyMlZVDGhKiQMJPTvHqrbCuEtvv+8V0R /q0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8eoH9KfOs+hCN0P8TyHxNIpq+Yw+C+KsTM42MvAgaJI=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=pFX/hzvA8wx8YT7I45UxRI4uXweV8GaM5ymXC++l8yUysY7hPQFKyQohLe/yZ+ykRf xqUNCTnkszlBlWj0i8TuKZpJolmGhM4n/3dQHUEtpT+dTOc7YciQICTRU98Pn6jEFoHg Phki+GWPSQAAW2KvS1sDRMYUufaSAcoIVxnKPU1NmJ/JUcBmdNY2md2paq1XbHSN5DHB iWwFUkMQuJtL+tN/MWiiglgW0LCwFkZKL2A9vTlVCavTGzz1/jvDn+mj2Y1D6lw2KYia muEuGk2SWLKoO1mkX7FTjY4jGoeYPsYZ0OO/75biABdNnpJkOWgzp5iScSWr56PKGGuE 3g1A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sy7w0d4e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 38/43] target/hppa: Implement PSW_X Date: Wed, 15 May 2024 11:40:38 +0200 Message-Id: <20240515094043.82850-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use PAGE_WRITE_INV to temporarily enable write permission on for a given page, driven by PSW_X being set. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/mem_helper.c | 46 +++++++++++++++++++++++----------------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index d09877afd7..ca7bbe0a7c 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -296,30 +296,38 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, goto egress; } - /* In reverse priority order, check for conditions which raise faults. - As we go, remove PROT bits that cover the condition we want to check. - In this way, the resulting PROT will force a re-check of the - architectural TLB entry for the next access. */ - if (unlikely(!ent->d)) { - if (type & PAGE_WRITE) { - /* The D bit is not set -- TLB Dirty Bit Fault. */ - ret = EXCP_TLB_DIRTY; - } - prot &= PAGE_READ | PAGE_EXEC; - } - if (unlikely(ent->b)) { - if (type & PAGE_WRITE) { - /* The B bit is set -- Data Memory Break Fault. */ - ret = EXCP_DMB; - } - prot &= PAGE_READ | PAGE_EXEC; - } + /* + * In priority order, check for conditions which raise faults. + * Remove PROT bits that cover the condition we want to check, + * so that the resulting PROT will force a re-check of the + * architectural TLB entry for the next access. + */ if (unlikely(ent->t)) { + prot &= PAGE_EXEC; if (!(type & PAGE_EXEC)) { /* The T bit is set -- Page Reference Fault. */ ret = EXCP_PAGE_REF; } - prot &= PAGE_EXEC; + } else if (!ent->d) { + prot &= PAGE_READ | PAGE_EXEC; + if (type & PAGE_WRITE) { + /* The D bit is not set -- TLB Dirty Bit Fault. */ + ret = EXCP_TLB_DIRTY; + } + } else if (unlikely(ent->b)) { + prot &= PAGE_READ | PAGE_EXEC; + if (type & PAGE_WRITE) { + /* + * The B bit is set -- Data Memory Break Fault. + * Except when PSW_X is set, allow this single access to succeed. + * The write bit will be invalidated for subsequent accesses. + */ + if (env->psw_xb & PSW_X) { + prot |= PAGE_WRITE_INV; + } else { + ret = EXCP_DMB; + } + } } egress: From patchwork Wed May 15 09:40:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796932 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2891009wra; Wed, 15 May 2024 02:44:33 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXjHk4ZISmBQyF413symYfEDLW6/XBF/q7mCskAPqk8tSvZxeyTowR2z9ElNazFnYFABOlTFA3GJRiiz/WyC5uZ X-Google-Smtp-Source: AGHT+IEptkAsrsWqaMXsG8eoSNBXUcwwgeFA7wYKfKqwAwx0r3f/yiJumt8PxSDh6XsgwdqY2ZJM X-Received: by 2002:a25:ba47:0:b0:de5:5ba5:4e5f with SMTP id 3f1490d57ef6-dee4f4c1e5fmr17546499276.51.1715766273134; Wed, 15 May 2024 02:44:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766273; cv=none; d=google.com; s=arc-20160816; b=hzg2FV0k0IDIQAM9pSYEpNlUQk6/7y13d/amBK+GhEiimdVhqndxzTeAdCZxl7nhlp MW2TWUmqpcAjk01ZRYvCxVEN+Vy/UVHHD8+1ZabWbISWEW0jCsq75b0Qzlu4+O7hZoJm C5ZUo0Sn3LYuppvmuuyjud5fDBQbpAACSggLh3/L5GS5OETkA7g1+re2cOCHQBOFC2UB bDUhyJRUlvnLezjEOqSukmJZnWMX4ihOFjTRAfVQUWBgADyK79BK1zabQlvs0eVHaEUL lv4ozlDHD34X6jazGjR5KU2g9FsZAjTyvWEctO4sz6yX/5kRytc6bxtas4HqYhCnrSQn EYyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OHSKGAmjZyXyEy3oYnNkxuEn/tIxbChlR7lq6N97lGc=; fh=3//KcqJEsa04kIBt5Nb/DJuP+2GuH1NwDRxnSl44zdw=; b=fnunQEgDG0YqksMAyd1Q5VDltDLe/NM5w+14LyJSzTbeyXfz0gU8NK25TQ+UcTpvQa w1UhJXi3nux9Qpt6GbuZLzFo4rpBWT8+wVjqHsMAzTZim8tIqG9wJl7FA9W7LU0XgwmC E3QwFpERFVOLLMpqE1XZMwP4ONFrF2iSZO9Xc9JTV/+/ImrT5uCOP9TfSNeFvR76W8b+ 2dBjlbDQhh/gbOEQ5PRH25UibpV/3AbWxGBsTtlwpnFA3KTbcLyRbbFBmRSxZVHOjjxD kVljSCD4eiZlKeZL14JJswKse2gbBEYrN3hsuPcJicNz84XGZ7O5+j0PkeTt60PuirN7 PGKQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nQS6kSog; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbefdsm15897058f8f.94.2024.05.15.02.41.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:41:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 39/43] target/hppa: Drop tlb_entry return from hppa_get_physical_address Date: Wed, 15 May 2024 11:40:39 +0200 Message-Id: <20240515094043.82850-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The return-by-reference is never used. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 3 +-- target/hppa/int_helper.c | 2 +- target/hppa/mem_helper.c | 19 ++++--------------- target/hppa/op_helper.c | 3 +-- 4 files changed, 7 insertions(+), 20 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index f247ad56d7..78ab0adcd0 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -371,8 +371,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, - int type, hwaddr *pphys, int *pprot, - HPPATLBEntry **tlb_entry); + int type, hwaddr *pphys, int *pprot); void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 97e5f0b9a7..b82f32fd12 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -167,7 +167,7 @@ void hppa_cpu_do_interrupt(CPUState *cs) vaddr = hppa_form_gva_psw(old_psw, env->iasq_f, vaddr); t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX, - 0, &paddr, &prot, NULL); + 0, &paddr, &prot); if (t >= 0) { /* We can't re-load the instruction. */ env->cr[CR_IIR] = 0; diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index ca7bbe0a7c..2929226874 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -197,18 +197,13 @@ static int match_prot_id64(CPUHPPAState *env, uint32_t access_id) } int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, - int type, hwaddr *pphys, int *pprot, - HPPATLBEntry **tlb_entry) + int type, hwaddr *pphys, int *pprot) { hwaddr phys; int prot, r_prot, w_prot, x_prot, priv; HPPATLBEntry *ent; int ret = -1; - if (tlb_entry) { - *tlb_entry = NULL; - } - /* Virtual translation disabled. Map absolute to physical. */ if (MMU_IDX_MMU_DISABLED(mmu_idx)) { switch (mmu_idx) { @@ -238,10 +233,6 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, goto egress; } - if (tlb_entry) { - *tlb_entry = ent; - } - /* We now know the physical address. */ phys = ent->pa + (addr - ent->itree.start); @@ -350,7 +341,7 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) cpu->env.psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX); excp = hppa_get_physical_address(&cpu->env, addr, mmu_idx, 0, - &phys, &prot, NULL); + &phys, &prot); /* Since we're translating for debugging, the only error that is a hard error is no translation at all. Otherwise, while a real cpu @@ -432,7 +423,6 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, { HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; - HPPATLBEntry *ent; int prot, excp, a_prot; hwaddr phys; @@ -448,8 +438,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, break; } - excp = hppa_get_physical_address(env, addr, mmu_idx, - a_prot, &phys, &prot, &ent); + excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, &phys, &prot); if (unlikely(excp >= 0)) { if (probe) { return false; @@ -690,7 +679,7 @@ target_ulong HELPER(lpa)(CPUHPPAState *env, target_ulong addr) int prot, excp; excp = hppa_get_physical_address(env, addr, MMU_KERNEL_IDX, 0, - &phys, &prot, NULL); + &phys, &prot); if (excp >= 0) { if (excp == EXCP_DTLB_MISS) { excp = EXCP_NA_DTLB_MISS; diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 66cad78a57..7f79196fff 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -334,8 +334,7 @@ target_ulong HELPER(probe)(CPUHPPAState *env, target_ulong addr, } mmu_idx = PRIV_P_TO_MMU_IDX(level, env->psw & PSW_P); - excp = hppa_get_physical_address(env, addr, mmu_idx, 0, &phys, - &prot, NULL); + excp = hppa_get_physical_address(env, addr, mmu_idx, 0, &phys, &prot); if (excp >= 0) { cpu_restore_state(env_cpu(env), GETPC()); hppa_set_ior_and_isr(env, addr, MMU_IDX_MMU_DISABLED(mmu_idx)); From patchwork Wed May 15 09:40:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796936 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2891325wra; Wed, 15 May 2024 02:45:38 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUdBHn88bj1BQXOKDt9kQuW6XEfhR5p9yxOGG5EApU4o+uqg6FPfXdaxCQeCk+nAGHwcPDWropriJTObzv2cc1d X-Google-Smtp-Source: AGHT+IFWJcDYbV1eo01nBDXyZf2vg9yXerhml92PskKukkNG1wYA/+deFKMILch7o3mqdB4MtCuA X-Received: by 2002:a05:622a:316:b0:43a:b1e3:d6db with SMTP id d75a77b69052e-43dfdb71c89mr168081051cf.62.1715766338384; Wed, 15 May 2024 02:45:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766338; cv=none; d=google.com; s=arc-20160816; b=zWfdkNc2PeEDdl09pv19xfDAN62hGs6C8UDwgrlvQ77zrgiqt3FTAxI1V0MhPgFhUS JPfz9UXEuOMdax8isOdGGH3aXqxBFl4t4cUuHwNd4pEqMkHzJ6I6sOxtGKLqCNivXCQC m28/E29QIwKhFYkDhxtbeHl8UwCKVH6uEcKOIDnfmKWtg8ZN2U44sZFrwcugNujf0CgQ tFpfW+y72Mt//aClEr12Mv07Z7lSDTX4SviVaWHYAuo+RvP7QmWjyxUZngCJtRLXJKDU L6/POCaDQw6E2IPbZ4vBYsIoZ2NuUYDG97kgeeteOKvAI3nC0iVgM/d7Q8spFpgwXrk1 hEFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rcpRneuuBHCGfIHWgKcPe2ud0xuCeDPw4xb9NImYzmI=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=P7Ky0k1F2r1ltfUGfKYCIP37MXj1L3V8Uw/EqLt9SZN7+3WoE3DWZvEqITZxsHejKL DCavgqnz8uDszwyz1e0vd3tyaQcsXjpconpr5tFc7BW9cPFxgUPcj0qKcmiXjNhSccNX eabeFAu15BoF2hJssfiw5buLSKEwYm6ZjfrsoV2yCJYs784XAAtGGjhBzYXYQvxM5GV1 ejVz29KxbCrjNyPSHnTA6xUsI0olv4h57SxskL+H3KmV4K3KEgi4ICckxbZt5UEPvMt/ aOLUnjRYJMb6ZdjDZwYWlv//kYQQBKB+DOCHmPxjmNBo+QQS50+JIiEY0MJ1M8Zt0167 I1iw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="oW3/YGXT"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbc334sm15926239f8f.103.2024.05.15.02.44.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:44:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 40/43] target/hppa: Adjust priv for B,GATE at runtime Date: Wed, 15 May 2024 11:40:40 +0200 Message-Id: <20240515094043.82850-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Do not compile in the priv change based on the first translation; look up the PTE at execution time. This is required for CF_PCREL, where a page may be mapped multiple times with different attributes. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 - target/hppa/helper.h | 1 + target/hppa/mem_helper.c | 34 +++++++++++++++++++++++++++------- target/hppa/translate.c | 36 +++++++++++++++++++----------------- 4 files changed, 47 insertions(+), 25 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 78ab0adcd0..2bcb3b602b 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -380,7 +380,6 @@ void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, extern const MemoryRegionOps hppa_io_eir_ops; extern const VMStateDescription vmstate_hppa_cpu; void hppa_cpu_alarm_timer(void *); -int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr); #endif G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); diff --git a/target/hppa/helper.h b/target/hppa/helper.h index c12b48a04a..de411923d9 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -86,6 +86,7 @@ DEF_HELPER_1(halt, noreturn, env) DEF_HELPER_1(reset, noreturn, env) DEF_HELPER_1(rfi, void, env) DEF_HELPER_1(rfi_r, void, env) +DEF_HELPER_FLAGS_2(b_gate_priv, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tl, env, tl) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 2929226874..b984f730aa 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -691,13 +691,6 @@ target_ulong HELPER(lpa)(CPUHPPAState *env, target_ulong addr) return phys; } -/* Return the ar_type of the TLB at VADDR, or -1. */ -int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr) -{ - HPPATLBEntry *ent = hppa_find_tlb(env, vaddr); - return ent ? ent->ar_type : -1; -} - /* * diag_btlb() emulates the PDC PDC_BLOCK_TLB firmware call to * allow operating systems to modify the Block TLB (BTLB) entries. @@ -793,3 +786,30 @@ void HELPER(diag_btlb)(CPUHPPAState *env) break; } } + +uint64_t HELPER(b_gate_priv)(CPUHPPAState *env, uint64_t iaoq_f) +{ + uint64_t gva = hppa_form_gva(env, env->iasq_f, iaoq_f); + HPPATLBEntry *ent = hppa_find_tlb(env, gva); + + if (ent == NULL) { + raise_exception_with_ior(env, EXCP_ITLB_MISS, GETPC(), gva, false); + } + + /* + * There should be no need to check page permissions, as that will + * already have been done by tb_lookup via get_page_addr_code. + * All we need at this point is to check the ar_type. + * + * No change for non-gateway pages or for priv decrease. + */ + if (ent->ar_type & 4) { + int old_priv = iaoq_f & 3; + int new_priv = ent->ar_type & 3; + + if (new_priv < old_priv) { + iaoq_f = (iaoq_f & -4) | new_priv; + } + } + return iaoq_f; +} diff --git a/target/hppa/translate.c b/target/hppa/translate.c index f40ac92e98..c2cee89a6a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3961,6 +3961,7 @@ static bool trans_bl(DisasContext *ctx, arg_bl *a) static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) { int64_t disp = a->disp; + bool indirect = false; /* Trap if PSW[B] is set. */ if (ctx->psw_xb & PSW_B) { @@ -3970,24 +3971,22 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) nullify_over(ctx); #ifndef CONFIG_USER_ONLY - if (ctx->tb_flags & PSW_C) { - int type = hppa_artype_for_page(cpu_env(ctx->cs), ctx->base.pc_next); - /* If we could not find a TLB entry, then we need to generate an - ITLB miss exception so the kernel will provide it. - The resulting TLB fill operation will invalidate this TB and - we will re-translate, at which point we *will* be able to find - the TLB entry and determine if this is in fact a gateway page. */ - if (type < 0) { - gen_excp(ctx, EXCP_ITLB_MISS); - return true; - } - /* No change for non-gateway pages or for priv decrease. */ - if (type >= 4 && type - 4 < ctx->privilege) { - disp -= ctx->privilege; - disp += type - 4; - } + if (ctx->privilege == 0) { + /* Privilege cannot decrease. */ + } else if (!(ctx->tb_flags & PSW_C)) { + /* With paging disabled, priv becomes 0. */ + disp -= ctx->privilege; } else { - disp -= ctx->privilege; /* priv = 0 */ + /* Adjust the dest offset for the privilege change from the PTE. */ + TCGv_i64 off = tcg_temp_new_i64(); + + gen_helper_b_gate_priv(off, tcg_env, + tcg_constant_i64(ctx->iaoq_first + + ctx->iaq_f.disp)); + + ctx->iaq_j.base = off; + ctx->iaq_j.disp = disp + 8; + indirect = true; } #endif @@ -4000,6 +3999,9 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) save_gpr(ctx, a->l, tmp); } + if (indirect) { + return do_ibranch(ctx, 0, false, a->n); + } return do_dbranch(ctx, disp, 0, a->n); } From patchwork Wed May 15 09:40:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796941 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2891986wra; 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbc334sm15926239f8f.103.2024.05.15.02.44.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:44:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 41/43] target/hppa: Implement CF_PCREL Date: Wed, 15 May 2024 11:40:41 +0200 Message-Id: <20240515094043.82850-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=richard.henderson@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that the groundwork has been laid, enabling CF_PCREL within the translator proper is a simple matter of updating copy_iaoq_entry and install_iaq_entries. We also need to modify the unwind info, since we no longer have absolute addresses to install. As expected, this reduces the runtime overhead of compilation when running a Linux kernel with address space randomization enabled. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/cpu.c | 19 ++++++------ target/hppa/translate.c | 68 ++++++++++++++++++++++++++++------------- 2 files changed, 55 insertions(+), 32 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 5f0df0697a..f0507874ce 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -62,10 +62,6 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, *pc = hppa_cpu_get_pc(env_cpu(env)); flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; - if (hppa_is_pa20(env)) { - cs_base = env->iaoq_f & MAKE_64BIT_MASK(32, 32); - } - /* * The only really interesting case is if IAQ_Back is on the same page * as IAQ_Front, so that we can use goto_tb between the blocks. In all @@ -113,19 +109,19 @@ static void hppa_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - HPPACPU *cpu = HPPA_CPU(cs); + CPUHPPAState *env = cpu_env(cs); - cpu->env.iaoq_f = data[0]; - if (data[1] != (target_ulong)-1) { - cpu->env.iaoq_b = data[1]; + env->iaoq_f = (env->iaoq_f & TARGET_PAGE_MASK) | data[0]; + if (data[1] != INT32_MIN) { + env->iaoq_b = env->iaoq_f + data[1]; } - cpu->env.unwind_breg = data[2]; + env->unwind_breg = data[2]; /* * Since we were executing the instruction at IAOQ_F, and took some * sort of action that provoked the cpu_restore_state, we can infer * that the instruction was not nullified. */ - cpu->env.psw_n = 0; + env->psw_n = 0; } static bool hppa_cpu_has_work(CPUState *cs) @@ -191,6 +187,9 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) hppa_ptlbe(&cpu->env); } #endif + + /* Use pc-relative instructions always to simplify the translator. */ + tcg_cflags_set(cs, CF_PCREL); } static void hppa_cpu_initfn(Object *obj) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c2cee89a6a..c0920a3c29 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -47,7 +47,7 @@ typedef struct DisasIAQE { TCGv_i64 space; /* IAOQ base; may be null for relative address. */ TCGv_i64 base; - /* IAOQ addend; if base is null, relative to ctx->iaoq_first. */ + /* IAOQ addend; if base is null, relative to cpu_iaoq_f. */ int64_t disp; } DisasIAQE; @@ -664,11 +664,7 @@ static DisasIAQE iaqe_next_absv(DisasContext *ctx, TCGv_i64 var) static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, const DisasIAQE *src) { - if (src->base == NULL) { - tcg_gen_movi_i64(dest, ctx->iaoq_first + src->disp); - } else { - tcg_gen_addi_i64(dest, src->base, src->disp); - } + tcg_gen_addi_i64(dest, src->base ? : cpu_iaoq_f, src->disp); } static void install_iaq_entries(DisasContext *ctx, const DisasIAQE *f, @@ -680,8 +676,28 @@ static void install_iaq_entries(DisasContext *ctx, const DisasIAQE *f, b_next = iaqe_incr(f, 4); b = &b_next; } - copy_iaoq_entry(ctx, cpu_iaoq_f, f); - copy_iaoq_entry(ctx, cpu_iaoq_b, b); + + /* + * There is an edge case + * bv r0(rN) + * b,l disp,r0 + * for which F will use cpu_iaoq_b (from the indirect branch), + * and B will use cpu_iaoq_f (from the direct branch). + * In this case we need an extra temporary. + */ + if (f->base != cpu_iaoq_b) { + copy_iaoq_entry(ctx, cpu_iaoq_b, b); + copy_iaoq_entry(ctx, cpu_iaoq_f, f); + } else if (f->base == b->base) { + copy_iaoq_entry(ctx, cpu_iaoq_f, f); + tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, b->disp - f->disp); + } else { + TCGv_i64 tmp = tcg_temp_new_i64(); + copy_iaoq_entry(ctx, tmp, b); + copy_iaoq_entry(ctx, cpu_iaoq_f, f); + tcg_gen_mov_i64(cpu_iaoq_b, tmp); + } + if (f->space) { tcg_gen_mov_i64(cpu_iasq_f, f->space); } @@ -3980,9 +3996,8 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) /* Adjust the dest offset for the privilege change from the PTE. */ TCGv_i64 off = tcg_temp_new_i64(); - gen_helper_b_gate_priv(off, tcg_env, - tcg_constant_i64(ctx->iaoq_first - + ctx->iaq_f.disp)); + copy_iaoq_entry(ctx, off, &ctx->iaq_f); + gen_helper_b_gate_priv(off, tcg_env, off); ctx->iaq_j.base = off; ctx->iaq_j.disp = disp + 8; @@ -4603,7 +4618,7 @@ static bool trans_diag_unimp(DisasContext *ctx, arg_diag_unimp *a) static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - uint64_t cs_base, iaoq_f, iaoq_b; + uint64_t cs_base; int bound; ctx->cs = cs; @@ -4622,12 +4637,8 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) : ctx->tb_flags & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX); #endif - /* Recover the IAOQ values from the GVA + PRIV. */ cs_base = ctx->base.tb->cs_base; - iaoq_f = cs_base & MAKE_64BIT_MASK(32, 32); - iaoq_f |= ctx->base.pc_first & MAKE_64BIT_MASK(2, 30); - iaoq_f |= ctx->privilege; - ctx->iaoq_first = iaoq_f; + ctx->iaoq_first = ctx->base.pc_first + ctx->privilege; if (unlikely(cs_base & CS_BASE_DIFFSPACE)) { ctx->iaq_b.space = cpu_iasq_b; @@ -4635,8 +4646,9 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) } else if (unlikely(cs_base & CS_BASE_DIFFPAGE)) { ctx->iaq_b.base = cpu_iaoq_b; } else { - iaoq_b = (iaoq_f & TARGET_PAGE_MASK) | (cs_base & ~TARGET_PAGE_MASK); - ctx->iaq_b.disp = iaoq_b - iaoq_f; + uint64_t iaoq_f_pgofs = ctx->iaoq_first & ~TARGET_PAGE_MASK; + uint64_t iaoq_b_pgofs = cs_base & ~TARGET_PAGE_MASK; + ctx->iaq_b.disp = iaoq_b_pgofs - iaoq_f_pgofs; } ctx->zero = tcg_constant_i64(0); @@ -4663,11 +4675,23 @@ static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); + uint64_t iaoq_f, iaoq_b; + int64_t diff; tcg_debug_assert(!iaqe_variable(&ctx->iaq_f)); - tcg_gen_insn_start(ctx->iaoq_first + ctx->iaq_f.disp, - (iaqe_variable(&ctx->iaq_b) ? -1 : - ctx->iaoq_first + ctx->iaq_b.disp), 0); + + iaoq_f = ctx->iaoq_first + ctx->iaq_f.disp; + if (iaqe_variable(&ctx->iaq_b)) { + diff = INT32_MIN; + } else { + iaoq_b = ctx->iaoq_first + ctx->iaq_b.disp; + diff = iaoq_b - iaoq_f; + /* Direct branches can only produce a 24-bit displacement. */ + tcg_debug_assert(diff == (int32_t)diff); + tcg_debug_assert(diff != INT32_MIN); + } + + tcg_gen_insn_start(iaoq_f & ~TARGET_PAGE_MASK, diff, 0); ctx->insn_start_updated = false; } From patchwork Wed May 15 09:40:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796933 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2891127wra; Wed, 15 May 2024 02:44:58 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX7CO1gg3itwRdaqI9bajf3t05Yx8jK3fBPkshS3vDNx+snjooGCI6/fn3LQblDCXuL1Y/2iejZJrCNvTXhr67e X-Google-Smtp-Source: AGHT+IHWvJJIWiJ3TdAKWxLpj16DRtC1I4P0FVFncLb4zxZWhPXmu7SkEPpAux+g9K9sjqtihcM2 X-Received: by 2002:a0c:e743:0:b0:6a0:ce32:3152 with SMTP id 6a1803df08f44-6a15cc7fea1mr291382606d6.24.1715766298113; Wed, 15 May 2024 02:44:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766298; cv=none; d=google.com; s=arc-20160816; b=PbBDRwPGOxj5NtPVkhfE2OnkLdU9W0ZfbuO/OVDZzkXYreGNDlQrZ6hVQzav4nFWab cd+U0qdJI0t2nMif/g00YRjIUAgb7HFhU/5HsVxX1dm279bT4583aj7sqI6Mc1Ub5VWO SmqZ5rP/ih40MSniAwZL8JjWiVatpp2RLeL4hvETNGBX8Gp7v0NCK8+tnDJL+l3REo5Q JSg9CsCCoZY7Qn2uHsvvNZHZyTy30yPU2cb/1UQmBY00G6xtkJuPOxEYbl1rz62zG7jH KU3G9k+ATCuQVnxxfYznzj0lYaNRafzmoeRmWzUNfdv44rPllNUKSnyyBPNk+6qsBjLW tAEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=420RbZAGJjbzrfJsdBQyYhnJyXLQSLvrDO7PgYHuwLQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Pa2XhzRG1f5KUDK9fQDSmTXBUYZIATtF0y12Ail0TVMCDJzfbSrXaQjqUJe2LXWTfy kCFvAhhkcCNKbVCqsru0JcAhdSbQwGRzp6m4AAOgD33013EUgfAmcCXgkW1q1lmPa06O wXmiZuykwuD1dFGGPWiqPn8PLahQUrJf+7b/2vLVpRSF7J+YgcgerrFUR1nuzswhEPkz RMeh9/0A+eXCdM9z0Q4BASBxQKll0NQkETBYF5SBZ3dYEGNcyca2tHQ8F9kapvANaFZN bjmOnkqiyqCwvC+Ffvm7nERxbrY7lNuw11E/io3BC/wz7Ca8BKDx9LNmOkneKBL6SxGG 5AYg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BVDME0AI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbc334sm15926239f8f.103.2024.05.15.02.44.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:44:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 42/43] target/hppa: Log cpu state at interrupt Date: Wed, 15 May 2024 11:40:42 +0200 Message-Id: <20240515094043.82850-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This contains all of the information logged before, plus more. Signed-off-by: Richard Henderson --- target/hppa/int_helper.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index b82f32fd12..391f32f27d 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -241,21 +241,22 @@ void hppa_cpu_do_interrupt(CPUState *cs) [EXCP_SYSCALL_LWS] = "syscall-lws", [EXCP_TOC] = "TOC (transfer of control)", }; - static int count; - const char *name = NULL; - char unknown[16]; - if (i >= 0 && i < ARRAY_SIZE(names)) { - name = names[i]; + FILE *logfile = qemu_log_trylock(); + if (logfile) { + const char *name = NULL; + + if (i >= 0 && i < ARRAY_SIZE(names)) { + name = names[i]; + } + if (name) { + fprintf(logfile, "INT: cpu %d %s\n", cs->cpu_index, name); + } else { + fprintf(logfile, "INT: cpu %d unknown %d\n", cs->cpu_index, i); + } + hppa_cpu_dump_state(cs, logfile, 0); + qemu_log_unlock(logfile); } - if (!name) { - snprintf(unknown, sizeof(unknown), "unknown %d", i); - name = unknown; - } - qemu_log("INT %6d: %s @ " TARGET_FMT_lx ":" TARGET_FMT_lx - " for " TARGET_FMT_lx ":" TARGET_FMT_lx "\n", - ++count, name, env->cr[CR_IIASQ], env->cr[CR_IIAOQ], - env->cr[CR_ISR], env->cr[CR_IOR]); } cs->exception_index = -1; } From patchwork Wed May 15 09:40:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796945 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp2892190wra; Wed, 15 May 2024 02:48:25 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVhPhE65sro7DznrbU/PeYeZpAM+k0jb9hO+kxfZA1USbBQzEUZ8Ot9iH6GHYoTFXDWmuihX2OCuwt9ilX9qdZy X-Google-Smtp-Source: AGHT+IHcDH0nH5njz9zShSlOCb9EYQnplYPrbebsmlt1g4KAvEzhtf4Y/ZLAGaol5R2wkVxHnOeq X-Received: by 2002:a05:6214:3b87:b0:6a0:c96e:c4e3 with SMTP id 6a1803df08f44-6a168147d5emr182434476d6.4.1715766505628; Wed, 15 May 2024 02:48:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715766505; cv=none; d=google.com; s=arc-20160816; b=t1Fl/E1a/sK7KxXuvLIR9uz5KbqntMl9mPo4g9FKU3y1DMtbW9XaosLzt5XS8drHCs 3k0aRMChK0/x9wEoo35HLUJ5ta03tDl52s62+WeqqIE4Y2N+Ry+IKfuBxIUO6PJRZCZV Nh0TNLbZNdf6IYs41R4xNXkuuKmyOsft5xlu0lL21R/k4ESOhmDqG2PdUYJB35aleqzE aL2wRLR+DLOcG1f3PLU8ddeEd+PqVNvRROLrMOvxfIYJ8Iw8WsuSOWgqGSzAneh8aqDc VeXk+QUN6KtDKvZkc03oJ+CK8Pc247EYp7yt+0XBN3L2/uM1/kUY9EuTdaA1HRM9LFpI iAcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IL2hAokqpmQr3sSx0rCsqvvhI5ki9eqOu02SaoXaEMQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=k/g2nDoo1RH/BagtlW1sKBN2fIzNgtQvcf43UlqrvVNKUVwxFfCehvMuF/A+hz5jQJ D2n3/NV/W23V4y2ydaEsF/56agPaDCCi3QluhedJl/65b4xnxfa03Mo325LKZPTVAJvV n4WsM4PjTVyM30/WEhtzhlq8q0U0hZNjQPqBwHPiIjtKw2i9oSezqE/o9iTs9lKBXN4y vz0nLAP5Q9WE0otUBxlqpBZukowzsX5/ifsZd61Icu1M+gsgc14WaYVR/p/q0831GWCu sx3baxfIToUa44yWI4XnZhPG8CrR/Gx5vkSqRpX9qSpMoQJMqlP7HclAdmBpWaPinQm6 IW4A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WtiV8xHQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbc334sm15926239f8f.103.2024.05.15.02.44.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 02:44:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 43/43] target/hppa: Log cpu state on return-from-interrupt Date: Wed, 15 May 2024 11:40:43 +0200 Message-Id: <20240515094043.82850-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=richard.henderson@linaro.org; helo=mail-lf1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Inverse of the logging on taking an interrupt. Signed-off-by: Richard Henderson --- target/hppa/sys_helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c index 22d6c89964..9b43b556fd 100644 --- a/target/hppa/sys_helper.c +++ b/target/hppa/sys_helper.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -93,6 +94,17 @@ void HELPER(rfi)(CPUHPPAState *env) env->iaoq_b = env->cr_back[1]; env->iasq_f = (env->cr[CR_IIASQ] << 32) & ~(env->iaoq_f & mask); env->iasq_b = (env->cr_back[0] << 32) & ~(env->iaoq_b & mask); + + if (qemu_loglevel_mask(CPU_LOG_INT)) { + FILE *logfile = qemu_log_trylock(); + if (logfile) { + CPUState *cs = env_cpu(env); + + fprintf(logfile, "RFI: cpu %d\n", cs->cpu_index); + hppa_cpu_dump_state(cs, logfile, 0); + qemu_log_unlock(logfile); + } + } } static void getshadowregs(CPUHPPAState *env)