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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ1PEPF00001CDE.mail.protection.outlook.com (10.167.242.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7587.21 via Frontend Transport; Mon, 13 May 2024 02:07:46 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Sun, 12 May 2024 21:07:43 -0500 From: Perry Yuan To: , , , CC: , , , , , , Subject: [PATCH v2 01/10] cpufreq: amd-pstate: optimize the initial frequency values verification Date: Mon, 13 May 2024 10:07:19 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CDE:EE_|SA1PR12MB7272:EE_ X-MS-Office365-Filtering-Correlation-Id: e4e6ca92-189c-4c05-1506-08dc72f17beb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|1800799015|376005|36860700004|82310400017; X-Microsoft-Antispam-Message-Info: MquwzWO+LNaGCV18Kwf3lBvMw0iSRZ1n+iarvL6RXcRaO1MbStp+kmflvrcMCnYZRm2WcbbYRBH1mes842w4K2JUFvX4LORVFPmm8WyiVXplJM0GoC063J91LYTMecQhdEvPKCQSiLIYbAh51iGP4USfQPXMoUxju6FFBCLfkpIG+3PZjHnrzLhMW11ZtZN/mDjmh5nB/i2bdiMA5IJQNeLum/NiZtJwzR3cgzTUtz7YHhoah2ljuCC3HW0phfd8QIGMdk0/TrzWxkHogzWLm+8cKwKGd7DXoI1EIhRKQpet/z2+AeSHe/H6Np5wu7zDZiuPIh0KfY/TtXQ9pKNao81/AOjjhP5LZwqXabKhC/6D2udELc2dJxDNgmAzEq/B30hC9qjYNn3l/cH0ZHJUosP2QyISQ9A8rGlkuHuBEYdLVOI/rx2BqtpoovxSRvDZKYCFGsDG39YtelslrGlqVyA3Z15zCYLgO14/x82A2sZkHsw2GFebN7QdEl16ddZbEokhx8UJrd/B4/gJYM/x28uiKmYhg5yzVoRbHOe2tYUEe3Y7sFqk5SHM8li4Mlx/1HG4VSDFq+KlCHELpiwan4DMIev+e6WEBpq3xr4lhWVyXbkt40Q3TYk0D+D3tgjrFQGOYI03boxXRaWRzifSp/1W74vAIog22FCuz6CtCkIHK5jU2rgnMoBpQ1g3+r551nHXDDCOivDq0urEBmSFkSzSAc2PDtYjSnzp2EA2VrkkmoK+F5BG448m7GAqL6el/9OEF6eA2DgP8QI3q8FOp48xXuYUskRhYrCpUnJPMrYi6wXNhPIV9e+AdOrS8Eet3QxJt4ay/gIr/RlXwv+RpSGbmpMPKM7xFMx+lLENbiF3n60JyDZ7L5n4QWCflnDLkNHh7d9d/rUd+J28MhWlW8a4znfa2z2P65gYz49ZlSH5tPiIw++Aqc4t3WG1cHi86kmuzL1GLF7/N/dnZQhAUBes77bt4mD6ZXmlYC57Vp7o5mkeXPPLPR77wfEBBFM2NWm84QInz5eRZYrRjmoEaexev7mKM75god5afThfRNRESTOiQSwPS5Rg5BO1bqDsec7VjG3BkHzLPl+DTZ8b6F5Y4a7pdjDSPDS/tmjPpE0MgeOVIciA68ipK3YeXGUH+mjoT+Is3tCQZArSWLwP4dwp4Vv6QV3uasBCWEXDY+ylYwVe1UvAk84AdRT1YvoFx8iWSY4Ic+Yi3otr9FRfxb4MhKZp+HWjTeVWXIdFjYiFuK4NxtlK/ZW2a6UV52CNuToOqwzZ99CH0r1eUsYQpam9ObmOFbmmKnNFGHuxJnru2Fu+vsVGucKwx6s6yQFU87v29qnk2aTVa8oNcXNKzUVL0+jbTYck63EahqRvVe0k8KTMfpqgzDYDEQL+ekzz X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(1800799015)(376005)(36860700004)(82310400017); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 May 2024 02:07:46.9581 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e4e6ca92-189c-4c05-1506-08dc72f17beb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CDE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7272 To enhance the debugging capability of the driver loading failure for broken CPPC ACPI tables, it can optimize the expression by moving the verification of `min_freq`, `nominal_freq`, and other dependency values to the `amd_pstate_init_freq()` function where they are initialized. If any of these values are incorrect, the `amd-pstate` driver will not be registered. By ensuring that these values are correct before they are used, it will facilitate the debugging process when encountering driver loading failures due to faulty CPPC ACPI tables from BIOS Signed-off-by: Perry Yuan Acked-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 35 ++++++++++++++++++----------------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 6a342b0c0140..614f6fac0764 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -889,6 +889,24 @@ static int amd_pstate_init_freq(struct amd_cpudata *cpudata) WRITE_ONCE(cpudata->nominal_freq, nominal_freq); WRITE_ONCE(cpudata->max_freq, max_freq); + /** + * Below values need to be initialized correctly, otherwise driver will fail to load + * max_freq is calculated according to (nominal_freq * highest_perf)/nominal_perf + * lowest_nonlinear_freq is a value between [min_freq, nominal_freq] + * Check _CPC in ACPI table objects if any values are incorrect + */ + if (min_freq <= 0 || max_freq <= 0 || nominal_freq <= 0 || min_freq > max_freq) { + pr_err("min_freq(%d) or max_freq(%d) or nominal_freq(%d) value is incorrect\n", + min_freq, max_freq, nominal_freq); + return -EINVAL; + } + + if (lowest_nonlinear_freq <= min_freq || lowest_nonlinear_freq > nominal_freq * 1000) { + pr_err("lowest_nonlinear_freq(%d) value is out of range [min_freq(%d), nominal_freq(%d)]\n", + lowest_nonlinear_freq, min_freq, nominal_freq * 1000); + return -EINVAL; + } + return 0; } @@ -927,15 +945,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) max_freq = READ_ONCE(cpudata->max_freq); nominal_freq = READ_ONCE(cpudata->nominal_freq); - if (min_freq <= 0 || max_freq <= 0 || - nominal_freq <= 0 || min_freq > max_freq) { - dev_err(dev, - "min_freq(%d) or max_freq(%d) or nominal_freq (%d) value is incorrect, check _CPC in ACPI tables\n", - min_freq, max_freq, nominal_freq); - ret = -EINVAL; - goto free_cpudata1; - } - policy->cpuinfo.transition_latency = amd_pstate_get_transition_latency(policy->cpu); policy->transition_delay_us = amd_pstate_get_transition_delay_us(policy->cpu); @@ -1388,14 +1397,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) min_freq = READ_ONCE(cpudata->min_freq); max_freq = READ_ONCE(cpudata->max_freq); nominal_freq = READ_ONCE(cpudata->nominal_freq); - if (min_freq <= 0 || max_freq <= 0 || - nominal_freq <= 0 || min_freq > max_freq) { - dev_err(dev, - "min_freq(%d) or max_freq(%d) or nominal_freq(%d) value is incorrect, check _CPC in ACPI tables\n", - min_freq, max_freq, nominal_freq); - ret = -EINVAL; - goto free_cpudata1; - } policy->cpuinfo.min_freq = min_freq; policy->cpuinfo.max_freq = max_freq; From patchwork Mon May 13 02:07:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 796731 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2041.outbound.protection.outlook.com [40.107.93.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89B7385C4E; Mon, 13 May 2024 02:08:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sun, 12 May 2024 21:07:46 -0500 From: Perry Yuan To: , , , CC: , , , , , , Subject: [PATCH v2 02/10] cpufreq: amd-pstate: remove unused variable nominal_freq Date: Mon, 13 May 2024 10:07:20 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CDF:EE_|PH7PR12MB6537:EE_ X-MS-Office365-Filtering-Correlation-Id: 53f96de2-edb2-4d2c-b94c-08dc72f180ba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|1800799015|36860700004|376005|82310400017; X-Microsoft-Antispam-Message-Info: Rf1+5i9LnRei7Dm2guv2BS8s1Z7gI9NRC1+4bN3AgILeKWHcSyt+kIOWfauqbjFS1+omM/MYurNu7Zt1/pyE3cq+N7JjI8KCqebS8wyGbPl1HmjcIWq15TNMXTI+uoZn0SFINSgkwpOeFalHKMXiEeXKg4nG14iZczL8+tET5TTTCzFpbJba4eNxOSwZJw/O/o2MddCVMpFjZwYciES9r3g7FUqVAYS2KLiNFdcfl05ht4W/7zEPmPIGU8XPe9x8nzftJJb0dlyzehOFXBL9p/AVaFphqvXs/f4ylLVhyabWDL5OiusgWujmDAINhH5CCOYnwehDQmKJk97EFBSHvEv22GJGY15CKXtC0T3Wxx/k1MT45PKJbUmSqy2D+Go7IzPvhOVbdmcXdy0Q5iPvFO16N8yu84rkHpYNgnAMGeUxhzNy5iADyuuhlEyOvwUH/Y7orY15z2kTFfkhKAJcbz9rLLLvUQ9DsIkBx6kizpqWVpxOjaEIo5N0SdFy248Dwh0uPcd7H8UdHWW/cWsmHLGiTpzcmt36Mk54LCYzC6IP3jseTqSD0DqrIMPPr1Bx/6ohdHpZNAin+a0lux9jVFCMCjyT7BEuY7sIe5JPBTGpSifZqt8NDwQOVSFNq/c9CL45MF4YeLSkYLn9FUp9cuwQ4ntRYWyJshSknConvUmOoB1MSZ1UCjfu3RuTQouJr0QY78aAZDA68qNDIEf7p9Z4WNXh+Dbtu7qsstMa2QT86Mc3KPhODp2UsV67+2A9MXiP2FLNvJmJ3RHanT26PDlHZiEG58SAQhlOIxxzJAS8GPGgDa6ilDpZWJxTAZmQYKDblMbUvOIDFTwB2/2S0b1jACzr4dc+CcU0CzZ5A6494n8SZ+ZxHWCv9xyuNKV5I9DbZ6Jyb6DJ8Oym5/UsaE2+zjkhbBFLGgZuaDGqf+0cUvuIULtZDXOLSiB2L1UQKvvF3ZmlcIfEP0TsK8PUjFaIMmScDTl/TzVHghXkHPAamSqzrs4Dwod00fn3MBGsEect7Ijycqj+R5sXCgGt8scD0byoMahsq4djLfDVMDnR3lD1Y+uHDqSBGa+vuD45/Og0W7cZ+UJweq6duT12usdsbhZFka4cMiFcqQooKG6KeXmdDDaVZ0jKjyLPLliTYBr2hEduVljkddbu0uJYnFfzBqLF00vdko/U9zHwtt8fadXGJfunnCH6vkT/BVxQfpGuPLpHDhY89xOIDhB4xFdzXlojB/FGLFvW6cf8aJqHKkKBmaq5+KNOJVrmmvAjEdVOg42Qh2WHncVSCKlOd+eNnLKbnO3XI2dr9x7SulUXJRq0mYrx8TGiMc8dsV+C X-Forefront-Antispam-Report: CIP:165.204.84.17; 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This variable was defined and assigned a value in the previous code, but it was not used in the subsequent code. Closes: https://lore.kernel.org/oe-kbuild-all/202405080431.BPU6Yg9s-lkp@intel.com/ Reported-by: kernel test robot Signed-off-by: Perry Yuan Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 614f6fac0764..9ca22e94f3f3 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -912,7 +912,7 @@ static int amd_pstate_init_freq(struct amd_cpudata *cpudata) static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { - int min_freq, max_freq, nominal_freq, ret; + int min_freq, max_freq, ret; struct device *dev; struct amd_cpudata *cpudata; @@ -943,7 +943,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) min_freq = READ_ONCE(cpudata->min_freq); max_freq = READ_ONCE(cpudata->max_freq); - nominal_freq = READ_ONCE(cpudata->nominal_freq); policy->cpuinfo.transition_latency = amd_pstate_get_transition_latency(policy->cpu); policy->transition_delay_us = amd_pstate_get_transition_delay_us(policy->cpu); @@ -1363,7 +1362,7 @@ static bool amd_pstate_acpi_pm_profile_undefined(void) static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) { - int min_freq, max_freq, nominal_freq, ret; + int min_freq, max_freq, ret; struct amd_cpudata *cpudata; struct device *dev; u64 value; @@ -1396,7 +1395,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) min_freq = READ_ONCE(cpudata->min_freq); max_freq = READ_ONCE(cpudata->max_freq); - nominal_freq = READ_ONCE(cpudata->nominal_freq); policy->cpuinfo.min_freq = min_freq; policy->cpuinfo.max_freq = max_freq; From patchwork Mon May 13 02:07:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 796841 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2043.outbound.protection.outlook.com [40.107.220.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3493884FCC; Mon, 13 May 2024 02:07:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.220.43 ARC-Seal: i=2; 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And the warning message will not be shown if CPPC is not supported. It will also print debug message if the CPU has no CPPC support that helps to debug the driver loading failure issue. Reported-by: Paul Menzel Closes: https://lore.kernel.org/linux-pm/CYYPR12MB8655D32EA18574C9497E888A9C122@CYYPR12MB8655.namprd12.prod.outlook.com/T/#t Signed-off-by: Perry Yuan Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 9ca22e94f3f3..3109b46fb02e 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1701,6 +1701,20 @@ static int __init amd_pstate_set_driver(int mode_idx) return -EINVAL; } +/** + * CPPC function is not supported for family ID 17H with model_ID ranging from 0x10 to 0x2F. + * show the debug message that helps to check if the CPU has CPPC support for loading issue. + */ +static bool amd_cppc_supported(void) +{ + if ((boot_cpu_data.x86 == 0x17) && (boot_cpu_data.x86_model < 0x30)) { + pr_debug_once("CPPC feature is not supported by the processor\n"); + return false; + } + + return true; +} + static int __init amd_pstate_init(void) { struct device *dev_root; @@ -1709,6 +1723,11 @@ static int __init amd_pstate_init(void) if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) return -ENODEV; + /* show debug message only if CPPC is not supported */ + if (!amd_cppc_supported()) + return -EOPNOTSUPP; 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So adding one more debug message to inform user to check the SBIOS setting, The change also can help maintainers to debug why amd_pstate driver failed to be loaded at system booting if the processor support CPPC. Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218686 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 3109b46fb02e..8b624c79c287 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1707,12 +1707,37 @@ static int __init amd_pstate_set_driver(int mode_idx) */ static bool amd_cppc_supported(void) { + struct cpuinfo_x86 *c = &cpu_data(0); + if ((boot_cpu_data.x86 == 0x17) && (boot_cpu_data.x86_model < 0x30)) { pr_debug_once("CPPC feature is not supported by the processor\n"); return false; } + /* + * If the CPPC flag is disabled in the BIOS for processors that support MSR-based CPPC + * the AMD Pstate driver may not function correctly. + */ + if (!cpu_feature_enabled(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_ZEN1) || cpu_feature_enabled(X86_FEATURE_ZEN2)) { + if (c->x86_model > 0x60 && c->x86_model < 0xaf) + goto warn; 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Sun, 12 May 2024 21:08:00 -0500 From: Perry Yuan To: , , , CC: , , , , , , Subject: [PATCH v2 05/10] Documentation: PM: amd-pstate: add debugging section for driver loading failure Date: Mon, 13 May 2024 10:07:23 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CDE:EE_|BY5PR12MB4177:EE_ X-MS-Office365-Filtering-Correlation-Id: 6840d32f-ac07-461a-0e9c-08dc72f186a8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|1800799015|376005|36860700004|82310400017; X-Microsoft-Antispam-Message-Info: CHw3pZd6G7NMu8gvH5b8HXw3+AcyaUaq4/GC3+uUPv1iEHPDikgEPcWbjuKynkwsa13I9/lhThek8FRUIz2YrOquHEc0bQoYKTr9yRXKizt4AGRTir0UQf8yqtoIicw0dYKVaOJGVGKh3oZJc3P4DhCl43sljdl5cnrjHgNGXk8GcHAiONU7YGNRSGw975bY8SZwTC8NJ/wOFtyXAidi2YvctukBOw/4+C+OhtbRGLgZDqel1YgFdewWVKiWbHZwUwBI38qD2fvi5LOfZN35YQdCCSPq+sbPoYL5juITRcte7xvLwuGaGZ6DmuqScFyEZAN8IqMkReUK/B+J7VJz103goTtWx37jvYyPQBfTinZUpLvVa20ZXVvSIFaxgdlnS1kP0aH8wmGvFk3WTA26FOZS8V6fNRdHABTPRr9bGby6bcRzT15YAThkEjWC63dVhgW0wgzueuQAHGIURAC0weD7A+l87eZGI8CkX+7IrtaZrLZw71az6ROlaHuppfwZzNWPXrVUsqhVQYRwV47dt9j8iWB6dyXTON6kUppwu6fcukaINyvJQal2q175sDJoEHkiP6bGtMGFFmpOEi1ABymDCDJo01zlNnMD02+o4TM5F+uT+x7OFtjdi1IalHMSqfeDAtmWZKqjxtF2jAB+tHBHpUmqWu+EMMUI5IBuAPt2nQUX8a5MFltJXoVI+OHIZGb6FwsdZMgBMYawouTjv7XvbLObZ83mRvWGXBT1J43H+gPVkruXztsWXspK7ooCLoUFYGpxFoPnOAgY+ct/nJVT0n2mUi+TQI4Au3gDUtOAleESaa8BmL9pHt9Jlv8ejzoRtA6Bx30TD6Hvl6y5cI7mdEIFtwUj+vTBSlmUbxp5g+Gs77ffM3RzUEkZ2I48mB9zdXjn4ifYKfIrLQxE4hhjktn2mB7B8nbH4K7hPhsDtlPmYvRrLfznzMUdYcakEXTmPFESE3cZA2kZWF6qDqwDsUA1S0IDDCWITa6rNNYuTfzlS5mMaySEPG04VWxijrEI569DDG3U2h/LkXCnYOFUTuOx+bXPowoLX0yDJseWFreGLttUv90qZ0lkocbPbhkCdGDJ5eIfdiGoASZXYjfHrexv39bAxLUymV2QCDeZ8XxAwcM/knrhIRo4Ku/TrRSS/PwLqFZZPGcxZ3oWH8SRuxVa3BJA/Ps5aDJkpcTB0UB7KuKomLwwBfSkDyzD7YqN37Og6gxX+pqcGfML1U4qy5H0w+i1RNG9ZvgiZ8wt1XHMpehxAnNJeoBmGqj0LW1vT/wLEeNtgzRGU42J58D2jA+LshDq8dl8Uk63jrrd6yglCgEiapEkWaFEVDEM99dlO5DEgPtSbaDt5kSalKlTLu6jQJ62KJ+jaORecKqZZ1XekkT8dNTCQ0oFONEo X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(1800799015)(376005)(36860700004)(82310400017); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 May 2024 02:08:05.0519 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6840d32f-ac07-461a-0e9c-08dc72f186a8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CDE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4177 To address issues with the loading of the amd-pstate driver on certain platforms, It needs to enable dynamic debugging to capture debug messages during the driver loading process. By adding "amd_pstate.dyndbg=+p cppc_acpi.dyndbg=+p loglevel=4 debug amd_pstate=active" to the kernel command line, driver debug logging is enabled. Signed-off-by: Perry Yuan --- Documentation/admin-guide/pm/amd-pstate.rst | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 1e0d101b020a..de83e742738e 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -472,6 +472,19 @@ operations for the new ``amd-pstate`` module with this tool. :: Diagnostics and Tuning ======================= +Debugging AMD P-State Driver Loading Issues +------------------------------------------ + +On some platforms, there may be issues with the loading of the amd-pstate driver. +To capture debug messages for issue analysis, users can add below parameter, +"amd_pstate.dyndbg=+p cppc_acpi.dyndbg=+p debug" +to the kernel command line. This will enable dynamic debugging and allow better +analysis and troubleshooting of the driver loading process. + +Please note that adding this parameter will only enable debug logging during the +driver loading phase and may affect system behavior. Use this option with caution +and only for debugging purposes. + Trace Events -------------- From patchwork Mon May 13 02:07:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 796840 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2074.outbound.protection.outlook.com [40.107.243.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62DCD137925; Mon, 13 May 2024 02:08:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.243.74 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715566091; cv=fail; b=a+JScYWhNS8pr1r5gog4M+diVIW2LSbA1bvk8grHZ6u3iPXZ80AluHOFUjg98shZFOLki4B5fznFOvXqu1XsGjX+zJkKFn/HHuwtUyKb9nvqOY8H9NyNwzwtWcNfhcDe1LGXWVG7KMiFbDl3E1XhZDN1XIcC3yCID+qZ9io5yio= ARC-Message-Signature: i=2; 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Reviewed-by: Mario Limonciello Signed-off-by: Perry Yuan --- Documentation/admin-guide/pm/amd-pstate.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index de83e742738e..7eb35ad21c7d 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -406,7 +406,7 @@ control its functionality at the system level. They are located in the ``/sys/devices/system/cpu/amd_pstate/`` directory and affect all CPUs. ``status`` - Operation mode of the driver: "active", "passive" or "disable". + Operation mode of the driver: "active", "passive", "guided" or "disable". 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The switch to cpu_feature_enabled() ensures compatibility with the latest CPU feature detection mechanisms and improves code maintainability. Acked-by: Mario Limonciello Suggested-by: Borislav Petkov (AMD) Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 8b624c79c287..8b8cae1b678d 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -125,7 +125,7 @@ static int __init dmi_matched_7k62_bios_bug(const struct dmi_system_id *dmi) * broken BIOS lack of nominal_freq and lowest_freq capabilities * definition in ACPI tables */ - if (boot_cpu_has(X86_FEATURE_ZEN2)) { + if (cpu_feature_enabled(X86_FEATURE_ZEN2)) { quirks = dmi->driver_data; pr_info("Overriding nominal and lowest frequencies for %s\n", dmi->ident); return 1; @@ -167,7 +167,7 @@ static s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) u64 epp; int ret; - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { if (!cppc_req_cached) { epp = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &cppc_req_cached); @@ -220,7 +220,7 @@ static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp) int ret; struct cppc_perf_ctrls perf_ctrls; - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { u64 value = READ_ONCE(cpudata->cppc_req_cached); value &= ~GENMASK_ULL(31, 24); @@ -721,7 +721,7 @@ static int amd_pstate_get_highest_perf(int cpu, u32 *highest_perf) { int ret; - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { u64 cap1; ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); @@ -956,7 +956,7 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) /* It will be updated by governor */ policy->cur = policy->cpuinfo.min_freq; - if (boot_cpu_has(X86_FEATURE_CPPC)) + if (cpu_feature_enabled(X86_FEATURE_CPPC)) policy->fast_switch_possible = true; ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], @@ -1189,7 +1189,7 @@ static int amd_pstate_change_mode_without_dvr_change(int mode) cppc_state = mode; - if (boot_cpu_has(X86_FEATURE_CPPC) || cppc_state == AMD_PSTATE_ACTIVE) + if (cpu_feature_enabled(X86_FEATURE_CPPC) || cppc_state == AMD_PSTATE_ACTIVE) return 0; for_each_present_cpu(cpu) { @@ -1418,7 +1418,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) else policy->policy = CPUFREQ_POLICY_POWERSAVE; - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); if (ret) return ret; @@ -1501,7 +1501,7 @@ static void amd_pstate_epp_update_limit(struct cpufreq_policy *policy) epp = 0; /* Set initial EPP value */ - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { value &= ~GENMASK_ULL(31, 24); value |= (u64)epp << 24; } @@ -1540,7 +1540,7 @@ static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) value = READ_ONCE(cpudata->cppc_req_cached); max_perf = READ_ONCE(cpudata->highest_perf); - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); } else { perf_ctrls.max_perf = max_perf; @@ -1574,7 +1574,7 @@ static void amd_pstate_epp_offline(struct cpufreq_policy *policy) value = READ_ONCE(cpudata->cppc_req_cached); mutex_lock(&amd_pstate_limits_lock); - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { cpudata->epp_policy = CPUFREQ_POLICY_UNKNOWN; /* Set max perf same as min perf */ @@ -1776,7 +1776,7 @@ static int __init amd_pstate_init(void) */ if (amd_pstate_acpi_pm_profile_undefined() || amd_pstate_acpi_pm_profile_server() || - !boot_cpu_has(X86_FEATURE_CPPC)) { + !cpu_feature_enabled(X86_FEATURE_CPPC)) { pr_info("driver load is disabled, boot with specific mode to enable this\n"); return -ENODEV; } @@ -1795,7 +1795,7 @@ static int __init amd_pstate_init(void) } /* capability check */ - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { pr_debug("AMD CPPC MSR based functionality is supported\n"); if (cppc_state != AMD_PSTATE_ACTIVE) current_pstate_driver->adjust_perf = amd_pstate_adjust_perf; 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For better utilization of feature words and help to identify core type, X86_FEATURE_HETERO_CORE_TOPOLOGY is added as a few scattered feature bits. Link: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf PDF p274 Signed-off-by: Perry Yuan --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 3c7434329661..39a92338c015 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -470,6 +470,7 @@ #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* "" BHI_DIS_S HW control available */ #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* "" BHI_DIS_S HW control enabled */ #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* "" Clear branch history at vmexit using SW loop */ +#define X86_FEATURE_HETERO_CORE_TOPOLOGY (21*32+ 5) /* "" Heterogeneous Core Topology */ /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index af5aa2c754c2..9e237a3daf7e 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -51,6 +51,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 }, + { X86_FEATURE_HETERO_CORE_TOPOLOGY, CPUID_EAX, 30, 0x80000026, 0 }, { 0, 0, 0, 0, 0 } }; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(376005)(36860700004)(1800799015)(82310400017); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 May 2024 02:08:16.3332 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71010524-b9ee-4708-d3eb-08dc72f18d63 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CDE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6323 Introduces an optimization to the AMD-Pstate driver by implementing a heterogeneous core topology for the initialization of the highest performance value while driver loading. There are two type cores designed including performance core and Efficiency Core. Each core type has different highest performance and frequency values configured by the platform. The `amd_pstate` driver needs to identify the type of core to correctly set an appropriate highest perf value. X86_FEATURE_HETERO_CORE_TOPOLOGY is used to identify whether the processor support heterogeneous core type by reading CPUID leaf Fn_0x80000026_EAX and bit 30. if the bit is set as one, then amd_pstate driver will check EBX 30:28 bits to get the core type. Link: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf PDF p274 Signed-off-by: Perry Yuan --- arch/x86/include/asm/processor.h | 2 + arch/x86/kernel/cpu/amd.c | 19 +++++++++ drivers/cpufreq/amd-pstate.c | 66 ++++++++++++++++++++------------ include/linux/amd-pstate.h | 8 ++++ 4 files changed, 71 insertions(+), 24 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 78e51b0d6433..04d30dd35d0a 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -682,10 +682,12 @@ static inline u32 per_cpu_l2c_id(unsigned int cpu) extern u32 amd_get_highest_perf(void); extern void amd_clear_divider(void); extern void amd_check_microcode(void); +extern int amd_get_this_core_type(void); #else static inline u32 amd_get_highest_perf(void) { return 0; } static inline void amd_clear_divider(void) { } static inline void amd_check_microcode(void) { } +static inline int amd_get_this_core_type(void) { return -1; } #endif extern unsigned long arch_align_stack(unsigned long sp); diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 307302af0aee..67966bdcde65 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1219,3 +1219,22 @@ void noinstr amd_clear_divider(void) :: "a" (0), "d" (0), "r" (1)); } EXPORT_SYMBOL_GPL(amd_clear_divider); + +#define X86_CPU_TYPE_ID_SHIFT 28 + +/** + * amd_get_this_core_type - Get the type of this heterogeneous CPU + * + * Returns the CPU type [31:28] (i.e., performance or efficient) of + * a CPU in the processor. + * If the processor has no core type support, returns -1. + */ + +int amd_get_this_core_type(void) +{ + if (!cpu_feature_enabled(X86_FEATURE_HETERO_CORE_TOPOLOGY)) + return -1; + + return cpuid_ebx(0x80000026) >> X86_CPU_TYPE_ID_SHIFT; +} +EXPORT_SYMBOL_GPL(amd_get_this_core_type); diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 8b8cae1b678d..dce901a403c9 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -50,8 +50,9 @@ #define AMD_PSTATE_TRANSITION_LATENCY 20000 #define AMD_PSTATE_TRANSITION_DELAY 1000 -#define CPPC_HIGHEST_PERF_PERFORMANCE 196 -#define CPPC_HIGHEST_PERF_DEFAULT 166 +#define CPPC_HIGHEST_PERF_EFFICIENT 132 +#define CPPC_HIGHEST_PERF_PERFORMANCE 196 +#define CPPC_HIGHEST_PERF_DEFAULT 166 /* * TODO: We need more time to fine tune processors with shared memory solution @@ -327,19 +328,47 @@ static inline int amd_pstate_enable(bool enable) return static_call(amd_pstate_enable)(enable); } +static void get_this_core_type(void *data) +{ + int *cpu_type = data; + + *cpu_type = amd_get_this_core_type(); +} + +static int amd_pstate_get_cpu_type(int cpu) +{ + int cpu_type = 0; + + smp_call_function_single(cpu, get_this_core_type, &cpu_type, 1); + + return cpu_type; +} + static u32 amd_pstate_highest_perf_set(struct amd_cpudata *cpudata) { - struct cpuinfo_x86 *c = &cpu_data(0); + u32 highest_perf; + int core_type; - /* - * For AMD CPUs with Family ID 19H and Model ID range 0x70 to 0x7f, - * the highest performance level is set to 196. - * https://bugzilla.kernel.org/show_bug.cgi?id=218759 - */ - if (c->x86 == 0x19 && (c->x86_model >= 0x70 && c->x86_model <= 0x7f)) - return CPPC_HIGHEST_PERF_PERFORMANCE; + core_type = amd_pstate_get_cpu_type(cpudata->cpu); + pr_debug("core_type %d found\n", core_type); - return CPPC_HIGHEST_PERF_DEFAULT; + switch (core_type) { + case CPU_CORE_TYPE_NO_HETERO_SUP: + highest_perf = CPPC_HIGHEST_PERF_DEFAULT; + break; + case CPU_CORE_TYPE_PERFORMANCE: + highest_perf = CPPC_HIGHEST_PERF_PERFORMANCE; + break; + case CPU_CORE_TYPE_EFFICIENCY: + highest_perf = CPPC_HIGHEST_PERF_EFFICIENT; + break; + default: + highest_perf = CPPC_HIGHEST_PERF_DEFAULT; + WARN_ONCE(true, "WARNING: Undefined core type found"); + break; + } + + return highest_perf; } static int pstate_init_perf(struct amd_cpudata *cpudata) @@ -352,15 +381,7 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) if (ret) return ret; - /* For platforms that do not support the preferred core feature, the - * highest_pef may be configured with 166 or 255, to avoid max frequency - * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as - * the default max perf. - */ - if (cpudata->hw_prefcore) - highest_perf = amd_pstate_highest_perf_set(cpudata); - else - highest_perf = AMD_CPPC_HIGHEST_PERF(cap1); + highest_perf = amd_pstate_highest_perf_set(cpudata); WRITE_ONCE(cpudata->highest_perf, highest_perf); WRITE_ONCE(cpudata->max_limit_perf, highest_perf); @@ -381,10 +402,7 @@ static int cppc_init_perf(struct amd_cpudata *cpudata) if (ret) return ret; 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Sun, 12 May 2024 21:08:16 -0500 From: Perry Yuan To: , , , CC: , , , , , , Subject: [PATCH v2 10/10] cpufreq: amd-pstate: automatically load pstate driver by default Date: Mon, 13 May 2024 10:07:28 +0800 Message-ID: <9b31fbcdfd4e4f00c3302f45e655aa43589b224c.1715356532.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE3:EE_|PH7PR12MB5950:EE_ X-MS-Office365-Filtering-Correlation-Id: 3cd7070c-2e07-4dba-d49f-08dc72f18f8d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|1800799015|36860700004|376005|82310400017; X-Microsoft-Antispam-Message-Info: IrmaSVe3lV6SjTM77XFP6Te4PLy7SG0Yd7hfArHutkNZdFQJD45tBmx8430QGaCcEEbLR4XahUt55Cor4bIlKmitnOd5vGHh/Bk7KtYbA0qUdgtFeBkzD+oVAKaLkpxlGm//rRyCfcf/3+dcRLn4Y7fuRTRy/VbrVyGc6/t4jqpk2CbKg1mqIgt37mZzqxUSOWXHRvICzSU6dOVBNQaJ1/Pf4COboxET7QLsIcmieEk4onPt5Q1FjcWOCPH7goIVIdgEXkbxa60Bq3RNiU61cqsTVrGOE1eZX6PBJ58IbjdB0PIZjseWhtelRymqWRxBu3OisEwRZoFm3AD+XmrAPaQykPz/AGI/i3waK7fiOjf4h5FXTza8Mg7UbypV4UTncUJWp9JetkeKJZ3hsPcLKYh3jBBSuYmuo1vm7UkqsWdKOp/Oo7luuA7Kuhy1Hx19lshp81SZLTk31uR25dCNJzidvV2XazBepQ+W0PpEQfEJUb5l8ADUH+ENeOdMi+HjOdyE4c818gnKA6xaYpqebnHA9g5drhPynMeC/zQKgNiKsNc2OyLWMldXqa+IObiPvPJ0S3WkS15c0fQNsCYgzcbCCd753UdTBCNgQf+J+WpIfPAXslWilgymFLwtjwtuIG6U80RssUUfuQagwuO3597BZvkR0sz24xvQIrsBtd5PXN7fHopRtqjL8T0Y4+Oj/zyAxcOT55BuPelPErUkXmNfIPorU60s4yGBrROIIEfWxTKCk74GBj4GGQTdjJ5WTsToX1ErepsTNpGrNyoZBlnWTFqGMcgT8Ur2E7C5/hejyc75cjg1wbQT6zOMB3Su+JurDsvM06QEJ4LZHpeBTHva0PATqCr4eg1FDsoZbjPCb68v4Fi5AgjeYUnBxBEUAhezq5h1c1oIkl2wQ0/gnxtj6LRiEDXoFgOJCuLbAJE5mIX3BP08kaWqk6M/1LNVYgD8d1Ep1h1wXQXXuZ1J8PuLcKKiTNZoLX0bYn6NjNCMkbKL5Am1vK2POlDHZk7L+uE/jzk+EXtsPUIw8NGG8dwhGHs8NY2hU+Xxal5aIevA6DFPuXYL+GJwoqzbgaxdOVgUHYtPd+/ioeCs5NGRcQHBT7IM8MHx6CmLJXHEIGh2yelMbuLk4RtZHXCAxUALQKWTFIZTM6Fa1C2SAzqQFkbFSwsk34m/EyHzIBtL0w3FBk0jWWkni7FhU9tpbhnFpFGmCmMeSpKfyJU9AptC4bpS+2ZQimOwJ4abBmgoEayWxpQ2/iWGyIBpaOgbwYIsw1hcOaYAuZu5ejfSEZ5nSMa6wcQT71ctCWWJUwY3m3g08Tc0oIgHpHT/pW/Z8X+c X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(1800799015)(36860700004)(376005)(82310400017); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 May 2024 02:08:19.9014 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3cd7070c-2e07-4dba-d49f-08dc72f18f8d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5950 If the `amd-pstate` driver is not loaded automatically by default, it is because the kernel command line parameter has not been added. To resolve this issue, it is necessary to call the `amd_pstate_set_driver()` function to enable the desired mode (passive/active/guided) before registering the driver instance. This ensures that the driver is loaded correctly without relying on the kernel command line parameter. [ 0.917789] usb usb6: Manufacturer: Linux 6.9.0-rc6-amd-pstate-new-fix-v1 xhci-hcd [ 0.982579] amd_pstate: failed to register with return -22 Reported-by: Andrei Amuraritei Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218705 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index dce901a403c9..03342fef7d94 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1785,28 +1785,30 @@ static int __init amd_pstate_init(void) /* check if this machine need CPPC quirks */ dmi_check_system(amd_pstate_quirks_table); + /* get default driver mode for loading */ + if (cppc_state == AMD_PSTATE_UNDEFINED) + cppc_state = CONFIG_X86_AMD_PSTATE_DEFAULT_MODE; + + /* Disable on the following configs by default: + * 1. Undefined platforms + * 2. Server platforms + */ + if (amd_pstate_acpi_pm_profile_undefined() || + amd_pstate_acpi_pm_profile_server()) { + pr_info("driver load is disabled for server or undefined platform\n"); + return -ENODEV; + } + switch (cppc_state) { - case AMD_PSTATE_UNDEFINED: - /* Disable on the following configs by default: - * 1. Undefined platforms - * 2. Server platforms - * 3. Shared memory designs - */ - if (amd_pstate_acpi_pm_profile_undefined() || - amd_pstate_acpi_pm_profile_server() || - !cpu_feature_enabled(X86_FEATURE_CPPC)) { - pr_info("driver load is disabled, boot with specific mode to enable this\n"); - return -ENODEV; - } - ret = amd_pstate_set_driver(CONFIG_X86_AMD_PSTATE_DEFAULT_MODE); - if (ret) - return ret; - break; case AMD_PSTATE_DISABLE: + pr_info("driver load is disabled, boot with specific mode to enable this\n"); return -ENODEV; case AMD_PSTATE_PASSIVE: case AMD_PSTATE_ACTIVE: case AMD_PSTATE_GUIDED: + ret = amd_pstate_set_driver(cppc_state); + if (ret) + return ret; break; default: return -EINVAL; @@ -1827,7 +1829,7 @@ static int __init amd_pstate_init(void) /* enable amd pstate feature */ ret = amd_pstate_enable(true); if (ret) { - pr_err("failed to enable with return %d\n", ret); + pr_err("failed to enable driver mode(%d)\n", cppc_state); return ret; }