From patchwork Wed Oct 16 11:31:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 176458 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp7233749ill; Wed, 16 Oct 2019 04:32:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqyKJNVvJHOTAjXHZnH3MbFKhVKKGbf8fmhbcnjyyA3OueaiG2jq8cMPi/3uI1PdSKTcjq15 X-Received: by 2002:a50:ef17:: with SMTP id m23mr16522632eds.200.1571225522483; Wed, 16 Oct 2019 04:32:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571225522; cv=none; d=google.com; s=arc-20160816; b=jucZ2MYHB3mXZTIu/3eYEkCbxgIQ6M1nql8ji5/Z+47agpl5GuMcHCm29BT/C1qvYa b4y8Q7E6/AUpNS7Z16a/NOhp9sfUAfPXZ0DsogUuwpdbpektuxyYqu3RJL+yrUbHRpGk 4m1WNk24e+7PIEZzdPbGRyvyVjT2INwUohhUrHK0Znwl4q2Fq1PWON8LovpsUwzHHZT6 XugGSOmdGJTE9Yh1hAUq4D5P46LkwtPciUFSwqh/yk84Qn+6IsWw1nJ5hN4S6kjT36k2 OqByu9m6yA7f/KUBCMBwexFl6OCgpjix1p+ahKFvgA4wanhZswx56UhU3/NTBU224wAg 2JUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=VhJSSgKonMP8J+UZxJu16JLCrKr2Kl8xqPLRdnV/E1E=; b=KX4iGBRCFV7D0Ta3JZeWBJVq7x+2WP7/vvc/Kv4KpHf2alhM57dpllP017NIZceIrY EYIFBk6ER4r+MoVAkjG+VvUhRacHyZ36eUkTxf9PnDqzDPyV/XJUf9yYsUSPFL4wZpRi aThi61iMVxcs0Y41NFsn8ezAGe6cKUfCsmXW1pSSho8xK55m0crjO01jp3csfYdcUCN0 4PbrQTFlS3ns6WGZPZ6XJipqnQv0jFrpALQyjm3s67Y+v3idLO17MXQsxvajSAV/zKFU Qy0db5iaEHjCtHKYqt+Ya4DAsbPFap/FQZ6uAsKEklA/blR5mTuccvFMmlrFSBA60wov 2xag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jy+8qIr0; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bt6si15442387edb.69.2019.10.16.04.32.02; Wed, 16 Oct 2019 04:32:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jy+8qIr0; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404999AbfJPLb6 (ORCPT + 26 others); Wed, 16 Oct 2019 07:31:58 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:50324 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728372AbfJPLb4 (ORCPT ); Wed, 16 Oct 2019 07:31:56 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9GBVsnt097071; Wed, 16 Oct 2019 06:31:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571225514; bh=VhJSSgKonMP8J+UZxJu16JLCrKr2Kl8xqPLRdnV/E1E=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jy+8qIr01IM/gmiU+A50/bStAZe2NOW7T80EeRTY6vn/W1Kggku70tkQt5nJ9fTp8 PfESu9sXugfsj7sw5EQNc+I+dYbKlUQVou3VHBVjYz8I3EIDkLTMK/WmVzq4b011sc sdK6OwMy3AvUMdSOd5nIyOiwii3aPdADoaax72ug= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9GBVsN1079952 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 16 Oct 2019 06:31:54 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 16 Oct 2019 06:31:53 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 16 Oct 2019 06:31:47 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9GBVkm6097485; Wed, 16 Oct 2019 06:31:52 -0500 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Roger Quadros , Jyri Sarha CC: Anil Varughese , , Subject: [PATCH 02/13] phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resources Date: Wed, 16 Oct 2019 17:01:06 +0530 Message-ID: <20191016113117.12370-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191016113117.12370-1-kishon@ti.com> References: <20191016113117.12370-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Certain platforms like TI J721E using Cadence Sierra Serdes doesn't provide explicit phy_clk and reset (APB reset) control. Make them optional here. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index de10402f2931..bed68c25682f 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -193,7 +193,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) platform_set_drvdata(pdev, sp); - sp->clk = devm_clk_get(dev, "phy_clk"); + sp->clk = devm_clk_get_optional(dev, "phy_clk"); if (IS_ERR(sp->clk)) { dev_err(dev, "failed to get clock phy_clk\n"); return PTR_ERR(sp->clk); @@ -205,7 +205,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) return PTR_ERR(sp->phy_rst); } - sp->apb_rst = devm_reset_control_get(dev, "sierra_apb"); + sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb"); if (IS_ERR(sp->apb_rst)) { dev_err(dev, "failed to get apb reset\n"); return PTR_ERR(sp->apb_rst); From patchwork Wed Oct 16 11:31:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 176459 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp7233763ill; Wed, 16 Oct 2019 04:32:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqxvQosZBrnOaZMwm+DGmW0AedoIxDU1kEHZD1/A6jswHWzxTWch3gTLOLNbflHOc7LCHcSD X-Received: by 2002:a17:906:6a15:: with SMTP id o21mr8352910ejr.79.1571225523003; Wed, 16 Oct 2019 04:32:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571225522; cv=none; d=google.com; s=arc-20160816; b=h/MbOrcwg72rE+GYLaaqPTZ9FdT6BdWsxONa6S5IwPvn1VR1CuhKdeXn7uScd5CIBk HKwuXibev24dXrMtn4DLkyUb2vcN8/FAkIzQOOFGUws75MBCHJtUO6OvlUyi0+Od8oPa JaDD5StAVks0xmH75chrlQVqTIjTW+4o6NEfVlqG/1j8ljZ+Iwp6IESf9VVTMPcVHB2c 8L5uvdW23ul3Eu2ERuo9xB7JJZ2ZD8HugXdUcfM/AYDMeQaUjTlisT2L6/Zsu/Nr7cxN HjNs0YEnYSkN/bMNoL5f4nRECXBYP3XRtG/NXWgnkrRu9/o+nbhFijGphh2GBNc7+Yly i98A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=jRiMBMJmewgGUtO0LFCTHdqgyIH530kaVVBhLOHLdL8=; b=xAzdB5IjEdkHoDHLcT+zeuwBxEngSj3tZd5U5hwu22YxH3/uL6BLHHXZR5vhwReoV2 2TW30YVlArL63coP1/O6hoJV9vg1q7Cy8EuxDs95vpJzMumpJjq9s0M99QYYlwCBC8E5 Vs0pAV8VyEo6eutHpynKPeL+DVxxa9qGGhT2dFcHDM1t7MoxfBC0EqQnif02dX/F4pc4 +Oyxb4ixe7UpgsZWFLhXJhtC0F/O0zSCwDhqnHYzh82yOomQOv1e2rqbbNd1g/UtJHob /THkdDc+TJypGFnj21ClBcPEQuyYfHlQeO98YDAXXeoOZqVvk08KhbZdhmH798j52VgX oN7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=VbyqXw99; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This is in perparation for adding SERDES_16G support present in TI's J721E SoC. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 289 ++++++++++++++++++----- 1 file changed, 235 insertions(+), 54 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index bed68c25682f..d0e7ae1c67b1 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -22,49 +22,61 @@ #include /* PHY register offsets */ -#define SIERRA_PHY_PLL_CFG (0xc00e << 2) -#define SIERRA_DET_STANDEC_A (0x4000 << 2) -#define SIERRA_DET_STANDEC_B (0x4001 << 2) -#define SIERRA_DET_STANDEC_C (0x4002 << 2) -#define SIERRA_DET_STANDEC_D (0x4003 << 2) -#define SIERRA_DET_STANDEC_E (0x4004 << 2) -#define SIERRA_PSM_LANECAL (0x4008 << 2) -#define SIERRA_PSM_DIAG (0x4015 << 2) -#define SIERRA_PSC_TX_A0 (0x4028 << 2) -#define SIERRA_PSC_TX_A1 (0x4029 << 2) -#define SIERRA_PSC_TX_A2 (0x402A << 2) -#define SIERRA_PSC_TX_A3 (0x402B << 2) -#define SIERRA_PSC_RX_A0 (0x4030 << 2) -#define SIERRA_PSC_RX_A1 (0x4031 << 2) -#define SIERRA_PSC_RX_A2 (0x4032 << 2) -#define SIERRA_PSC_RX_A3 (0x4033 << 2) -#define SIERRA_PLLCTRL_SUBRATE (0x403A << 2) -#define SIERRA_PLLCTRL_GEN_D (0x403E << 2) -#define SIERRA_DRVCTRL_ATTEN (0x406A << 2) -#define SIERRA_CLKPATHCTRL_TMR (0x4081 << 2) -#define SIERRA_RX_CREQ_FLTR_A_MODE1 (0x4087 << 2) -#define SIERRA_RX_CREQ_FLTR_A_MODE0 (0x4088 << 2) -#define SIERRA_CREQ_CCLKDET_MODE01 (0x408E << 2) -#define SIERRA_RX_CTLE_MAINTENANCE (0x4091 << 2) -#define SIERRA_CREQ_FSMCLK_SEL (0x4092 << 2) -#define SIERRA_CTLELUT_CTRL (0x4098 << 2) -#define SIERRA_DFE_ECMP_RATESEL (0x40C0 << 2) -#define SIERRA_DFE_SMP_RATESEL (0x40C1 << 2) -#define SIERRA_DEQ_VGATUNE_CTRL (0x40E1 << 2) -#define SIERRA_TMRVAL_MODE3 (0x416E << 2) -#define SIERRA_TMRVAL_MODE2 (0x416F << 2) -#define SIERRA_TMRVAL_MODE1 (0x4170 << 2) -#define SIERRA_TMRVAL_MODE0 (0x4171 << 2) -#define SIERRA_PICNT_MODE1 (0x4174 << 2) -#define SIERRA_CPI_OUTBUF_RATESEL (0x417C << 2) -#define SIERRA_LFPSFILT_NS (0x418A << 2) -#define SIERRA_LFPSFILT_RD (0x418B << 2) -#define SIERRA_LFPSFILT_MP (0x418C << 2) -#define SIERRA_SDFILT_H2L_A (0x4191 << 2) +#define SIERRA_COMMON_CDB_OFFSET 0x0 +#define SIERRA_MACRO_ID_REG 0x0 + +#define SIERRA_LANE_CDB_OFFSET(ln, offset) \ + (0x4000 + ((ln) * (0x800 >> (2 - (offset))))) +#define SIERRA_DET_STANDEC_A 0x000 +#define SIERRA_DET_STANDEC_B 0x001 +#define SIERRA_DET_STANDEC_C 0x002 +#define SIERRA_DET_STANDEC_D 0x003 +#define SIERRA_DET_STANDEC_E 0x004 +#define SIERRA_PSM_LANECAL 0x008 +#define SIERRA_PSM_DIAG 0x015 +#define SIERRA_PSC_TX_A0 0x028 +#define SIERRA_PSC_TX_A1 0x029 +#define SIERRA_PSC_TX_A2 0x02A +#define SIERRA_PSC_TX_A3 0x02B +#define SIERRA_PSC_RX_A0 0x030 +#define SIERRA_PSC_RX_A1 0x031 +#define SIERRA_PSC_RX_A2 0x032 +#define SIERRA_PSC_RX_A3 0x033 +#define SIERRA_PLLCTRL_SUBRATE 0x03A +#define SIERRA_PLLCTRL_GEN_D 0x03E +#define SIERRA_DRVCTRL_ATTEN 0x06A +#define SIERRA_CLKPATHCTRL_TMR 0x081 +#define SIERRA_RX_CREQ_FLTR_A_MODE1 0x087 +#define SIERRA_RX_CREQ_FLTR_A_MODE0 0x088 +#define SIERRA_CREQ_CCLKDET_MODE01 0x08E +#define SIERRA_RX_CTLE_MAINTENANCE 0x091 +#define SIERRA_CREQ_FSMCLK_SEL 0x092 +#define SIERRA_CTLELUT_CTRL 0x098 +#define SIERRA_DFE_ECMP_RATESEL 0x0C0 +#define SIERRA_DFE_SMP_RATESEL 0x0C1 +#define SIERRA_DEQ_VGATUNE_CTRL 0x0E1 +#define SIERRA_TMRVAL_MODE3 0x16E +#define SIERRA_TMRVAL_MODE2 0x16F +#define SIERRA_TMRVAL_MODE1 0x170 +#define SIERRA_TMRVAL_MODE0 0x171 +#define SIERRA_PICNT_MODE1 0x174 +#define SIERRA_CPI_OUTBUF_RATESEL 0x17C +#define SIERRA_LFPSFILT_NS 0x18A +#define SIERRA_LFPSFILT_RD 0x18B +#define SIERRA_LFPSFILT_MP 0x18C +#define SIERRA_SDFILT_H2L_A 0x191 + +#define SIERRA_PHY_CONFIG_CTRL_OFFSET 0xc000 +#define SIERRA_PHY_PLL_CFG 0xe #define SIERRA_MACRO_ID 0x00007364 #define SIERRA_MAX_LANES 4 +static const struct reg_field macro_id_type = + REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); +static const struct reg_field phy_pll_cfg_1 = + REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1); + struct cdns_sierra_inst { struct phy *phy; u32 phy_type; @@ -80,28 +92,93 @@ struct cdns_reg_pairs { struct cdns_sierra_data { u32 id_value; + u8 block_offset_shift; + u8 reg_offset_shift; u32 pcie_regs; u32 usb_regs; struct cdns_reg_pairs *pcie_vals; struct cdns_reg_pairs *usb_vals; }; -struct cdns_sierra_phy { +struct cdns_regmap_cdb_context { struct device *dev; void __iomem *base; + u8 reg_offset_shift; +}; + +struct cdns_sierra_phy { + struct device *dev; + struct regmap *regmap; struct cdns_sierra_data *init_data; struct cdns_sierra_inst phys[SIERRA_MAX_LANES]; struct reset_control *phy_rst; struct reset_control *apb_rst; + struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES]; + struct regmap *regmap_phy_config_ctrl; + struct regmap *regmap_common_cdb; + struct regmap_field *macro_id_type; + struct regmap_field *phy_pll_cfg_1; struct clk *clk; int nsubnodes; bool autoconf; }; +static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) +{ + struct cdns_regmap_cdb_context *ctx = context; + u32 offset = reg << ctx->reg_offset_shift; + + writew(val, ctx->base + offset); + + return 0; +} + +static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) +{ + struct cdns_regmap_cdb_context *ctx = context; + u32 offset = reg << ctx->reg_offset_shift; + + *val = readw(ctx->base + offset); + return 0; +} + +#define SIERRA_LANE_CDB_REGMAP_CONF(n) \ +{ \ + .name = "sierra_lane" n "_cdb", \ + .reg_stride = 1, \ + .fast_io = true, \ + .reg_write = cdns_regmap_write, \ + .reg_read = cdns_regmap_read, \ +} + +static struct regmap_config cdns_sierra_lane_cdb_config[] = { + SIERRA_LANE_CDB_REGMAP_CONF("0"), + SIERRA_LANE_CDB_REGMAP_CONF("1"), + SIERRA_LANE_CDB_REGMAP_CONF("2"), + SIERRA_LANE_CDB_REGMAP_CONF("3"), +}; + +static struct regmap_config cdns_sierra_common_cdb_config = { + .name = "sierra_common_cdb", + .reg_stride = 1, + .fast_io = true, + .reg_write = cdns_regmap_write, + .reg_read = cdns_regmap_read, +}; + +static struct regmap_config cdns_sierra_phy_config_ctrl_config = { + .name = "sierra_phy_config_ctrl", + .reg_stride = 1, + .fast_io = true, + .reg_write = cdns_regmap_write, + .reg_read = cdns_regmap_read, +}; + static void cdns_sierra_phy_init(struct phy *gphy) { struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent); + struct regmap *regmap = phy->regmap; int i, j; struct cdns_reg_pairs *vals; u32 num_regs; @@ -115,10 +192,12 @@ static void cdns_sierra_phy_init(struct phy *gphy) } else { return; } - for (i = 0; i < ins->num_lanes; i++) - for (j = 0; j < num_regs ; j++) - writel(vals[j].val, phy->base + - vals[j].off + (i + ins->mlane) * 0x800); + for (i = 0; i < ins->num_lanes; i++) { + for (j = 0; j < num_regs ; j++) { + regmap = phy->regmap_lane_cdb[i + ins->mlane]; + regmap_write(regmap, vals[j].off, vals[j].val); + } + } } static int cdns_sierra_phy_on(struct phy *gphy) @@ -159,37 +238,136 @@ static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, static const struct of_device_id cdns_sierra_id_table[]; +static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, + u32 block_offset, u8 block_offset_shift, + u8 reg_offset_shift, + const struct regmap_config *config) +{ + struct cdns_regmap_cdb_context *ctx; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return ERR_PTR(-ENOMEM); + + ctx->dev = dev; + ctx->base = base + (block_offset << block_offset_shift); + ctx->reg_offset_shift = reg_offset_shift; + + return devm_regmap_init(dev, NULL, ctx, config); +} + +static int cdns_regfield_init(struct cdns_sierra_phy *sp) +{ + struct device *dev = sp->dev; + struct regmap_field *field; + struct regmap *regmap; + + regmap = sp->regmap_common_cdb; + field = devm_regmap_field_alloc(dev, regmap, macro_id_type); + if (IS_ERR(field)) { + dev_err(dev, "MACRO_ID_TYPE reg field init failed\n"); + return PTR_ERR(field); + } + sp->macro_id_type = field; + + regmap = sp->regmap_phy_config_ctrl; + field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); + if (IS_ERR(field)) { + dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n"); + return PTR_ERR(field); + } + sp->phy_pll_cfg_1 = field; + + return 0; +} + +static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, + void __iomem *base, u8 block_offset_shift, + u8 reg_offset_shift) +{ + struct device *dev = sp->dev; + struct regmap *regmap; + u32 block_offset; + int i; + + for (i = 0; i < SIERRA_MAX_LANES; i++) { + block_offset = SIERRA_LANE_CDB_OFFSET(i, reg_offset_shift); + regmap = cdns_regmap_init(dev, base, block_offset, + block_offset_shift, reg_offset_shift, + &cdns_sierra_lane_cdb_config[i]); + if (IS_ERR(regmap)) { + dev_err(dev, "Failed to init lane CDB regmap\n"); + return PTR_ERR(regmap); + } + sp->regmap_lane_cdb[i] = regmap; + } + + regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET, + block_offset_shift, reg_offset_shift, + &cdns_sierra_common_cdb_config); + if (IS_ERR(regmap)) { + dev_err(dev, "Failed to init common CDB regmap\n"); + return PTR_ERR(regmap); + } + sp->regmap_common_cdb = regmap; + + regmap = cdns_regmap_init(dev, base, SIERRA_PHY_CONFIG_CTRL_OFFSET, + block_offset_shift, reg_offset_shift, + &cdns_sierra_phy_config_ctrl_config); + if (IS_ERR(regmap)) { + dev_err(dev, "Failed to init PHY config and control regmap\n"); + return PTR_ERR(regmap); + } + sp->regmap_phy_config_ctrl = regmap; + + return 0; +} + static int cdns_sierra_phy_probe(struct platform_device *pdev) { struct cdns_sierra_phy *sp; struct phy_provider *phy_provider; struct device *dev = &pdev->dev; const struct of_device_id *match; + struct cdns_sierra_data *data; + unsigned int id_value; struct resource *res; int i, ret, node = 0; + void __iomem *base; struct device_node *dn = dev->of_node, *child; if (of_get_child_count(dn) == 0) return -ENODEV; + /* Get init data for this PHY */ + match = of_match_device(cdns_sierra_id_table, dev); + if (!match) + return -EINVAL; + + data = (struct cdns_sierra_data *)match->data; + sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL); if (!sp) return -ENOMEM; dev_set_drvdata(dev, sp); sp->dev = dev; + sp->init_data = data; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - sp->base = devm_ioremap_resource(dev, res); - if (IS_ERR(sp->base)) { + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) { dev_err(dev, "missing \"reg\"\n"); - return PTR_ERR(sp->base); + return PTR_ERR(base); } - /* Get init data for this PHY */ - match = of_match_device(cdns_sierra_id_table, dev); - if (!match) - return -EINVAL; - sp->init_data = (struct cdns_sierra_data *)match->data; + ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift, + data->reg_offset_shift); + if (ret) + return ret; + + ret = cdns_regfield_init(sp); + if (ret) + return ret; platform_set_drvdata(pdev, sp); @@ -219,7 +397,8 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) reset_control_deassert(sp->apb_rst); /* Check that PHY is present */ - if (sp->init_data->id_value != readl(sp->base)) { + regmap_field_read(sp->macro_id_type, &id_value); + if (sp->init_data->id_value != id_value) { ret = -EINVAL; goto clk_disable; } @@ -267,7 +446,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) /* If more than one subnode, configure the PHY as multilink */ if (!sp->autoconf && sp->nsubnodes > 1) - writel(2, sp->base + SIERRA_PHY_PLL_CFG); + regmap_field_write(sp->phy_pll_cfg_1, 0x1); pm_runtime_enable(dev); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); @@ -364,6 +543,8 @@ static struct cdns_reg_pairs cdns_pcie_regs[] = { static const struct cdns_sierra_data cdns_map_sierra = { SIERRA_MACRO_ID, + 0x2, + 0x2, ARRAY_SIZE(cdns_pcie_regs), ARRAY_SIZE(cdns_usb_regs), cdns_pcie_regs, From patchwork Wed Oct 16 11:31:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 176469 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp7234496ill; Wed, 16 Oct 2019 04:32:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqxuCx5YbfsWWd7fmS4H3+N9BVrCRZdgu7lFw6GrFzKO/dUzMTDHNOzjRsMyJJ3cTTyTvhLu X-Received: by 2002:a17:906:fca8:: with SMTP id qw8mr40288772ejb.188.1571225560321; Wed, 16 Oct 2019 04:32:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571225560; cv=none; d=google.com; s=arc-20160816; b=vxoZw9QPt7PhbAhTIf1UgPWLvazs0PMROxResWR4GFf4kMd0TDOpODyQLn+Vq+urNS QqsqiEohJumKE3JuYE/F/a+Pvp0L80lvUjqLNLEMSZiLSmAoJw7v2M1j0BRW2uJTled2 GDjwEz+BW+4cBUe/nEhh4QxqEX8HiE+lMuCNA19csY1aLoWHfYUwzu8nag8ls5Nrp8IF 9uPzaMCiKcLFATpaIoZRZmTiwGBDvJZqzZ+PhfcrFTRyn7YMVRToG/1rKQd3/yGBbTuG fYwcPtcfsgFUN7alR/Qeo+KLJ/+WmmpaQTfsHpgAKxZGox+PM/OagC9J5og1RKGeT5Fv IK9g== ARC-Message-Signature: i=1; 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Wed, 16 Oct 2019 06:31:53 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9GBVkm9097485; Wed, 16 Oct 2019 06:31:58 -0500 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Roger Quadros , Jyri Sarha CC: Anil Varughese , , Subject: [PATCH 05/13] phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops Date: Wed, 16 Oct 2019 17:01:09 +0530 Message-ID: <20191016113117.12370-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191016113117.12370-1-kishon@ti.com> References: <20191016113117.12370-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Instead of invoking cdns_sierra_phy_init() from probe, add it in phy_ops so that it's initialized when the PHY consumer invokes phy_init() Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 89a3b732c311..5c617248841f 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -174,7 +174,7 @@ static struct regmap_config cdns_sierra_phy_config_ctrl_config = { .reg_read = cdns_regmap_read, }; -static void cdns_sierra_phy_init(struct phy *gphy) +static int cdns_sierra_phy_init(struct phy *gphy) { struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent); @@ -183,6 +183,10 @@ static void cdns_sierra_phy_init(struct phy *gphy) struct cdns_reg_pairs *vals; u32 num_regs; + /* Initialise the PHY registers, unless auto configured */ + if (phy->autoconf) + return 0; + if (ins->phy_type == PHY_TYPE_PCIE) { num_regs = phy->init_data->pcie_regs; vals = phy->init_data->pcie_vals; @@ -190,7 +194,7 @@ static void cdns_sierra_phy_init(struct phy *gphy) num_regs = phy->init_data->usb_regs; vals = phy->init_data->usb_vals; } else { - return; + return -EINVAL; } for (i = 0; i < ins->num_lanes; i++) { for (j = 0; j < num_regs ; j++) { @@ -198,6 +202,8 @@ static void cdns_sierra_phy_init(struct phy *gphy) regmap_write(regmap, vals[j].off, vals[j].val); } } + + return 0; } static int cdns_sierra_phy_on(struct phy *gphy) @@ -216,6 +222,7 @@ static int cdns_sierra_phy_off(struct phy *gphy) } static const struct phy_ops ops = { + .init = cdns_sierra_phy_init, .power_on = cdns_sierra_phy_on, .power_off = cdns_sierra_phy_off, .owner = THIS_MODULE, @@ -436,10 +443,6 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) sp->phys[node].phy = gphy; phy_set_drvdata(gphy, &sp->phys[node]); - /* Initialise the PHY registers, unless auto configured */ - if (!sp->autoconf) - cdns_sierra_phy_init(gphy); - node++; } sp->nsubnodes = node; From patchwork Wed Oct 16 11:31:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 176461 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp7233865ill; Wed, 16 Oct 2019 04:32:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqxrmpGaj7mVBUVTJefH7kFRPg6Mg0MrzoGmA0ni2QSXpEC0yPvPc+4dDs29pXz2peYvS/C+ X-Received: by 2002:a17:906:2961:: with SMTP id x1mr39200844ejd.91.1571225529289; Wed, 16 Oct 2019 04:32:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571225529; cv=none; d=google.com; s=arc-20160816; b=TqfDSDkYv4tQaduK7SuKeteKGEY3Vc4I/m0KlIkc0846lFG3REdoKWDMq6piXFwSKC Uhn54P6EjYHlXkzCujXFUFmpGJFYDBr/3/FPCIT1uEoTTk0vwjw3LjBGYgv7wTpzpV97 7ENq6AgzmHteCOKgbH+LZCgsoi7Wm0Vp1GprCRDgLRhKVzokii8XZMzBTbmG1lOlntj6 FeYZiq5/rcLOaRbtJ6MTQ1/q6wBET2ajEdIFxtiYnylffjyaqJbta+bHy21Gkm0End+3 jqEzh6s/zFvE8G4mJgRzoBslCLhmYNZaymDgU19EfH3y4I8/7d9Vr4KEhA/AjhPKYeYL USkQ== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id g17si14916374ejd.123.2019.10.16.04.32.09; Wed, 16 Oct 2019 04:32:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jfYi9nNs; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405033AbfJPLcG (ORCPT + 26 others); Wed, 16 Oct 2019 07:32:06 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:36978 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732754AbfJPLcF (ORCPT ); Wed, 16 Oct 2019 07:32:05 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9GBW3gL049985; Wed, 16 Oct 2019 06:32:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571225523; bh=zj8LhWBrezAiHESWsOa2clUU6Den7gB6daayHxHKv7E=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jfYi9nNsSpvcfZVE3yxvXs7pzUI3z9ggauee84GEPNT0ryw/Q7J35R4EGBeZlnsAg OmRs3Ic9QHD2uE/7f6QKuiqmxKaE1Sr0g/esErxmnnUNAv+4cO3V+Sncn++9JCIayR uZyHpgZMQOxKBbvoNglhim9AD+5KCDEiZf78B+t0= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9GBW3Rr113883 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 16 Oct 2019 06:32:03 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 16 Oct 2019 06:31:56 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 16 Oct 2019 06:31:56 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9GBVkmA097485; Wed, 16 Oct 2019 06:32:01 -0500 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Roger Quadros , Jyri Sarha CC: Anil Varughese , , Subject: [PATCH 06/13] phy: cadence: Sierra: Modify register macro names to be in sync with Sierra user guide Date: Wed, 16 Oct 2019 17:01:10 +0530 Message-ID: <20191016113117.12370-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191016113117.12370-1-kishon@ti.com> References: <20191016113117.12370-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Modify register offset macro names to be in sync with Sierra user guide. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 173 ++++++++++++----------- 1 file changed, 87 insertions(+), 86 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 5c617248841f..c0ea0863d050 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -22,55 +22,56 @@ #include /* PHY register offsets */ -#define SIERRA_COMMON_CDB_OFFSET 0x0 -#define SIERRA_MACRO_ID_REG 0x0 +#define SIERRA_COMMON_CDB_OFFSET 0x0 +#define SIERRA_MACRO_ID_REG 0x0 #define SIERRA_LANE_CDB_OFFSET(ln, offset) \ (0x4000 + ((ln) * (0x800 >> (2 - (offset))))) -#define SIERRA_DET_STANDEC_A 0x000 -#define SIERRA_DET_STANDEC_B 0x001 -#define SIERRA_DET_STANDEC_C 0x002 -#define SIERRA_DET_STANDEC_D 0x003 -#define SIERRA_DET_STANDEC_E 0x004 -#define SIERRA_PSM_LANECAL 0x008 -#define SIERRA_PSM_DIAG 0x015 -#define SIERRA_PSC_TX_A0 0x028 -#define SIERRA_PSC_TX_A1 0x029 -#define SIERRA_PSC_TX_A2 0x02A -#define SIERRA_PSC_TX_A3 0x02B -#define SIERRA_PSC_RX_A0 0x030 -#define SIERRA_PSC_RX_A1 0x031 -#define SIERRA_PSC_RX_A2 0x032 -#define SIERRA_PSC_RX_A3 0x033 -#define SIERRA_PLLCTRL_SUBRATE 0x03A -#define SIERRA_PLLCTRL_GEN_D 0x03E -#define SIERRA_DRVCTRL_ATTEN 0x06A -#define SIERRA_CLKPATHCTRL_TMR 0x081 -#define SIERRA_RX_CREQ_FLTR_A_MODE1 0x087 -#define SIERRA_RX_CREQ_FLTR_A_MODE0 0x088 -#define SIERRA_CREQ_CCLKDET_MODE01 0x08E -#define SIERRA_RX_CTLE_MAINTENANCE 0x091 -#define SIERRA_CREQ_FSMCLK_SEL 0x092 -#define SIERRA_CTLELUT_CTRL 0x098 -#define SIERRA_DFE_ECMP_RATESEL 0x0C0 -#define SIERRA_DFE_SMP_RATESEL 0x0C1 -#define SIERRA_DEQ_VGATUNE_CTRL 0x0E1 -#define SIERRA_TMRVAL_MODE3 0x16E -#define SIERRA_TMRVAL_MODE2 0x16F -#define SIERRA_TMRVAL_MODE1 0x170 -#define SIERRA_TMRVAL_MODE0 0x171 -#define SIERRA_PICNT_MODE1 0x174 -#define SIERRA_CPI_OUTBUF_RATESEL 0x17C -#define SIERRA_LFPSFILT_NS 0x18A -#define SIERRA_LFPSFILT_RD 0x18B -#define SIERRA_LFPSFILT_MP 0x18C -#define SIERRA_SDFILT_H2L_A 0x191 - -#define SIERRA_PHY_CONFIG_CTRL_OFFSET 0xc000 -#define SIERRA_PHY_PLL_CFG 0xe - -#define SIERRA_MACRO_ID 0x00007364 -#define SIERRA_MAX_LANES 4 + +#define SIERRA_DET_STANDEC_A_PREG 0x000 +#define SIERRA_DET_STANDEC_B_PREG 0x001 +#define SIERRA_DET_STANDEC_C_PREG 0x002 +#define SIERRA_DET_STANDEC_D_PREG 0x003 +#define SIERRA_DET_STANDEC_E_PREG 0x004 +#define SIERRA_PSM_LANECAL_PREG 0x008 +#define SIERRA_PSM_DIAG_PREG 0x015 +#define SIERRA_PSC_TX_A0_PREG 0x028 +#define SIERRA_PSC_TX_A1_PREG 0x029 +#define SIERRA_PSC_TX_A2_PREG 0x02A +#define SIERRA_PSC_TX_A3_PREG 0x02B +#define SIERRA_PSC_RX_A0_PREG 0x030 +#define SIERRA_PSC_RX_A1_PREG 0x031 +#define SIERRA_PSC_RX_A2_PREG 0x032 +#define SIERRA_PSC_RX_A3_PREG 0x033 +#define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A +#define SIERRA_PLLCTRL_GEN_D_PREG 0x03E +#define SIERRA_DRVCTRL_ATTEN_PREG 0x06A +#define SIERRA_CLKPATHCTRL_TMR_PREG 0x081 +#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087 +#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088 +#define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E +#define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091 +#define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092 +#define SIERRA_CTLELUT_CTRL_PREG 0x098 +#define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0 +#define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1 +#define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1 +#define SIERRA_TMRVAL_MODE3_PREG 0x16E +#define SIERRA_TMRVAL_MODE2_PREG 0x16F +#define SIERRA_TMRVAL_MODE1_PREG 0x170 +#define SIERRA_TMRVAL_MODE0_PREG 0x171 +#define SIERRA_PICNT_MODE1_PREG 0x174 +#define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C +#define SIERRA_LFPSFILT_NS_PREG 0x18A +#define SIERRA_LFPSFILT_RD_PREG 0x18B +#define SIERRA_LFPSFILT_MP_PREG 0x18C +#define SIERRA_SDFILT_H2L_A_PREG 0x191 + +#define SIERRA_PHY_CONFIG_CTRL_OFFSET 0xc000 +#define SIERRA_PHY_PLL_CFG 0xe + +#define SIERRA_MACRO_ID 0x00007364 +#define SIERRA_MAX_LANES 4 static const struct reg_field macro_id_type = REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); @@ -494,42 +495,42 @@ static struct cdns_reg_pairs cdns_usb_regs[] = { * These values are specific to this specific hardware * configuration. */ - {0xFE0A, SIERRA_DET_STANDEC_A}, - {0x000F, SIERRA_DET_STANDEC_B}, - {0x55A5, SIERRA_DET_STANDEC_C}, - {0x69AD, SIERRA_DET_STANDEC_D}, - {0x0241, SIERRA_DET_STANDEC_E}, - {0x0110, SIERRA_PSM_LANECAL}, - {0xCF00, SIERRA_PSM_DIAG}, - {0x001F, SIERRA_PSC_TX_A0}, - {0x0007, SIERRA_PSC_TX_A1}, - {0x0003, SIERRA_PSC_TX_A2}, - {0x0003, SIERRA_PSC_TX_A3}, - {0x0FFF, SIERRA_PSC_RX_A0}, - {0x0003, SIERRA_PSC_RX_A1}, - {0x0003, SIERRA_PSC_RX_A2}, - {0x0001, SIERRA_PSC_RX_A3}, - {0x0001, SIERRA_PLLCTRL_SUBRATE}, - {0x0406, SIERRA_PLLCTRL_GEN_D}, - {0x0000, SIERRA_DRVCTRL_ATTEN}, - {0x823E, SIERRA_CLKPATHCTRL_TMR}, - {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1}, - {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0}, - {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01}, - {0x023C, SIERRA_RX_CTLE_MAINTENANCE}, - {0x3232, SIERRA_CREQ_FSMCLK_SEL}, - {0x8452, SIERRA_CTLELUT_CTRL}, - {0x4121, SIERRA_DFE_ECMP_RATESEL}, - {0x4121, SIERRA_DFE_SMP_RATESEL}, - {0x9999, SIERRA_DEQ_VGATUNE_CTRL}, - {0x0330, SIERRA_TMRVAL_MODE0}, - {0x01FF, SIERRA_PICNT_MODE1}, - {0x0009, SIERRA_CPI_OUTBUF_RATESEL}, - {0x000F, SIERRA_LFPSFILT_NS}, - {0x0009, SIERRA_LFPSFILT_RD}, - {0x0001, SIERRA_LFPSFILT_MP}, - {0x8013, SIERRA_SDFILT_H2L_A}, - {0x0400, SIERRA_TMRVAL_MODE1}, + {0xFE0A, SIERRA_DET_STANDEC_A_PREG}, + {0x000F, SIERRA_DET_STANDEC_B_PREG}, + {0x55A5, SIERRA_DET_STANDEC_C_PREG}, + {0x69AD, SIERRA_DET_STANDEC_D_PREG}, + {0x0241, SIERRA_DET_STANDEC_E_PREG}, + {0x0110, SIERRA_PSM_LANECAL_PREG}, + {0xCF00, SIERRA_PSM_DIAG_PREG}, + {0x001F, SIERRA_PSC_TX_A0_PREG}, + {0x0007, SIERRA_PSC_TX_A1_PREG}, + {0x0003, SIERRA_PSC_TX_A2_PREG}, + {0x0003, SIERRA_PSC_TX_A3_PREG}, + {0x0FFF, SIERRA_PSC_RX_A0_PREG}, + {0x0003, SIERRA_PSC_RX_A1_PREG}, + {0x0003, SIERRA_PSC_RX_A2_PREG}, + {0x0001, SIERRA_PSC_RX_A3_PREG}, + {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG}, + {0x0406, SIERRA_PLLCTRL_GEN_D_PREG}, + {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, + {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG}, + {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, + {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, + {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, + {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, + {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG}, + {0x8452, SIERRA_CTLELUT_CTRL_PREG}, + {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG}, + {0x4121, SIERRA_DFE_SMP_RATESEL_PREG}, + {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG}, + {0x0330, SIERRA_TMRVAL_MODE0_PREG}, + {0x01FF, SIERRA_PICNT_MODE1_PREG}, + {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG}, + {0x000F, SIERRA_LFPSFILT_NS_PREG}, + {0x0009, SIERRA_LFPSFILT_RD_PREG}, + {0x0001, SIERRA_LFPSFILT_MP_PREG}, + {0x8013, SIERRA_SDFILT_H2L_A_PREG}, + {0x0400, SIERRA_TMRVAL_MODE1_PREG}, }; static struct cdns_reg_pairs cdns_pcie_regs[] = { @@ -538,10 +539,10 @@ static struct cdns_reg_pairs cdns_pcie_regs[] = { * These values are specific to this specific hardware * configuration. */ - {0x891f, SIERRA_DET_STANDEC_D}, - {0x0053, SIERRA_DET_STANDEC_E}, - {0x0400, SIERRA_TMRVAL_MODE2}, - {0x0200, SIERRA_TMRVAL_MODE3}, + {0x891f, SIERRA_DET_STANDEC_D_PREG}, + {0x0053, SIERRA_DET_STANDEC_E_PREG}, + {0x0400, SIERRA_TMRVAL_MODE2_PREG}, + {0x0200, SIERRA_TMRVAL_MODE3_PREG}, }; static const struct cdns_sierra_data cdns_map_sierra = { From patchwork Wed Oct 16 11:31:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 176463 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp7233981ill; Wed, 16 Oct 2019 04:32:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqySuGVmVou/rRjPUSKTv93mQTnIzYGQkklR48HIVdPi/5epeFnah/Z1/TUg1+ueacrShCsT X-Received: by 2002:a17:906:b245:: with SMTP id ce5mr39156782ejb.52.1571225535079; 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[209.132.180.67]) by mx.google.com with ESMTP id b4si15301142edq.221.2019.10.16.04.32.14; Wed, 16 Oct 2019 04:32:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Ml1AI1H+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405048AbfJPLcK (ORCPT + 26 others); Wed, 16 Oct 2019 07:32:10 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:50354 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732754AbfJPLcI (ORCPT ); Wed, 16 Oct 2019 07:32:08 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9GBW5HX097115; Wed, 16 Oct 2019 06:32:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571225525; bh=pTDs+F9DlwcWqOO7mCdM7pTZQAYeGldBe85WSbu6hBI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Ml1AI1H+1+MJcHfDe19sFBhCOvoIuEPxlYUh+og7D4uwo9WC+qOqG7PGSXCNPYbNh NMvTRHsHb5CLcbjiYQBKNLBIzS1iD1FE7ubK8Vif+GTeiYGvNMycchSRya3jU37mAh i9PqW1+C0v4l3/sMV2J883sjTZg1u7YwTlxz/BlU= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9GBW5lJ037861 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 16 Oct 2019 06:32:05 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 16 Oct 2019 06:32:05 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 16 Oct 2019 06:31:58 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9GBVkmB097485; Wed, 16 Oct 2019 06:32:03 -0500 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Roger Quadros , Jyri Sarha CC: Anil Varughese , , Subject: [PATCH 07/13] phy: cadence: Sierra: Configure both lane cdb and common cdb registers for external SSC Date: Wed, 16 Oct 2019 17:01:11 +0530 Message-ID: <20191016113117.12370-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191016113117.12370-1-kishon@ti.com> References: <20191016113117.12370-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Anil Varughese The existing configuration done in Cadence Sierra driver is only for reference and is not used in any platforms. Remove them and configure both lane cdb and common cdb registers to be used with external SSC configuration. This is validated in TI J721E platform. Signed-off-by: Anil Varughese Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 356 ++++++++++++++++------- 1 file changed, 257 insertions(+), 99 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index c0ea0863d050..b555d4c3633b 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -22,56 +22,123 @@ #include /* PHY register offsets */ -#define SIERRA_COMMON_CDB_OFFSET 0x0 -#define SIERRA_MACRO_ID_REG 0x0 +#define SIERRA_COMMON_CDB_OFFSET 0x0 +#define SIERRA_MACRO_ID_REG 0x0 +#define SIERRA_CMN_PLLLC_MODE_PREG 0x48 +#define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 +#define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A +#define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B +#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F +#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 +#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 #define SIERRA_LANE_CDB_OFFSET(ln, offset) \ (0x4000 + ((ln) * (0x800 >> (2 - (offset))))) -#define SIERRA_DET_STANDEC_A_PREG 0x000 -#define SIERRA_DET_STANDEC_B_PREG 0x001 -#define SIERRA_DET_STANDEC_C_PREG 0x002 -#define SIERRA_DET_STANDEC_D_PREG 0x003 -#define SIERRA_DET_STANDEC_E_PREG 0x004 -#define SIERRA_PSM_LANECAL_PREG 0x008 -#define SIERRA_PSM_DIAG_PREG 0x015 -#define SIERRA_PSC_TX_A0_PREG 0x028 -#define SIERRA_PSC_TX_A1_PREG 0x029 -#define SIERRA_PSC_TX_A2_PREG 0x02A -#define SIERRA_PSC_TX_A3_PREG 0x02B -#define SIERRA_PSC_RX_A0_PREG 0x030 -#define SIERRA_PSC_RX_A1_PREG 0x031 -#define SIERRA_PSC_RX_A2_PREG 0x032 -#define SIERRA_PSC_RX_A3_PREG 0x033 -#define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A -#define SIERRA_PLLCTRL_GEN_D_PREG 0x03E -#define SIERRA_DRVCTRL_ATTEN_PREG 0x06A -#define SIERRA_CLKPATHCTRL_TMR_PREG 0x081 -#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087 -#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088 -#define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E -#define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091 -#define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092 -#define SIERRA_CTLELUT_CTRL_PREG 0x098 -#define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0 -#define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1 -#define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1 -#define SIERRA_TMRVAL_MODE3_PREG 0x16E -#define SIERRA_TMRVAL_MODE2_PREG 0x16F -#define SIERRA_TMRVAL_MODE1_PREG 0x170 -#define SIERRA_TMRVAL_MODE0_PREG 0x171 -#define SIERRA_PICNT_MODE1_PREG 0x174 -#define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C -#define SIERRA_LFPSFILT_NS_PREG 0x18A -#define SIERRA_LFPSFILT_RD_PREG 0x18B -#define SIERRA_LFPSFILT_MP_PREG 0x18C -#define SIERRA_SDFILT_H2L_A_PREG 0x191 - -#define SIERRA_PHY_CONFIG_CTRL_OFFSET 0xc000 -#define SIERRA_PHY_PLL_CFG 0xe - -#define SIERRA_MACRO_ID 0x00007364 -#define SIERRA_MAX_LANES 4 +#define SIERRA_DET_STANDEC_A_PREG 0x000 +#define SIERRA_DET_STANDEC_B_PREG 0x001 +#define SIERRA_DET_STANDEC_C_PREG 0x002 +#define SIERRA_DET_STANDEC_D_PREG 0x003 +#define SIERRA_DET_STANDEC_E_PREG 0x004 +#define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008 +#define SIERRA_PSM_A0IN_TMR_PREG 0x009 +#define SIERRA_PSM_DIAG_PREG 0x015 +#define SIERRA_PSC_TX_A0_PREG 0x028 +#define SIERRA_PSC_TX_A1_PREG 0x029 +#define SIERRA_PSC_TX_A2_PREG 0x02A +#define SIERRA_PSC_TX_A3_PREG 0x02B +#define SIERRA_PSC_RX_A0_PREG 0x030 +#define SIERRA_PSC_RX_A1_PREG 0x031 +#define SIERRA_PSC_RX_A2_PREG 0x032 +#define SIERRA_PSC_RX_A3_PREG 0x033 +#define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A +#define SIERRA_PLLCTRL_GEN_D_PREG 0x03E +#define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F +#define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B +#define SIERRA_DFE_BIASTRIM_PREG 0x04C +#define SIERRA_DRVCTRL_ATTEN_PREG 0x06A +#define SIERRA_CLKPATHCTRL_TMR_PREG 0x081 +#define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085 +#define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086 +#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087 +#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088 +#define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E +#define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091 +#define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092 +#define SIERRA_CREQ_EQ_CTRL_PREG 0x093 +#define SIERRA_CREQ_SPARE_PREG 0x096 +#define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG 0x097 +#define SIERRA_CTLELUT_CTRL_PREG 0x098 +#define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0 +#define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1 +#define SIERRA_DEQ_PHALIGN_CTRL 0x0C4 +#define SIERRA_DEQ_CONCUR_CTRL1_PREG 0x0C8 +#define SIERRA_DEQ_CONCUR_CTRL2_PREG 0x0C9 +#define SIERRA_DEQ_EPIPWR_CTRL2_PREG 0x0CD +#define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG 0x0CE +#define SIERRA_DEQ_ERRCMP_CTRL_PREG 0x0D0 +#define SIERRA_DEQ_OFFSET_CTRL_PREG 0x0D8 +#define SIERRA_DEQ_GAIN_CTRL_PREG 0x0E0 +#define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1 +#define SIERRA_DEQ_GLUT0 0x0E8 +#define SIERRA_DEQ_GLUT1 0x0E9 +#define SIERRA_DEQ_GLUT2 0x0EA +#define SIERRA_DEQ_GLUT3 0x0EB +#define SIERRA_DEQ_GLUT4 0x0EC +#define SIERRA_DEQ_GLUT5 0x0ED +#define SIERRA_DEQ_GLUT6 0x0EE +#define SIERRA_DEQ_GLUT7 0x0EF +#define SIERRA_DEQ_GLUT8 0x0F0 +#define SIERRA_DEQ_GLUT9 0x0F1 +#define SIERRA_DEQ_GLUT10 0x0F2 +#define SIERRA_DEQ_GLUT11 0x0F3 +#define SIERRA_DEQ_GLUT12 0x0F4 +#define SIERRA_DEQ_GLUT13 0x0F5 +#define SIERRA_DEQ_GLUT14 0x0F6 +#define SIERRA_DEQ_GLUT15 0x0F7 +#define SIERRA_DEQ_GLUT16 0x0F8 +#define SIERRA_DEQ_ALUT0 0x108 +#define SIERRA_DEQ_ALUT1 0x109 +#define SIERRA_DEQ_ALUT2 0x10A +#define SIERRA_DEQ_ALUT3 0x10B +#define SIERRA_DEQ_ALUT4 0x10C +#define SIERRA_DEQ_ALUT5 0x10D +#define SIERRA_DEQ_ALUT6 0x10E +#define SIERRA_DEQ_ALUT7 0x10F +#define SIERRA_DEQ_ALUT8 0x110 +#define SIERRA_DEQ_ALUT9 0x111 +#define SIERRA_DEQ_ALUT10 0x112 +#define SIERRA_DEQ_ALUT11 0x113 +#define SIERRA_DEQ_ALUT12 0x114 +#define SIERRA_DEQ_ALUT13 0x115 +#define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128 +#define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134 +#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 +#define SIERRA_DEQ_TAU_CTRL2_PREG 0x151 +#define SIERRA_DEQ_PICTRL_PREG 0x161 +#define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170 +#define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171 +#define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174 +#define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C +#define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183 +#define SIERRA_LFPSDET_SUPPORT_PREG 0x188 +#define SIERRA_LFPSFILT_NS_PREG 0x18A +#define SIERRA_LFPSFILT_RD_PREG 0x18B +#define SIERRA_LFPSFILT_MP_PREG 0x18C +#define SIERRA_SIGDET_SUPPORT_PREG 0x190 +#define SIERRA_SDFILT_H2L_A_PREG 0x191 +#define SIERRA_SDFILT_L2H_PREG 0x193 +#define SIERRA_RXBUFFER_CTLECTRL_PREG 0x19E +#define SIERRA_RXBUFFER_RCDFECTRL_PREG 0x19F +#define SIERRA_RXBUFFER_DFECTRL_PREG 0x1A0 +#define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F +#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 + +#define SIERRA_PHY_CONFIG_CTRL_OFFSET 0xc000 +#define SIERRA_PHY_PLL_CFG 0xe + +#define SIERRA_MACRO_ID 0x00007364 +#define SIERRA_MAX_LANES 4 static const struct reg_field macro_id_type = REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); @@ -95,10 +162,14 @@ struct cdns_sierra_data { u32 id_value; u8 block_offset_shift; u8 reg_offset_shift; - u32 pcie_regs; - u32 usb_regs; - struct cdns_reg_pairs *pcie_vals; - struct cdns_reg_pairs *usb_vals; + u32 pcie_cmn_regs; + u32 pcie_ln_regs; + u32 usb_cmn_regs; + u32 usb_ln_regs; + struct cdns_reg_pairs *pcie_cmn_vals; + struct cdns_reg_pairs *pcie_ln_vals; + struct cdns_reg_pairs *usb_cmn_vals; + struct cdns_reg_pairs *usb_ln_vals; }; struct cdns_regmap_cdb_context { @@ -181,26 +252,35 @@ static int cdns_sierra_phy_init(struct phy *gphy) struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent); struct regmap *regmap = phy->regmap; int i, j; - struct cdns_reg_pairs *vals; - u32 num_regs; + struct cdns_reg_pairs *cmn_vals, *ln_vals; + u32 num_cmn_regs, num_ln_regs; /* Initialise the PHY registers, unless auto configured */ if (phy->autoconf) return 0; if (ins->phy_type == PHY_TYPE_PCIE) { - num_regs = phy->init_data->pcie_regs; - vals = phy->init_data->pcie_vals; + num_cmn_regs = phy->init_data->pcie_cmn_regs; + num_ln_regs = phy->init_data->pcie_ln_regs; + cmn_vals = phy->init_data->pcie_cmn_vals; + ln_vals = phy->init_data->pcie_ln_vals; } else if (ins->phy_type == PHY_TYPE_USB3) { - num_regs = phy->init_data->usb_regs; - vals = phy->init_data->usb_vals; + num_cmn_regs = phy->init_data->usb_cmn_regs; + num_ln_regs = phy->init_data->usb_ln_regs; + cmn_vals = phy->init_data->usb_cmn_vals; + ln_vals = phy->init_data->usb_ln_vals; } else { return -EINVAL; } + + regmap = phy->regmap_common_cdb; + for (j = 0; j < num_cmn_regs ; j++) + regmap_write(regmap, cmn_vals[j].off, cmn_vals[j].val); + for (i = 0; i < ins->num_lanes; i++) { - for (j = 0; j < num_regs ; j++) { + for (j = 0; j < num_ln_regs ; j++) { regmap = phy->regmap_lane_cdb[i + ins->mlane]; - regmap_write(regmap, vals[j].off, vals[j].val); + regmap_write(regmap, ln_vals[j].off, ln_vals[j].val); } } @@ -489,80 +569,158 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) return 0; } -static struct cdns_reg_pairs cdns_usb_regs[] = { - /* - * Write USB configuration parameters to the PHY. - * These values are specific to this specific hardware - * configuration. - */ +/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */ +static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { + {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, + {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, + {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, + {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, + {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} +}; + +/* refclk100MHz_32b_PCIe_ln_ext_ssc */ +static struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { + {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, + {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, + {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, + {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, + {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, + {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, + {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG} +}; + +/* refclk100MHz_20b_USB_cmn_pll_ext_ssc */ +static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = { + {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, + {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, + {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, + {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} +}; + +/* refclk100MHz_20b_USB_ln_ext_ssc */ +static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = { {0xFE0A, SIERRA_DET_STANDEC_A_PREG}, {0x000F, SIERRA_DET_STANDEC_B_PREG}, - {0x55A5, SIERRA_DET_STANDEC_C_PREG}, - {0x69AD, SIERRA_DET_STANDEC_D_PREG}, + {0x00A5, SIERRA_DET_STANDEC_C_PREG}, + {0x69ad, SIERRA_DET_STANDEC_D_PREG}, {0x0241, SIERRA_DET_STANDEC_E_PREG}, - {0x0110, SIERRA_PSM_LANECAL_PREG}, + {0x0010, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG}, + {0x0014, SIERRA_PSM_A0IN_TMR_PREG}, {0xCF00, SIERRA_PSM_DIAG_PREG}, {0x001F, SIERRA_PSC_TX_A0_PREG}, {0x0007, SIERRA_PSC_TX_A1_PREG}, {0x0003, SIERRA_PSC_TX_A2_PREG}, {0x0003, SIERRA_PSC_TX_A3_PREG}, {0x0FFF, SIERRA_PSC_RX_A0_PREG}, - {0x0003, SIERRA_PSC_RX_A1_PREG}, + {0x0619, SIERRA_PSC_RX_A1_PREG}, {0x0003, SIERRA_PSC_RX_A2_PREG}, {0x0001, SIERRA_PSC_RX_A3_PREG}, {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG}, {0x0406, SIERRA_PLLCTRL_GEN_D_PREG}, + {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, + {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG}, + {0x2512, SIERRA_DFE_BIASTRIM_PREG}, {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, - {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG}, - {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, - {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, + {0x873E, SIERRA_CLKPATHCTRL_TMR_PREG}, + {0x03CF, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, + {0x01CE, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, - {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, + {0x033F, SIERRA_RX_CTLE_MAINTENANCE_PREG}, {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG}, - {0x8452, SIERRA_CTLELUT_CTRL_PREG}, - {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG}, - {0x4121, SIERRA_DFE_SMP_RATESEL_PREG}, - {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG}, - {0x0330, SIERRA_TMRVAL_MODE0_PREG}, - {0x01FF, SIERRA_PICNT_MODE1_PREG}, + {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, + {0x8000, SIERRA_CREQ_SPARE_PREG}, + {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, + {0x8453, SIERRA_CTLELUT_CTRL_PREG}, + {0x4110, SIERRA_DFE_ECMP_RATESEL_PREG}, + {0x4110, SIERRA_DFE_SMP_RATESEL_PREG}, + {0x0002, SIERRA_DEQ_PHALIGN_CTRL}, + {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG}, + {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG}, + {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, + {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, + {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG}, + {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG}, + {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG}, + {0x9A8A, SIERRA_DEQ_VGATUNE_CTRL_PREG}, + {0x0014, SIERRA_DEQ_GLUT0}, + {0x0014, SIERRA_DEQ_GLUT1}, + {0x0014, SIERRA_DEQ_GLUT2}, + {0x0014, SIERRA_DEQ_GLUT3}, + {0x0014, SIERRA_DEQ_GLUT4}, + {0x0014, SIERRA_DEQ_GLUT5}, + {0x0014, SIERRA_DEQ_GLUT6}, + {0x0014, SIERRA_DEQ_GLUT7}, + {0x0014, SIERRA_DEQ_GLUT8}, + {0x0014, SIERRA_DEQ_GLUT9}, + {0x0014, SIERRA_DEQ_GLUT10}, + {0x0014, SIERRA_DEQ_GLUT11}, + {0x0014, SIERRA_DEQ_GLUT12}, + {0x0014, SIERRA_DEQ_GLUT13}, + {0x0014, SIERRA_DEQ_GLUT14}, + {0x0014, SIERRA_DEQ_GLUT15}, + {0x0014, SIERRA_DEQ_GLUT16}, + {0x0BAE, SIERRA_DEQ_ALUT0}, + {0x0AEB, SIERRA_DEQ_ALUT1}, + {0x0A28, SIERRA_DEQ_ALUT2}, + {0x0965, SIERRA_DEQ_ALUT3}, + {0x08A2, SIERRA_DEQ_ALUT4}, + {0x07DF, SIERRA_DEQ_ALUT5}, + {0x071C, SIERRA_DEQ_ALUT6}, + {0x0659, SIERRA_DEQ_ALUT7}, + {0x0596, SIERRA_DEQ_ALUT8}, + {0x0514, SIERRA_DEQ_ALUT9}, + {0x0492, SIERRA_DEQ_ALUT10}, + {0x0410, SIERRA_DEQ_ALUT11}, + {0x038E, SIERRA_DEQ_ALUT12}, + {0x030C, SIERRA_DEQ_ALUT13}, + {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG}, + {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG}, + {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, + {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, + {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG}, + {0x0033, SIERRA_DEQ_PICTRL_PREG}, + {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG}, + {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, + {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG}, {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG}, + {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG}, + {0x0005, SIERRA_LFPSDET_SUPPORT_PREG}, {0x000F, SIERRA_LFPSFILT_NS_PREG}, {0x0009, SIERRA_LFPSFILT_RD_PREG}, {0x0001, SIERRA_LFPSFILT_MP_PREG}, {0x8013, SIERRA_SDFILT_H2L_A_PREG}, - {0x0400, SIERRA_TMRVAL_MODE1_PREG}, -}; - -static struct cdns_reg_pairs cdns_pcie_regs[] = { - /* - * Write PCIe configuration parameters to the PHY. - * These values are specific to this specific hardware - * configuration. - */ - {0x891f, SIERRA_DET_STANDEC_D_PREG}, - {0x0053, SIERRA_DET_STANDEC_E_PREG}, - {0x0400, SIERRA_TMRVAL_MODE2_PREG}, - {0x0200, SIERRA_TMRVAL_MODE3_PREG}, + {0x8009, SIERRA_SDFILT_L2H_PREG}, + {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG}, + {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG}, + {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG} }; static const struct cdns_sierra_data cdns_map_sierra = { SIERRA_MACRO_ID, 0x2, 0x2, - ARRAY_SIZE(cdns_pcie_regs), - ARRAY_SIZE(cdns_usb_regs), - cdns_pcie_regs, - cdns_usb_regs + ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), + ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), + ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), + ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), + cdns_pcie_cmn_regs_ext_ssc, + cdns_pcie_ln_regs_ext_ssc, + cdns_usb_cmn_regs_ext_ssc, + cdns_usb_ln_regs_ext_ssc, }; static const struct cdns_sierra_data cdns_ti_map_sierra = { SIERRA_MACRO_ID, 0x0, 0x1, - ARRAY_SIZE(cdns_pcie_regs), - ARRAY_SIZE(cdns_usb_regs), - cdns_pcie_regs, - cdns_usb_regs + ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), + ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), + ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), + ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), + cdns_pcie_cmn_regs_ext_ssc, + cdns_pcie_ln_regs_ext_ssc, + cdns_usb_cmn_regs_ext_ssc, + cdns_usb_ln_regs_ext_ssc, }; static const struct of_device_id cdns_sierra_id_table[] = { From patchwork Wed Oct 16 11:31:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 176462 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp7233989ill; Wed, 16 Oct 2019 04:32:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqzt6JPnnacVRpcY9eoBY9grDz96T3HUl7qnF1i0bXo1QK98QPGVygLxIpdAR6rZwC7HGGVT X-Received: by 2002:a17:906:a294:: with SMTP id i20mr38580659ejz.165.1571225535517; Wed, 16 Oct 2019 04:32:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571225535; cv=none; d=google.com; s=arc-20160816; b=Ax39TzP8T9YaEhL9O03Co9EVzuSHBveNA/FY+fNhMsXtFmc0cfOh3Rx0vJYai3Zuwx oUkCl8lzHNNOETcF4/g2uCim9CkoEUw+Cp9BLUw+/077TTbWF/Hhoxh6Ijm+oULie9V4 Qy5UySZ2bZdrd4HYv4zeEHFP18d4qCFn8jMdkt1EstQFEnNd7IRsoO41B2EDoHDRrMqM K1CZnshuip6pgFaLU3TQITvWS7yLYtd5BGN1iq5OSz4eBaE3jPJSd6d2s+6kJIMJj5kK s7B5f05iq1cE01S2GXGoKNCWLylHRPSbmJkj0yjqmTI1fvfTK4r37zcPOctF/shlnBWl HFNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=NpTgzRPuWtGy7XqgqTEEYzUMhl497x1SrGIY18ty3Pk=; b=E+iuXcaPeulXcFbPSseeD9Hg4wS7h9PH/d1xtBtPW4R2w0KtrCFz5128tcjKKETQMt zZE3WNRBlD4buFJmOWfUEos7Ukp7apySAVjKI1dWP07vFkwDqsRbZ9MeouoR3jQoyBqY LyZUHYE9fWY12ydlExXRjJ9B0+JSAjxlVvizGQ2fRzI5DZa6NPPHWIb/AjUx05E2Rga4 /Gxtx69jOJyGZGTh0egeELPpUnfPGvZL+zLYEyZfCim70FYrRQE7WQk5OsmSMZY+LkJp TEppGMX4Zx+vopET0UIpiG0HL9orBqL8TpfPuaAvgOlRYbORskP6GWIsspUJQCfYcoEa IsYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=QtsBS+15; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b4si15301142edq.221.2019.10.16.04.32.15; Wed, 16 Oct 2019 04:32:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=QtsBS+15; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405058AbfJPLcL (ORCPT + 26 others); Wed, 16 Oct 2019 07:32:11 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:36998 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405036AbfJPLcJ (ORCPT ); Wed, 16 Oct 2019 07:32:09 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9GBW7wx050015; Wed, 16 Oct 2019 06:32:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571225527; bh=NpTgzRPuWtGy7XqgqTEEYzUMhl497x1SrGIY18ty3Pk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=QtsBS+151ygP8+0kDVOeXpCEWQ9sL762W4sCKe9siLMU0OGe3Rj8gRrqnwEsi7uf7 DRdhKYHPkoQYv8TrSOTvLL99OX9nMkiXbqe+d8STTmBGFmo0YuUR9245QwMYlmYT8s eYEnkQNVcsshjFBe7P8BexgkxTp9RaOlhd+dzu2g= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9GBW7sA037972 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 16 Oct 2019 06:32:07 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 16 Oct 2019 06:32:00 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 16 Oct 2019 06:32:00 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9GBVkmC097485; Wed, 16 Oct 2019 06:32:05 -0500 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Roger Quadros , Jyri Sarha CC: Anil Varughese , , Subject: [PATCH 08/13] phy: cadence: Sierra: Get reset control "array" for each link Date: Wed, 16 Oct 2019 17:01:12 +0530 Message-ID: <20191016113117.12370-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191016113117.12370-1-kishon@ti.com> References: <20191016113117.12370-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A link may have multiple lanes each with a separate reset. Get reset control "array" in order to reset all the lanes associated with the link. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index b555d4c3633b..2648a01f90b3 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -497,7 +497,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) struct phy *gphy; sp->phys[node].lnk_rst = - of_reset_control_get_exclusive_by_index(child, 0); + of_reset_control_array_get_exclusive(child); if (IS_ERR(sp->phys[node].lnk_rst)) { dev_err(dev, "failed to get reset %s\n", From patchwork Wed Oct 16 11:31:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 176465 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp7234064ill; Wed, 16 Oct 2019 04:32:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqxb/MBTHBa3bY2c7/nd3vYbIgSf7Qt7sjrx1iwPGerdKhNM0SizCaKvFylIo/Ed7BEwufqB X-Received: by 2002:aa7:c959:: with SMTP id h25mr38726352edt.216.1571225538886; Wed, 16 Oct 2019 04:32:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571225538; cv=none; d=google.com; s=arc-20160816; b=Ue5lUlIac+WfqRA4hNYIJsUG+JYiXK7PyqJGlC7uyeIrfnKtOaVQD5WIbRN+uf1neu 3Vn8k1D2Hs0ZJEvrWwiZ9J+meHeCpxw8WYKWRyHCGHszt/C9wNwx9kzJHSfeQlXu2haJ 6fO5h3IthhKFP6IwHq/gbUKby7KcVBu+e6dcyPkpl9Nt+ewVWHN8bCG2M+btAUiPANk0 PMDBBLnKAuj8qfZvjuAnXuY5IuE/oH3uZUKHHINy/6chD5v/3nuGZmqnfvxSrKNTwNEi Ihf1Rvjq+Acr/MvmRobP8y+/ufjPpUHVBx3XVi8fBjWx/6oMTByx1wHkIG36bed4mceZ Hj0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=0wNKaASInt1k8YuOc3I1egQn9FpeL+eFcyUOwrqISs4=; b=cY1VWWfe0A5pckL3UGl7HneyJIcY7i104ZGqO24SXo/c22x2cjRLJwikFtiFX7n0dZ tWKuLurtXOqM+uTymQholFEHyUl2z5lXAWH88R1Ewd3ZiHNNBK2hu9ymOL8kCuC5Foxf +zNx7wvyql99shcuDOymcARg4BQic7uaR4X0uiHi16CQ0XWcV48xiSD9qdQ5G3KYYZV3 njgZGG7oeqoXY+UyEhENNJlMbArjuFt5thMlzOW1GuVDgF8MSyfbA3DewNs0xmDT/Z3w QNSSIBRha7urq3xJsqprdi8HnJnHAtOPPTJBs2OKnPumPuzopb8kF+RNwYUA3SvAr56P y7nQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=lD4nJLSA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z6si17083687edm.316.2019.10.16.04.32.18; Wed, 16 Oct 2019 04:32:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=lD4nJLSA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405082AbfJPLcP (ORCPT + 26 others); Wed, 16 Oct 2019 07:32:15 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:50376 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405061AbfJPLcO (ORCPT ); Wed, 16 Oct 2019 07:32:14 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9GBWCi1097204; Wed, 16 Oct 2019 06:32:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571225532; bh=0wNKaASInt1k8YuOc3I1egQn9FpeL+eFcyUOwrqISs4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lD4nJLSAoj2O/iX0oyUT3qrcugpojM4Zbk/iUS6inDn9tfNBiRDPraw0nU/rkXfW4 LXJsUsk6SP23vzfc6y+FYrczhvAUABSE3uvEDLHVVvKB9XmBYxneHWrU3xSD0zeF0x VR9gEDYqYqzwAd5uSrLIU/CClwwHfrsSHPuAQGjU= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9GBWCGP114125 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 16 Oct 2019 06:32:12 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 16 Oct 2019 06:32:05 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 16 Oct 2019 06:32:12 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9GBVkmE097485; Wed, 16 Oct 2019 06:32:10 -0500 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Roger Quadros , Jyri Sarha CC: Anil Varughese , , Subject: [PATCH 10/13] phy: cadence: Sierra: Change MAX_LANES of Sierra to 16 Date: Wed, 16 Oct 2019 17:01:14 +0530 Message-ID: <20191016113117.12370-11-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191016113117.12370-1-kishon@ti.com> References: <20191016113117.12370-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Sierra SERDES IP supports upto 16 lanes (though not all of it will be enabled in a platform). Allow Sierra driver to support a maximum of upto 16 lanes. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 82f7617b2dac..dd54a0ab89b7 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -139,7 +139,7 @@ #define SIERRA_PHY_PLL_CFG 0xe #define SIERRA_MACRO_ID 0x00007364 -#define SIERRA_MAX_LANES 4 +#define SIERRA_MAX_LANES 16 #define PLL_LOCK_TIME 100000 static const struct reg_field macro_id_type = @@ -197,6 +197,7 @@ struct cdns_sierra_phy { struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; struct clk *clk; int nsubnodes; + u32 num_lanes; bool autoconf; }; @@ -233,6 +234,18 @@ static struct regmap_config cdns_sierra_lane_cdb_config[] = { SIERRA_LANE_CDB_REGMAP_CONF("1"), SIERRA_LANE_CDB_REGMAP_CONF("2"), SIERRA_LANE_CDB_REGMAP_CONF("3"), + SIERRA_LANE_CDB_REGMAP_CONF("4"), + SIERRA_LANE_CDB_REGMAP_CONF("5"), + SIERRA_LANE_CDB_REGMAP_CONF("6"), + SIERRA_LANE_CDB_REGMAP_CONF("7"), + SIERRA_LANE_CDB_REGMAP_CONF("8"), + SIERRA_LANE_CDB_REGMAP_CONF("9"), + SIERRA_LANE_CDB_REGMAP_CONF("10"), + SIERRA_LANE_CDB_REGMAP_CONF("11"), + SIERRA_LANE_CDB_REGMAP_CONF("12"), + SIERRA_LANE_CDB_REGMAP_CONF("13"), + SIERRA_LANE_CDB_REGMAP_CONF("14"), + SIERRA_LANE_CDB_REGMAP_CONF("15"), }; static struct regmap_config cdns_sierra_common_cdb_config = { @@ -546,6 +559,8 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) } } + sp->num_lanes += sp->phys[node].num_lanes; + gphy = devm_phy_create(dev, child, &ops); if (IS_ERR(gphy)) { @@ -559,6 +574,11 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) } sp->nsubnodes = node; + if (sp->num_lanes > SIERRA_MAX_LANES) { + dev_err(dev, "Invalid lane configuration\n"); + goto put_child2; + } + /* If more than one subnode, configure the PHY as multilink */ if (!sp->autoconf && sp->nsubnodes > 1) regmap_field_write(sp->phy_pll_cfg_1, 0x1); From patchwork Wed Oct 16 11:31:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 176468 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp7234282ill; Wed, 16 Oct 2019 04:32:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqxk6SZl8qyxB11SHGN6vAheTvKC7+RlBh6nJLUPnkPxju6SWKXb6+jepsJQcpfO667Ay28Y X-Received: by 2002:a17:906:c2c1:: with SMTP id ch1mr37850928ejb.321.1571225551076; Wed, 16 Oct 2019 04:32:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571225551; cv=none; d=google.com; s=arc-20160816; b=UScT1t61Uv6vXwZeoUAQab4y4zlRkY1WZjCAcG9Jrg5ewOetUTbdOIcxh2qcI9fsMa 2DMrF7rHbuPr8ST9EDgeaH+cJ3XNDXa0nYlYi3HvQ44ruIBgRO107r1u7WoUih8XxGze 2FMUx5TlMoeGdFndX95VbvX3pmOmIxWhgOdqYp216bzCnv4xsU2W8DbhF2jrw1yLCe1z 8yl02KlQ/ZGrEtHsGJwWFBhNPB0jvH3AqGpF848N5TMluuFhEP7pgSrXoUw5kFWidI2g gK+40FzZQqYjqYwW5MadBYrY+73lBeukfdLTgo8ghqj9aLYRJAetY3RCj6WWlOdDNZRg ensw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=lu2aQMjEO+OiMZpRh1hPo2mocSefRsjFC/UXdwkkxKU=; b=Hk+Melx2/dqAde8W+A0RKkTERJFxyj9yN8NINJ68Ry9rTEhof/nfP6+Pe+O6gp2eqx x1iCONsVLmeLB8Ce2ZYB6cJfQuHNEXL3zhmd+5arlTUP9sGkH5Zt3NM5fOG6V3LCl2nn hWwl247Aax28b5Op9fnxHm3JMuQ05oo68s5Qc5Fn736OwZqug98wsiPvOaWkxDNdSdZo xYFWBx8Wvrjab8v8ouJBPpVpksQ9y6T5y9vD+eFNKOCc8so9ytNGfOXNaFBRx8mGGVkn 7bSpOVGgXPtonwrSbE+IFDzMq+CQmUmHQASNXlPlUF6Kt6NLypybHKSf+fZE1+P4piA/ cBnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Oa4uQPWJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u27si15646361ejb.172.2019.10.16.04.32.30; Wed, 16 Oct 2019 04:32:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Oa4uQPWJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405117AbfJPLc2 (ORCPT + 26 others); Wed, 16 Oct 2019 07:32:28 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:50402 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405101AbfJPLcY (ORCPT ); Wed, 16 Oct 2019 07:32:24 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9GBWH6b097221; Wed, 16 Oct 2019 06:32:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571225537; bh=lu2aQMjEO+OiMZpRh1hPo2mocSefRsjFC/UXdwkkxKU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Oa4uQPWJmTFq2ojCyQJEjopnK6B85t0jI6tVV4B5+vf4MoRPRPARPt0G5XMnDLr/u XNjjPQq3kdb0J5IBqRzxBNUP26Oapmg8nBt8YIOD6l5ePR+9jaMWPGSJaEQnl1MzHI lI2ia2i9Nz8vTPu3vhNPKW4dijXK86exuXdpIgu0= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9GBWHM9114223 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 16 Oct 2019 06:32:17 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 16 Oct 2019 06:32:10 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 16 Oct 2019 06:32:10 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9GBVkmG097485; Wed, 16 Oct 2019 06:32:14 -0500 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Roger Quadros , Jyri Sarha CC: Anil Varughese , , , Rob Herring Subject: [PATCH 12/13] dt-bindings: phy: Document WIZ (SERDES wrapper) bindings Date: Wed, 16 Oct 2019 17:01:16 +0530 Message-ID: <20191016113117.12370-13-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191016113117.12370-1-kishon@ti.com> References: <20191016113117.12370-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DT binding documentation for WIZ (SERDES wrapper). WIZ is *NOT* a PHY but a wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) serdes. Cc: Rob Herring Signed-off-by: Kishon Vijay Abraham I [jsarha@ti.com: Add separate compatible for Sierra(16G) and Torrent(10G) SERDES] Signed-off-by: Jyri Sarha --- .../bindings/phy/ti,phy-j721e-wiz.txt | 95 +++++++++++++++++++ 1 file changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt -- 2.17.1 diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt new file mode 100644 index 000000000000..19b4c3e855d6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt @@ -0,0 +1,95 @@ +TI J721E WIZ (SERDES Wrapper) + +Required properties: + - compatible: Should be "ti,j721e-wiz-16g" for Sierra phy wrapper, + or "ti,j721e-wiz-10g" for Torrent phy wrapper. + - #address-cells : should be 2 to indicate the child node should use 2 cell + for address + - #size-cells: should be 2 to indicate the child node should use 2 cell for + size + - power-domains: As documented by the generic PM domain bindings in + Documentation/devicetree/bindings/power/power_domain.txt. + - clocks: clock-specifier to represent input to the WIZ required for WIZ + module to be functional + - num-lanes: Represents thenumber of lanes enabled in the SoC + Should be '2' for Sierra wrapper in J721E + Should be '4' for Torrent wrapper in J721E + - #reset-cells: As documented by the generic reset bindings in + Documentation/devicetree/bindings/reset/reset.txt + Should be '1' + - ranges: Empty ranges property to describe 1:1 translation between parent + address space and child address space + +Optional properties: +assigned-clocks and assigned-clock-parents: As documented in the generic +clock bindings in Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required subnodes: + - Clock Subnode: WIZ node should have '3' subnodes for each of the clock + selects it supports. The clock subnodes should have the following names + 1) pll0_refclk + 2) pll1_refclk + 3) refclk_dig + Each of these subnodes should clocks, clock-output-names, #clock-cells, + assigned-clocks and assigned-clock-parents. All these properties are + documented in the generic clock bindings in + Documentation/devicetree/bindings/clock/clock-bindings.txt + - SERDES Subnode: WIZ node should have '1' subnode for the SERDES + *) Sierra SERDES should follow the bindings specified in + Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt + *) Torrent SERDES should follow the bindings specified in + Documentation/devicetree/bindings/phy/phy-cadence-dp.txt + +Example: Example shows binding for SERDES_16G (Sierra SERDES with WIZ wrapper) +serdes_wiz0: wiz@5000000 { + compatible = "ti,j721e-wiz-16g"; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 292 5>; + num-lanes = <2>; + #reset-cells = <1>; + ranges; + + pll0_refclk: pll0_refclk { + clocks = <&k3_clks 292 11>, <&cmn_refclk>; + clock-output-names = "pll0_refclk"; + #clock-cells = <0>; + assigned-clocks = <&pll0_refclk>; + assigned-clock-parents = <&k3_clks 292 11>; + }; + + pll1_refclk: pll1_refclk { + clocks = <&k3_clks 292 0>, <&cmn_refclk1>; + clock-output-names = "pll1_refclk"; + #clock-cells = <0>; + assigned-clocks = <&pll1_refclk>; + assigned-clock-parents = <&k3_clks 292 0>; + }; + + refclk_dig: refclk_dig { + clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, + <&cmn_refclk>, <&cmn_refclk1>; + clock-output-names = "refclk_dig"; + #clock-cells = <0>; + assigned-clocks = <&refclk_dig>; + assigned-clock-parents = <&k3_clks 292 11>; + }; + + serdes0: serdes@5000000 { + compatible = "cdns,ti,sierra-phy-t0"; + reg-names = "serdes"; + reg = <0x00 0x5000000 0x00 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&serdes_wiz0 0>; + reset-names = "sierra_reset"; + pcie0_phy0: link@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; + }; +};