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[35.204.239.8]) by smtp.gmail.com with ESMTPSA id x2-20020a056402414200b00572cf08369asm5621928eda.23.2024.05.07.07.14.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 May 2024 07:14:45 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Tue, 07 May 2024 15:14:44 +0100 Subject: [PATCH 1/5] phy: exynos5-usbdrd: uniform order of register bit macros Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240507-samsung-usb-phy-fixes-v1-1-4ccba5afa7cc@linaro.org> References: <20240507-samsung-usb-phy-fixes-v1-0-4ccba5afa7cc@linaro.org> In-Reply-To: <20240507-samsung-usb-phy-fixes-v1-0-4ccba5afa7cc@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Krzysztof Kozlowski , Alim Akhtar , Sam Protsenko Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9?= =?utf-8?q?_Draszik?= X-Mailer: b4 0.12.4 Most of the macros are ordered high -> low, but there are some outliers. Order them all uniformly from high to low. This will allow adding additional register (field) definitions in a consistent way. While at it, also remove some extra empty lines to group register bit field definitions together with the relevant register. This makes the registers easier to distinguish visually. No functional change. Signed-off-by: André Draszik Reviewed-by: Peter Griffin --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 44 +++++++++++--------------------- 1 file changed, 15 insertions(+), 29 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 04171eed5b16..2af192c15d78 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -35,13 +35,11 @@ /* Exynos5: USB 3.0 DRD PHY registers */ #define EXYNOS5_DRD_LINKSYSTEM 0x04 - +#define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27) #define LINKSYSTEM_FLADJ_MASK (0x3f << 1) #define LINKSYSTEM_FLADJ(_x) ((_x) << 1) -#define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27) #define EXYNOS5_DRD_PHYUTMI 0x08 - #define PHYUTMI_OTGDISABLE BIT(6) #define PHYUTMI_FORCESUSPEND BIT(1) #define PHYUTMI_FORCESLEEP BIT(0) @@ -49,40 +47,31 @@ #define EXYNOS5_DRD_PHYPIPE 0x0c #define EXYNOS5_DRD_PHYCLKRST 0x10 - #define PHYCLKRST_EN_UTMISUSPEND BIT(31) - #define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) #define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23) - #define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) #define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21) - #define PHYCLKRST_SSC_EN BIT(20) #define PHYCLKRST_REF_SSP_EN BIT(19) #define PHYCLKRST_REF_CLKDIV2 BIT(18) - #define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11) #define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11) #define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x32 << 11) #define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11) #define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11) #define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11) - -#define PHYCLKRST_FSEL_UTMI_MASK (0x7 << 5) #define PHYCLKRST_FSEL_PIPE_MASK (0x7 << 8) +#define PHYCLKRST_FSEL_UTMI_MASK (0x7 << 5) #define PHYCLKRST_FSEL(_x) ((_x) << 5) #define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5) #define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5) #define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5) #define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5) - #define PHYCLKRST_RETENABLEN BIT(4) - #define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2) #define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2) #define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2) - #define PHYCLKRST_PORTRESET BIT(1) #define PHYCLKRST_COMMONONN BIT(0) @@ -100,30 +89,27 @@ #define PHYREG1_CR_ACK BIT(0) #define EXYNOS5_DRD_PHYPARAM0 0x1c - #define PHYPARAM0_REF_USE_PAD BIT(31) #define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26) #define PHYPARAM0_REF_LOSLEVEL (0x9 << 26) #define EXYNOS5_DRD_PHYPARAM1 0x20 - #define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0) #define PHYPARAM1_PCS_TXDEEMPH (0x1c) #define EXYNOS5_DRD_PHYTERM 0x24 #define EXYNOS5_DRD_PHYTEST 0x28 - #define PHYTEST_POWERDOWN_SSP BIT(3) #define PHYTEST_POWERDOWN_HSP BIT(2) #define EXYNOS5_DRD_PHYADP 0x2c #define EXYNOS5_DRD_PHYUTMICLKSEL 0x30 - #define PHYUTMICLKSEL_UTMI_CLKSEL BIT(2) #define EXYNOS5_DRD_PHYRESUME 0x34 + #define EXYNOS5_DRD_LINKPORT 0x44 /* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */ @@ -147,28 +133,28 @@ /* Exynos850: USB DRD PHY registers */ #define EXYNOS850_DRD_LINKCTRL 0x04 -#define LINKCTRL_BUS_FILTER_BYPASS(_x) ((_x) << 4) #define LINKCTRL_FORCE_QACT BIT(8) +#define LINKCTRL_BUS_FILTER_BYPASS(_x) ((_x) << 4) #define EXYNOS850_DRD_CLKRST 0x20 -#define CLKRST_LINK_SW_RST BIT(0) -#define CLKRST_PORT_RST BIT(1) #define CLKRST_PHY_SW_RST BIT(3) +#define CLKRST_PORT_RST BIT(1) +#define CLKRST_LINK_SW_RST BIT(0) #define EXYNOS850_DRD_UTMI 0x50 -#define UTMI_FORCE_SLEEP BIT(0) -#define UTMI_FORCE_SUSPEND BIT(1) -#define UTMI_DM_PULLDOWN BIT(2) -#define UTMI_DP_PULLDOWN BIT(3) -#define UTMI_FORCE_BVALID BIT(4) #define UTMI_FORCE_VBUSVALID BIT(5) +#define UTMI_FORCE_BVALID BIT(4) +#define UTMI_DP_PULLDOWN BIT(3) +#define UTMI_DM_PULLDOWN BIT(2) +#define UTMI_FORCE_SUSPEND BIT(1) +#define UTMI_FORCE_SLEEP BIT(0) #define EXYNOS850_DRD_HSP 0x54 -#define HSP_COMMONONN BIT(8) -#define HSP_EN_UTMISUSPEND BIT(9) -#define HSP_VBUSVLDEXT BIT(12) -#define HSP_VBUSVLDEXTSEL BIT(13) #define HSP_FSV_OUT_EN BIT(24) +#define HSP_VBUSVLDEXTSEL BIT(13) +#define HSP_VBUSVLDEXT BIT(12) +#define HSP_EN_UTMISUSPEND BIT(9) +#define HSP_COMMONONN BIT(8) #define EXYNOS850_DRD_HSP_TEST 0x5c #define HSP_TEST_SIDDQ BIT(24) From patchwork Tue May 7 14:14:45 2024 Content-Type: text/plain; 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[35.204.239.8]) by smtp.gmail.com with ESMTPSA id x2-20020a056402414200b00572cf08369asm5621928eda.23.2024.05.07.07.14.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 May 2024 07:14:46 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Tue, 07 May 2024 15:14:45 +0100 Subject: [PATCH 2/5] phy: exynos5-usbdrd: convert udelay() to fsleep() Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240507-samsung-usb-phy-fixes-v1-2-4ccba5afa7cc@linaro.org> References: <20240507-samsung-usb-phy-fixes-v1-0-4ccba5afa7cc@linaro.org> In-Reply-To: <20240507-samsung-usb-phy-fixes-v1-0-4ccba5afa7cc@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Krzysztof Kozlowski , Alim Akhtar , Sam Protsenko Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9?= =?utf-8?q?_Draszik?= X-Mailer: b4 0.12.4 The timers-howto recommends using usleep_range() and friends anytime waiting for >= ~10us is required. Doing so can help the timer subsystem a lot to coalesce wakeups. Additionally, fsleep() exists as a convenient wrapper so we do not have to think about which exact sleeping function is required in which case. Convert all udelay() calls in this driver to use fsleep() to follow the recommendataion. Signed-off-by: André Draszik Reviewed-by: Peter Griffin --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 2af192c15d78..1b209ab7a268 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -448,7 +448,7 @@ static int exynos5_usbdrd_phy_init(struct phy *phy) writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); - udelay(10); + fsleep(10); reg &= ~PHYCLKRST_PORTRESET; writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); @@ -779,11 +779,11 @@ static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST); /* Finish PHY reset (POR=low) */ - udelay(10); /* required before doing POR=low */ + fsleep(10); /* required before doing POR=low */ reg = readl(regs_base + EXYNOS850_DRD_CLKRST); reg &= ~(CLKRST_PHY_SW_RST | CLKRST_PORT_RST); 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[35.204.239.8]) by smtp.gmail.com with ESMTPSA id x2-20020a056402414200b00572cf08369asm5621928eda.23.2024.05.07.07.14.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 May 2024 07:14:46 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Tue, 07 May 2024 15:14:46 +0100 Subject: [PATCH 3/5] phy: exynos5-usbdrd: make phy_isol() take a bool for clarity Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240507-samsung-usb-phy-fixes-v1-3-4ccba5afa7cc@linaro.org> References: <20240507-samsung-usb-phy-fixes-v1-0-4ccba5afa7cc@linaro.org> In-Reply-To: <20240507-samsung-usb-phy-fixes-v1-0-4ccba5afa7cc@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Krzysztof Kozlowski , Alim Akhtar , Sam Protsenko Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9?= =?utf-8?q?_Draszik?= X-Mailer: b4 0.12.4 on / not on is just a boolean flag and is a bit misleading as currently on==1 means to turn off the power, and on==0 to turn power on. Rename the flag and make it a bool to avoid confusion of future readers of this code. No functional change. While at it, fix a whitespace issue in nearby comment. No functional change. Signed-off-by: André Draszik Reviewed-by: Peter Griffin --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 1b209ab7a268..ed4898741c99 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -173,7 +173,7 @@ struct exynos5_usbdrd_phy; struct exynos5_usbdrd_phy_config { u32 id; - void (*phy_isol)(struct phy_usb_instance *inst, u32 on); + void (*phy_isol)(struct phy_usb_instance *inst, bool isolate); void (*phy_init)(struct exynos5_usbdrd_phy *phy_drd); unsigned int (*set_refclk)(struct phy_usb_instance *inst); }; @@ -273,14 +273,14 @@ static unsigned int exynos5_rate_to_clk(unsigned long rate, u32 *reg) } static void exynos5_usbdrd_phy_isol(struct phy_usb_instance *inst, - unsigned int on) + bool isolate) { unsigned int val; if (!inst->reg_pmu) return; - val = on ? 0 : EXYNOS4_PHY_ENABLE; + val = isolate ? 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[35.204.239.8]) by smtp.gmail.com with ESMTPSA id x2-20020a056402414200b00572cf08369asm5621928eda.23.2024.05.07.07.14.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 May 2024 07:14:47 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Tue, 07 May 2024 15:14:47 +0100 Subject: [PATCH 4/5] phy: exynos5-usbdrd: fix definition of EXYNOS5_FSEL_26MHZ Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240507-samsung-usb-phy-fixes-v1-4-4ccba5afa7cc@linaro.org> References: <20240507-samsung-usb-phy-fixes-v1-0-4ccba5afa7cc@linaro.org> In-Reply-To: <20240507-samsung-usb-phy-fixes-v1-0-4ccba5afa7cc@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Krzysztof Kozlowski , Alim Akhtar , Sam Protsenko Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9?= =?utf-8?q?_Draszik?= X-Mailer: b4 0.12.4 Using 0x82 seems odd, where everything else is just a sequence. On E850, this macro isn't used (as a register value), only to assign its value to the 'extrefclk' variable, which is otherwise unused on that platform. Older platforms don't appear to support 26MHz in the first place (since this macro was added for E850). Furthermore, the downstream driver uses 0x82 to denote USBPHY_REFCLK_DIFF_26MHZ (whatever that means exactly), but for all the other values we match downstream's non-DIFF macros. Update to avoid confusion. No functional change intended. Signed-off-by: André Draszik Reviewed-by: Peter Griffin --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index ed4898741c99..1da7a4881f72 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -30,7 +30,7 @@ #define EXYNOS5_FSEL_19MHZ2 0x3 #define EXYNOS5_FSEL_20MHZ 0x4 #define EXYNOS5_FSEL_24MHZ 0x5 -#define EXYNOS5_FSEL_26MHZ 0x82 +#define EXYNOS5_FSEL_26MHZ 0x6 #define EXYNOS5_FSEL_50MHZ 0x7 /* Exynos5: USB 3.0 DRD PHY registers */ From patchwork Tue May 7 14:14:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Draszik?= X-Patchwork-Id: 795670 Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71BE416F0DC for ; Tue, 7 May 2024 14:14:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715091291; cv=none; b=lkFlO7+Xtxuocr2ABY2jCahcz9kOAvmV+rlwkNHTmKhVTidVu+3M6Gz3aqD4EqarIdRyHxFuwk2c8bLjEVItWYK9mmlIU3Zd5AGtnoAzAQYOe5it0E1XBGD88rEOuhitINgwGljXwaAVVVwiOXgamdzykl1eccjddIw/aPGewpo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715091291; c=relaxed/simple; bh=nNkzepDc1fooDRMrZKnyw8mRCNAwIUztgx5zJ3NkPpA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pCNi7rjUajYV4O0MHdz0cs4TI/zSfYo8oalq/EVNQhZ/3QtQigW6xKyLo1EqGBycFm4QA7sqvGdvj2rPUy9ZcTU5L3oWFd71SP9TK+ZqtM6wOzCjWG+3xCJl5IoqAqXOkXeSr7K6nE0g1qbyo5mapLx4Z8GH1DUMs5r3zvDtmpI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=rwz6PqYh; arc=none smtp.client-ip=209.85.208.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="rwz6PqYh" Received: by mail-ed1-f47.google.com with SMTP id 4fb4d7f45d1cf-572c65cea55so5053060a12.0 for ; Tue, 07 May 2024 07:14:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715091288; x=1715696088; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2AhGxPfO0jxLeMCNC4W84i2OQnqDzy87o4JACQM4lhg=; b=rwz6PqYh12EfdzpbqGaIhigcNlzEMv20hALD5YwidYNpOkQ3mZFfYllao27HnUysO2 vD+jZIm8N6iESTx92EzUgXnsFqlzTOzrpIYHCIDsIGUzppEOnfJ4BBDniDzEW5invIfb we7pa6HsMUsQ6WQRl9zi4WJ95rkFjxLitmNVoRCkeJxjJrFBLDbWG9UeUo0DYBnFTfh6 tukubdeWu9zbAfVhJfV3+ZqvhXuimZWzPknW33ThWF5zVWP7qVunTF9+Ucb2/o9J/e+G HXV5By8Mp5E1KaT2m8w+60jow6Gc81pF3Jjr/11Be2ScV3cGTHNAU7b6Ryi9roAN90eq fQLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715091288; x=1715696088; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2AhGxPfO0jxLeMCNC4W84i2OQnqDzy87o4JACQM4lhg=; b=UWacFqKPOOMGStx9UMGfl55CTtHpIsna6iXj3Z+siTkEF/qYHi6idW4WRHDA2W9/aQ 4aQ6X3mHAaOZDsT5fFx8hvXpwT/rUsSf+p5xza9Tc3j2y9y2TQIPHtEchq5LypCGa5ee ABVji4MTZlsgAmG4D6zllvoBy2hY80L/V9jZUYvGOXAAsr1sqDdG3oYfxrWVhIuIYyiB RwJz7akgX5K51EBv1u0eJOV4qCCGnVG5xNB96TRkBiFlYI5h2LpFzsalRmR53z+K8qn2 J0L+xcPS1MeqLG078plQdKHI0kmYqrP1O4b2t1i0yl8rjbr0evG1vfl69w1vhlvZ7Mt2 ZgvQ== X-Forwarded-Encrypted: i=1; AJvYcCWivwkDANlH34sDlk3dafitLEm7o5xIW7DwJkxknbn+owrOe7RP6fpB/zkZDWcgmig/H96joRK0jie9hRJpI//XlzkS4sRLrm0UpUyj/N5l4cU= X-Gm-Message-State: AOJu0YyyD07afIBaUHFE937hHTc2Sn4hRFtaO9qUm8vGm8MvvSymGsk7 e//WuDlV58KbrijJpIphXO/xIWISE0FCemWM4YylPB6oF8agIg/zmNStuuRTj2HQ7Zs7dtpF4WY ul39NeA== X-Google-Smtp-Source: AGHT+IF93U5EbjSwxazXGCgRUoQpkJwYIG6vkvVms1C680kr/QzgHDatBvsRnvscl1lkUzBabOX3fA== X-Received: by 2002:a50:f683:0:b0:572:a158:8a7b with SMTP id d3-20020a50f683000000b00572a1588a7bmr2479836edn.8.1715091287917; Tue, 07 May 2024 07:14:47 -0700 (PDT) Received: from puffmais.c.googlers.com (8.239.204.35.bc.googleusercontent.com. [35.204.239.8]) by smtp.gmail.com with ESMTPSA id x2-20020a056402414200b00572cf08369asm5621928eda.23.2024.05.07.07.14.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 May 2024 07:14:47 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Tue, 07 May 2024 15:14:48 +0100 Subject: [PATCH 5/5] phy: exynos5-usbdrd: set ref clk freq in exynos850_usbdrd_utmi_init() Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240507-samsung-usb-phy-fixes-v1-5-4ccba5afa7cc@linaro.org> References: <20240507-samsung-usb-phy-fixes-v1-0-4ccba5afa7cc@linaro.org> In-Reply-To: <20240507-samsung-usb-phy-fixes-v1-0-4ccba5afa7cc@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Krzysztof Kozlowski , Alim Akhtar , Sam Protsenko Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9?= =?utf-8?q?_Draszik?= X-Mailer: b4 0.12.4 While commit 255ec3879dd4 ("phy: exynos5-usbdrd: Add 26MHz ref clk support") correctly states that CLKRSTCTRL[7:5] doesn't need to be set on modern Exynos platforms, SSPPLLCTL[2:0] should be programmed with the frequency of the reference clock for the USB2.0 phy instead. I stumbled across this while adding support for the Google Tensor gs101, but this should apply to E850 just the same. Do so. Fixes: 691525074db9 ("phy: exynos5-usbdrd: Add Exynos850 support") Signed-off-by: André Draszik Reviewed-by: Peter Griffin --- Feel free to drop the Fixes: if you think that is unwarranted here. v2: add missing bitfield.h include (seems this is implied on some platforms, but not on others) --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 1da7a4881f72..15be966b50ae 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -8,6 +8,7 @@ * Author: Vivek Gautam */ +#include #include #include #include @@ -141,6 +142,9 @@ #define CLKRST_PORT_RST BIT(1) #define CLKRST_LINK_SW_RST BIT(0) +#define EXYNOS850_DRD_SSPPLLCTL 0x30 +#define SSPPLLCTL_FSEL GENMASK(2, 0) + #define EXYNOS850_DRD_UTMI 0x50 #define UTMI_FORCE_VBUSVALID BIT(5) #define UTMI_FORCE_BVALID BIT(4) @@ -773,6 +777,31 @@ static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) reg |= HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL; writel(reg, regs_base + EXYNOS850_DRD_HSP); + reg = readl(regs_base + EXYNOS850_DRD_SSPPLLCTL); + reg &= ~SSPPLLCTL_FSEL; + switch (phy_drd->extrefclk) { + case EXYNOS5_FSEL_50MHZ: + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 7); + break; + case EXYNOS5_FSEL_26MHZ: + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 6); + break; + case EXYNOS5_FSEL_24MHZ: + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 2); + break; + case EXYNOS5_FSEL_20MHZ: + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 1); + break; + case EXYNOS5_FSEL_19MHZ2: + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 0); + break; + default: + dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n", + phy_drd->extrefclk); + break; + } + writel(reg, regs_base + EXYNOS850_DRD_SSPPLLCTL); + /* Power up PHY analog blocks */ reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST); reg &= ~HSP_TEST_SIDDQ;