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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF00017099.mail.protection.outlook.com (10.167.18.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7544.18 via Frontend Transport; Tue, 7 May 2024 07:15:53 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 7 May 2024 02:15:49 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH 01/11] cpufreq: amd-pstate: optimiza the initial frequency values verification Date: Tue, 7 May 2024 15:15:17 +0800 Message-ID: <0049ad44052b051cf57d1059bf71b7ce227a5f21.1715065568.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017099:EE_|PH7PR12MB7793:EE_ X-MS-Office365-Filtering-Correlation-Id: b9af58c0-607e-42a4-a09c-08dc6e65880b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|1800799015|36860700004|376005|82310400017; X-Microsoft-Antispam-Message-Info: 97S6plXnCR5DUXT8F3zJnbufV3Zu+CUmPX2FrMOWnwuGhN5UCSLjLsmKamP3TLHlF0yGI9OwSOXAZ2a0hj3nRj1lHFbJtvWSIxYThzICNu9v4jyHduwz3zO/E4KimnY7hZKBvruw8KBxhDisW9STkV9vNp1NXjGIDfbt5sgeuwASNFCrTB5doHw5Y7ZXhj4OaiBMj8RRCjUzB59afmLb6PRtJuEtWSvfJ2xdyaoSm71SfYlXU4VL+zIzMQs+OtvGNlEL40iss3SgWkDmD9EmxI0MMj89hlVeO36nCBAddpDav17pslS04y9uPyhHIh851rivixkni2MCd3/u+exF0BATAvBdn8Kk0f2YNiGiLtnOeJbS4K+utpnS1wqFTyxyxWn7taDsvrEqV54sjkbdJqdJIRZpNnh1wmuhw/02IeWpSzf6FDVTPCfdZ94LPZCtQnCnFpsQNaSdcfR1SJzkE7sHDL2ubzCouDJZNGXCtBxbrBUXhXrq3vzYvpYKIVggK17bG3oHF8+JXRTPMOhy/+6LrAtiQ+KWONEL/0wYHoZLv6bdMBlBmOp+38Y2Z1EiXbqZAGQbobIbCHxUqu5vX6r2V4+XLIKa/CjFafW42cPm/E4zl0oAKWTy//O3EhRoNdolX5vYG/bt4XV5b+y/xYS0tRMUMIbvPjGDL43fGpXkffg3gc/gp+VnQcpQpHfXbQfOLuzgLvnVqg5n3DQ77qNFeMVnADY6PkbqTLSpecmwlLX+0XZ3xcVeGepdWgaHuPN0acoza8hxG3/GJkNt0/oEiLPJAdbbS9SnYpKYl3j3wiH7KWFZWg9EOsk3MJdYr85/pzd4bdAXxE5sbHgwWpCZxPk0nxnCijEeQ5e2jMkp5jCdSB2NEMmd5q6YIaRHQsfUPWrpDCPU+94vA5Ngnvq+5JpE+P1RhtuBSoCX8Gud9Rc+V3L7ZFZhyVJEBElXyOcn/KZnwDOPn7OVncgIujpgiQJp9bRVvvl4voUYxrPx47LBx/XFko6D/1OCbHBYLRzDNOCGUvCEmyvvxjRceQst8xN+AIApKjKR00IXcUhuQ+hH3hwVV3IOh1qN04NO4U5mHJhw7JEtZ74UYx59hPIz/foS1xCZxdwBNZkLUPOxiVArAD1L0ZcFyc/URM9hIcpSvU2ROqtjM0AUEc+UcFeyPob7iKQ4wuHAV0R5O4prsH8rF5LV6qqnNE2vnByByIWVF361gU3UZb9HVNO8bHbJM0J6S0Luf9MbhUVjdBZlQRfnRMm1kYCXcCKisRsEfmdwjDBtFhDyKdAiZRovk0DTHo+jJB/OnuYaZ1gqxqJkf1FU9ApI8KM/Ktd+Dn0GDHmkvJKED4ehkaKPTkQpW39V8ZsauW46CEPH8Tib2C2eV3UA2zzHd3xlLhBov2po X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(1800799015)(36860700004)(376005)(82310400017); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 May 2024 07:15:53.2202 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b9af58c0-607e-42a4-a09c-08dc6e65880b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017099.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7793 To enhance the debugging capability of the driver loading failure for broken CPPC ACPI tables, we can optimize the expression by moving the verification of `min_freq`, `nominal_freq`, and other dependency values to the `amd_pstate_init_freq()` function where they are initialized. If any of these values are incorrect, the `amd-pstate` driver will not be registered. By ensuring that these values are correct before they are used, it will facilitate the debugging process when encountering driver loading failures due to faulty CPPC ACPI tables from BIOS Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 35 ++++++++++++++++++----------------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 2db095867d03..be7f2d3c86b6 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -873,6 +873,24 @@ static int amd_pstate_init_freq(struct amd_cpudata *cpudata) WRITE_ONCE(cpudata->nominal_freq, nominal_freq); WRITE_ONCE(cpudata->max_freq, max_freq); + /** + * Below values need to be initialized correctly, otherwise driver will be failed to load + * max_freq is calculated accoreding to (nominal_freq * highest_perf)/nominal_perf + * lowest_nonlinear_freq is a value between [min_freq, nominal_freq] + * Check _CPC in ACPI table ojbects if any values are incorrect + */ + if (min_freq <= 0 || max_freq <= 0 || nominal_freq <= 0 || min_freq > max_freq) { + pr_err("min_freq(%d) or max_freq(%d) or nominal_freq(%d) value is incorrect\n", + min_freq, max_freq, nominal_freq); + return -EINVAL; + } + + if (lowest_nonlinear_freq <= min_freq || lowest_nonlinear_freq > nominal_freq * 1000) { + pr_err("lowest_nonlinear_freq(%d) value is out of range [min_freq(%d), nominal_freq(%d)]\n", + lowest_nonlinear_freq, min_freq, nominal_freq * 1000); + return -EINVAL; + } + return 0; } @@ -911,15 +929,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) max_freq = READ_ONCE(cpudata->max_freq); nominal_freq = READ_ONCE(cpudata->nominal_freq); - if (min_freq <= 0 || max_freq <= 0 || - nominal_freq <= 0 || min_freq > max_freq) { - dev_err(dev, - "min_freq(%d) or max_freq(%d) or nominal_freq (%d) value is incorrect, check _CPC in ACPI tables\n", - min_freq, max_freq, nominal_freq); - ret = -EINVAL; - goto free_cpudata1; - } - policy->cpuinfo.transition_latency = amd_pstate_get_transition_latency(policy->cpu); policy->transition_delay_us = amd_pstate_get_transition_delay_us(policy->cpu); @@ -1372,14 +1381,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) min_freq = READ_ONCE(cpudata->min_freq); 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Tue, 7 May 2024 02:15:52 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH 02/11] cpufreq: amd-pstate: show CPPC debug message if CPPC is not supported Date: Tue, 7 May 2024 15:15:18 +0800 Message-ID: <4b4a1a6b30a2dc6c95e550c62b230bc3788af415.1715065568.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709D:EE_|LV8PR12MB9264:EE_ X-MS-Office365-Filtering-Correlation-Id: 124674fc-ce6d-4384-2095-08dc6e6589a2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|82310400017|1800799015|36860700004|376005; X-Microsoft-Antispam-Message-Info: qBZWZYMb4KAWYN56vz62KhXQXqaUSYU+nZKjq+txccKRtcRpC3SW5Lse+2DKXBqumC2tIIHvqjjvOMx4MG9AuE107pTunejSc6ks1ujUZAMOkp9LwTtXbpgmbXwDICNGZrGXMGhY5VZNFtECt/MxfU/DbGGn0KcIx3TL3L2L7VFUWmVVPxwKnfYkPLh4G5x8rHnzq+j1PHYZhSwVIHWUtslinHtS/2QQLUXx7Qy2Kj9WA3u7VFqNJKYNk2PAu0fQqPmacQqv9V1qbKlT85qaLTkQRTO/FXdyWVMkEEpnopwj/ZEkwO2lgXYc59ry4Z0LQfRO5d1CCu+gUfCEGtT+uNYd5aqmOunsomFoWuEiul6WW4cjLIpZY5Q87/GYgsB9Ylec3f45ScrkI3kq2tvtKcCrrNBsBDkrPVKFPmgjmloc9PvhanDtUQxuDDp58VgJn3agxrwxp9EvzYTN6vFqH+nVOQGY7VegI8UlYJM2HJ6uoiyNdl0OI57cXqHNON+0EvIUInGpHggiNFAGOJb4JvrSyk71OVmLnrXlBvUBJG6i2eXNCnaFF8i04c1UbkKttYKVVgnYG0IFDnsVYGAkjRg5EqhCCZfFKLUwdBR8hvHo+jLa9Z2F8LsPFFlvQjKq37/ljNwoPioBg06lVGPdJ3PW/R5aanffi3sd/NFSFby73feYjEGNJkUkL7VkRhpkzvK3CDhLWOoEarBIyt7X69vwW7EsvZNQZkObjwPuTtUiOoOfc7W3FF70MVlWclJ9RPcJebDiVjmPyDVRVwhVm9AZh7rlNgNuVY3FA0NJhCyp30gz57IF2vkp+B9Fw/mpb2t9iJle4femoyyGZoT+wyNR24XtJq+PaoeXH5DM5dvwjxg4okQPsKArr6TXaj9xtxwOGar+pJYB3wHf5KLvvgupA+f3f6ctGCB0KG7rUt+2aG6xrhU3DAff2E/ovia6f2dCs0tOTTVmbcMntEWx15jPqhuDICAbaLyafxA4N4/BhNbEo4Y0ZYchThLfeBcBjC3Wgjyc1IDUKBjWvQzSWDx+o1xyVYPVcTZ0bZg+/zQgVu0RqhNwU7jsOypiaC5Z1qq2xJ1ODrccFtloX7kN05uHpS7yKpvN0mMhlfJX75WAozxKhBHJCahYEtMWvsMq+ecVUx5pSWZdaVj/H8OFW+ImEX4AEBMjt9E7HQau4wWXaDOL7UljWqIupEA5VyYTVztZKLDoYSa1yg2qOyG5QBdgpKHI8gLHuBFeQ0evJaVIp/9vch0X3yw2NonJxnNh7oKYRhleqMk77vmjlu4VGmJEOFygg8KlBLquVnYcKNs7BY3K0u/ChFOwEV/MzmxQ X-Forefront-Antispam-Report: CIP:165.204.84.17; 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And the warning message will not be showed if CPPC is not supported. It will also print debug message if the CPU has no CPPC support that helps to debug the driver loading failure issue. Closes: https://lore.kernel.org/linux-pm/CYYPR12MB8655D32EA18574C9497E888A9C122@CYYPR12MB8655.namprd12.prod.outlook.com/T/#t Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index be7f2d3c86b6..cb766c061c86 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1687,6 +1687,20 @@ static int __init amd_pstate_set_driver(int mode_idx) return -EINVAL; } +/** + * CPPC function is not supported for family ID 17H with model_ID ranging from 0x10 to 0x2F. + * show the debug message that helps to check if the CPU has CPPC support for loading issue. + */ +static bool amd_cppc_supported(void) +{ + if ((boot_cpu_data.x86 == 0x17) && (boot_cpu_data.x86_model < 0x30)) { + pr_debug_once("CPPC feature is not supported by the processor\n"); + return false; + } + + return true; +} + static int __init amd_pstate_init(void) { struct device *dev_root; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(1800799015)(36860700004)(376005)(82310400017); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 May 2024 07:15:59.6577 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7095868-004d-49a3-4b81-08dc6e658be4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017099.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8476 If CPPC feature is supported by the CPU however the CPUID flag bit is not set by SBIOS, the `amd_pstate` will be failed to load while system booting. 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" + "Please enable it if your BIOS has the CPPC option.\n"); + return false; + } + return true; } From patchwork Tue May 7 07:15:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 795431 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2081.outbound.protection.outlook.com [40.107.244.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 494A813BAF1; Tue, 7 May 2024 07:16:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.244.81 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715066171; cv=fail; b=YyO4F8C3UBqfYaqNxDwmKdzcDQr7O/xxEhhVKs9V8T3z6hnwkw03mmR31w3Nq64QpDcJclk9mxkShp/JwvJipHwLy4eggCoAjgPMgs635XmQ7E1ulOR21pIF0n+pq6bAg7kdQT7MvH1EudlWKnXEVvDuoj7SG+pTY9JB5JWhxpE= ARC-Message-Signature: i=2; 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Rebooting will ensure that the system properly applies the changes and allows for a seamless transition between the drivers. Reported-by : Reported-by: Artem S. Tashkinov Closes: https://bugzilla.kernel.org/show_bug.cgi?id=215801 Signed-off-by: Perry Yuan --- Documentation/admin-guide/pm/amd-pstate.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 1e0d101b020a..2695feec1baa 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -299,6 +299,10 @@ module which supports the new AMD P-States mechanism on most of the future AMD platforms. The AMD P-States mechanism is the more performance and energy efficiency frequency management method on AMD processors. +When users attempt to switch from the acpi-cpufreq driver to the amd-pstate driver's working mode, +it is recommended to reboot the system. This is to ensure that any low-level power management +control states are properly switched to pstate control. By rebooting, the firmware can initialize +with optimal power states, reducing the likelihood of unexpected issues. ``amd-pstate`` Driver Operation Modes ====================================== From patchwork Tue May 7 07:15:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 795656 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2087.outbound.protection.outlook.com [40.107.223.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF37413CA8D; Tue, 7 May 2024 07:16:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.223.87 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715066176; cv=fail; b=d0Sj+DpqVkVZDb1YY0FVISPiL1tOsRT4xChdvQHYT5LAq4+F2pX0boZ5TyESMN041Tp1EmtAd8Wy+nM+6HK+NkdR9Jca9NTsQNfjrFyYPwnKGLQDuW8181pYX6ZxX25uDNbYUtySwcp7LGwzhEi9cS8bBrl516n8hXSTFtM2iL8= ARC-Message-Signature: i=2; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(376005)(82310400017)(36860700004)(1800799015); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 May 2024 07:16:09.6843 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2eb1dbcb-1ffc-4a10-dc5a-08dc6e6591db X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017098.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7543 To address issues with the loading of the amd-pstate driver on certain platforms, It needs to enable dynamic debugging to capture debug messages during the driver loading process. By adding "amd_pstate.dyndbg=+p cppc_acpi.dyndbg=+p loglevel=4 debug amd_pstate=active" to the kernel command line, driver debug logging is enabled. Signed-off-by: Perry Yuan --- Documentation/admin-guide/pm/amd-pstate.rst | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 2695feec1baa..230e236796f7 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -476,6 +476,19 @@ operations for the new ``amd-pstate`` module with this tool. :: Diagnostics and Tuning ======================= +Debugging AMD P-State Driver Loading Issues +------------------------------------------ + +On some platforms, there may be issues with the loading of the amd-pstate driver. +To capture debug messages for issue analysis, users can add below parameter, +"amd_pstate.dyndbg=+p cppc_acpi.dyndbg=+p loglevel=4 debug amd_pstate=active" +to the kernel command line. This will enable dynamic debugging and allow better +analysis and troubleshooting of the driver loading process. + +Please note that adding this parameter will only enable debug logging during the +driver loading phase and may affect system behavior. Use this option with caution +and only for debugging purposes. + Trace Events -------------- From patchwork Tue May 7 07:15:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 795430 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2068.outbound.protection.outlook.com [40.107.243.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F5C113CA93; Tue, 7 May 2024 07:16:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.243.68 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715066177; cv=fail; b=d4IduL4P1Y5dHswa7An1StDU2e836j4vh0XQueUdXpZMRLdtNpgfRQfY4B89XkS4W1GJ6PgsPMKx51JKEcwtB1QOcKWmqZDR/YUKOxv+IfnLEXWzB496LkoHSug6lMOUxzslBS03kibQs3hgWPyZ4K2LoHKBIAQayeH4Fja0f3k= ARC-Message-Signature: i=2; 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Reviewed-by: Mario Limonciello Signed-off-by: Perry Yuan --- Documentation/admin-guide/pm/amd-pstate.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 230e236796f7..9fc924930595 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -410,7 +410,7 @@ control its functionality at the system level. They are located in the ``/sys/devices/system/cpu/amd_pstate/`` directory and affect all CPUs. ``status`` - Operation mode of the driver: "active", "passive" or "disable". + Operation mode of the driver: "active", "passive", "guided" or "disable". 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The switch to cpu_feature_enabled() ensures compatibility with the latest CPU feature detection mechanisms and improves code maintainability. Suggested-by: Borislav Petkov (AMD) Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index e94b55a7bb59..7145248b38ec 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -124,7 +124,7 @@ static int __init dmi_matched_7k62_bios_bug(const struct dmi_system_id *dmi) * broken BIOS lack of nominal_freq and lowest_freq capabilities * definition in ACPI tables */ - if (boot_cpu_has(X86_FEATURE_ZEN2)) { + if (cpu_feature_enabled(X86_FEATURE_ZEN2)) { quirks = dmi->driver_data; pr_info("Overriding nominal and lowest frequencies for %s\n", dmi->ident); return 1; @@ -166,7 +166,7 @@ static s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) u64 epp; int ret; - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { if (!cppc_req_cached) { epp = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &cppc_req_cached); @@ -219,7 +219,7 @@ static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp) int ret; struct cppc_perf_ctrls perf_ctrls; - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { u64 value = READ_ONCE(cpudata->cppc_req_cached); value &= ~GENMASK_ULL(31, 24); @@ -705,7 +705,7 @@ static int amd_pstate_get_highest_perf(int cpu, u32 *highest_perf) { int ret; - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { u64 cap1; ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); @@ -941,7 +941,7 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) /* It will be updated by governor */ policy->cur = policy->cpuinfo.min_freq; - if (boot_cpu_has(X86_FEATURE_CPPC)) + if (cpu_feature_enabled(X86_FEATURE_CPPC)) policy->fast_switch_possible = true; ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], @@ -1174,7 +1174,7 @@ static int amd_pstate_change_mode_without_dvr_change(int mode) cppc_state = mode; - if (boot_cpu_has(X86_FEATURE_CPPC) || cppc_state == AMD_PSTATE_ACTIVE) + if (cpu_feature_enabled(X86_FEATURE_CPPC) || cppc_state == AMD_PSTATE_ACTIVE) return 0; for_each_present_cpu(cpu) { @@ -1404,7 +1404,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) else policy->policy = CPUFREQ_POLICY_POWERSAVE; - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); if (ret) return ret; @@ -1487,7 +1487,7 @@ static void amd_pstate_epp_update_limit(struct cpufreq_policy *policy) epp = 0; /* Set initial EPP value */ - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { value &= ~GENMASK_ULL(31, 24); value |= (u64)epp << 24; } @@ -1526,7 +1526,7 @@ static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) value = READ_ONCE(cpudata->cppc_req_cached); max_perf = READ_ONCE(cpudata->highest_perf); - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); } else { perf_ctrls.max_perf = max_perf; @@ -1560,7 +1560,7 @@ static void amd_pstate_epp_offline(struct cpufreq_policy *policy) value = READ_ONCE(cpudata->cppc_req_cached); mutex_lock(&amd_pstate_limits_lock); - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { cpudata->epp_policy = CPUFREQ_POLICY_UNKNOWN; /* Set max perf same as min perf */ @@ -1748,7 +1748,7 @@ static int __init amd_pstate_init(void) */ if (amd_pstate_acpi_pm_profile_undefined() || amd_pstate_acpi_pm_profile_server() || - !boot_cpu_has(X86_FEATURE_CPPC)) { + !cpu_feature_enabled(X86_FEATURE_CPPC)) { pr_info("driver load is disabled, boot with specific mode to enable this\n"); return -ENODEV; } @@ -1767,7 +1767,7 @@ static int __init amd_pstate_init(void) } /* capability check */ - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { pr_debug("AMD CPPC MSR based functionality is supported\n"); if (cppc_state != AMD_PSTATE_ACTIVE) current_pstate_driver->adjust_perf = amd_pstate_adjust_perf; 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For better utilization of feature words and help to identify core type, X86_FEATURE_HETERO_CORE_TOPOLOGY is added as a few scattered feature bits. Link: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf PDF p274 Signed-off-by: Perry Yuan --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 3c7434329661..39a92338c015 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -470,6 +470,7 @@ #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* "" BHI_DIS_S HW control available */ #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* "" BHI_DIS_S HW control enabled */ #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* "" Clear branch history at vmexit using SW loop */ +#define X86_FEATURE_HETERO_CORE_TOPOLOGY (21*32+ 5) /* "" Heterogeneous Core Topology */ /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index af5aa2c754c2..9e237a3daf7e 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -51,6 +51,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 }, + { X86_FEATURE_HETERO_CORE_TOPOLOGY, CPUID_EAX, 30, 0x80000026, 0 }, { 0, 0, 0, 0, 0 } }; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0001709A.mail.protection.outlook.com (10.167.18.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7544.18 via Frontend Transport; Tue, 7 May 2024 07:16:19 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 7 May 2024 02:16:15 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH 09/11] cpufreq: amd-pstate: implement heterogeneous core topology for highest performance initialization Date: Tue, 7 May 2024 15:15:25 +0800 Message-ID: <731a28ea8dda4ca1db64f673c87770de4646290b.1715065568.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709A:EE_|SJ2PR12MB8158:EE_ X-MS-Office365-Filtering-Correlation-Id: 496c1030-cbd6-48c9-8393-08dc6e6597b9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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There are two type cores designed including performance core and efficiency Core. each core type has different highest performance value and highest frequency initialized by power firmware, `amd_pstate` driver need to identify the core types and set correct highest perf value. X86_FEATURE_HETERO_CORE_TOPOLOGY is used to identify whether the processor support heterogeneous core type by reading CPUID leaf Fn_0x80000026_EAX and bit 30. if the bit is set as one, then amd_pstate driver will check EBX 30:28 bits to get the core type. Value Description: 0h Performance Core. 1h Efficiency Core. https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf PDF p274 Signed-off-by: Perry Yuan --- arch/x86/include/asm/processor.h | 2 ++ arch/x86/kernel/cpu/amd.c | 19 ++++++++++ drivers/cpufreq/amd-pstate.c | 62 ++++++++++++++++++++++++-------- include/linux/amd-pstate.h | 8 +++++ 4 files changed, 77 insertions(+), 14 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 811548f131f4..30d1900bb7e0 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -683,10 +683,12 @@ static inline u32 per_cpu_l2c_id(unsigned int cpu) extern u32 amd_get_highest_perf(void); extern void amd_clear_divider(void); extern void amd_check_microcode(void); +extern int amd_get_this_core_type(void); #else static inline u32 amd_get_highest_perf(void) { return 0; } static inline void amd_clear_divider(void) { } static inline void amd_check_microcode(void) { } +static inline int amd_get_this_core_type(void) { } #endif extern unsigned long arch_align_stack(unsigned long sp); diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 307302af0aee..67966bdcde65 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1219,3 +1219,22 @@ void noinstr amd_clear_divider(void) :: "a" (0), "d" (0), "r" (1)); } EXPORT_SYMBOL_GPL(amd_clear_divider); + +#define X86_CPU_TYPE_ID_SHIFT 28 + +/** + * amd_get_this_core_type - Get the type of this heterogeneous CPU + * + * Returns the CPU type [31:28] (i.e., performance or efficient) of + * a CPU in the processor. + * If the processor has no core type support, returns -1. + */ + +int amd_get_this_core_type(void) +{ + if (!cpu_feature_enabled(X86_FEATURE_HETERO_CORE_TOPOLOGY)) + return -1; + + return cpuid_ebx(0x80000026) >> X86_CPU_TYPE_ID_SHIFT; +} +EXPORT_SYMBOL_GPL(amd_get_this_core_type); diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 7145248b38ec..7fe8a8fc6227 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -50,7 +50,9 @@ #define AMD_PSTATE_TRANSITION_LATENCY 20000 #define AMD_PSTATE_TRANSITION_DELAY 1000 -#define AMD_PSTATE_PREFCORE_THRESHOLD 166 +#define CPPC_HIGHEST_PERF_EFFICIENT 132 +#define CPPC_HIGHEST_PERF_PERFORMANCE 196 +#define CPPC_HIGHEST_PERF_DEFAULT 166 /* * TODO: We need more time to fine tune processors with shared memory solution @@ -326,6 +328,49 @@ static inline int amd_pstate_enable(bool enable) return static_call(amd_pstate_enable)(enable); } +static void get_this_core_type(void *data) +{ + int *cpu_type = data; + + *cpu_type = amd_get_this_core_type(); +} + +static int amd_pstate_get_cpu_type(int cpu) +{ + int cpu_type = 0; + + smp_call_function_single(cpu, get_this_core_type, &cpu_type, 1); + + return cpu_type; +} + +static u32 amd_pstate_highest_perf_set(struct amd_cpudata *cpudata) +{ + u32 highest_perf; + int core_type; + + core_type = amd_pstate_get_cpu_type(cpudata->cpu); + pr_debug("core_type %d found\n", core_type); + + switch (core_type) { + case CPU_CORE_TYPE_NO_HETERO_SUP: + highest_perf = CPPC_HIGHEST_PERF_DEFAULT; + break; + case CPU_CORE_TYPE_PERFORMANCE: + highest_perf = CPPC_HIGHEST_PERF_PERFORMANCE; + break; + case CPU_CORE_TYPE_EFFICIENCY: + highest_perf = CPPC_HIGHEST_PERF_EFFICIENT; + break; + default: + highest_perf = CPPC_HIGHEST_PERF_DEFAULT; + WARN_ONCE(true, "WARNING: Undefined core type found"); + break; + } + + return highest_perf; +} + static int pstate_init_perf(struct amd_cpudata *cpudata) { u64 cap1; @@ -336,15 +381,7 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) if (ret) return ret; - /* For platforms that do not support the preferred core feature, the - * highest_pef may be configured with 166 or 255, to avoid max frequency - * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as - * the default max perf. - */ - if (cpudata->hw_prefcore) - highest_perf = AMD_PSTATE_PREFCORE_THRESHOLD; - else - highest_perf = AMD_CPPC_HIGHEST_PERF(cap1); + highest_perf = amd_pstate_highest_perf_set(cpudata); WRITE_ONCE(cpudata->highest_perf, highest_perf); WRITE_ONCE(cpudata->max_limit_perf, highest_perf); @@ -365,10 +402,7 @@ static int cppc_init_perf(struct amd_cpudata *cpudata) if (ret) return ret; - if (cpudata->hw_prefcore) - highest_perf = AMD_PSTATE_PREFCORE_THRESHOLD; - else - highest_perf = cppc_perf.highest_perf; + highest_perf = amd_pstate_highest_perf_set(cpudata); WRITE_ONCE(cpudata->highest_perf, highest_perf); WRITE_ONCE(cpudata->max_limit_perf, highest_perf); diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index d58fc022ec46..869d916003f1 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -134,4 +134,12 @@ struct quirk_entry { u32 lowest_freq; }; +/* defined by CPUID_Fn80000026_EBX BIT [31:28] */ +enum amd_core_type { + CPU_CORE_TYPE_NO_HETERO_SUP = -1, + CPU_CORE_TYPE_PERFORMANCE = 0, + CPU_CORE_TYPE_EFFICIENCY = 1, + CPU_CORE_TYPE_UNDEFINED = 2, +}; + #endif /* _LINUX_AMD_PSTATE_H */ From patchwork Tue May 7 07:15:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 795428 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2079.outbound.protection.outlook.com [40.107.223.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52F3F13D2B6; Tue, 7 May 2024 07:16:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 7 May 2024 02:16:19 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH 10/11] cpufreq: amd-pstate: fix the highest frequency issue which limit performance Date: Tue, 7 May 2024 15:15:26 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709D:EE_|PH0PR12MB5680:EE_ X-MS-Office365-Filtering-Correlation-Id: 14eec558-7428-4d0a-51b0-08dc6e6599c8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|36860700004|1800799015|376005|82310400017; X-Microsoft-Antispam-Message-Info: mmyP1hIfFpU92Q3YoXJhDyr/Q73DL1qv4L2uU/rM4g4w/aQa221kn0a8P3sjuMZDIecH9MxoFhk4NK6G95Ds6WUZNqok8s+ks8FHR9sIkaVp/8/v3PyVwNBsVooZiZujE/mqWGDdO8fIMsjaKKvvHvwTbcEQapt0WfLJKOyjm0lyYdZMimE3Ep4C42PnxZ2luwYz6Jo4ZBisz1Z4XSv/01eBI8n6DAX7SiPzoOEADIo+SXdwSUkD96mnD801xzEiMbnFCcpcN+qdZ7PjW5oPiDBWbnc2MvbOHUdPTubrG+3ZT+i715c30N9s0Q9Qx9xjwO6qvQ+KCvwbasynmiMJh7n8csMuW/r96zHi4BVdtohWxhiaTbAFEsv3RL2irwHfi/dtnuxR0c7/R2DbHCasfhYjOf8eK8DM6P3pWSsV0dAXvw7vyTX+CQGdtug0xMnJzD4PhBBLpIBJJ0kNqzzotNb0ZfunRhIqdrBN0DBbdOBjllHBoMo7q5XjR/BwXCoe5J9wxFyTOBZmIDrT1F4U+bsRB7UCmYDHyIDl+jMAg2B0IIis+KYpWk+zb/FmMEyJK1inV/W1TJShMnDWoiUz38NHjMpN04f/eiBjMDiNuyJXkHtONY44xv+h8wx4zcBtoiHqf2pXXlZkv82nswtXzA9QKCyDfwagqML5FgeyrUCx9PZvhNvQKPgjKcFPUjzBz3BDiFKHfGm6wulv2pEzzMs2/Gpg7gy6yhEXqt35ddxtxnDVTu7cBoPZiHdVuRwfPjEWVVEoGRvaJJKNdwOH/ZkD5jBBANSKjR6VVMY0q2KbIokxgz1hSj/UGtJU8HOamfWNIXKHrG93aBM4FTsIp+rMrGuMtA/Xz5Ze0VqRFidcnDW9EL0JXkGoo0pq8igcIT5EilrlWa7/zZAhzSXiJZkadPESGqoMCWksN+VgB3pauMoQWhsRMOES4agBR85QHpnBDA2o+QB8GGK1N+NwNP6zCk6gm0ssAtaC2YR6f1YqDFMxwZZ0iV9NT8UQRTjV5R1IU+Y7aI9B0F3I9RZgls/CGr49XOiVit1GLeNlNn0uaE8mB5p/kxSaS+FENpL6C1Nn2mxxN26G22KyyMbFQhN29Sf1T0BtfWFTlEABGj0RhRkVgArbwUzuLfm+MMMB4wJj1Zg/V1qUejx10yZMjg83ESwMOk/Yj2Tq3VRLOm01QVYuB2HW6oIrVJCbTLiTSmBqa0/p/ePi05cvlMlFx9MplIiqgR6YinLGhbiux65WRYszusUF4486FXsBXmLJnO2BGwApdwFGwHdGWttH9f2EafbH5EdIHnwRncR5D+bXSkBSwonP/rWXJ3KYqLD6 X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(36860700004)(1800799015)(376005)(82310400017); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 May 2024 07:16:22.9780 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 14eec558-7428-4d0a-51b0-08dc6e6599c8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5680 To address the performance drop issue, an optimization has been implemented. The incorrect highest performance value previously set by the low-level power firmware for AMD CPUs with Family ID 0x19 and Model ID ranging from 0x70 to 0x7F series has been identified as the cause. To resolve this, a check has been implemented to accurately determine the CPU family and model ID. The correct highest performance value is now set and the performance drop caused by the incorrect highest performance value are eliminated. Before the fix, the highest frequency was set to 4200MHz, now it is set to 4971MHz which is correct. CPU NODE SOCKET CORE L1d:L1i:L2:L3 ONLINE MAXMHZ MINMHZ MHZ 0 0 0 0 0:0:0:0 yes 4971.0000 400.0000 400.0000 1 0 0 0 0:0:0:0 yes 4971.0000 400.0000 400.0000 2 0 0 1 1:1:1:0 yes 4971.0000 400.0000 4865.8140 3 0 0 1 1:1:1:0 yes 4971.0000 400.0000 400.0000 Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218759 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 7fe8a8fc6227..3ff381c4edf7 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -348,6 +348,7 @@ static u32 amd_pstate_highest_perf_set(struct amd_cpudata *cpudata) { u32 highest_perf; int core_type; + struct cpuinfo_x86 *c = &cpu_data(0); core_type = amd_pstate_get_cpu_type(cpudata->cpu); pr_debug("core_type %d found\n", core_type); @@ -355,6 +356,13 @@ static u32 amd_pstate_highest_perf_set(struct amd_cpudata *cpudata) switch (core_type) { case CPU_CORE_TYPE_NO_HETERO_SUP: highest_perf = CPPC_HIGHEST_PERF_DEFAULT; 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Tue, 7 May 2024 07:16:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF00017098.mail.protection.outlook.com (10.167.18.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7544.18 via Frontend Transport; Tue, 7 May 2024 07:16:25 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 7 May 2024 02:16:22 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH 11/11] cpufreq: amd-pstate: automatically load pstate driver by default Date: Tue, 7 May 2024 15:15:27 +0800 Message-ID: <60bdfbeb426512d74faa91597453fd7960ebd7b5.1715065568.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017098:EE_|IA1PR12MB7495:EE_ X-MS-Office365-Filtering-Correlation-Id: dae60c5a-5284-4eb4-e8be-08dc6e659b81 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|1800799015|376005|36860700004|82310400017; X-Microsoft-Antispam-Message-Info: SMMbUUQPNLER+NOgnwdIb16PhD7oahc24Yu9Y9X0+fpno59tYVlCRm0KcyusW085SWsj47G1YgIwdCDY/NIwWRa/eGOFRk06DRmzZWi8T5etHVKiCN5Ag24pJWdDB2cCbXQO1PgMkOo5t4MoQ6+xxq/eLejZjxDnMAE/Jp+Z1pLjAi1vDReaVDN9t2MBFm5iDpK6S8pDMd4xlCJ1V3p7XTZipYnpAUT3HvMK89GmPigDrc6MTlx2SMfwM8O/y7ACu6gajYuWUSTnAxLfb2uLgTvbWujzOvBZ60ot5YlDGOTP+P+67143XQpkduInb0P2CUwmboA2Yz0yByomvLghEHLP/CNtTT9Y7HDJJJv7XBtu2jjwkLF7JQMoBeRACWxYD0VovQqasHKKmjRODXcPRVy0afw89MgtOypZCn0JAapHzbzNRACe/cSFt0CNSN8Hlh56cG4h8BuIAm73UT7gx0q4pLzYJmJi+oyxUizKdX7E8PkSWr6fttT1HpTZb9N8Qx80PV02q1E5L9G0SPPoEGvintytIrr6d4IZ1rhu1Q00WZFI9BR+cC7rAHuOZvrIpbXXiTQbyXBsX2+9F9Dk1cUQgJUwMcpkxi+tMuFc/3+b3s1AkJNCEHgrdPuwJSr9i241MCfAP3piwjUaf7dHH0D9C+5Ccrs/mzwKF+xR+EuLB6t0PNWUHTDlvWdRORsGWO3gPIR3xF6j5drP0GmID/wfmUPjv1ADM6IDZBRZa69l1IcsKwLVShFYKzZXa1i+iPB6v2NsaUHZ8v66g44BBTZg6jo6eHr/SzfjQv2FtapRTPcUvBVS39pqH8T4vCxWhVUvaq6i1Yyjic/IsNuvjVzDpvlMKqPP78Gf6ryxaaGxPxKmYK5jQZ5nKG0/sG6nzYl5UPyqCNqgI0OqHIifsqTxT/Yb+KGmwRjuuZWHNOqzHeh/Ugh5rGZ6Za/jwQQeS6yXWoaKOPPyhIYxqJcG8tfHt8UrzeKsKeMKSTwxRe9zD5wdOVzXOhw643Q+8ADu6Tx+Duch0v5gF5OUaLxyLmI592HKJenlX1XxIODzc2XH8RxreHXXEF/wCZ+nXKqssPR96c02M0F51BPUuR9YjQrNS7w0RGy9eZRxSSRS+m5CiZHVg6Emv+Q2TN8ZpmqF8UCUJQA1YJEJu8YKutsAUddr7Slz+e7j6ZQRF9IUI7etKgDClvBYgga6RzS4Dp26TiS6QmMdYV+lr57fG0TzTCmPxL/UkSrIbgWMMe9PY6cbyf2lYk79OHIbsludPbl8JdWj8byRo7UC0pUwwmUqfgfktqcIWNd6dv8+2A8Z68YooWRsbwU1lFSUuHnFRloJ X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(1800799015)(376005)(36860700004)(82310400017); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 May 2024 07:16:25.8563 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dae60c5a-5284-4eb4-e8be-08dc6e659b81 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017098.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7495 If the `amd-pstate` driver is not loaded automatically by default, it is because the kernel command line parameter has not been added. To resolve this issue, it is necessary to call the `amd_pstate_set_driver()` function to enable the desired mode (passive/active/guided) before registering the driver instance. This ensures that the driver is loaded correctly without relying on the kernel command line parameter. [ 0.917789] usb usb6: Manufacturer: Linux 6.9.0-rc6-amd-pstate-new-fix-v1 xhci-hcd [ 0.982579] amd_pstate: failed to register with return -22 Reported-by: Andrei Amuraritei Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218705 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 39 +++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 18 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 3ff381c4edf7..f5368497ee79 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -66,7 +66,7 @@ static struct cpufreq_driver *current_pstate_driver; static struct cpufreq_driver amd_pstate_driver; static struct cpufreq_driver amd_pstate_epp_driver; -static int cppc_state = AMD_PSTATE_UNDEFINED; +static int cppc_state; static bool cppc_enabled; static bool amd_pstate_prefcore = true; static struct quirk_entry *quirks; @@ -1762,6 +1762,16 @@ static int __init amd_pstate_init(void) if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) return -ENODEV; + /* Disable on the following configs by default: + * 1. Undefined platforms + * 2. Server platforms + */ + if (amd_pstate_acpi_pm_profile_undefined() || + amd_pstate_acpi_pm_profile_server()) { + pr_info("driver load is disabled for server or undefined platform\n"); + return -ENODEV; + } + /* show debug message only if CPPC is not supported */ if (!amd_cppc_supported()) return -EOPNOTSUPP; @@ -1781,28 +1791,21 @@ static int __init amd_pstate_init(void) /* check if this machine need CPPC quirks */ dmi_check_system(amd_pstate_quirks_table); + /* get default driver mode for loading*/ + cppc_state = CONFIG_X86_AMD_PSTATE_DEFAULT_MODE; + pr_debug("cppc working state set to mode:%d\n", cppc_state); + switch (cppc_state) { - case AMD_PSTATE_UNDEFINED: - /* Disable on the following configs by default: - * 1. Undefined platforms - * 2. Server platforms - * 3. Shared memory designs - */ - if (amd_pstate_acpi_pm_profile_undefined() || - amd_pstate_acpi_pm_profile_server() || - !cpu_feature_enabled(X86_FEATURE_CPPC)) { - pr_info("driver load is disabled, boot with specific mode to enable this\n"); - return -ENODEV; - } - ret = amd_pstate_set_driver(CONFIG_X86_AMD_PSTATE_DEFAULT_MODE); - if (ret) - return ret; - break; case AMD_PSTATE_DISABLE: + pr_info("driver load is disabled, boot with specific mode to enable this\n"); return -ENODEV; + case AMD_PSTATE_UNDEFINED: case AMD_PSTATE_PASSIVE: case AMD_PSTATE_ACTIVE: case AMD_PSTATE_GUIDED: + ret = amd_pstate_set_driver(cppc_state); + if (ret) + return ret; break; default: return -EINVAL; @@ -1823,7 +1826,7 @@ static int __init amd_pstate_init(void) /* enable amd pstate feature */ ret = amd_pstate_enable(true); if (ret) { - pr_err("failed to enable with return %d\n", ret); + pr_err("failed to enable driver mode(%d) with return %d\n", cppc_state, ret); return ret; }