From patchwork Tue Oct 15 17:30:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 176391 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp6077412ocf; Tue, 15 Oct 2019 10:30:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqw3utrdWVBK150r+NyzKXbQMz9CSHx4JbIHV0Y2V5s6M/nzzIv8nmuSBDKibq+yPRc6Aei1 X-Received: by 2002:a17:906:300a:: with SMTP id 10mr35660214ejz.104.1571160656614; Tue, 15 Oct 2019 10:30:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571160656; cv=none; d=google.com; s=arc-20160816; b=iLgXOxD/f4JxXXL4BuXX5aWBADBTC4LQJY26HEmvaX7zOg/adiu29O6f1OBzyAU7OA 3EFiSxC1WjHbw4RDneiW1t5c/loQcq0wwfyS64R/sKHc6bJMU9Vv7yD2B2WgkqFdNM0+ Ru79lXjFtC6CoXXAV9N0IElcF3Gnuh1IUjU8A5ABQspJOJT6DkVEFL6ptOEqWXa5km9z nbs5XdgxXAWWrk3bV1/EgdSMGjvRG/i7ue0UJ9IVPwXCgj18JJDa/G1tJiM1T+QkeCkW UbZUh8qRfIrLFnKh+ypjByonKQzs/qVGbyOzs9GNSCSP4yPUgsi0O3zdQlTMpP4cdOgg wCNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=y09+A5UHDqq1M123Rs3HINM2fRslFLIQNP0UXzIqt20=; b=K0GpCMSxffrq4TfFiaO5XJAYqBPdFCN0Mn0478aG8TUATg+wG7jDxRKUkQ1zqy8neb V+t72+eojAlfJQhSHJE356j9VIt4X8AjjcNW6JxfzshSC6uXUBSW7xSpwGaYcp9CXCF2 DlibucRYedv++vwLHFHt15GAUZmUfoWdJIifAwWQwWVjHhb8S+YWTDwqmO/JdVUN5Phg hAcaEUAe1fm8D/je9Hab6IjdsbODVzT3RVliyGlVg6v877cDwNq5SWoB9UdU75NZ2Vj5 Led1sx7cwEPJSrT9benewdKl2r/Lj1HJ4taSZBJUpcTzendEn+OGCvWNZ5ZBICTnkm7v T+lQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eZ82Yhwt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g37si15745289edg.59.2019.10.15.10.30.56; Tue, 15 Oct 2019 10:30:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eZ82Yhwt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388794AbfJORaw (ORCPT + 23 others); Tue, 15 Oct 2019 13:30:52 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:33533 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729632AbfJORau (ORCPT ); Tue, 15 Oct 2019 13:30:50 -0400 Received: by mail-pl1-f195.google.com with SMTP id d22so9928973pls.0 for ; Tue, 15 Oct 2019 10:30:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=y09+A5UHDqq1M123Rs3HINM2fRslFLIQNP0UXzIqt20=; b=eZ82YhwtUAOVg9G2zs0bTyLwRz0ch+7l+1a7/7Qr+2qWB2PvexBHVq2rpE2mMUHlE8 69cksLWwsICq8VYOOQVEcdkVSUZEj4lz/IJvdKN457KBXh3QXdfO3GrvWb1TJLALJOr7 Ti6ewei0hf0hy8j0YxESEUn/79rKNQhTOW3CIQqgecONAFnQi8Ca93kMujRzNa5FRabu VmGvXYPdukV8FLvCNlhMf6xWyncyMH3VzgfomB4vjvpoljfVhoaKenw9WH6NVry7t6gv 11DUYl30BqMBJnyqE933rTCr2o40uTZdERufP80A3wjxXssozn3ngkvUuHnXlmWDteTd bqcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=y09+A5UHDqq1M123Rs3HINM2fRslFLIQNP0UXzIqt20=; b=tYOKxeeDiucmr9+sb27loYOLuIOIYwvJ6Yworqxksdm255fMqveCkxwzSvxMYqQmyc Af0xNdbQyvLgH21JtfTTn8Epxy66QU7AsaHpOpA42ijZMA4EayL1gGqqe5EumuIN88t6 CdveAweRIuAQqqZQdiHxCWcDtx2N5bendjX9/hyT0dHYa1PeXRVuv3zuzj0+5umBNuP4 XJWOHCvWkm+UvIpZ1JOIOPP1599yNQVTtVvixGBiGmsqV5bBNWk6Z0LAaRtZFFfuwm9E Zz0PrIlafiI/Bc36AlORx4OU7eLPJwZWGKXGawbJn6xrHFcAN5vB0s20oF/oZ0f2qM6O 5eaw== X-Gm-Message-State: APjAAAXcj92Qw6PJzlIo52qpIaHAFaoq01qhmsmEbjlUf9QZ9sxnwHtz wuLDjB0GauWbMCn4gg/FQnAv X-Received: by 2002:a17:902:d698:: with SMTP id v24mr36554507ply.89.1571160649769; Tue, 15 Oct 2019 10:30:49 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:6003:7cb8:25e8:2c45:fab2:b0c7]) by smtp.gmail.com with ESMTPSA id w11sm28033563pfd.116.2019.10.15.10.30.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 10:30:49 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, bgolaszewski@baylibre.com Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, orsonzhai@gmail.com, Manivannan Sadhasivam Subject: [PATCH v2 2/4] ARM: dts: Add RDA8810PL GPIO controllers Date: Tue, 15 Oct 2019 23:00:24 +0530 Message-Id: <20191015173026.9962-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191015173026.9962-1-manivannan.sadhasivam@linaro.org> References: <20191015173026.9962-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add GPIO controllers for RDA8810PL SoC. There are 4 GPIO controllers in this SoC with maximum of 32 gpios. Except GPIOC, all controllers are capable of generating edge/level interrupts from first 8 lines. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/rda8810pl.dtsi | 48 ++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- 2.17.1 diff --git a/arch/arm/boot/dts/rda8810pl.dtsi b/arch/arm/boot/dts/rda8810pl.dtsi index 19cde895bf65..f30d6ece49fb 100644 --- a/arch/arm/boot/dts/rda8810pl.dtsi +++ b/arch/arm/boot/dts/rda8810pl.dtsi @@ -33,6 +33,21 @@ ranges; }; + modem@10000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000000 0xfffffff>; + + gpioc@1a08000 { + compatible = "rda,8810pl-gpio"; + reg = <0x1a08000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + }; + }; + apb@20800000 { compatible = "simple-bus"; #address-cells = <1>; @@ -60,6 +75,39 @@ <17 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hwtimer", "ostimer"; }; + + gpioa@30000 { + compatible = "rda,8810pl-gpio"; + reg = <0x30000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpiob@31000 { + compatible = "rda,8810pl-gpio"; + reg = <0x31000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpiod@32000 { + compatible = "rda,8810pl-gpio"; + reg = <0x32000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + }; }; apb@20a00000 { From patchwork Tue Oct 15 17:30:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 176393 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp6077517ocf; Tue, 15 Oct 2019 10:31:01 -0700 (PDT) X-Google-Smtp-Source: APXvYqxK8JT0P2ii5NJTL9GfbJ63ZveQd2pfMSN3tLBqBC+4vvGl3SPL0SgomTV3B7eofStxsqOO X-Received: by 2002:a17:906:2cca:: with SMTP id r10mr36001751ejr.108.1571160661219; Tue, 15 Oct 2019 10:31:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571160661; cv=none; d=google.com; s=arc-20160816; b=dfJrf+1KYD87nPNbb45GsBGMMj51ITabl9vX0PkA5JhewwaMplYWBW9NAb6BdY2Vfb uiBMqPGAXI/dc5bYS0uQOzbWfUf/CYBHhK1Oz1f3yZJlAISTCqK9gwFCQ4a0ZBtzydcj ySAF0vjNBUR4/Llij8lk5vcvbdt1vmn7vmlhUBFi8aPZy1Z1uIDdeigyLUcWZgDovV0N SOOC/j5f2kgDEodV6zbo7Gtov3gDbp/bal6GAJC5dst+LPob1PbReMpyvAP331qOiHMh 5Ml19jg1EYLIOw2UOP4uTJs4jCt39yEaJzT2n1dO6PA7dBV1Ks/LKBK+vN5vi/JtTqZH Xekw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=XS2R4FunLivDfSHsnShzXwsYoiKZ56RWG4w8jiOliI8=; b=u14gR0nkksAIFEsUgSrOnTwWSSQCO8rZ1rU+UiKk/KaXUMHHEjRGnbvLTSoGm9j4uR wRL6w9Ux/6na/bc/16Uh5CLVVjKY7k4dsvjwv61FFnQ5cz7FsLCXo+wxePYM6w1/TqfG VTzwDpkIjp48PSp1Rjjr161lxacOUy77sJ39dNBzfxpBLoFt27Xj6pD+0zLyrLjsTnSj MdYcBnrtGEGmZaOKL65gDA58SMT3E/ZxLgZqUt+0E2hUlAEERkTZD/3sOhV+B+y9tOzx TxvB8j/J1hUrtKCntEMSQ0ukyKr9Q7dCnRkoYdqFKt9APPaVgS9YEMCfDMVkbliOmjN6 6pXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WpUrKf+H; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i3si14069114edq.163.2019.10.15.10.31.00; Tue, 15 Oct 2019 10:31:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WpUrKf+H; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388807AbfJORa4 (ORCPT + 23 others); Tue, 15 Oct 2019 13:30:56 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:45969 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729632AbfJORaz (ORCPT ); Tue, 15 Oct 2019 13:30:55 -0400 Received: by mail-pg1-f196.google.com with SMTP id r1so11362001pgj.12 for ; Tue, 15 Oct 2019 10:30:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XS2R4FunLivDfSHsnShzXwsYoiKZ56RWG4w8jiOliI8=; b=WpUrKf+HJMcjNG2jW8yMEmlE0gt018p1xtNM7tYgBR4qvjURPid0Y0w/zgY9ara1hx nIrMFwJiF65WrJYzTLmYKvBHgoOfJAdnuNoWC9q2yNwN31YebWgAS1SNyTyIJ3ZJDh76 Xv8DwSIbaLPhmZ0HOmGnefb5Ng3117twEfYrXI8IRMBJi3PXNMba0rhb4BHyAM5N/TW3 rmnNHXkMVKjZRhbTFKNaCGkSdTmAqS1YWgeAKTp6TVkgUXuughEmeYgaArLcvqISl4x4 BS9DjFy23F6+rjyny2zmryjEHNtDE+my7LHmihfjVXshUh7GVojfCkHxrky6ybOcfJFE cIRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XS2R4FunLivDfSHsnShzXwsYoiKZ56RWG4w8jiOliI8=; b=FB/P3KfQj1tjz39Uv0KkPl6dyZEh0zUazmtaiF8iGMWAT07WtDJTvvMwd33CreMSdd cdxouZeNwD6t+3M0CslUhR9Z+2k2FUEzFrjcJHWTWMriHXRNGOQ4U+LZpXhpILHELQNo fN13yRpnOGmjUta4+Ov1M78gT7yeeReIhMfF91hXqHBvmoQRv2CFotqxxrff5zIGYFcA a+N+4R6f2JdnEKa4f4Gs7n8NwmBhZtuZ8H6JL0REapTreBI5TPGJRyebstjwvOAQ3utr hH6jL1fzVuEeU4FiYdz46gdVgfdgW2TFQIdmSjF23MOe3qTvC7Uo9MWSqV/JiweMFmVr P6KQ== X-Gm-Message-State: APjAAAWhsJg5IxCm+hjxn+n1eTZ91nTFmw0z1qjSRL69zMYAHeQ6V7mK MZ165gA9jrWLiyvJuxkjPDNU X-Received: by 2002:a63:ff56:: with SMTP id s22mr2141428pgk.44.1571160654729; Tue, 15 Oct 2019 10:30:54 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:6003:7cb8:25e8:2c45:fab2:b0c7]) by smtp.gmail.com with ESMTPSA id w11sm28033563pfd.116.2019.10.15.10.30.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 10:30:54 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, bgolaszewski@baylibre.com Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, orsonzhai@gmail.com, Manivannan Sadhasivam Subject: [PATCH v2 3/4] gpio: Add RDA Micro GPIO controller support Date: Tue, 15 Oct 2019 23:00:25 +0530 Message-Id: <20191015173026.9962-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191015173026.9962-1-manivannan.sadhasivam@linaro.org> References: <20191015173026.9962-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for GPIO controller from RDA Micro. Signed-off-by: Manivannan Sadhasivam --- drivers/gpio/Kconfig | 8 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-rda.c | 315 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 324 insertions(+) create mode 100644 drivers/gpio/gpio-rda.c -- 2.17.1 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 38e096e6925f..71826e61fdb3 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -435,6 +435,14 @@ config GPIO_RCAR help Say yes here to support GPIO on Renesas R-Car SoCs. +config GPIO_RDA + bool "RDA Micro GPIO controller support" + depends on ARCH_RDA || COMPILE_TEST + depends on OF_GPIO + select GPIOLIB_IRQCHIP + help + Say Y here to support RDA Micro GPIO controller. + config GPIO_REG bool help diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index d2fd19c15bae..5c68c9a48fa3 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -115,6 +115,7 @@ obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o +obj-$(CONFIG_GPIO_RDA) += gpio-rda.o obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o obj-$(CONFIG_GPIO_REG) += gpio-reg.o obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o diff --git a/drivers/gpio/gpio-rda.c b/drivers/gpio/gpio-rda.c new file mode 100644 index 000000000000..1e6ffe27897f --- /dev/null +++ b/drivers/gpio/gpio-rda.c @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RDA Micro GPIO driver + * + * Copyright (C) 2012 RDA Micro Inc. + * Copyright (C) 2019 Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include + +#define RDA_GPIO_OEN_VAL 0x00 +#define RDA_GPIO_OEN_SET_OUT 0x04 +#define RDA_GPIO_OEN_SET_IN 0x08 +#define RDA_GPIO_VAL 0x0c +#define RDA_GPIO_SET 0x10 +#define RDA_GPIO_CLR 0x14 +#define RDA_GPIO_INT_CTRL_SET 0x18 +#define RDA_GPIO_INT_CTRL_CLR 0x1c +#define RDA_GPIO_INT_CLR 0x20 +#define RDA_GPIO_INT_STATUS 0x24 + +#define RDA_GPIO_IRQ_RISE_SHIFT 0 +#define RDA_GPIO_IRQ_FALL_SHIFT 8 +#define RDA_GPIO_DEBOUCE_SHIFT 16 +#define RDA_GPIO_LEVEL_SHIFT 24 + +#define RDA_GPIO_IRQ_MASK 0xff + +/* Each bank consists of 32 GPIOs */ +#define RDA_GPIO_BANK_NR 32 + +struct rda_gpio { + struct gpio_chip chip; + void __iomem *base; + spinlock_t lock; + struct irq_chip irq_chip; + int irq; +}; + +static void rda_gpio_update(struct gpio_chip *chip, unsigned int offset, + u16 reg, int val) +{ + struct rda_gpio *rda_gpio = gpiochip_get_data(chip); + void __iomem *base = rda_gpio->base; + unsigned long flags; + u32 tmp; + + spin_lock_irqsave(&rda_gpio->lock, flags); + tmp = readl_relaxed(base + reg); + + if (val) + tmp |= BIT(offset); + else + tmp &= ~BIT(offset); + + writel_relaxed(tmp, base + reg); + spin_unlock_irqrestore(&rda_gpio->lock, flags); +} + +static int rda_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + rda_gpio_update(chip, offset, RDA_GPIO_OEN_SET_IN, 1); + + return 0; +} + +static int rda_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + rda_gpio_update(chip, offset, RDA_GPIO_OEN_SET_OUT, 1); + + return 0; +} + +static int rda_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct rda_gpio *rda_gpio = gpiochip_get_data(chip); + void __iomem *base = rda_gpio->base; + + if (readl_relaxed(base + RDA_GPIO_OEN_VAL) & BIT(offset)) + return !!(readl_relaxed(base + RDA_GPIO_VAL) & BIT(offset)); + else + return !!(readl_relaxed(base + RDA_GPIO_SET) & BIT(offset)); +} + +static void rda_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + if (value) + rda_gpio_update(chip, offset, RDA_GPIO_SET, 1); + else + rda_gpio_update(chip, offset, RDA_GPIO_CLR, 1); +} + +static void rda_gpio_irq_mask(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + struct rda_gpio *rda_gpio = gpiochip_get_data(chip); + void __iomem *base = rda_gpio->base; + u32 offset = irqd_to_hwirq(data); + u32 value; + + value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT; + value |= BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT; + + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR); +} + +static void rda_gpio_irq_ack(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + u32 offset = irqd_to_hwirq(data); + + rda_gpio_update(chip, offset, RDA_GPIO_INT_CLR, 1); +} + +static int rda_gpio_set_irq(struct gpio_chip *chip, u32 offset, + unsigned int flow_type) +{ + struct rda_gpio *rda_gpio = gpiochip_get_data(chip); + void __iomem *base = rda_gpio->base; + u32 value; + + switch (flow_type) { + case IRQ_TYPE_EDGE_RISING: + /* Set rising edge trigger */ + value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); + + /* Switch to edge trigger interrupt */ + value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR); + break; + + case IRQ_TYPE_EDGE_FALLING: + /* Set falling edge trigger */ + value = BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); + + /* Switch to edge trigger interrupt */ + value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR); + break; + + case IRQ_TYPE_EDGE_BOTH: + /* Set both edge trigger */ + value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT; + value |= BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); + + /* Switch to edge trigger interrupt */ + value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR); + break; + + case IRQ_TYPE_LEVEL_HIGH: + /* Set high level trigger */ + value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT; + + /* Switch to level trigger interrupt */ + value |= BIT(offset) << RDA_GPIO_LEVEL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); + break; + + case IRQ_TYPE_LEVEL_LOW: + /* Set low level trigger */ + value = BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT; + + /* Switch to level trigger interrupt */ + value |= BIT(offset) << RDA_GPIO_LEVEL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); + break; + + default: + return -EINVAL; + } + + return 0; +} + +static void rda_gpio_irq_unmask(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + u32 offset = irqd_to_hwirq(data); + u32 trigger = irqd_get_trigger_type(data); + + rda_gpio_set_irq(chip, offset, trigger); +} + +static int rda_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + u32 offset = irqd_to_hwirq(data); + int ret; + + ret = rda_gpio_set_irq(chip, offset, flow_type); + if (ret) + return ret; + + if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + irq_set_handler_locked(data, handle_level_irq); + else if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + irq_set_handler_locked(data, handle_edge_irq); + + return 0; +} + +static void rda_gpio_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *chip = irq_desc_get_handler_data(desc); + struct irq_chip *ic = irq_desc_get_chip(desc); + struct rda_gpio *rda_gpio = gpiochip_get_data(chip); + unsigned long status; + u32 n, girq; + + chained_irq_enter(ic, desc); + + status = readl_relaxed(rda_gpio->base + RDA_GPIO_INT_STATUS); + /* Only lower 8 bits are capable of generating interrupts */ + status &= RDA_GPIO_IRQ_MASK; + + for_each_set_bit(n, &status, RDA_GPIO_BANK_NR) { + girq = irq_find_mapping(chip->irq.domain, n); + generic_handle_irq(girq); + } + + chained_irq_exit(ic, desc); +} + +static int rda_gpio_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct gpio_irq_chip *irq_chip; + struct rda_gpio *rda_gpio; + u32 ngpios; + int ret; + + rda_gpio = devm_kzalloc(&pdev->dev, sizeof(*rda_gpio), GFP_KERNEL); + if (!rda_gpio) + return -ENOMEM; + + ret = device_property_read_u32(&pdev->dev, "ngpios", &ngpios); + if (ret < 0) + return ret; + + /* + * Not all ports have interrupt capability. For instance, on + * RDA8810PL, GPIOC doesn't support interrupt. So we must handle + * those also. + */ + rda_gpio->irq = platform_get_irq(pdev, 0); + + rda_gpio->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(rda_gpio->base)) + return PTR_ERR(rda_gpio->base); + + spin_lock_init(&rda_gpio->lock); + + rda_gpio->chip.label = dev_name(&pdev->dev); + rda_gpio->chip.ngpio = ngpios; + rda_gpio->chip.base = -1; + rda_gpio->chip.parent = &pdev->dev; + rda_gpio->chip.of_node = np; + rda_gpio->chip.get = rda_gpio_get; + rda_gpio->chip.set = rda_gpio_set; + rda_gpio->chip.direction_input = rda_gpio_direction_input; + rda_gpio->chip.direction_output = rda_gpio_direction_output; + + if (rda_gpio->irq >= 0) { + rda_gpio->irq_chip.name = "rda-gpio", + rda_gpio->irq_chip.irq_ack = rda_gpio_irq_ack, + rda_gpio->irq_chip.irq_mask = rda_gpio_irq_mask, + rda_gpio->irq_chip.irq_unmask = rda_gpio_irq_unmask, + rda_gpio->irq_chip.irq_set_type = rda_gpio_irq_set_type, + rda_gpio->irq_chip.flags = IRQCHIP_SKIP_SET_WAKE, + + irq_chip = &rda_gpio->chip.irq; + irq_chip->chip = &rda_gpio->irq_chip; + irq_chip->handler = handle_bad_irq; + irq_chip->default_type = IRQ_TYPE_NONE; + irq_chip->parent_handler = rda_gpio_irq_handler; + irq_chip->parent_handler_data = rda_gpio; + irq_chip->num_parents = 1; + irq_chip->parents = &rda_gpio->irq; + } + + platform_set_drvdata(pdev, rda_gpio); + + return devm_gpiochip_add_data(&pdev->dev, &rda_gpio->chip, rda_gpio); +} + +static const struct of_device_id rda_gpio_of_match[] = { + { .compatible = "rda,8810pl-gpio", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rda_gpio_of_match); + +static struct platform_driver rda_gpio_driver = { + .probe = rda_gpio_probe, + .driver = { + .name = "rda-gpio", + .of_match_table = rda_gpio_of_match, + }, +}; + +module_platform_driver_probe(rda_gpio_driver, rda_gpio_probe); + +MODULE_DESCRIPTION("RDA Micro GPIO driver"); +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_LICENSE("GPL v2");