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Wed, 1 May 2024 16:36:32 GMT Received: from adas-linux5.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 1 May 2024 09:36:31 -0700 From: Shashank Babu Chinta Venkata To: , , , , , , CC: , , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Yoshihiro Shimoda , Serge Semin , Conor Dooley , , , Subject: [PATCH v4 1/3] PCI: qcom: Refactor common code Date: Wed, 1 May 2024 09:35:32 -0700 Message-ID: <20240501163610.8900-2-quic_schintav@quicinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240501163610.8900-1-quic_schintav@quicinc.com> References: <20240501163610.8900-1-quic_schintav@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: AImVTm7ZR4d_evZpw9lvZ-a7nvpk-h8B X-Proofpoint-GUID: AImVTm7ZR4d_evZpw9lvZ-a7nvpk-h8B X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-01_16,2024-04-30_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 malwarescore=0 phishscore=0 spamscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 bulkscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2405010117 Refactor common code from RC(Root Complex) and EP(End Point) drivers and move them to a common driver. This acts as placeholder for common source code for both drivers, thus avoiding duplication. Signed-off-by: Shashank Babu Chinta Venkata --- drivers/pci/controller/dwc/Kconfig | 5 ++ drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-qcom-common.c | 76 +++++++++++++++++++ drivers/pci/controller/dwc/pcie-qcom-common.h | 12 +++ drivers/pci/controller/dwc/pcie-qcom-ep.c | 39 +--------- drivers/pci/controller/dwc/pcie-qcom.c | 69 +++-------------- 6 files changed, 108 insertions(+), 94 deletions(-) create mode 100644 drivers/pci/controller/dwc/pcie-qcom-common.c create mode 100644 drivers/pci/controller/dwc/pcie-qcom-common.h diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 8afacc90c63b..1599550cd628 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -265,12 +265,16 @@ config PCIE_DW_PLAT_EP order to enable device-specific features PCI_DW_PLAT_EP must be selected. +config PCIE_QCOM_COMMON + bool + config PCIE_QCOM bool "Qualcomm PCIe controller (host mode)" depends on OF && (ARCH_QCOM || COMPILE_TEST) depends on PCI_MSI select PCIE_DW_HOST select CRC8 + select PCIE_QCOM_COMMON help Say Y here to enable PCIe controller support on Qualcomm SoCs. The PCIe controller uses the DesignWare core plus Qualcomm-specific @@ -281,6 +285,7 @@ config PCIE_QCOM_EP depends on OF && (ARCH_QCOM || COMPILE_TEST) depends on PCI_ENDPOINT select PCIE_DW_EP + select PCIE_QCOM_COMMON help Say Y here to enable support for the PCIe controllers on Qualcomm SoCs to work in endpoint mode. The PCIe controller uses the DesignWare core diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index bac103faa523..3f557dd60c38 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom-ep.o +obj-$(CONFIG_PCIE_QCOM_COMMON) += pcie-qcom-common.o obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c new file mode 100644 index 000000000000..228d9eec0222 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2014-2015, 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2015, 2021 Linaro Limited. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + */ + +#include +#include + +#include "../../pci.h" +#include "pcie-designware.h" +#include "pcie-qcom-common.h" + +#define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \ + Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed])) + +struct icc_path *qcom_pcie_common_icc_get_resource(struct dw_pcie *pci, const char *path) +{ + struct icc_path *icc_mem_p; + + icc_mem_p = devm_of_icc_get(pci->dev, path); + if (IS_ERR_OR_NULL(icc_mem_p)) + return PTR_ERR(icc_mem_p); + return icc_mem_p; +} +EXPORT_SYMBOL_GPL(qcom_pcie_common_icc_get_resource); + +int qcom_pcie_common_icc_init(struct dw_pcie *pci, struct icc_path *icc_mem) +{ + int ret; + + /* + * Some Qualcomm platforms require interconnect bandwidth constraints + * to be set before enabling interconnect clocks. + * + * Set an initial peak bandwidth corresponding to single-lane Gen 1 + * for the pcie-mem path. + */ + ret = icc_set_bw(icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); + if (ret) { + dev_err(pci->dev, "Failed to set interconnect bandwidth: %d\n", + ret); + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(qcom_pcie_common_icc_init); + +void qcom_pcie_common_icc_update(struct dw_pcie *pci, struct icc_path *icc_mem) +{ + u32 offset, status; + int speed, width; + int ret; + + if (!icc_mem) + return; + + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + + /* Only update constraints if link is up. */ + if (!(status & PCI_EXP_LNKSTA_DLLLA)) + return; + + speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); + width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); + + ret = icc_set_bw(icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); + if (ret) + dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", + ret); +} +EXPORT_SYMBOL_GPL(qcom_pcie_common_icc_update); diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.h b/drivers/pci/controller/dwc/pcie-qcom-common.h new file mode 100644 index 000000000000..da1760c7e164 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-qcom-common.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2014-2015, 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2015, 2021 Linaro Limited. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "pcie-designware.h" + +struct icc_path *qcom_pcie_common_icc_get_resource(struct dw_pcie *pci, const char *path); +int qcom_pcie_common_icc_init(struct dw_pcie *pci, struct icc_path *icc_mem); +void qcom_pcie_common_icc_update(struct dw_pcie *pci, struct icc_path *icc_mem); diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 36e5e80cd22f..f0c61d847643 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -25,6 +25,7 @@ #include "../../pci.h" #include "pcie-designware.h" +#include "pcie-qcom-common.h" /* PARF registers */ #define PARF_SYS_CTRL 0x00 @@ -137,9 +138,6 @@ #define CORE_RESET_TIME_US_MAX 1005 #define WAKE_DELAY_US 2000 /* 2 ms */ -#define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \ - Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed])) - #define to_pcie_ep(x) dev_get_drvdata((x)->dev) enum qcom_pcie_ep_link_status { @@ -278,28 +276,6 @@ static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base, writel(0, pcie_ep->elbi + ELBI_CS2_ENABLE); } -static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) -{ - struct dw_pcie *pci = &pcie_ep->pci; - u32 offset, status; - int speed, width; - int ret; - - if (!pcie_ep->icc_mem) - return; - - offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); - - speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); - width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); - - ret = icc_set_bw(pcie_ep->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); - if (ret) - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", - ret); -} - static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) { struct dw_pcie *pci = &pcie_ep->pci; @@ -325,14 +301,7 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) if (ret) goto err_phy_exit; - /* - * Some Qualcomm platforms require interconnect bandwidth constraints - * to be set before enabling interconnect clocks. - * - * Set an initial peak bandwidth corresponding to single-lane Gen 1 - * for the pcie-mem path. - */ - ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); + ret = qcom_pcie_common_icc_init(pci, pcie_ep->icc_mem); if (ret) { dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", ret); @@ -616,7 +585,7 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev, if (IS_ERR(pcie_ep->phy)) ret = PTR_ERR(pcie_ep->phy); - pcie_ep->icc_mem = devm_of_icc_get(dev, "pcie-mem"); + pcie_ep->icc_mem = qcom_pcie_common_icc_get_resource(&pcie_ep->pci, "pcie-mem"); if (IS_ERR(pcie_ep->icc_mem)) ret = PTR_ERR(pcie_ep->icc_mem); @@ -643,7 +612,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { dev_dbg(dev, "Received BME event. Link is enabled!\n"); pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED; - qcom_pcie_ep_icc_update(pcie_ep); + qcom_pcie_common_icc_update(pci, pcie_ep->icc_mem); pci_epc_bme_notify(pci->ep.epc); } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) { dev_dbg(dev, "Received PM Turn-off event! Entering L23\n"); diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 2ce2a3bd932b..0095c42aeee0 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -32,6 +32,7 @@ #include #include "../../pci.h" +#include "pcie-qcom-common.h" #include "pcie-designware.h" /* PARF registers */ @@ -147,9 +148,6 @@ #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) -#define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \ - Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed])) - #define QCOM_PCIE_1_0_0_MAX_CLOCKS 4 struct qcom_pcie_resources_1_0_0 { struct clk_bulk_data clks[QCOM_PCIE_1_0_0_MAX_CLOCKS]; @@ -1363,59 +1361,6 @@ static const struct dw_pcie_ops dw_pcie_ops = { .start_link = qcom_pcie_start_link, }; -static int qcom_pcie_icc_init(struct qcom_pcie *pcie) -{ - struct dw_pcie *pci = pcie->pci; - int ret; - - pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem"); - if (IS_ERR(pcie->icc_mem)) - return PTR_ERR(pcie->icc_mem); - - /* - * Some Qualcomm platforms require interconnect bandwidth constraints - * to be set before enabling interconnect clocks. - * - * Set an initial peak bandwidth corresponding to single-lane Gen 1 - * for the pcie-mem path. - */ - ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); - if (ret) { - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", - ret); - return ret; - } - - return 0; -} - -static void qcom_pcie_icc_update(struct qcom_pcie *pcie) -{ - struct dw_pcie *pci = pcie->pci; - u32 offset, status; - int speed, width; - int ret; - - if (!pcie->icc_mem) - return; - - offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); - - /* Only update constraints if link is up. */ - if (!(status & PCI_EXP_LNKSTA_DLLLA)) - return; - - speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); - width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); - - ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); - if (ret) { - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", - ret); - } -} - static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) { struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private); @@ -1524,7 +1469,13 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } - ret = qcom_pcie_icc_init(pcie); + pcie->icc_mem = qcom_pcie_common_icc_get_resource(pcie->pci, "pcie-mem"); + if (IS_ERR_OR_NULL(pcie->icc_mem)) { + ret = PTR_ERR(pcie->icc_mem); + goto err_pm_runtime_put; + } + + ret = qcom_pcie_common_icc_init(pcie->pci, pcie->icc_mem); if (ret) goto err_pm_runtime_put; @@ -1546,7 +1497,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_phy_exit; } - qcom_pcie_icc_update(pcie); + qcom_pcie_common_icc_update(pcie->pci, pcie->icc_mem); if (pcie->mhi) qcom_pcie_init_debugfs(pcie); @@ -1613,7 +1564,7 @@ static int qcom_pcie_resume_noirq(struct device *dev) pcie->suspended = false; } - qcom_pcie_icc_update(pcie); + qcom_pcie_common_icc_update(pcie->pci, pcie->icc_mem); return 0; } From patchwork Wed May 1 16:35:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shashank Babu Chinta Venkata X-Patchwork-Id: 793755 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56F391803E; Wed, 1 May 2024 16:36:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714581420; cv=none; b=q9oskWQQbgbHDbsGeFvAf8GV+caMGo7fE6jnQv+sb8GBDZl9tk3/BJMS/XYqPumFiPuns6kE5oT2cgUtQpGDGrquGqm4h8DF4Q3b954ziGI9XyhZXVH1kQVo52u0UY/3qfCYlrr4eHcyReOKg8JO1qV1Mc9jyLDQtJ2LZtDcoaI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Wed, 1 May 2024 16:36:40 GMT Received: from adas-linux5.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 1 May 2024 09:36:39 -0700 From: Shashank Babu Chinta Venkata To: , , , , , , CC: , , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Yoshihiro Shimoda , Serge Semin , Conor Dooley , , , Subject: [PATCH v4 2/3] PCI: qcom: Add equalization settings for 16 GT/s Date: Wed, 1 May 2024 09:35:33 -0700 Message-ID: <20240501163610.8900-3-quic_schintav@quicinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240501163610.8900-1-quic_schintav@quicinc.com> References: <20240501163610.8900-1-quic_schintav@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 2VjDNPEdwNB061ByoSa_sVG6lT5tqC8E X-Proofpoint-ORIG-GUID: 2VjDNPEdwNB061ByoSa_sVG6lT5tqC8E X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-01_16,2024-04-30_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=908 priorityscore=1501 phishscore=0 mlxscore=0 adultscore=0 bulkscore=0 clxscore=1015 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2405010117 During high data transmission rates such as 16 GT/s , there is an increased risk of signal loss due to poor channel quality and interference. This can impact receiver's ability to capture signals accurately. Hence, signal compensation is achieved through appropriate lane equilization settings at both transmitter and receiver. This will result in increasing PCIe signal strength. Signed-off-by: Shashank Babu Chinta Venkata Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware.h | 12 ++++++ drivers/pci/controller/dwc/pcie-qcom-common.c | 37 +++++++++++++++++++ drivers/pci/controller/dwc/pcie-qcom-common.h | 1 + drivers/pci/controller/dwc/pcie-qcom-ep.c | 3 ++ drivers/pci/controller/dwc/pcie-qcom.c | 3 ++ 5 files changed, 56 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 26dae4837462..ed0045043847 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -122,6 +122,18 @@ #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) +#define GEN3_EQ_CONTROL_OFF 0x8a8 +#define GEN3_EQ_CONTROL_OFF_FB_MODE GENMASK(3, 0) +#define GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE BIT(4) +#define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC GENMASK(23, 8) +#define GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL BIT(24) + +#define GEN3_EQ_FB_MODE_DIR_CHANGE_OFF 0x8ac +#define GEN3_EQ_FMDC_T_MIN_PHASE23 GENMASK(4, 0) +#define GEN3_EQ_FMDC_N_EVALS GENMASK(9, 5) +#define GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA GENMASK(13, 10) +#define GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA GENMASK(17, 14) + #define PCIE_PORT_MULTI_LANE_CTRL 0x8C0 #define PORT_MLTI_UPCFG_SUPPORT BIT(7) diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c index 228d9eec0222..16c277b2e9d4 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-common.c +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c @@ -16,6 +16,43 @@ #define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \ Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed])) +void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci) +{ + u32 reg; + + /* + * GEN3_RELATED_OFF register is repurposed to apply equilaztion + * settings at various data transmission rates through registers + * namely GEN3_EQ_*. RATE_SHADOW_SEL bit field of GEN3_RELATED_OFF + * determines data rate for which this equilization settings are + * applied. + */ + reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); + reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; + reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; + reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, 0x1); + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); + + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); + reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | + GEN3_EQ_FMDC_N_EVALS | + GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | + GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA); + reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | + FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | + FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | + FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); + dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); + + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); + reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE | + GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | + GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | + GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); + dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); +} +EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_eq_settings); + struct icc_path *qcom_pcie_common_icc_get_resource(struct dw_pcie *pci, const char *path) { struct icc_path *icc_mem_p; diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.h b/drivers/pci/controller/dwc/pcie-qcom-common.h index da1760c7e164..5c01f6c18b3b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-common.h +++ b/drivers/pci/controller/dwc/pcie-qcom-common.h @@ -10,3 +10,4 @@ struct icc_path *qcom_pcie_common_icc_get_resource(struct dw_pcie *pci, const char *path); int qcom_pcie_common_icc_init(struct dw_pcie *pci, struct icc_path *icc_mem); void qcom_pcie_common_icc_update(struct dw_pcie *pci, struct icc_path *icc_mem); +void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci); diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index f0c61d847643..7940222d35f6 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -438,6 +438,9 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) goto err_disable_resources; } + if (pcie_link_speed[pci->link_gen] == PCIE_SPEED_16_0GT) + qcom_pcie_common_set_16gt_eq_settings(pci); + /* * The physical address of the MMIO region which is exposed as the BAR * should be written to MHI BASE registers. diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 0095c42aeee0..525942f2cf98 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -263,6 +263,9 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) { struct qcom_pcie *pcie = to_qcom_pcie(pci); + if (pcie_link_speed[pci->link_gen] == PCIE_SPEED_16_0GT) + qcom_pcie_common_set_16gt_eq_settings(pci); + /* Enable Link Training state machine */ if (pcie->cfg->ops->ltssm_enable) pcie->cfg->ops->ltssm_enable(pcie); From patchwork Wed May 1 16:35:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shashank Babu Chinta Venkata X-Patchwork-Id: 794183 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E011B1B59A; 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Wed, 01 May 2024 16:36:48 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 441Gal6d023532 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 1 May 2024 16:36:47 GMT Received: from adas-linux5.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 1 May 2024 09:36:46 -0700 From: Shashank Babu Chinta Venkata To: , , , , , , CC: , , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Yoshihiro Shimoda , Serge Semin , Conor Dooley , , , Subject: [PATCH v4 3/3] PCI: qcom: Add RX margining settings for 16 GT/s Date: Wed, 1 May 2024 09:35:34 -0700 Message-ID: <20240501163610.8900-4-quic_schintav@quicinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240501163610.8900-1-quic_schintav@quicinc.com> References: <20240501163610.8900-1-quic_schintav@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 6pESSpz_z8xm8orijpm67aKzyVuUv5bZ X-Proofpoint-GUID: 6pESSpz_z8xm8orijpm67aKzyVuUv5bZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-01_16,2024-04-30_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 priorityscore=1501 suspectscore=0 adultscore=0 clxscore=1015 impostorscore=0 spamscore=0 mlxlogscore=930 lowpriorityscore=0 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2405010117 Add RX lane margining settings for 16 GT/s(GEN 4) data rate. These settings improve link stability while operating at high date rates and helps to improve signal quality. Signed-off-by: Shashank Babu Chinta Venkata --- drivers/pci/controller/dwc/pcie-designware.h | 18 +++++++++++ drivers/pci/controller/dwc/pcie-qcom-common.c | 31 +++++++++++++++++++ drivers/pci/controller/dwc/pcie-qcom-common.h | 1 + drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 ++- drivers/pci/controller/dwc/pcie-qcom.c | 4 ++- 5 files changed, 56 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index ed0045043847..343450c04e05 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -203,6 +203,24 @@ #define PCIE_PL_CHK_REG_ERR_ADDR 0xB28 +/* + * 16 GT/s (GEN4) lane margining register definitions + */ +#define GEN4_LANE_MARGINING_1_OFF 0xb80 +#define MARGINING_MAX_VOLTAGE_OFFSET GENMASK(29, 24) +#define MARGINING_NUM_VOLTAGE_STEPS GENMASK(22, 16) +#define MARGINING_MAX_TIMING_OFFSET GENMASK(13, 8) +#define MARGINING_NUM_TIMING_STEPS GENMASK(5, 0) + +#define GEN4_LANE_MARGINING_2_OFF 0xb84 +#define MARGINING_IND_ERROR_SAMPLER BIT(28) +#define MARGINING_SAMPLE_REPORTING_METHOD BIT(27) +#define MARGINING_IND_LEFT_RIGHT_TIMING BIT(26) +#define MARGINING_IND_UP_DOWN_VOLTAGE BIT(25) +#define MARGINING_VOLTAGE_SUPPORTED BIT(24) +#define MARGINING_MAXLANES GENMASK(20, 16) +#define MARGINING_SAMPLE_RATE_TIMING GENMASK(13, 8) +#define MARGINING_SAMPLE_RATE_VOLTAGE GENMASK(5, 0) /* * iATU Unroll-specific register definitions * From 4.80 core version the address translation will be made by unroll diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c index 16c277b2e9d4..fe6f7dde5d8c 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-common.c +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c @@ -53,6 +53,37 @@ void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci) } EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_eq_settings); +void qcom_pcie_common_set_16gt_rx_margining_settings(struct dw_pcie *pci) +{ + u32 reg; + + reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF); + reg &= ~(MARGINING_MAX_VOLTAGE_OFFSET | + MARGINING_NUM_VOLTAGE_STEPS | + MARGINING_MAX_TIMING_OFFSET | + MARGINING_NUM_TIMING_STEPS); + reg |= FIELD_PREP(MARGINING_MAX_VOLTAGE_OFFSET, 0x24) | + FIELD_PREP(MARGINING_NUM_VOLTAGE_STEPS, 0x78) | + FIELD_PREP(MARGINING_MAX_TIMING_OFFSET, 0x32) | + FIELD_PREP(MARGINING_NUM_TIMING_STEPS, 0x10); + dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_1_OFF, reg); + + reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_2_OFF); + reg |= MARGINING_IND_ERROR_SAMPLER | + MARGINING_SAMPLE_REPORTING_METHOD | + MARGINING_IND_LEFT_RIGHT_TIMING | + MARGINING_VOLTAGE_SUPPORTED; + reg &= ~(MARGINING_IND_UP_DOWN_VOLTAGE | + MARGINING_MAXLANES | + MARGINING_SAMPLE_RATE_TIMING | + MARGINING_SAMPLE_RATE_VOLTAGE); + reg |= FIELD_PREP(MARGINING_MAXLANES, pci->num_lanes) | + FIELD_PREP(MARGINING_SAMPLE_RATE_TIMING, 0x3f) | + FIELD_PREP(MARGINING_SAMPLE_RATE_VOLTAGE, 0x3f); + dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_2_OFF, reg); +} +EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_rx_margining_settings); + struct icc_path *qcom_pcie_common_icc_get_resource(struct dw_pcie *pci, const char *path) { struct icc_path *icc_mem_p; diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.h b/drivers/pci/controller/dwc/pcie-qcom-common.h index 5c01f6c18b3b..c7eb87aa0677 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-common.h +++ b/drivers/pci/controller/dwc/pcie-qcom-common.h @@ -11,3 +11,4 @@ struct icc_path *qcom_pcie_common_icc_get_resource(struct dw_pcie *pci, const ch int qcom_pcie_common_icc_init(struct dw_pcie *pci, struct icc_path *icc_mem); void qcom_pcie_common_icc_update(struct dw_pcie *pci, struct icc_path *icc_mem); void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci); +void qcom_pcie_common_set_16gt_rx_margining_settings(struct dw_pcie *pci); diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 7940222d35f6..2aea78da9c5b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -438,8 +438,10 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) goto err_disable_resources; } - if (pcie_link_speed[pci->link_gen] == PCIE_SPEED_16_0GT) + if (pcie_link_speed[pci->link_gen] == PCIE_SPEED_16_0GT) { qcom_pcie_common_set_16gt_eq_settings(pci); + qcom_pcie_common_set_16gt_rx_margining_settings(pci); + } /* * The physical address of the MMIO region which is exposed as the BAR diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 525942f2cf98..9b3d7729b34b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -263,8 +263,10 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) { struct qcom_pcie *pcie = to_qcom_pcie(pci); - if (pcie_link_speed[pci->link_gen] == PCIE_SPEED_16_0GT) + if (pcie_link_speed[pci->link_gen] == PCIE_SPEED_16_0GT) { qcom_pcie_common_set_16gt_eq_settings(pci); + qcom_pcie_common_set_16gt_rx_margining_settings(pci); + } /* Enable Link Training state machine */ if (pcie->cfg->ops->ltssm_enable)