From patchwork Thu Oct 10 17:15:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 175791 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp2583122ocf; Thu, 10 Oct 2019 10:15:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqwR6EPqdoysXNxbgPQLOS0NXdqhehloMmXlDJ4KUmQpogEq/MHLCmpbbsSH9mAYDKzFAX6Y X-Received: by 2002:aa7:cd06:: with SMTP id b6mr9557970edw.58.1570727737502; Thu, 10 Oct 2019 10:15:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570727737; cv=none; d=google.com; s=arc-20160816; b=ZSzNZMRJZG7AiuIiYb+QaWfjHsyacqa/ItdFgrDOUi1pRhvjkdo4vTsephLyoLhxdk KfDTF8+diUYVXuUd4oDviiXux9zNH6g20mQz9h0o2W6b8a4fSyNwr6u66Nv58HNNM/Bg KunCkOh6I8ve2RPsxj6pMvJxPnJqZmlC2QwIEUWh8QAXLsQ9diqq3pPHgr9nH5r2Xgs3 vtZpVvjskVH7l+yW2XicS/O0wmivzRY9ef8KedH63JBtK4U5kMBmA7fx0ZiiS8ZQVMUN JG/JKyiPlWd3LD0/YjUCkXoyK6tQjZfKM3Ajl7DHsbuSzLIFnxSC1S50MNwT1IOjji5Q exgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=NzoLXkuBE3uZwfTyn3bN45NmrGp2sJl+WrfGjTbOjfA=; b=A19e2jvsaisXEBC+jDZtiAxbSZc2HUNc8vl5A4YwJJ3IMxMCg/qKpmdj94B5jhO6tK Ui2Xkf17evBMpHMGHY6aDoSq9zVD/vLBq+XRbW8YsD4dIkEQx7BHz2/mWQKjOl7kFVX8 X5VChNzxYf40rpijYJjTnHyoDfrjBZMb4tjvpE967w3mK4/xoObTmibLXGgH8xFP5o9S nZNbgTML1+sbiZ0KpjmJsRNpgphheyH0v8ukTO4NG8Mos/W5xzLs4esL2P9K2xBBeODv Nd8WM33RWGVkVl4e8E7obJY7tDwKNi/KHvxclqmGqJeZ0j6RT0k8StIHBAzU85NuKU/R y7Zw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l20si3417247ejb.111.2019.10.10.10.15.37; Thu, 10 Oct 2019 10:15:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726799AbfJJRPg (ORCPT + 21 others); Thu, 10 Oct 2019 13:15:36 -0400 Received: from foss.arm.com ([217.140.110.172]:36346 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726479AbfJJRPf (ORCPT ); Thu, 10 Oct 2019 13:15:35 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 76E4C1000; Thu, 10 Oct 2019 10:15:35 -0700 (PDT) Received: from dawn-kernel.cambridge.arm.com (unknown [10.1.197.116]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 74C4B3F71A; Thu, 10 Oct 2019 10:15:34 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, will@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, dave.martin@arm.com, Suzuki K Poulose Subject: [PATCH 1/3] arm64: cpufeature: Fix the type of no FP/SIMD capability Date: Thu, 10 Oct 2019 18:15:15 +0100 Message-Id: <20191010171517.28782-2-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191010171517.28782-1-suzuki.poulose@arm.com> References: <20191010171517.28782-1-suzuki.poulose@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The NO_FPSIMD capability is defined with scope SYSTEM, which implies that the "absence" of FP/SIMD on at least one CPU is detected only after all the SMP CPUs are brought up. However, we use the status of this capability for every context switch. So, let us change the scop to LOCAL_CPU to allow the detection of this capability as and when the first CPU without FP is brought up. Also, the current type allows hotplugged CPU to be brought up without FP/SIMD when all the current CPUs have FP/SIMD and we have the userspace up. Fix both of these issues by changing the capability to BOOT_RESTRICTED_LOCAL_CPU_FEATURE. Fixes: 82e0191a1aa11abf ("arm64: Support systems without FP/ASIMD") Cc: Will Deacon Cc: Mark Rutland Cc: Catalin Marinas Signed-off-by: Suzuki K Poulose --- arch/arm64/kernel/cpufeature.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.21.0 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 9323bcc40a58..0f9eace6c64b 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1361,7 +1361,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { { /* FP/SIMD is not implemented */ .capability = ARM64_HAS_NO_FPSIMD, - .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, .min_field_value = 0, .matches = has_no_fpsimd, }, From patchwork Thu Oct 10 17:15:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 175792 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp2583205ocf; Thu, 10 Oct 2019 10:15:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqwgS1VBG0A4NCXDuOXjfdFntinzrWHTH4Lc5AQ26euBTbcfwP4U6D+1galozTH9bAQiYhd7 X-Received: by 2002:a17:906:4748:: with SMTP id j8mr9410362ejs.210.1570727742080; Thu, 10 Oct 2019 10:15:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570727742; cv=none; d=google.com; s=arc-20160816; b=D4P1Yf1wfNR73wp0yTCtceV8sTZYPdpgMXSZvLubTE9mfKgo46JojDdUhkN28Xu34Y cl67fErPwOZhqBESQpejgL9JHm0XO5OlIt7AlTe7aItAGJf84mr/6sYQLhKsVmWsYYsC wb7RqVPt3RDV1FRgbD7L3ZUncapmQvRxKR3VOICoRNck7EQmoXbXtYxG+BC9vHPfgRw7 6pU5x8JqTNoWUcWjkdNy5U2GUwYT2/xKatlW1O9x/HTXrL1kc0hH1z2HB1OuHB1V8ReA /auGBD+InhO/p6LPsSD++LGXyJaUVFp8QHTmlJtBGk5RthUYGz271wCPgE2juLkuNeKz Vi6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=+rM4zS/Onf5YiA3s+mqs5kRYJU1pQ4FreUmTpVyJX3U=; b=i+nBQMbN09U5MQ67g8OxSt6kHNZ+WQLfhGRbWm0WBP5S2J00juEC5FffjTe34QbHIZ QPQ/+kAJDU0yYOz1l0X1SNmJ4+novCCEOSIiij108UhFrz9eXSysaFZpJJr+c6Wd4tjI TwV0S1KNVLbcy6OV+lychXkJ/p9aVANATA0O6yWA51R9O8WNnx3a3uXJGupq6Tk1oT9C QPIQi/u2cSwE8/twKhal/835nfMoAnQwL3MLcJLlTBuTQk3YnMKBpjqCBvOQ2g07D15a D6eUtpHa/PDj49Cb5BYgBvwwWaU3kEVwOz/jt2wzgV+YwbTpT0hOSCugfkxzXpHj1Ssm Io3w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z26si3421168ejw.359.2019.10.10.10.15.41; Thu, 10 Oct 2019 10:15:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726824AbfJJRPj (ORCPT + 21 others); Thu, 10 Oct 2019 13:15:39 -0400 Received: from foss.arm.com ([217.140.110.172]:36356 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726796AbfJJRPh (ORCPT ); Thu, 10 Oct 2019 13:15:37 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AC89C1570; Thu, 10 Oct 2019 10:15:36 -0700 (PDT) Received: from dawn-kernel.cambridge.arm.com (unknown [10.1.197.116]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AA6B13F71A; Thu, 10 Oct 2019 10:15:35 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, will@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, dave.martin@arm.com, Suzuki K Poulose Subject: [PATCH 2/3] arm64: nofpsmid: Clear TIF_FOREIGN_FPSTATE flag for early tasks Date: Thu, 10 Oct 2019 18:15:16 +0100 Message-Id: <20191010171517.28782-3-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191010171517.28782-1-suzuki.poulose@arm.com> References: <20191010171517.28782-1-suzuki.poulose@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We detect the absence of FP/SIMD after we boot the SMP CPUs, and by then we have kernel threads running already with TIF_FOREIGN_FPSTATE set which could be inherited by early userspace applications (e.g, modprobe triggered from initramfs). This could end up in the applications stuck in do_nofity_resume() as we never clear the TIF flag, once we now know that we don't support FP. Fix this by making sure that we clear the TIF_FOREIGN_FPSTATE flag for tasks which may have them set, as we would have done in the normal case, but avoiding touching the hardware state (since we don't support any). Fixes: 82e0191a1aa11abf ("arm64: Support systems without FP/ASIMD") Cc: Will Deacon Cc: Mark Rutland Cc: Catalin Marinas Signed-off-by: Suzuki K Poulose --- arch/arm64/kernel/fpsimd.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) -- 2.21.0 diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index 37d3912cfe06..dfcdd077aeca 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -1128,12 +1128,19 @@ void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *st, void *sve_state, */ void fpsimd_restore_current_state(void) { - if (!system_supports_fpsimd()) - return; - get_cpu_fpsimd_context(); - - if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) { + /* + * For the tasks that were created before we detected the absence of + * FP/SIMD, the TIF_FOREIGN_FPSTATE could be set via fpsimd_thread_switch() + * and/or could be inherited from the parent(init_task has this set). Even + * though userspace has not run yet, this could be inherited by the + * processes forked from one of those tasks (e.g, modprobe from initramfs). + * If the system doesn't support FP/SIMD, we must clear the flag for the + * tasks mentioned above, to indicate that the FPSTATE is clean (as we + * can't have one) to avoid looping for ever to clear the flag. + */ + if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE) && + system_supports_fpsimd()) { task_fpsimd_load(); fpsimd_bind_task_to_cpu(); } @@ -1148,17 +1155,16 @@ void fpsimd_restore_current_state(void) */ void fpsimd_update_current_state(struct user_fpsimd_state const *state) { - if (!system_supports_fpsimd()) - return; - get_cpu_fpsimd_context(); current->thread.uw.fpsimd_state = *state; if (system_supports_sve() && test_thread_flag(TIF_SVE)) fpsimd_to_sve(current); - task_fpsimd_load(); - fpsimd_bind_task_to_cpu(); + if (system_supports_fpsimd()) { + task_fpsimd_load(); + fpsimd_bind_task_to_cpu(); + } clear_thread_flag(TIF_FOREIGN_FPSTATE); From patchwork Thu Oct 10 17:15:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 175793 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp2583225ocf; Thu, 10 Oct 2019 10:15:43 -0700 (PDT) X-Google-Smtp-Source: APXvYqzO9UvZhWGDmr2tGwbrsVaoU7U+fF1tgTJ/AoBItCACx1kvTdTBKVX1TLxu4OOu167cjHYE X-Received: by 2002:a17:906:e113:: with SMTP id gj19mr9309731ejb.203.1570727743288; Thu, 10 Oct 2019 10:15:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570727743; cv=none; d=google.com; s=arc-20160816; b=tetLvNmVE0WYT9/g6YRwnr9tOMl4+URUtqJGA7fHI6KcLjtuqp/GcA222ucfuc5+eV nyw5zgyvODZgffJK9A7Huvg0xxEUpJPubh/PhDughv/PguCteAGm0CPqbBBMSzBtkrr7 bOxwYKG79xKXmlyCNxtdnn1uFcE6mm07338pRHzyEl/Yz+cB2bvNkV5BIM+xDA2857B5 ta2HlXVTmx1r6EUA9pywRQX5tfV10Nai6ejceFoc5uPaldkCHpZ+cwtQtNECXuop/COM Pp8iUyKdv4/M8G1TlN5YuQcr0tBeJPet7qIjXpxeAOYbcm+lSCJb93Ww4XvX7VuzeIYi VJHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=BJ4ecw+HrtACYhIwbizW6JZN3rIWyiazTOVeg3qBUcM=; b=AX+HKlodT1lfi82rQx3SFBN3/yjM0oYPZj8q3bvTWMN+tXPYj/MfXE9GEE4gD1cdWi UlVAtynwcMAaOv0LzxhsDl06ndLye7qaAi0K2tz3t/6oMkPDfJI3cEzV75x+tOgWq88h Rgu2wehyR6Y0GN1ofI6QJyYE9g3tmJcPkrNzIBjgwGtcQufHFJanYDGnFYC5t2JZRU5N nZDb4OxAyNa3uSeRoOeaC+l+3FrdFn+kNDRwkesAnzHf6Y8a9fJ/LKPTRUPKzc77aoVJ ty16tRMe0t4Vvtfl63gcBaSplZoNIzqfl7CTYIRznIhbvXpnlUQeuCY+52+vlB5mwRVQ D8Dg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z26si3421168ejw.359.2019.10.10.10.15.43; Thu, 10 Oct 2019 10:15:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726836AbfJJRPm (ORCPT + 21 others); Thu, 10 Oct 2019 13:15:42 -0400 Received: from foss.arm.com ([217.140.110.172]:36362 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726800AbfJJRPi (ORCPT ); Thu, 10 Oct 2019 13:15:38 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E279E1597; Thu, 10 Oct 2019 10:15:37 -0700 (PDT) Received: from dawn-kernel.cambridge.arm.com (unknown [10.1.197.116]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E02AE3F71A; Thu, 10 Oct 2019 10:15:36 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, will@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, dave.martin@arm.com, Suzuki K Poulose Subject: [PATCH 3/3] arm64: cpufeature: Set the FP/SIMD compat HWCAP bits properly Date: Thu, 10 Oct 2019 18:15:17 +0100 Message-Id: <20191010171517.28782-4-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191010171517.28782-1-suzuki.poulose@arm.com> References: <20191010171517.28782-1-suzuki.poulose@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We set the compat_elf_hwcap bits unconditionally on arm64 to include the VFP and NEON support. However, the FP/SIMD unit is optional on Arm v8 and thus could be missing. We already handle this properly in the kernel, but still advertise to the COMPAT applications that the VFP is available. Fix this to make sure we only advertise when we really have them. Fixes: 82e0191a1aa11abf ("arm64: Support systems without FP/ASIMD") Cc: Will Deacon Cc: Catalin Marinas Cc: Mark Rutland Signed-off-by: Suzuki K Poulose --- Changes since v1: - Switch to using cpuid_feature_extract_unsigned_field() rather than hard coding field extraction. --- arch/arm64/kernel/cpufeature.c | 37 +++++++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) -- 2.21.0 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 0f9eace6c64b..d260e3bdf07b 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -32,9 +32,7 @@ static unsigned long elf_hwcap __read_mostly; #define COMPAT_ELF_HWCAP_DEFAULT \ (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ - COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ - COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ - COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\ + COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ COMPAT_HWCAP_LPAE) unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; unsigned int compat_elf_hwcap2 __read_mostly; @@ -1589,6 +1587,12 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .match_list = list, \ } +#define HWCAP_CAP_MATCH(match, cap_type, cap) \ + { \ + __HWCAP_CAP(#cap, cap_type, cap) \ + .matches = match, \ + } + #ifdef CONFIG_ARM64_PTR_AUTH static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { { @@ -1662,8 +1666,35 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { {}, }; +#ifdef CONFIG_COMPAT +static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) +{ + /* + * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, + * in line with that of arm32 as in vfp_init(). We make sure that the + * check is future proof, by making sure value is non-zero. + */ + u32 mvfr1; + + WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); + if (scope == SCOPE_SYSTEM) + mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); + else + mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); + + return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && + cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && + cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); +} +#endif + static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { #ifdef CONFIG_COMPAT + HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), + HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), + /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ + HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), + HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),