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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w17-20020a05600c475100b004162d06768bsm6886839wmo.21.2024.04.18.08.20.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 08:20:05 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/5] docs/system/arm/emulation.rst: Add missing implemented features Date: Thu, 18 Apr 2024 16:20:00 +0100 Message-Id: <20240418152004.2106516-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240418152004.2106516-1-peter.maydell@linaro.org> References: <20240418152004.2106516-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org As of version DDI0487K.a of the Arm ARM, some architectural features which previously didn't have official names have been named. Add these to the list of features which QEMU's TCG emulation supports. Mostly these are features which we thought of as part of baseline 8.0 support. For SVE and SVE2, the names have been brought into line with the FEAT_* naming convention of other extensions, and some sub-components split into separate FEAT_ items. In a few cases (eg FEAT_CCIDX, FEAT_DPB2) the omission from our list was just an oversight. Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 37 +++++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 2a7bbb82dc4..9388c7dd553 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -8,13 +8,25 @@ Armv8 versions of the A-profile architecture. It also has support for the following architecture extensions: - FEAT_AA32BF16 (AArch32 BFloat16 instructions) +- FEAT_AA32EL0 (Support for AArch32 at EL0) +- FEAT_AA32EL1 (Support for AArch32 at EL1) +- FEAT_AA32EL2 (Support for AArch32 at EL2) +- FEAT_AA32EL3 (Support for AArch32 at EL3) - FEAT_AA32HPD (AArch32 hierarchical permission disables) - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions) +- FEAT_AA64EL0 (Support for AArch64 at EL0) +- FEAT_AA64EL1 (Support for AArch64 at EL1) +- FEAT_AA64EL2 (Support for AArch64 at EL2) +- FEAT_AA64EL3 (Support for AArch64 at EL3) +- FEAT_AdvSIMD (Advanced SIMD Extension) - FEAT_AES (AESD and AESE instructions) +- FEAT_ASID16 (16 bit ASID) - FEAT_BBM at level 2 (Translation table break-before-make levels) - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) +- FEAT_CCIDX (Extended cache index) - FEAT_CRC32 (CRC32 instructions) +- FEAT_Crypto (Cryptographic Extension) - FEAT_CSV2 (Cache speculation variant 2) - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) @@ -23,18 +35,27 @@ the following architecture extensions: - FEAT_DGH (Data gathering hint) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) +- FEAT_DPB2 (DC CVADP instruction) +- FEAT_Debugv8p1 (Debug with VHE) - FEAT_Debugv8p2 (Debug changes for v8.2) - FEAT_Debugv8p4 (Debug changes for v8.4) - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_DoubleFault (Double Fault Extension) - FEAT_E0PD (Preventing EL0 access to halves of address maps) - FEAT_ECV (Enhanced Counter Virtualization) +- FEAT_EL0 (Support for execution at EL0) +- FEAT_EL1 (Support for execution at EL1) +- FEAT_EL2 (Support for execution at EL2) +- FEAT_EL3 (Support for execution at EL3) - FEAT_EPAC (Enhanced pointer authentication) - FEAT_ETS (Enhanced Translation Synchronization) - FEAT_EVT (Enhanced Virtualization Traps) +- FEAT_F32MM (Single-precision Matrix Multiplication) +- FEAT_F64MM (Double-precision Matrix Multiplication) - FEAT_FCMA (Floating-point complex number instructions) - FEAT_FGT (Fine-Grained Traps) - FEAT_FHM (Floating-point half-precision multiplication instructions) +- FEAT_FP (Floating Point extensions) - FEAT_FP16 (Half-precision floating-point data processing) - FEAT_FPAC (Faulting on AUT* instructions) - FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions) @@ -60,10 +81,13 @@ the following architecture extensions: - FEAT_LSE (Large System Extensions) - FEAT_LSE2 (Large System Extensions v2) - FEAT_LVA (Large Virtual Address space) +- FEAT_MixedEnd (Mixed-endian support) +- FEAT_MixdEndEL0 (Mixed-endian support at EL0) - FEAT_MOPS (Standardization of memory operations) - FEAT_MTE (Memory Tagging Extension) - FEAT_MTE2 (Memory Tagging Extension) - FEAT_MTE3 (MTE Asymmetric Fault Handling) +- FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults) - FEAT_NV (Nested Virtualization) - FEAT_NV2 (Enhanced nested virtualization support) - FEAT_PACIMP (Pointer authentication - IMPLEMENTATION DEFINED algorithm) @@ -75,6 +99,7 @@ the following architecture extensions: - FEAT_PAuth (Pointer authentication) - FEAT_PAuth2 (Enhancements to pointer authentication) - FEAT_PMULL (PMULL, PMULL2 instructions) +- FEAT_PMUv3 (PMU extension version 3) - FEAT_PMUv3p1 (PMU Extensions v3.1) - FEAT_PMUv3p4 (PMU Extensions v3.4) - FEAT_PMUv3p5 (PMU Extensions v3.5) @@ -96,8 +121,18 @@ the following architecture extensions: - FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode) - FEAT_SME_F64F64 (Double-precision floating-point outer product instructions) - FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions) +- FEAT_SVE (Scalable Vector Extension) +- FEAT_SVE_AES (Scalable Vector AES instructions) +- FEAT_SVE_BitPerm (Scalable Vector Bit Permutes instructions) +- FEAT_SVE_PMULL128 (Scalable Vector PMULL instructions) +- FEAT_SVE_SHA3 (Scalable Vector SHA3 instructions) +- FEAT_SVE_SM4 (Scalable Vector SM4 instructions) +- FEAT_SVE2 (Scalable Vector Extension version 2) - FEAT_SPECRES (Speculation restriction instructions) - FEAT_SSBS (Speculative Store Bypass Safe) +- FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1) +- FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1) +- FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1) - FEAT_TIDCP1 (EL0 use of IMPLEMENTATION DEFINED functionality) - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain) - FEAT_TLBIRANGE (TLB invalidate range instructions) @@ -108,8 +143,6 @@ the following architecture extensions: - FEAT_VHE (Virtualization Host Extensions) - FEAT_VMID16 (16-bit VMID) - FEAT_XNX (Translation table stage 2 Unprivileged Execute-never) -- SVE (The Scalable Vector Extension) -- SVE2 (The Scalable Vector Extension v2) For information on the specifics of these extensions, please refer to the `Armv8-A Arm Architecture Reference Manual From patchwork Thu Apr 18 15:20:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 789786 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp623207wrm; Thu, 18 Apr 2024 08:22:15 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXNOmjh+0yvrLMo3gp4MgBcXIYCICK0LqzbgGF9IBp2CzA3B98KNYNdgPKG1SL2A3V45lo7EkKqbyy6EudqzZU4 X-Google-Smtp-Source: AGHT+IFo1IHjjoUEHocnQsNw64sCGo9bSIzoj1OPNSt9u32cpCeDIT2jhOjT4cKuyCw4Vq0mK8dF X-Received: by 2002:a05:620a:438a:b0:78e:fe6b:5e5f with SMTP id a10-20020a05620a438a00b0078efe6b5e5fmr3919425qkp.47.1713453735017; Thu, 18 Apr 2024 08:22:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713453735; cv=none; d=google.com; s=arc-20160816; b=bD/kpLl0Fww4pzuGawdzWNv6bIDj0wEe1MUK/dwWIElSYv/tm8AC6/1f8K6ydQSYYf jSYve8rU/J97lwCXY4kRXRrXWgJmBraOa0HlfPALEuKohj7aDcPSlOCFRhisaSO2Gubt d+qN6WMy+wD/swdXyrEQojxxgNNaFP4oROfe7EAADsA8RwwpSYmIoOU55WOp55yJZEls u93x373iaPvQiZF2+iOmbc/dsCc1mIfnZPW43yWT8sZjTemz5hMVD2jtefO7al9gmCKu xmM8JQb2cK8Z9Y3wW53RL72Jmm8LYaEU1yfB3Gjamc6deXrNE4mUoju7INP0/wP47ANn om4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HR4H5Zi29P/KVcxukA597bVylKrZeVE9mrUkxAza3G0=; fh=tptECk+5zD3v1R32/hEWhHwWAnkc0ylJ4mVG57TF6yw=; b=lOWvakzSNvBBIov4TJDOuWNFFHANUdQkjsvsNqDzvbELnWC9yJIJse/nCwN0OkScp+ QbSrK4HGmICDVT7ILLgdTCauFPMBSkgI/lNJUTf0XNTxLRlbeJni+bQWucsVGHRGZV2r 865qlIvBw10h2utIcwtd5SMSScu76Kovlq3CDfMN2oQkXxIz9EHrCCbrg9aDZusBVITi 7dhE4U1oHeR769Vzqd7qpbcwxHy5DXn38ANnY1cYG9Whc5k6wowIatNEwIg8qhp/pz45 DEqnhciHulm2o6GvuuZnGRCEHsd8/izWiCPnMEcQquNCzrfIcec69cAZPM1TIzO2LqSz sMTA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Uw1IcSpd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w17-20020a05600c475100b004162d06768bsm6886839wmo.21.2024.04.18.08.20.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 08:20:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/5] target/arm: Enable FEAT_CSV2_3 for -cpu max Date: Thu, 18 Apr 2024 16:20:01 +0100 Message-Id: <20240418152004.2106516-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240418152004.2106516-1-peter.maydell@linaro.org> References: <20240418152004.2106516-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::236; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org FEAT_CSV2_3 adds a mechanism to identify if hardware cannot disclose information about whether branch targets and branch history trained in one hardware described context can control speculative execution in a different hardware context. There is no branch prediction in TCG, so we don't need to do anything to be compliant with this. Upadte the '-cpu max' ID registers to advertise the feature. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 9388c7dd553..958c69f3799 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -31,6 +31,7 @@ the following architecture extensions: - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) - FEAT_CSV2_2 (Cache speculation variant 2, version 2) +- FEAT_CSV2_3 (Cache speculation variant 2, version 3) - FEAT_CSV3 (Cache speculation variant 3) - FEAT_DGH (Data gathering hint) - FEAT_DIT (Data Independent Timing instructions) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 9f7a9f3d2cc..4445c5a212b 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1159,7 +1159,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ - t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ + t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* FEAT_CSV2_3 */ t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ cpu->isar.id_aa64pfr0 = t; @@ -1174,7 +1174,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */ t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ - t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ + t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */ cpu->isar.id_aa64pfr1 = t; t = cpu->isar.id_aa64mmfr0; From patchwork Thu Apr 18 15:20:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 789782 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp622875wrm; Thu, 18 Apr 2024 08:21:35 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXvcWJXRhUJ7vjfZrU5fjSecVjax5+GrXFbJeasxN87b/OSmXN1HU+WM6WFu6o/NmKXc9qYqWSFCZVOkRBzHYrK X-Google-Smtp-Source: AGHT+IHMjBU5K/HlCbCEG9ghMZNSdF7dpqnJ6JQp2FqOkdUKJKeTLqK7XwPd6Scs5Nsv+bgs7roL X-Received: by 2002:a05:6214:4a44:b0:69b:551b:ef88 with SMTP id ph4-20020a0562144a4400b0069b551bef88mr2836739qvb.50.1713453694889; Thu, 18 Apr 2024 08:21:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713453694; cv=none; d=google.com; s=arc-20160816; b=y3X0kWLBOfpOZniixCe8vowCTdnNJbV909SB8DKQyo3VvsGex1hKv1n1KBCx8tD9Cp XUwQhQefO3ZE5jqXC2HZBJTAYZIggUCWtlA6LtHtQn0D4Z3gyRdCOikjFblgQv75s6Ib euRoF+KV0eb1FHcW4Q0CXYG54DZeHrPvUWYQbO3Zx2owOd595JZgn6XeR31zAUfR7w2g A4xPU4t+wGQ37Ew9ijqRfcHGoCReaFZ0Und6xRKyYvayC8aLGwAuujzZ2hbd6uKBP9b6 PIkYEb4pDYyWMpZ1TRVKKcY6cSxU6WtnIepeSH9Vp5Wb4vnXWZSOvQfgTBRdNwC1vj4h iU8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=n5QqC5TWO216H4QGIIquQv5JWDc3hZs2/K7GnFUQidw=; fh=37Q4AChYHp1OoMckvXDybHAkumcg9/JX+jDrrWJ03x8=; b=bGeC0TQgFcuEhDkj3wj7Osl1H/Kr+GhnLkG1Sss7dajPtOBMJ2+13OyHDEXQjAMplD bjzsmPbGHGqC+2oJcbvqmq839utEfbukLLi1QPA1wWFI1wYDjAa01QFa7jL1+6gIRkUX Bp8iJdnUNLfr0xUxha2I9Pvu3ISI8RQ669PcIJvyMM2NiNuXt/AZSaM2C3H3cvK4o4Dn l7n67fQBo6U6IAL91NXggGvlbbv0FTu6BuAoswL8ondInY5EblBeWllp/VoFiq+fKYXT 0+9o5k+V99m3WjydvQUxNIzErSwdYWuCFNGeqmmlwDR2sJCkr7SmuFZiavq0dvudx6a7 buWA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tJbHDLDz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w17-20020a05600c475100b004162d06768bsm6886839wmo.21.2024.04.18.08.20.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 08:20:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/5] target/arm: Enable FEAT_ETS2 for -cpu max Date: Thu, 18 Apr 2024 16:20:02 +0100 Message-Id: <20240418152004.2106516-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240418152004.2106516-1-peter.maydell@linaro.org> References: <20240418152004.2106516-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org FEAT_ETS2 is a tighter set of guarantees about memory ordering involving translation table walks than the old FEAT_ETS; FEAT_ETS has been retired from the Arm ARM and the old ID_AA64MMFR1.ETS == 1 now gives no greater guarantees than ETS == 0. FEAT_ETS2 requires: * the virtual address of a load or store that appears in program order after a DSB cannot be translated until after the DSB completes (section B2.10.9) * TLB maintenance operations that only affect translations without execute permission are guaranteed complete after a DSB (R_BLDZX) * if a memory access RW2 is ordered-before memory access RW2, then RW1 is also ordered-before any translation table walk generated by RW2 that generates a Translation, Address size or Access flag fault (R_NNFPF, I_CLGHP) As with FEAT_ETS, QEMU is already compliant, because we do not reorder translation table walk memory accesses relative to other memory accesses, and we always guarantee to have finished TLB maintenance as soon as the TLB op is done. Update the documentation to list FEAT_ETS2 instead of the no-longer-existent FEAT_ETS, and update the 'max' CPU ID registers. Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 2 +- target/arm/tcg/cpu32.c | 2 +- target/arm/tcg/cpu64.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 958c69f3799..de39110692b 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -49,7 +49,7 @@ the following architecture extensions: - FEAT_EL2 (Support for execution at EL2) - FEAT_EL3 (Support for execution at EL3) - FEAT_EPAC (Enhanced pointer authentication) -- FEAT_ETS (Enhanced Translation Synchronization) +- FEAT_ETS2 (Enhanced Translation Synchronization) - FEAT_EVT (Enhanced Virtualization Traps) - FEAT_F32MM (Single-precision Matrix Multiplication) - FEAT_F64MM (Double-precision Matrix Multiplication) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index de8f2be9416..b5a60682fa6 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -67,7 +67,7 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_mmfr4 = t; t = cpu->isar.id_mmfr5; - t = FIELD_DP32(t, ID_MMFR5, ETS, 1); /* FEAT_ETS */ + t = FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ cpu->isar.id_mmfr5 = t; t = cpu->isar.id_pfr0; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 4445c5a212b..da15182595b 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1195,7 +1195,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */ t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ - t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */ + t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 2); /* FEAT_ETS2 */ t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ t = FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */ cpu->isar.id_aa64mmfr1 = t; From patchwork Thu Apr 18 15:20:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 789787 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp623237wrm; Thu, 18 Apr 2024 08:22:19 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWUgoYchQ3mdEAfYe1Pukv6NNSbzliUjKbxIcHQt1TMd5krfQOOSGmg5zUOVhERRw+dUEHfQVNRTn6cYjJtG+p4 X-Google-Smtp-Source: AGHT+IGM9pN4PbyFUGA4u8dCs5RN1h1g/Hefm+HiCUTsEZXOZjeYV97y8ue7LaPbx7mVMHODdD8J X-Received: by 2002:a05:622a:50d:b0:437:871a:bca5 with SMTP id l13-20020a05622a050d00b00437871abca5mr3094802qtx.67.1713453738845; Thu, 18 Apr 2024 08:22:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713453738; cv=none; d=google.com; s=arc-20160816; b=HZFlZ9rMm0qE0lTRoDBDUQ4wwow+eHULqSafDIu9aakeovJt8F6N8B/c0V8FQDAq32 ehHIMMGzaePyA3aEuA9h9oG8qMLaxdpgF6am5SJ9tjJFQx63HTkdKgJBnyuQXlUi1GYj GsGS/Z8uhg6d3GaP4O3tw9uiDAI2X2Px2hxt69p/Tdq/8WK/nPbiW6gsPd7kndb/k2tZ 4gYH4E9qYRmt9OKhgBqzVCUBgfHCdb/nFEBqCY7b+4+COHhTgo5cFAquSG2YTxuwXhq3 eSrsPDfWkxUJ4UF6yBabNte2cE5RdAo68Vtzqi1voJj4JaTR3B65O+a0SbbpC/aPAShf HRIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EgUWdXzTtkS0pYgFkeqEh/AXA2JNP+NIqv08IWtEXT8=; fh=VnRXq+hs/q00N11gTUugLTpsr98gMjpeIS/J1ZanuYs=; b=pDN8/7Ry32dhfHa/oyrlCmngAP5ezsqiWz5WArQ7XE7+hpcJpXJtNd7QeewLV+Sxzm pcbJqcNJ4tFhPI0XB8dViWdrEGsTB4nyV8gy7G5YHUnpmBIkw7ZoGXn0A7n4GKD989dt H7jRmCW388Z9ZIqjW0199nMRYKwTECX6a18H7nkcXnD0o8M/D00aEmbXiJbwJR/l75ji 6IMsgtoySUJHYGPF2NVCw/GdDHJqiZRPJHlAYILyGcRPv1jvbhNmUjfOpr0/MX0vfk9/ iljk6F+AgjUr3LN11b7n9SaZ2CV9nZPJ1JONAEulIAX2IMjqpqd4FX+mIO7v79mE4KzH 44DA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zzFOP1lA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w17-20020a05600c475100b004162d06768bsm6886839wmo.21.2024.04.18.08.20.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 08:20:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 4/5] target/arm: Implement ID_AA64MMFR3_EL1 Date: Thu, 18 Apr 2024 16:20:03 +0100 Message-Id: <20240418152004.2106516-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240418152004.2106516-1-peter.maydell@linaro.org> References: <20240418152004.2106516-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Newer versions of the Arm ARM (e.g. rev K.a) now define fields for ID_AA64MMFR3_EL1. Implement this register, so that we can set the fields if we need to. There's no behaviour change here since we don't currently set the register value to non-zero. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 17 +++++++++++++++++ target/arm/helper.c | 6 ++++-- target/arm/hvf/hvf.c | 2 ++ target/arm/kvm.c | 2 ++ 4 files changed, 25 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bc0c84873ff..20d8257c853 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1008,6 +1008,7 @@ struct ArchCPU { uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; uint64_t id_aa64mmfr2; + uint64_t id_aa64mmfr3; uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; uint64_t id_aa64zfr0; @@ -2200,6 +2201,22 @@ FIELD(ID_AA64MMFR2, BBM, 52, 4) FIELD(ID_AA64MMFR2, EVT, 56, 4) FIELD(ID_AA64MMFR2, E0PD, 60, 4) +FIELD(ID_AA64MMFR3, TCRX, 0, 4) +FIELD(ID_AA64MMFR3, SCTLRX, 4, 4) +FIELD(ID_AA64MMFR3, S1PIE, 8, 4) +FIELD(ID_AA64MMFR3, S2PIE, 12, 4) +FIELD(ID_AA64MMFR3, S1POE, 16, 4) +FIELD(ID_AA64MMFR3, S2POE, 20, 4) +FIELD(ID_AA64MMFR3, AIE, 24, 4) +FIELD(ID_AA64MMFR3, MEC, 28, 4) +FIELD(ID_AA64MMFR3, D128, 32, 4) +FIELD(ID_AA64MMFR3, D128_2, 36, 4) +FIELD(ID_AA64MMFR3, SNERR, 40, 4) +FIELD(ID_AA64MMFR3, ANERR, 44, 4) +FIELD(ID_AA64MMFR3, SDERR, 52, 4) +FIELD(ID_AA64MMFR3, ADERR, 56, 4) +FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) + FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) FIELD(ID_AA64DFR0, TRACEVER, 4, 4) FIELD(ID_AA64DFR0, PMUVER, 8, 4) diff --git a/target/arm/helper.c b/target/arm/helper.c index a620481d7cf..8bdbb404195 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8932,11 +8932,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, .resetvalue = cpu->isar.id_aa64mmfr2 }, - { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_AA64MMFR3_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = 0 }, + .resetvalue = cpu->isar.id_aa64mmfr3 }, { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, @@ -9093,6 +9093,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .exported_bits = R_ID_AA64MMFR1_AFP_MASK }, { .name = "ID_AA64MMFR2_EL1", .exported_bits = R_ID_AA64MMFR2_AT_MASK }, + { .name = "ID_AA64MMFR3_EL1", + .exported_bits = 0 }, { .name = "ID_AA64MMFR*_EL1_RESERVED", .is_glob = true }, { .name = "ID_AA64DFR0_EL1", diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 65a56018041..2cbc66dc791 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -498,6 +498,7 @@ static struct hvf_sreg_match hvf_sreg_match[] = { #endif { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) }, { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) }, + /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) }, { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) }, @@ -856,6 +857,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, + /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ }; hv_vcpu_t fd; hv_return_t r = HV_SUCCESS; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index ab85d628a8b..cfb87f8cba5 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -331,6 +331,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ARM64_SYS_REG(3, 0, 0, 7, 1)); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, ARM64_SYS_REG(3, 0, 0, 7, 2)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr3, + ARM64_SYS_REG(3, 0, 0, 7, 3)); /* * Note that if AArch32 support is not present in the host, From patchwork Thu Apr 18 15:20:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 789784 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp622889wrm; Thu, 18 Apr 2024 08:21:35 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWs252mmbBTqM1qy1Zq06voyCTFZAk+FVm7fP9MajSuBLMfJypcbFrKegj0hcn7NlDr3unI3zfV3JiJHD70avjY X-Google-Smtp-Source: AGHT+IFw9Lx/6NsHiXt+GdwujNtK8FX1IXXyS0E/4jDev6eVBGomX1Yzxy3M9E0XGdSEh9v5OkNz X-Received: by 2002:a05:6214:1fda:b0:69f:793d:cade with SMTP id jh26-20020a0562141fda00b0069f793dcademr3396608qvb.19.1713453695571; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w17-20020a05600c475100b004162d06768bsm6886839wmo.21.2024.04.18.08.20.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 08:20:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 5/5] target/arm: Enable FEAT_Spec_FPACC for -cpu max Date: Thu, 18 Apr 2024 16:20:04 +0100 Message-Id: <20240418152004.2106516-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240418152004.2106516-1-peter.maydell@linaro.org> References: <20240418152004.2106516-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org FEAT_Spec_FPACC is a feature describing speculative behaviour in the event of a PAC authontication failure when FEAT_FPACCOMBINE is implemented. FEAT_Spec_FPACC means that the speculative use of pointers processed by a PAC Authentication is not materially different in terms of the impact on cached microarchitectural state (caches, TLBs, etc) between passing and failing of the PAC Authentication. QEMU doesn't do speculative execution, so we can advertise this feature. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index de39110692b..fc616e48d30 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -60,6 +60,7 @@ the following architecture extensions: - FEAT_FP16 (Half-precision floating-point data processing) - FEAT_FPAC (Faulting on AUT* instructions) - FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions) +- FEAT_FPACC_SPEC (Speculative behavior of combined pointer authentication instructions) - FEAT_FRINTTS (Floating-point to integer instructions) - FEAT_FlagM (Flag manipulation instructions v2) - FEAT_FlagM2 (Enhancements to flag manipulation instructions) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index da15182595b..c3369f40824 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1216,6 +1216,10 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ cpu->isar.id_aa64mmfr2 = t; + t = cpu->isar.id_aa64mmfr3; + t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ + cpu->isar.id_aa64mmfr3 = t; + t = cpu->isar.id_aa64zfr0; t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */