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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240322161439.6448-2-philmd@linaro.org> --- include/gdbstub/helpers.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/include/gdbstub/helpers.h b/include/gdbstub/helpers.h index c573aef2dc..53e88d807c 100644 --- a/include/gdbstub/helpers.h +++ b/include/gdbstub/helpers.h @@ -12,7 +12,10 @@ #ifndef _GDBSTUB_HELPERS_H_ #define _GDBSTUB_HELPERS_H_ -#ifdef NEED_CPU_H +#ifndef NEED_CPU_H +#error "gdbstub helpers should only be included by target specific code" +#endif + #include "cpu.h" /* @@ -96,8 +99,4 @@ static inline uint8_t *gdb_get_reg_ptr(GByteArray *buf, int len) #define ldtul_p(addr) ldl_p(addr) #endif -#else -#error "gdbstub helpers should only be included by target specific code" -#endif - #endif /* _GDBSTUB_HELPERS_H_ */ From patchwork Wed Apr 17 18:27:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 789327 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp173350wrm; Wed, 17 Apr 2024 11:30:58 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWGqQw/h9Orp9mrgDO/HmTb43THmt/oVnlw8YwwaxfmhBpI//G4n7AoSz8tl8vhKTctzWWzk5FLcU4N9/FmUrWo X-Google-Smtp-Source: AGHT+IHnbJfAPDutMrDCxBlvgUi0ZjeYmqLi2YG4bdMs44pw2BB6jCvS+5xQFN+MHepbOXU9RrSy X-Received: by 2002:ac8:7d52:0:b0:434:6ea0:498a with SMTP id h18-20020ac87d52000000b004346ea0498amr373590qtb.33.1713378658129; Wed, 17 Apr 2024 11:30:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713378658; cv=none; d=google.com; s=arc-20160816; b=wSxeI05FqueF+XPVvX72hEYrIOcwSurWQ9iDC733fvEpgp0ZLyzIJh1FHlnNd/fgmr 0Ca7BFb2nsp87Va1ePHV+AGvR5lLmXtuA+ehJTS2rPMxXOiW8R/WkuCrDWY+Zm5Uwtvf pd/2cbpf8SUntOTZJQ75ge+U7zjtZuJTIC1Q9wHMJEd4GGSaR63xGFval5yCDL+mX1Ba 1ehEHidxuSoyw+4T3QMSvS9z/b3wXz+WvXL2QUZjcV+thX/U6FzVmcQvSG+ahMZsr9d0 fJ5m90AZG2pEJQq9qZGkPA7fK49+V2uVzesfX5UX81tr9HAJfJ8xWOoSzfE30LDlVqac dCaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RapDlHBEy1nkY/csZneQutCtWvQO/OhX6r5FqrgGfGI=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=gzpSwuAYFTAhgwvbeYcWygk4jGDIsnhlorshHySX3VdNvAab5JJbOGp/fg36qYEJvj sQnlshJkIMVe5uFJGm/wMJ7E2KtOmQMyzYHeVDt7cL7MKxwHLusZJfAGxpwlyu2A5CDY uD0+Qd2MzWrksThupodPnti1TSXrJ9ODI0UgtBPlMlLdx4VYqm7ssPK1teozBKe+UGav 65ingOFw6uv/qq34fND1xDFKX7ZdK1dy0q7Fd2opjdDG89Ozk0x5gPqbEvSM+aN95H16 eeWAOSvLg644VBxbFYlDyrGjnsX+PJ2GdIIf7+ZS0BGbhR6HwijDIxu6I95jMo7dDHBC jJvA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BeB7WEhg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240322161439.6448-3-philmd@linaro.org> --- include/hw/core/tcg-cpu-ops.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index bf8ff8e3ee..dc1f16a977 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -49,7 +49,6 @@ struct TCGCPUOps { /** @debug_excp_handler: Callback for handling debug exceptions */ void (*debug_excp_handler)(CPUState *cpu); -#ifdef NEED_CPU_H #ifdef CONFIG_USER_ONLY /** * @fake_user_interrupt: Callback for 'fake exception' handling. @@ -174,8 +173,6 @@ struct TCGCPUOps { */ bool (*need_replay_interrupt)(int interrupt_request); #endif /* !CONFIG_USER_ONLY */ -#endif /* NEED_CPU_H */ - }; #if defined(CONFIG_USER_ONLY) From patchwork Wed Apr 17 18:27:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 789315 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp172532wrm; Wed, 17 Apr 2024 11:29:08 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVLP/fUxqES1mJjFG87WHR8dk+2QEbofoKFUKPP0QouQaj2SjpnBPiVpz2axZEq9pGregdPu6UaDUZdJpU4nAJ2 X-Google-Smtp-Source: AGHT+IENBdXBZbKz94oLaNm4ite3luT0O7xj6SxnmqYBTPjpvuNGAmpaPxCYdYol5hEf4ef2jKNA X-Received: by 2002:a05:6214:311:b0:69f:6a4f:9c2f with SMTP id i17-20020a056214031100b0069f6a4f9c2fmr8689094qvu.15.1713378548136; Wed, 17 Apr 2024 11:29:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713378548; cv=none; d=google.com; s=arc-20160816; b=gM9ATzR1U+VdiZcGJsk4Sw3LsEWlfjK6UyTRS60bUBJ024CVq3aVFbDjuV85ybJ0eK SV+d22n9OXqzfJEJUcFAbDBBrcYSBYJUblJqhw+gi3vAf1GxJbBVQBVZgW3Jdrz4Pveb EY1d/xuTgqwzZDx1JA2eur/Pn/bFki4rfZRAG6nWuDtoVPVVhQ1nRSq+oxGBmQ1P0am8 1puLY7+NwBDCRZ0RwDVWtkT++LUC82owXStHeJWN1r18Nt7DOq0mRjEX4Xbl9EhBddnv nTy/21FmxJBX6HsKX9ZvFBmI/boVYOjmr1xsE1V5HxPlYoaXNwWq2ms8dqCAhEqvMfd2 67qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=u1xvIMY6HGx0bbX9xwwNC0zjHJ2ZBSfkq9UJ9n//aGE=; fh=hQGfmLnGt03ozV0BeGtrcDV49eZC+03gzuAusJtHKKE=; b=J5tWQJ2prdeIlwyP05FDCe0LjxX18mwNl8vPFYM+km+lTD2QuZCnIjn0613j/deaao Vo+RMobJOuRaxtHcHZdcsaYP8eP4mOSyv5/0OdUXY99aw/b0ffUCJnl34ndiRLE61ZZi t9wK3obLwYWOfrwnGeT/35IoBUkLB7s4MbY1M3T9feqBPBoY/c62ZVxwC4Vq7LKNDLgV LqAvMOn0TUqPuB4CJlh3dNbPBCvjvmmmr0zwiCoF/2sFpk/qNiAyqv0rTWjL+tVlZQe7 0sFDBpj0YoIokRbVU/B6YhbgbeUYueZalbhoBiB9t3TjECaTC8b4lgo2Ig6HZm6bWwQY V3lA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BTjdy4WY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Rename NEED_CPU_H as COMPILING_PER_TARGET to clarify its meaning. Mechanical change running: $ sed -i s/NEED_CPU_H/COMPILING_PER_TARGET/g $(git grep -l NEED_CPU_H) then manually add a /* COMPILING_PER_TARGET */ comment after the '#endif' when the block is large. Inspired-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240322161439.6448-4-philmd@linaro.org> --- meson.build | 4 ++-- include/exec/cpu-defs.h | 2 +- include/exec/helper-head.h | 4 ++-- include/exec/memop.h | 4 ++-- include/exec/memory.h | 4 ++-- include/exec/tswap.h | 4 ++-- include/gdbstub/helpers.h | 2 +- include/hw/core/cpu.h | 4 ++-- include/qemu/osdep.h | 2 +- include/sysemu/hvf.h | 8 ++++---- include/sysemu/kvm.h | 6 +++--- include/sysemu/nvmm.h | 4 ++-- include/sysemu/whpx.h | 4 ++-- include/sysemu/xen.h | 4 ++-- target/arm/kvm-consts.h | 4 ++-- scripts/analyze-inclusions | 6 +++--- 16 files changed, 33 insertions(+), 33 deletions(-) diff --git a/meson.build b/meson.build index 91a0aa64c6..da8295b405 100644 --- a/meson.build +++ b/meson.build @@ -3641,7 +3641,7 @@ foreach d, list : target_modules if target.endswith('-softmmu') config_target = config_target_mak[target] target_inc = [include_directories('target' / config_target['TARGET_BASE_ARCH'])] - c_args = ['-DNEED_CPU_H', + c_args = ['-DCOMPILING_PER_TARGET', '-DCONFIG_TARGET="@0@-config-target.h"'.format(target), '-DCONFIG_DEVICES="@0@-config-devices.h"'.format(target)] target_module_ss = module_ss.apply(config_target, strict: false) @@ -3824,7 +3824,7 @@ foreach target : target_dirs target_base_arch = config_target['TARGET_BASE_ARCH'] arch_srcs = [config_target_h[target]] arch_deps = [] - c_args = ['-DNEED_CPU_H', + c_args = ['-DCOMPILING_PER_TARGET', '-DCONFIG_TARGET="@0@-config-target.h"'.format(target), '-DCONFIG_DEVICES="@0@-config-devices.h"'.format(target)] link_args = emulator_link_args diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 3915438b83..0dbef3010c 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -19,7 +19,7 @@ #ifndef CPU_DEFS_H #define CPU_DEFS_H -#ifndef NEED_CPU_H +#ifndef COMPILING_PER_TARGET #error cpu.h included from common code #endif diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index 28ceab0a46..5ef467a79d 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -43,7 +43,7 @@ #define dh_ctype_noreturn G_NORETURN void #define dh_ctype(t) dh_ctype_##t -#ifdef NEED_CPU_H +#ifdef COMPILING_PER_TARGET # ifdef TARGET_LONG_BITS # if TARGET_LONG_BITS == 32 # define dh_alias_tl i32 @@ -54,7 +54,7 @@ # endif # endif # define dh_ctype_tl target_ulong -#endif +#endif /* COMPILING_PER_TARGET */ /* We can't use glue() here because it falls foul of C preprocessor recursive expansion rules. */ diff --git a/include/exec/memop.h b/include/exec/memop.h index a86dc6743a..06417ff361 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -35,7 +35,7 @@ typedef enum MemOp { MO_LE = 0, MO_BE = MO_BSWAP, #endif -#ifdef NEED_CPU_H +#ifdef COMPILING_PER_TARGET #if TARGET_BIG_ENDIAN MO_TE = MO_BE, #else @@ -135,7 +135,7 @@ typedef enum MemOp { MO_BESL = MO_BE | MO_SL, MO_BESQ = MO_BE | MO_SQ, -#ifdef NEED_CPU_H +#ifdef COMPILING_PER_TARGET MO_TEUW = MO_TE | MO_UW, MO_TEUL = MO_TE | MO_UL, MO_TEUQ = MO_TE | MO_UQ, diff --git a/include/exec/memory.h b/include/exec/memory.h index 8626a355b3..bb51e90fe1 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -3087,7 +3087,7 @@ address_space_write_cached(MemoryRegionCache *cache, hwaddr addr, MemTxResult address_space_set(AddressSpace *as, hwaddr addr, uint8_t c, hwaddr len, MemTxAttrs attrs); -#ifdef NEED_CPU_H +#ifdef COMPILING_PER_TARGET /* enum device_endian to MemOp. */ static inline MemOp devend_memop(enum device_endian end) { @@ -3105,7 +3105,7 @@ static inline MemOp devend_memop(enum device_endian end) return (end == non_host_endianness) ? MO_BSWAP : 0; #endif } -#endif +#endif /* COMPILING_PER_TARGET */ /* * Inhibit technologies that require discarding of pages in RAM blocks, e.g., diff --git a/include/exec/tswap.h b/include/exec/tswap.h index 68944a880b..5089cd6a4c 100644 --- a/include/exec/tswap.h +++ b/include/exec/tswap.h @@ -15,11 +15,11 @@ * If we're in target-specific code, we can hard-code the swapping * condition, otherwise we have to do (slower) run-time checks. */ -#ifdef NEED_CPU_H +#ifdef COMPILING_PER_TARGET #define target_needs_bswap() (HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN) #else #define target_needs_bswap() (target_words_bigendian() != HOST_BIG_ENDIAN) -#endif +#endif /* COMPILING_PER_TARGET */ static inline uint16_t tswap16(uint16_t s) { diff --git a/include/gdbstub/helpers.h b/include/gdbstub/helpers.h index 53e88d807c..6277a858a1 100644 --- a/include/gdbstub/helpers.h +++ b/include/gdbstub/helpers.h @@ -12,7 +12,7 @@ #ifndef _GDBSTUB_HELPERS_H_ #define _GDBSTUB_HELPERS_H_ -#ifndef NEED_CPU_H +#ifndef COMPILING_PER_TARGET #error "gdbstub helpers should only be included by target specific code" #endif diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index ec14f74ce5..7f037b158e 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1182,7 +1182,7 @@ bool target_words_bigendian(void); const char *target_name(void); -#ifdef NEED_CPU_H +#ifdef COMPILING_PER_TARGET #ifndef CONFIG_USER_ONLY @@ -1197,7 +1197,7 @@ extern const VMStateDescription vmstate_cpu_common; } #endif /* !CONFIG_USER_ONLY */ -#endif /* NEED_CPU_H */ +#endif /* COMPILING_PER_TARGET */ #define UNASSIGNED_CPU_INDEX -1 #define UNASSIGNED_CLUSTER_INDEX -1 diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index c7053cdc2b..f61edcfdc2 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -32,7 +32,7 @@ #endif #include "config-host.h" -#ifdef NEED_CPU_H +#ifdef COMPILING_PER_TARGET #include CONFIG_TARGET #else #include "exec/poison.h" diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h index 4a7c6af3a5..730f927f03 100644 --- a/include/sysemu/hvf.h +++ b/include/sysemu/hvf.h @@ -16,7 +16,7 @@ #include "qemu/accel.h" #include "qom/object.h" -#ifdef NEED_CPU_H +#ifdef COMPILING_PER_TARGET #include "cpu.h" #ifdef CONFIG_HVF @@ -26,7 +26,7 @@ extern bool hvf_allowed; #define hvf_enabled() 0 #endif /* !CONFIG_HVF */ -#endif /* NEED_CPU_H */ +#endif /* COMPILING_PER_TARGET */ #define TYPE_HVF_ACCEL ACCEL_CLASS_NAME("hvf") @@ -34,7 +34,7 @@ typedef struct HVFState HVFState; DECLARE_INSTANCE_CHECKER(HVFState, HVF_STATE, TYPE_HVF_ACCEL) -#ifdef NEED_CPU_H +#ifdef COMPILING_PER_TARGET struct hvf_sw_breakpoint { vaddr pc; vaddr saved_insn; @@ -66,6 +66,6 @@ void hvf_arch_update_guest_debug(CPUState *cpu); * Return whether the guest supports debugging. */ bool hvf_arch_supports_guest_debug(void); -#endif /* NEED_CPU_H */ +#endif /* COMPILING_PER_TARGET */ #endif diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index fad9a7e8ff..c618a59ba6 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -20,7 +20,7 @@ #include "qemu/accel.h" #include "qom/object.h" -#ifdef NEED_CPU_H +#ifdef COMPILING_PER_TARGET # ifdef CONFIG_KVM # include # define CONFIG_KVM_IS_POSSIBLE @@ -210,7 +210,7 @@ bool kvm_arm_supports_user_irq(void); int kvm_on_sigbus_vcpu(CPUState *cpu, int code, void *addr); int kvm_on_sigbus(int code, void *addr); -#ifdef NEED_CPU_H +#ifdef COMPILING_PER_TARGET #include "cpu.h" void kvm_flush_coalesced_mmio_buffer(void); @@ -435,7 +435,7 @@ void kvm_set_sigmask_len(KVMState *s, unsigned int sigmask_len); int kvm_physical_memory_addr_from_host(KVMState *s, void *ram_addr, hwaddr *phys_addr); -#endif /* NEED_CPU_H */ +#endif /* COMPILING_PER_TARGET */ void kvm_cpu_synchronize_state(CPUState *cpu); diff --git a/include/sysemu/nvmm.h b/include/sysemu/nvmm.h index be7bc9a62d..6971ddb3a5 100644 --- a/include/sysemu/nvmm.h +++ b/include/sysemu/nvmm.h @@ -12,7 +12,7 @@ #ifndef QEMU_NVMM_H #define QEMU_NVMM_H -#ifdef NEED_CPU_H +#ifdef COMPILING_PER_TARGET #ifdef CONFIG_NVMM @@ -24,6 +24,6 @@ int nvmm_enabled(void); #endif /* CONFIG_NVMM */ -#endif /* NEED_CPU_H */ +#endif /* COMPILING_PER_TARGET */ #endif /* QEMU_NVMM_H */ diff --git a/include/sysemu/whpx.h b/include/sysemu/whpx.h index 781ca5b2b6..00ff409b68 100644 --- a/include/sysemu/whpx.h +++ b/include/sysemu/whpx.h @@ -15,7 +15,7 @@ #ifndef QEMU_WHPX_H #define QEMU_WHPX_H -#ifdef NEED_CPU_H +#ifdef COMPILING_PER_TARGET #ifdef CONFIG_WHPX @@ -29,6 +29,6 @@ bool whpx_apic_in_platform(void); #endif /* CONFIG_WHPX */ -#endif /* NEED_CPU_H */ +#endif /* COMPILING_PER_TARGET */ #endif /* QEMU_WHPX_H */ diff --git a/include/sysemu/xen.h b/include/sysemu/xen.h index a9f591f26d..754ec2e6cb 100644 --- a/include/sysemu/xen.h +++ b/include/sysemu/xen.h @@ -16,13 +16,13 @@ #include "exec/cpu-common.h" -#ifdef NEED_CPU_H +#ifdef COMPILING_PER_TARGET # ifdef CONFIG_XEN # define CONFIG_XEN_IS_POSSIBLE # endif #else # define CONFIG_XEN_IS_POSSIBLE -#endif +#endif /* COMPILING_PER_TARGET */ #ifdef CONFIG_XEN_IS_POSSIBLE diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h index 7c6adc14f6..c44d23dbe7 100644 --- a/target/arm/kvm-consts.h +++ b/target/arm/kvm-consts.h @@ -14,13 +14,13 @@ #ifndef ARM_KVM_CONSTS_H #define ARM_KVM_CONSTS_H -#ifdef NEED_CPU_H +#ifdef COMPILING_PER_TARGET #ifdef CONFIG_KVM #include #include #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(X != Y) #endif -#endif +#endif /* COMPILING_PER_TARGET */ #ifndef MISMATCH_CHECK #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(0) diff --git a/scripts/analyze-inclusions b/scripts/analyze-inclusions index 45c821de32..b6280f25c8 100644 --- a/scripts/analyze-inclusions +++ b/scripts/analyze-inclusions @@ -92,7 +92,7 @@ echo trace/generated-tracers.h: analyze -include ../include/qemu/osdep.h trace/generated-tracers.h echo target/i386/cpu.h: -analyze -DNEED_CPU_H -I../target/i386 -Ii386-softmmu -include ../include/qemu/osdep.h ../target/i386/cpu.h +analyze -DCOMPILING_PER_TARGET -I../target/i386 -Ii386-softmmu -include ../include/qemu/osdep.h ../target/i386/cpu.h -echo hw/hw.h + NEED_CPU_H: -analyze -DNEED_CPU_H -I../target/i386 -Ii386-softmmu -include ../include/qemu/osdep.h ../include/hw/hw.h +echo hw/hw.h + COMPILING_PER_TARGET: +analyze -DCOMPILING_PER_TARGET -I../target/i386 -Ii386-softmmu -include ../include/qemu/osdep.h ../include/hw/hw.h From patchwork Wed Apr 17 18:27:49 2024 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id d11-20020a0cf6cb000000b0069b69c9ade3si10278631qvo.115.2024.04.17.11.30.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 Apr 2024 11:30:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VSTTlE+J; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rxA1O-0007dY-2d; Wed, 17 Apr 2024 14:28:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rxA1M-0007d8-Go for qemu-devel@nongnu.org; Wed, 17 Apr 2024 14:28:36 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rxA1K-0003JL-TA for qemu-devel@nongnu.org; Wed, 17 Apr 2024 14:28:36 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-416a8ec0239so568055e9.0 for ; Wed, 17 Apr 2024 11:28:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1713378513; x=1713983313; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NnqT/8KLlXL1A5GjOlmM9XBc7s531rVah3xCrUywBWs=; b=VSTTlE+JZTXVo9hmJ1LWMJ3FJxxeHLYFYBbubOiXxeVjaKAS+PxsNwdyeS9zJ3z7cj LY8Q/34i6+oVahCPucxg7f3sOwjZE9gqGICiACdN4hakuk69+QoAMWBGnrQPDY2+JZ92 ILEKTLZbq0M2ztfhPn1YA8iXKFOasFM+1rK/U9K2HRP4VfA0mI4bditAsomowAPwx+oc iuYpdj9zpIvp1/I6xT4tPKmlUl6hCOFiycTBIhb0yJauEeFluohD6PeYoV/2UXshPnpF 9fjfX3JnZyN3pEt9fDgJJ1uN8vdOgKXHg2FGxayXAYwqKfGkzO4P+hEc2krYkjV6Ji+v 3r6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713378513; x=1713983313; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NnqT/8KLlXL1A5GjOlmM9XBc7s531rVah3xCrUywBWs=; b=eBWDwMmr7Ju8eOVOKmFoTqPlSJ1sA0wooS6YcNiOAR80uwHiialmc48PLKvkRYpiC2 5So91R0w6FuT0TfxcDTor9hK4xnDJkJ2euEPzkobIYLidktW8LYx/pFEWhQ0s/evfZ/e DV4Y/Wb9pV6iMYD0OHIspzeDrXJStNW3WKS2S7QGmUaavmjshcCgY3INvllyuZUILOnv +fi7chQOpAyhYYjGNKdtI9hvNYNwUrnsrLuWaOQ/OqZYysJIA8MS4HtQCt+iORf4ccRQ /sRy+4MZEWzq8KXTTinTzOyiI9Gzc9f8YJFw7H42ehkZok6k3n/XRLLBxWk9RlkgFj3C 7xyQ== X-Gm-Message-State: AOJu0YxZWmU+aAONXk1g//hAd2TarnfS4rOekYwW12YPFzh2UMlzS/YP 2Sijq5z0mvK1v/qMzx9FURZPf1YoRsWlTYBQbuAUYGfuZRHRoz8dZSE9uu3x/ynm4Kmfu9FCrGb 8 X-Received: by 2002:a05:600c:1da9:b0:418:93d2:3bf8 with SMTP id p41-20020a05600c1da900b0041893d23bf8mr203138wms.3.1713378513074; Wed, 17 Apr 2024 11:28:33 -0700 (PDT) Received: from m1x-phil.lan ([176.187.201.23]) by smtp.gmail.com with ESMTPSA id h5-20020adff4c5000000b003437a76565asm18092458wrp.25.2024.04.17.11.28.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 17 Apr 2024 11:28:32 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Warner Losh Subject: [PATCH 04/21] exec: Include 'cpu.h' before validating CPUArchState placement Date: Wed, 17 Apr 2024 20:27:49 +0200 Message-ID: <20240417182806.69446-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240417182806.69446-1-philmd@linaro.org> References: <20240417182806.69446-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CPUArchState 'env' field is defined within the ArchCPU structure, so we need to include each target "cpu.h" header which defines it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Message-Id: <20231211212003.21686-2-philmd@linaro.org> --- include/exec/cpu-all.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 1a6510fd3b..b86209fc49 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -391,6 +391,7 @@ static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) #endif /* !CONFIG_USER_ONLY */ /* Validate correct placement of CPUArchState. */ +#include "cpu.h" QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0); QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState)); From patchwork Wed Apr 17 18:27:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 789316 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp172640wrm; Wed, 17 Apr 2024 11:29:23 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWevHMkU238cBncko8ZLdJY0uXz9ObHVB0MF7QH+MxEfWOgKlurmrLN/tvJKUvQxnyhAS1VdSrVMu87Ity5P1tV X-Google-Smtp-Source: AGHT+IHcCUSkUGI7BXk12Nesojf13y8UUEzUDseBDsw9OoXQuZm+8LENcde/T/XaAA6gl5wIbExs X-Received: by 2002:a05:620a:109a:b0:78e:c724:c813 with SMTP id g26-20020a05620a109a00b0078ec724c813mr212543qkk.5.1713378563045; Wed, 17 Apr 2024 11:29:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713378563; cv=none; d=google.com; s=arc-20160816; b=Qd5hM/Os/0RzD4p/Vo6YWfdOLsk1SMfsEFzki5qhwlOx9aLuvACu2waMa9Z6kUZc2C ZKAJB2AD4hbEmUHaev4kT/XxA9b4P4oL6jnevJc8l62awKRVTWl1b+QE/BqNk5C5xk3r rgk0918VkHXM0yaOw5fPEMv5kRBzshF9/M9pQsO9Y+tinIcK85RkXo2rMhgeZGRhPsCI 3ThkCHbL0QXpr9MlhtdphvpLSRAWqtQk5qHIyQzMDhSgftNdUJXKUazQ5joKrRRntdHm Wl82Zlx8MUMxmecm3S1/KbefKRBQXb2mZDysEnAkUY7z3IxqaM1aHeGTv2usqVxLIFOn 8GPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rI+phs//gjZco0fvuUEX1KPF7mTDgm4gz1xheV8LKk0=; fh=AGplSnt+WUiov1DMvmsoICTNBRvGlJbdW0SrX8Rpgr8=; b=FvRCLlLBFL5W7e/xtWLEkwMHZGxrb5UTII/jnE9/mOYM/6MnJedWdbJk89lucQwlc6 /b1AWTpRSiTWTrmGhhbFEtK+fxEZ+gIvmxe4+IawDOcw7/hkL+4ExXUgjjUVmyp8CFEj e/6fGiqqAHVebI/mPi0RSRmBN2pCli5vHjjVnh38O0JswqbOGzFRg3Bu2drWqnOaUNxl 168SP+QqIVNsKut1c0Uo9JYSyhQl+X7hH30iPLVJs5JC8wA/FyrFFN/kfzdFjVmGIAM+ AwSDd1ZJj4tK+Tvpa4v+I5K5bghwCRguuSkZDOS8AbeolS8TL0o76QZ97W/Zj1Wgq2q5 YHrw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Zwg14XFa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20231211212003.21686-3-philmd@linaro.org> --- meson.build | 2 +- page-target.c | 44 ++++++++++++++++++++++++++++++++++++++++++ system/physmem.c | 30 ---------------------------- target/target-common.c | 10 ---------- target/meson.build | 2 -- 5 files changed, 45 insertions(+), 43 deletions(-) create mode 100644 page-target.c delete mode 100644 target/target-common.c diff --git a/meson.build b/meson.build index da8295b405..44d337f67b 100644 --- a/meson.build +++ b/meson.build @@ -3554,7 +3554,7 @@ if get_option('b_lto') pagevary = declare_dependency(link_with: pagevary) endif common_ss.add(pagevary) -specific_ss.add(files('page-vary-target.c')) +specific_ss.add(files('page-target.c', 'page-vary-target.c')) subdir('backends') subdir('disas') diff --git a/page-target.c b/page-target.c new file mode 100644 index 0000000000..82211c8593 --- /dev/null +++ b/page-target.c @@ -0,0 +1,44 @@ +/* + * QEMU page values getters (target independent) + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "exec/target_page.h" +#include "exec/cpu-defs.h" +#include "cpu.h" +#include "exec/cpu-all.h" + +size_t qemu_target_page_size(void) +{ + return TARGET_PAGE_SIZE; +} + +int qemu_target_page_mask(void) +{ + return TARGET_PAGE_MASK; +} + +int qemu_target_page_bits(void) +{ + return TARGET_PAGE_BITS; +} + +int qemu_target_page_bits_min(void) +{ + return TARGET_PAGE_BITS_MIN; +} + +/* Convert target pages to MiB (2**20). */ +size_t qemu_target_pages_to_MiB(size_t pages) +{ + int page_bits = TARGET_PAGE_BITS; + + /* So far, the largest (non-huge) page size is 64k, i.e. 16 bits. */ + g_assert(page_bits < 20); + + return pages >> (20 - page_bits); +} diff --git a/system/physmem.c b/system/physmem.c index a4fe3d2bf8..dd7b222942 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -3504,36 +3504,6 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, return 0; } -/* - * Allows code that needs to deal with migration bitmaps etc to still be built - * target independent. - */ -size_t qemu_target_page_size(void) -{ - return TARGET_PAGE_SIZE; -} - -int qemu_target_page_bits(void) -{ - return TARGET_PAGE_BITS; -} - -int qemu_target_page_bits_min(void) -{ - return TARGET_PAGE_BITS_MIN; -} - -/* Convert target pages to MiB (2**20). */ -size_t qemu_target_pages_to_MiB(size_t pages) -{ - int page_bits = TARGET_PAGE_BITS; - - /* So far, the largest (non-huge) page size is 64k, i.e. 16 bits. */ - g_assert(page_bits < 20); - - return pages >> (20 - page_bits); -} - bool cpu_physical_memory_is_io(hwaddr phys_addr) { MemoryRegion*mr; diff --git a/target/target-common.c b/target/target-common.c deleted file mode 100644 index 903b10cfe4..0000000000 --- a/target/target-common.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -#include "qemu/osdep.h" - -#include "cpu.h" -#include "exec/target_page.h" - -int qemu_target_page_mask(void) -{ - return TARGET_PAGE_MASK; -} diff --git a/target/meson.build b/target/meson.build index dee2ac47e0..a53a60486f 100644 --- a/target/meson.build +++ b/target/meson.build @@ -19,5 +19,3 @@ subdir('sh4') subdir('sparc') subdir('tricore') subdir('xtensa') - -specific_ss.add(files('target-common.c')) From patchwork Wed Apr 17 18:27:51 2024 Content-Type: text/plain; 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The last one in "cpu.h", with a bunch of definitions irrelevant for TCG. By moving the TCG_GUEST_DEFAULT_MO definition to "cpu-param.h", we can simplify various accel/tcg includes. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Acked-by: Nicholas Piggin Message-Id: <20231211212003.21686-4-philmd@linaro.org> --- target/alpha/cpu-param.h | 3 +++ target/alpha/cpu.h | 3 --- target/arm/cpu-param.h | 8 +++++--- target/arm/cpu.h | 3 --- target/avr/cpu-param.h | 2 ++ target/avr/cpu.h | 2 -- target/hppa/cpu-param.h | 8 ++++++++ target/hppa/cpu.h | 6 ------ target/i386/cpu-param.h | 3 +++ target/i386/cpu.h | 3 --- target/loongarch/cpu-param.h | 2 ++ target/loongarch/cpu.h | 2 -- target/microblaze/cpu-param.h | 3 +++ target/microblaze/cpu.h | 3 --- target/mips/cpu-param.h | 2 ++ target/mips/cpu.h | 2 -- target/openrisc/cpu-param.h | 2 ++ target/openrisc/cpu.h | 2 -- target/ppc/cpu-param.h | 2 ++ target/ppc/cpu.h | 2 -- target/riscv/cpu-param.h | 2 ++ target/riscv/cpu.h | 2 -- target/s390x/cpu-param.h | 6 ++++++ target/s390x/cpu.h | 3 --- target/sparc/cpu-param.h | 23 +++++++++++++++++++++++ target/sparc/cpu.h | 23 ----------------------- target/xtensa/cpu-param.h | 3 +++ target/xtensa/cpu.h | 3 --- 28 files changed, 66 insertions(+), 62 deletions(-) diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index c969cb016b..5ce213a9a1 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -27,4 +27,7 @@ # define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) #endif +/* Alpha processors have a weak memory model */ +#define TCG_GUEST_DEFAULT_MO (0) + #endif diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 7188a409a0..f9e2ecb90a 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -24,9 +24,6 @@ #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" -/* Alpha processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #define ICACHE_LINE_SIZE 32 #define DCACHE_LINE_SIZE 32 diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index da3243ab21..2d5f3aa312 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -27,14 +27,16 @@ # else # define TARGET_PAGE_BITS 12 # endif -#else +#else /* !CONFIG_USER_ONLY */ /* * ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 * have to support 1K tiny pages. */ # define TARGET_PAGE_BITS_VARY # define TARGET_PAGE_BITS_MIN 10 - -#endif +#endif /* !CONFIG_USER_ONLY */ + +/* ARM processors have a weak memory model */ +#define TCG_GUEST_DEFAULT_MO (0) #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bc0c84873f..98f58d04c1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -30,9 +30,6 @@ #include "target/arm/multiprocessing.h" #include "target/arm/gtimer.h" -/* ARM processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #ifdef TARGET_AARCH64 #define KVM_HAVE_MCE_INJECTION 1 #endif diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 9a92bc74fc..93c2f470d0 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -32,4 +32,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24 +#define TCG_GUEST_DEFAULT_MO 0 + #endif diff --git a/target/avr/cpu.h b/target/avr/cpu.h index d185d20dcb..4725535102 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -30,8 +30,6 @@ #define CPU_RESOLVING_TYPE TYPE_AVR_CPU -#define TCG_GUEST_DEFAULT_MO 0 - /* * AVR has two memory spaces, data & code. * e.g. both have 0 address diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index bb3d7ef6f7..473d489f01 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -21,4 +21,12 @@ #define TARGET_PAGE_BITS 12 +/* PA-RISC 1.x processors have a strong memory model. */ +/* + * ??? While we do not yet implement PA-RISC 2.0, those processors have + * a weak memory model, but with TLB bits that force ordering on a per-page + * basis. It's probably easier to fall back to a strong memory model. + */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index a072d0bb63..fb2e4c4a98 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -25,12 +25,6 @@ #include "qemu/cpu-float.h" #include "qemu/interval-tree.h" -/* PA-RISC 1.x processors have a strong memory model. */ -/* ??? While we do not yet implement PA-RISC 2.0, those processors have - a weak memory model, but with TLB bits that force ordering on a per-page - basis. It's probably easier to fall back to a strong memory model. */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #define MMU_ABS_W_IDX 6 #define MMU_ABS_IDX 7 #define MMU_KERNEL_IDX 8 diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index 911b4cd51b..5e15335203 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -24,4 +24,7 @@ #endif #define TARGET_PAGE_BITS 12 +/* The x86 has a strong memory model with some store-after-load re-ordering */ +#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) + #endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6b05738079..a6ca593547 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -30,9 +30,6 @@ #define XEN_NR_VIRQS 24 -/* The x86 has a strong memory model with some store-after-load re-ordering */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) - #define KVM_HAVE_MCE_INJECTION 1 /* support for self modifying code even if the modified instruction is diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index cfe195db4e..db5ad1c69f 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -14,4 +14,6 @@ #define TARGET_PAGE_BITS 12 +#define TCG_GUEST_DEFAULT_MO (0) + #endif diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index ec37579fd6..abb01b2cc7 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -39,8 +39,6 @@ #define IOCSR_MEM_SIZE 0x428 -#define TCG_GUEST_DEFAULT_MO (0) - #define FCSR0_M1 0x1f /* FCSR1 mask, Enables */ #define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */ #define FCSR0_M3 0x300 /* FCSR3 mask, Round Mode */ diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index 9770b0eb52..e530fead1c 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -29,4 +29,7 @@ /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ #define TARGET_PAGE_BITS 12 +/* MicroBlaze is always in-order. */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index c0c7574dbd..3e5a3e5c60 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -24,9 +24,6 @@ #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" -/* MicroBlaze is always in-order. */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - typedef struct CPUArchState CPUMBState; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 594c91a156..6f6ac1688f 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -30,4 +30,6 @@ #define TARGET_PAGE_BITS_MIN 12 #endif +#define TCG_GUEST_DEFAULT_MO (0) + #endif diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 7329226d39..3e906a175a 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -10,8 +10,6 @@ #include "hw/clock.h" #include "mips-defs.h" -#define TCG_GUEST_DEFAULT_MO (0) - typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; /* MSA Context */ diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h index 3f08207485..fbfc0f568b 100644 --- a/target/openrisc/cpu-param.h +++ b/target/openrisc/cpu-param.h @@ -13,4 +13,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define TCG_GUEST_DEFAULT_MO (0) + #endif diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index b1b7db5cbd..c9fe9ae12d 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -24,8 +24,6 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" -#define TCG_GUEST_DEFAULT_MO (0) - /** * OpenRISCCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index b7ad52de03..77c5ed9a67 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -40,4 +40,6 @@ # define TARGET_PAGE_BITS 12 #endif +#define TCG_GUEST_DEFAULT_MO 0 + #endif diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 67e6b2effd..0ac55d6b25 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -29,8 +29,6 @@ #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU -#define TCG_GUEST_DEFAULT_MO 0 - #define TARGET_PAGE_BITS_64K 16 #define TARGET_PAGE_BITS_16M 24 diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index b2a9396dec..1fbd64939d 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -28,4 +28,6 @@ * - M mode HLV/HLVX/HSV 0b111 */ +#define TCG_GUEST_DEFAULT_MO 0 + #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3b1a02b944..2d0c02c35b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -43,8 +43,6 @@ typedef struct CPUArchState CPURISCVState; # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 #endif -#define TCG_GUEST_DEFAULT_MO 0 - /* * RISC-V-specific extra insn start words: * 1: Original instruction opcode diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index 84ca08626b..11d23b600d 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -13,4 +13,10 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 +/* + * The z/Architecture has a strong memory model with some + * store-after-load re-ordering. + */ +#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) + #endif diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 43a46a5a06..414680eed1 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -33,9 +33,6 @@ #define ELF_MACHINE_UNAME "S390X" -/* The z/Architecture has a strong memory model with some store-after-load re-ordering */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) - #define TARGET_HAS_PRECISE_SMC #define TARGET_INSN_START_EXTRA_WORDS 2 diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index cb11980404..82293fb844 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -23,4 +23,27 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif +/* + * From Oracle SPARC Architecture 2015: + * + * Compatibility notes: The PSO memory model described in SPARC V8 and + * SPARC V9 compatibility architecture specifications was never implemented + * in a SPARC V9 implementation and is not included in the Oracle SPARC + * Architecture specification. + * + * The RMO memory model described in the SPARC V9 specification was + * implemented in some non-Sun SPARC V9 implementations, but is not + * directly supported in Oracle SPARC Architecture 2015 implementations. + * + * Therefore always use TSO in QEMU. + * + * D.5 Specification of Partial Store Order (PSO) + * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. + * + * D.6 Specification of Total Store Order (TSO) + * ... PSO with the additional requirement that all [stores] are followed + * by an implied MEMBAR #StoreStore. + */ +#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) + #endif diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index f3cdd17c62..dfd9512a21 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -6,29 +6,6 @@ #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" -/* - * From Oracle SPARC Architecture 2015: - * - * Compatibility notes: The PSO memory model described in SPARC V8 and - * SPARC V9 compatibility architecture specifications was never implemented - * in a SPARC V9 implementation and is not included in the Oracle SPARC - * Architecture specification. - * - * The RMO memory model described in the SPARC V9 specification was - * implemented in some non-Sun SPARC V9 implementations, but is not - * directly supported in Oracle SPARC Architecture 2015 implementations. - * - * Therefore always use TSO in QEMU. - * - * D.5 Specification of Partial Store Order (PSO) - * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. - * - * D.6 Specification of Total Store Order (TSO) - * ... PSO with the additional requirement that all [stores] are followed - * by an implied MEMBAR #StoreStore. - */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) - #if !defined(TARGET_SPARC64) #define TARGET_DPREGS 16 #define TARGET_FCCREGS 1 diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index b1da0555de..0000725f2f 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -17,4 +17,7 @@ #define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif +/* Xtensa processors have a weak memory model */ +#define TCG_GUEST_DEFAULT_MO (0) + #endif diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 6b8d0636d2..9f2341d856 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -34,9 +34,6 @@ #include "hw/clock.h" #include "xtensa-isa.h" -/* Xtensa processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - enum { /* Additional instructions */ XTENSA_OPTION_CODE_DENSITY, From patchwork Wed Apr 17 18:27:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 789322 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp172878wrm; Wed, 17 Apr 2024 11:30:02 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWhE8NxYYQvUrqiLU+iv6WfUVALzHipRcd37JIIlKe5jgMJOsmH9wh1U5lucRbDt964indeHW+SlsDXEbwRlEOW X-Google-Smtp-Source: AGHT+IEiL1qzaJXCHGtK7wK4go8PArDEm4SRjxPbklCJTwZA6jn1iNx6r4Zu6Ry7URLjLYG3MGm0 X-Received: by 2002:ad4:5812:0:b0:69b:7b95:8ef1 with SMTP id dd18-20020ad45812000000b0069b7b958ef1mr243445qvb.22.1713378602681; Wed, 17 Apr 2024 11:30:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713378602; cv=none; d=google.com; s=arc-20160816; b=lp/ADVvgV1zkFTiAaPEDkQCLd5d5bInYgWfLNrgj/5vcrNimMDfDNnEwRuUBsmxK36 fMiMJcnShbCDOx0U8d6eIZeth8gPnE0YwDB03gFwD8OhMhkw5UxsodvLiHbzxZGuTcCu cPqHGn7FCmGDIM55fSwaeumgSfXS3P75vq0ONOg+JeqPY+saernV+kv4NvpxEG6+qI9a T+HdO1asqvlQFdICS2fT6u7G+m2k8vlNnZ1eax6OPGsK+xSKy0GkvoIQgO3/zs8LMjIf VjYYwzs+nzfzNF0Pd7iaQkzR2pVjgvHijkwVWTBROb0tUB3hTLivVYh+Fi7kGw+bfQEE cSTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=BO/V4plvXFYo3PYcgn25HOreAsh2/yu478RHuCQmS58=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=K3rh3Sq7RCCh897ih5A1uWMT25hPUdSaVbgqDhFmDQYBO9MBY7YBLK5oXmtA54WnOw In/MBLcW+3dgUzsTsUip3TZfpjAqef2104hz2ZP7x2qnoyomTUQrnsyARKPGAbwXtqOK g9qShdTWcPNe87+rh4V87kYu1MONsI3o3r6bLiFg5LxoljF7jIpsYAFDYEkxrGbfHho7 9mibOU972AX/0wgn8LQGSQ8aftP2eu6mQJVbOZPSORK0aQDoD47PJufkAj4bGaZBY4wi Klw/2Dd5pVVCTv/UbWX5fR62g8ofCclqVewX5BjKch+b4NmtExPwCF0OX22SPWKlUrTc fLsA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XqBJsYV+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231211212003.21686-5-philmd@linaro.org> --- accel/tcg/translator.c | 1 + target/hexagon/translate.c | 1 + target/microblaze/cpu.c | 1 + target/microblaze/translate.c | 1 + target/nios2/translate.c | 1 + 5 files changed, 5 insertions(+) diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 9de0bc34c8..6832e55135 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -12,6 +12,7 @@ #include "qemu/error-report.h" #include "exec/exec-all.h" #include "exec/translator.h" +#include "exec/cpu_ldst.h" #include "exec/plugin-gen.h" #include "tcg/tcg-op-common.h" #include "internal-target.h" diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index f163eefe97..47a870f42d 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -23,6 +23,7 @@ #include "exec/helper-gen.h" #include "exec/helper-proto.h" #include "exec/translation-block.h" +#include "exec/cpu_ldst.h" #include "exec/log.h" #include "internal.h" #include "attribs.h" diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 96c2b71f7f..d05e2e6ea7 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -28,6 +28,7 @@ #include "qemu/module.h" #include "hw/qdev-properties.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "exec/gdbstub.h" #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index fc451befae..6d89c1a175 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "disas/disas.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "tcg/tcg-op.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 7ddc6ac1a2..bcfcc3b112 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -25,6 +25,7 @@ #include "cpu.h" #include "tcg/tcg-op.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "disas/disas.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" From patchwork Wed Apr 17 18:27:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 789319 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp172748wrm; Wed, 17 Apr 2024 11:29:40 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUAf0khaPsndThw2inoJ5/uprBXVD2pSv6ODsf1t32BDiDhbF7z/jQRE+6qrgbxEDf2aIO1au2xSwrMp4GevJu1 X-Google-Smtp-Source: AGHT+IFFwQDm2+8G6Wvqk7ozFfglTQpu/8hdNTJXAyz4asCZbCWjYr1qLlBMnOoKTleic/NVkduZ X-Received: by 2002:a05:622a:38f:b0:436:5e08:9aef with SMTP id j15-20020a05622a038f00b004365e089aefmr9290584qtx.5.1713378580239; Wed, 17 Apr 2024 11:29:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713378580; cv=none; d=google.com; s=arc-20160816; b=YZDGHOfi32ms2o+9DwTWqfN7rUI+OPCp2YIVdWQJeh5kgLsfBdTG7/ciauVCaY6lcH TJtPtp86dOI41bozu0Z2n8VHSf5KJSHM/TMibrEYb2KpWrQBuu+vQYn7HfJExDnIvOtW wwduL8ja5xCUIgXF3uFscwrVoydQsOe8JflC2g7wdwmzpqHpbvTxEUQ7J80KyxIups46 YNEohpbv/UHEcmTXgfV9VmEunEgkoXF6+QQBgZ3i1dx7BNjBpj9VNh9tNiBGNbaZN6KV EzNcREhZh8RNNrVwSWUVZH87I9Y5TeSu2gVivoyRWKyySHvy95h6Eo5kRGRBswBg8Lhk 0axQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=E03TQ0GvhSAU3PvcwPGXVXyQZvjAqNweStAhT2Ncf1c=; fh=AGplSnt+WUiov1DMvmsoICTNBRvGlJbdW0SrX8Rpgr8=; b=Ob3Fgag9iKHzcSjmKFmN9yaI9b7Kbnkscuzsm8PWuJOly3Wn7lLGXRu3Upu06a2TLt sB1rNPc/D/PKhOPcpzIMoXr3lXykqeoPss8ErjhuNzAfNgwIzt/qbeJfH7rhucI82iPy KdYzX4u8Df91jWAoRosmfbVyAasdkGN3+82pZunH0EOyYlwfkel5VypyY4mL4nSIA+Wa ZR5lP2tdFUIRgdQQbU0HH5gvCktp3BJ/HJW4Z0lxK0Tb31ddPXDgBB44sickpVIVaAsK 6+npUE1HYboTudWDplELAB7ZPqoRJI7qL4TmkdK9yB2ddrHAoqVOHtZ1tdlno9zmNteW y3hA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="JQ/NRJMt"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Wed, 17 Apr 2024 11:28:55 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Warner Losh Subject: [PATCH 08/21] gdbstub: Include missing 'hw/core/cpu.h' header Date: Wed, 17 Apr 2024 20:27:53 +0200 Message-ID: <20240417182806.69446-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240417182806.69446-1-philmd@linaro.org> References: <20240417182806.69446-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Functions such gdb_get_cpu_pid() dereference CPUState so require the structure declaration from "hw/core/cpu.h": static uint32_t gdb_get_cpu_pid(CPUState *cpu) { ... return cpu->cluster_index + 1; } Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Message-Id: <20231211212003.21686-15-philmd@linaro.org> Reviewed-by: Richard Henderson --- gdbstub/gdbstub.c | 1 + 1 file changed, 1 insertion(+) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 9c23d44baf..9c2b8b5d0a 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -37,6 +37,7 @@ #include "hw/cpu/cluster.h" #include "hw/boards.h" #endif +#include "hw/core/cpu.h" #include "sysemu/hw_accel.h" #include "sysemu/runstate.h" From patchwork Wed Apr 17 18:27:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 789320 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp172791wrm; Wed, 17 Apr 2024 11:29:47 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUYl3YduVCw4yP6+ogS4TdkHiNIDv5lNMkt0IMzucnx6mgBZrVXhKJPilOY4uZEwLUJTAK+OtFZkruuvgmGUX/G X-Google-Smtp-Source: AGHT+IHC5SqoqpeYGZ7I1Ju3epbcFqKI1VRJ+M+gLuUmR+FMZ9KUnZuD8kgQgk1vYuDoo+RL/ph+ X-Received: by 2002:ac8:7e90:0:b0:435:9c32:ae57 with SMTP id w16-20020ac87e90000000b004359c32ae57mr363203qtj.26.1713378587205; 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Avoid including the huge "cpu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231211212003.21686-6-philmd@linaro.org> --- include/semihosting/uaccess.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/semihosting/uaccess.h b/include/semihosting/uaccess.h index 3963eafc3e..6c8835fbcb 100644 --- a/include/semihosting/uaccess.h +++ b/include/semihosting/uaccess.h @@ -14,7 +14,7 @@ #error Cannot include semihosting/uaccess.h from user emulation #endif -#include "cpu.h" +#include "exec/cpu-defs.h" #define get_user_u64(val, addr) \ ({ uint64_t val_ = 0; \ From patchwork Wed Apr 17 18:27:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 789335 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp173863wrm; Wed, 17 Apr 2024 11:32:09 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVg4ada5dCyGTVMHeklTGxOl1J8Eue7tTFk5cgGvllWlsbwcW+Aucc8Pm1oUvwOWrTcecvSWZuWTnABTBY3Ye1W X-Google-Smtp-Source: AGHT+IFIlpgDtK8gDqzdjQyyJNU3OUIp2gTtDJE94Rt79aUEe2yO3ujwwjqB5CpP3dz1N1EkpcXg X-Received: by 2002:a9d:7f8c:0:b0:6eb:5a72:3e57 with SMTP id t12-20020a9d7f8c000000b006eb5a723e57mr330672otp.10.1713378729520; Wed, 17 Apr 2024 11:32:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713378729; cv=none; d=google.com; s=arc-20160816; b=VdoweRjzFfRD1JkRmv0tKgGd9yiHJBP7ovj6L61asOcHXxggu2fv63bzUlXxp+cLTb 9gmdN/Nmq0zrvNKtceldePTwmwYmmEGYOvaMFbhRIlcPXxv2n+qOCEJ77pd52s4xXJEn 3KETmvqOm2F+0mGA3CBM4M7keKn1DOysUJVJq78SmvuRpbql+CISGP3lViKtsMTnYHP+ s3DdhIVxxArKBEcMEpT8Qnf8MJRylLDYbe6sl+z8nvR8XGd5fYvqtPGWxg2vVF9cYXOT c7+0Xm4kisOxWdAqqCL589vdGMmq3XmgTLcPgITEq3mgmU3tVjYwfiP2hVfd7OtXG3sN 4QDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Ui+hlZ4hNideAomElccoReBpzAydVF/XtIhgQiumYZo=; fh=4h2n32rS/QTVLHkSl86VTm16hqnAMuCXWV/jhovneZg=; b=UrFHxkj4O0Bx8brkR+dVM2uEdeanKJYLNKri8V5OHoORBSb0W70wtRxdExRMFXmq6A Xte8eZwb587CDIsiyqo/bD26l9j28pqukcLTHgKzReAX4Rfv6RsxwJbcLRZL9jsVgRLv 6sdKdP+ldOUOrQhznFrc+lMsfPViu/mIJFurslTcEad7wjCLQTBG6mb54ErnE7UX3uYb zS9voqXB0XaLWB+1rRURNwSPk84omQR0NEn1hUTeHDChl2WCaq9JonQbOdWhUeRvDDtT Uyhib2wE5HyUFy0LnniAuVF8tbZ0DfqsQlm4XntXj/NLPtOM42mbVzidov1H8kjyvuk5 KTjA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EGTUH2Ih; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Message-Id: <20231212123401.37493-8-philmd@linaro.org> Reviewed-by: Richard Henderson --- semihosting/guestfd.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/semihosting/guestfd.c b/semihosting/guestfd.c index 955c2efbd0..d3241434c5 100644 --- a/semihosting/guestfd.c +++ b/semihosting/guestfd.c @@ -12,10 +12,7 @@ #include "gdbstub/syscalls.h" #include "semihosting/semihost.h" #include "semihosting/guestfd.h" -#ifdef CONFIG_USER_ONLY -#include "qemu.h" -#else -#include "semihosting/uaccess.h" +#ifndef CONFIG_USER_ONLY #include CONFIG_DEVICES #endif From patchwork Wed Apr 17 18:27:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 789331 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp173655wrm; Wed, 17 Apr 2024 11:31:43 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVTb4Gn45RHhvoEiwey8REHXEoaRTictG0hm1z4odk41jwn842THQ/blymn2foTG+g/0wayI5v8+VnN6iWrcKFO X-Google-Smtp-Source: AGHT+IEG9W1LKkTs4NXhGGmYqrDKSyhEb6GnRG/bmhGFzqqk/5ZeAcC4FHZgsnSG1OfxM2cF3Ns6 X-Received: by 2002:ac8:5a43:0:b0:435:15d:8495 with SMTP id o3-20020ac85a43000000b00435015d8495mr427296qta.20.1713378703350; Wed, 17 Apr 2024 11:31:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713378703; cv=none; d=google.com; s=arc-20160816; b=DjZPPrNkkxPxEHMqKEpY9Sr7G0Yk+460ysoOUptN29j+dw1mfbA6KmC121g3WJeK0A XtLRYDkhTssoSCfVNtzcIi7kLkEhBCBGZnmV4+nXrvlh3hSxu5R2/Isn1wi/k9sqBfeH COAGq/ElaiDNarz0XKlR5v0G/t0dVPTYWGaZNl3diOiBvy8Vg42+kQDC7FHP6BmtmgzM Lx+sId35tRl7tlTTpHjOrpK/XIic4mstfMPmPZzr5Pvn3tNLv2gC3V7OMwMArV6FgV1A gHW9bJ3sgBP8wbTlHhkq9OYS8ptxra3zdKQgiOAsKr47KZKFF3motk/NEZCMI1k4Oihw mheg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QqXKfsFzG8GoX3EjCJAOwlqA9OuB4aRKiAFifCWZKos=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=c1cLECn2sm31pBhFt7jflt8XTexmlJf0937cUt9RCCN/807AJ/m0DvtIBGnxynXEBa sG63R0QzCJUFNBpf7mo3Yl4np+OPy15PaoFzL3jyq8tPRP5mscfeIO2s2c4Dub0sDAt+ DU541rbi6GMsqgxFVQK6zEeKsQxD101cXVwHNgW1dLmgKCTJa/oX5ESWAr8NwdqxygoU S/Gy+RYOew6kqXVATjVvDbbSdl0nDSUn9/3PwWk9YjgQkffugPnTSKFuG0+PoGdTm2gE zDX7K8yU38JOqn9IkJonwQeyOXIIY95uDeYIMEx3/6CP7yLdPahQVpnYesy2GfwMEYYj XAjQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zTVXbrXf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231211212003.21686-17-philmd@linaro.org> --- include/exec/cpu-all.h | 1 - include/exec/ram_addr.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index b86209fc49..586dc56d9e 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -24,7 +24,6 @@ #include "exec/tswap.h" #include "qemu/thread.h" #include "hw/core/cpu.h" -#include "qemu/rcu.h" /* some important defines: * diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index de45ba7bc9..3fc83587c0 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -26,6 +26,7 @@ #include "exec/ramlist.h" #include "exec/ramblock.h" #include "exec/exec-all.h" +#include "qemu/rcu.h" extern uint64_t total_dirty_pages; From patchwork Wed Apr 17 18:27:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 789332 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp173661wrm; Wed, 17 Apr 2024 11:31:43 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV5AMRkbkND2OwU7bxtVWBZvxwNWlkkjGdLPAbzlcq2rwEqNBY1D8C+hfllcfBygwLdfcTE01l9z118+FAbvhcG X-Google-Smtp-Source: AGHT+IH5CZDloa+C3AoKt7WKrcfcN0FZSKOgsnFovef4SN9xvVI1hepPCbAgaPHTUiKyQ6S9Anky X-Received: by 2002:a05:6808:3af:b0:3c5:f056:5df1 with SMTP id n15-20020a05680803af00b003c5f0565df1mr374824oie.30.1713378703621; Wed, 17 Apr 2024 11:31:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713378703; cv=none; d=google.com; s=arc-20160816; b=WyBIqb8KBeIYz6cJuavvhblPTFAvARG5Jnsh8kzyBdHuZ9TS03AuuFs6A8pjTlKNDW NR2XsqTVTnZYK4p/4cZa+Vh7yu53HJG0hmeCuMZ8dO7s9lR0SiHsP6JqF/qp5DF/23Po cRwT8x+nmWAnYx/p3UCY63LEMclyD6E6k93BuVw3rIoeObThngl0mQL9fOwTVTf6wNqZ Idn4+MNKxZ5r9eAo8M8Df1/D5iy3axhQe8gzMxNl3+58O3PkOalSsVnmBt1hAr8VDefu DgwGyPHyDqY1In3vF2CkJwrX0rWqYpvzza9AF8VE8NZtNghD/5AI4k10GA+YPYC3/aXI E7VQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=BDiTP7Q6dFZYOkY6r7oVGOIMgGCIl+1MkIYW9OY8XIA=; fh=K5z00ePDNrt3NTCZodGs41kbvqf9//eq5xcHzb1DlB8=; b=HtUQ+yZD5iPIbNNS7yldcrUq2+V9e68FpTNuGtv3z4FPe4sRmBaAc7MAU7SdXQ7jmk AfHDGtTrUCR/J/maA30n8hBn0448IZfrwRLtfd1+muYmrzlDvGUeLTZTCHEob+3uueCr 4l6gCvHQG6Tef+XAgh+XAHBB+8wyV3eQIIFcS9SN7BsIXEK/gZeeTpOFIEj3Jrc45ZdA ZcRGXh1gYBpwu7/tseAWi2ieoGH/6EHVSquIk5p0wIL26dRLnakmNChVgHQuL8Slkdyn 7+ccO9aLwLKTIms5Wwhb6Ryjyfjp6WFgfsTrtxLmQCIJOGeF9wXIydk9j/a9d5asch6X SrXg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Mdk9NDTJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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The system emulation equivalent is 'target_ulong'. Use it in ppc_ldl_code() to emphasis this is not an user emulation function. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Nicholas Piggin Reviewed-by: Thomas Huth Message-Id: <20231211212003.21686-18-philmd@linaro.org> Reviewed-by: Richard Henderson --- target/ppc/excp_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 674c05a2ce..0712098cf7 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -142,7 +142,7 @@ static inline bool insn_need_byteswap(CPUArchState *env) return !!(env->msr & ((target_ulong)1 << MSR_LE)); } -static uint32_t ppc_ldl_code(CPUArchState *env, abi_ptr addr) +static uint32_t ppc_ldl_code(CPUArchState *env, target_ulong addr) { uint32_t insn = cpu_ldl_code(env, addr); From patchwork Wed Apr 17 18:27:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 789321 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp172794wrm; Wed, 17 Apr 2024 11:29:47 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWuwSOqaCEGV3Jl1V+Nl2uQ/6Un5JMzDOEobWo3diaTJfvNvvWGvWdkqW7IbkMwNkRgzSlDf8UgRtz2vZXZT48u X-Google-Smtp-Source: AGHT+IHIW93F/s1ar83tZGwxuiaqV5Nogp8gDG7xKEtdGWwXas2bD9PMvASIc2mkL+SNdeAHuAZc X-Received: by 2002:a05:690c:f8e:b0:618:1ce6:b618 with SMTP id df14-20020a05690c0f8e00b006181ce6b618mr132749ywb.12.1713378587417; Wed, 17 Apr 2024 11:29:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713378587; cv=none; d=google.com; s=arc-20160816; b=Ow7ppHbzj43DUVw/D9ZHppfampQikUAHE+q5rIXqr9aJJcs7PuZqQO5GRlNJx1jWaI P/WbkyCtsT2vhE3K3JLia5UBnmWRw1a+O1JAYW05EuKhTUrhIGHit1dVP6IFMbL8o2y8 ePGMsT4kuaz3ZQX77UNebgYJf59bjvSQIGR1CcC5Wb6QMVpSobTJzOupGLXb6AGSh8SK h1PaB+qHaHgMHDQC9UDb1i8VFWZKJDefVOOmB/1+0LH9HqCyE0e0rhkTuIXXJWYgoL67 OweK+K/sTfAHbnMvLimgb+PfP6TtO3ukA28y/vEMSdFeKcfzAggEwbf1tT0SGbk1MFND IPag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZshIaCnSYMR+iOE/aqIWZYs6swUMEabN3Qo8HFzzTJI=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=LBzdDmVuB36OpDP21FtCCGOcKMeejv5hWxJ/PLzqg26zjDacyFrO8mvTWx9n3x/Gmd E7oCMqiEt0Si7DDCciCamSgw4apC0oIOQkAxwzaW6JfL9cqPblyhSVxPWw1Zgf6utz6s 18DStFdVGvPuPp2hrGenB+t6cY8LApEqsJRAmjVcPamd1T9tzZWkR1EwmH4waGa5f3mp QyjMSDtjX6w6FSl4ssYQ77JyJ8uk/9Wxb9mLGpSylzB1YaVwBU+sGXFBArDGBQ6xrub5 QSSnOiFr8bfB+BMOzCi4Yf9rAaOugXoQ7C4qoU/PqOx2laUMAqQOfdalxr9795eXyQFB kjSA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bDtWhC1d; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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No need to expose their definitions to all user-emulation files including "exec/cpu_ldst.h", move them to a new "user-retaddr.h" header (restricted to accel/tcg/). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231211212003.21686-19-philmd@linaro.org> --- accel/tcg/user-retaddr.h | 28 ++++++++++++++++++++++++++++ include/exec/cpu_ldst.h | 28 ++-------------------------- accel/tcg/cpu-exec.c | 3 +++ accel/tcg/user-exec.c | 1 + 4 files changed, 34 insertions(+), 26 deletions(-) create mode 100644 accel/tcg/user-retaddr.h diff --git a/accel/tcg/user-retaddr.h b/accel/tcg/user-retaddr.h new file mode 100644 index 0000000000..e0f57e1994 --- /dev/null +++ b/accel/tcg/user-retaddr.h @@ -0,0 +1,28 @@ +#ifndef ACCEL_TCG_USER_RETADDR_H +#define ACCEL_TCG_USER_RETADDR_H + +#include "qemu/atomic.h" + +extern __thread uintptr_t helper_retaddr; + +static inline void set_helper_retaddr(uintptr_t ra) +{ + helper_retaddr = ra; + /* + * Ensure that this write is visible to the SIGSEGV handler that + * may be invoked due to a subsequent invalid memory operation. + */ + signal_barrier(); +} + +static inline void clear_helper_retaddr(void) +{ + /* + * Ensure that previous memory operations have succeeded before + * removing the data visible to the signal handler. + */ + signal_barrier(); + helper_retaddr = 0; +} + +#endif diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index eb8f3f0595..82690d3947 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -300,31 +300,7 @@ Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, abi_ptr addr, Int128 cmpv, Int128 newv, MemOpIdx oi, uintptr_t retaddr); -#if defined(CONFIG_USER_ONLY) - -extern __thread uintptr_t helper_retaddr; - -static inline void set_helper_retaddr(uintptr_t ra) -{ - helper_retaddr = ra; - /* - * Ensure that this write is visible to the SIGSEGV handler that - * may be invoked due to a subsequent invalid memory operation. - */ - signal_barrier(); -} - -static inline void clear_helper_retaddr(void) -{ - /* - * Ensure that previous memory operations have succeeded before - * removing the data visible to the signal handler. - */ - signal_barrier(); - helper_retaddr = 0; -} - -#else +#if !defined(CONFIG_USER_ONLY) #include "tcg/oversized-guest.h" @@ -376,7 +352,7 @@ static inline CPUTLBEntry *tlb_entry(CPUState *cpu, uintptr_t mmu_idx, return &cpu->neg.tlb.f[mmu_idx].table[tlb_index(cpu, mmu_idx, addr)]; } -#endif /* defined(CONFIG_USER_ONLY) */ +#endif /* !defined(CONFIG_USER_ONLY) */ #if TARGET_BIG_ENDIAN # define cpu_lduw_data cpu_lduw_be_data diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5c70748060..225e5fbd3e 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -41,6 +41,9 @@ #include "tb-context.h" #include "internal-common.h" #include "internal-target.h" +#if defined(CONFIG_USER_ONLY) +#include "user-retaddr.h" +#endif /* -icount align implementation. */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 3cac3a78c4..1c621477ad 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -31,6 +31,7 @@ #include "tcg/tcg-ldst.h" #include "internal-common.h" #include "internal-target.h" +#include "user-retaddr.h" __thread uintptr_t helper_retaddr; From patchwork Wed Apr 17 18:27:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 789328 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp173388wrm; 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231211212003.21686-13-philmd@linaro.org> --- target/i386/tcg/fpu_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 4b965a5d6c..ece22a3553 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -21,6 +21,7 @@ #include #include "cpu.h" #include "tcg-cpu.h" +#include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" From patchwork Wed Apr 17 18:28:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 789334 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp173861wrm; Wed, 17 Apr 2024 11:32:09 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUUOLiCItvSjHovkp3qELEw8pq0Zydfzflr1XS9gC0bpiQckmWBuXepfEJTLaRXJLAnkM1u4UR36dh0QycRAPF3 X-Google-Smtp-Source: AGHT+IFW9MNUrufhHTRXzZRmtkNVY9KN9EqhFmp07+OlHA6ZCwOSRFbmQiUtrlnb9kv7BZfUcoJZ X-Received: by 2002:ac8:7d8f:0:b0:436:46ba:7a3f with SMTP id c15-20020ac87d8f000000b0043646ba7a3fmr291566qtd.48.1713378729218; Wed, 17 Apr 2024 11:32:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713378729; cv=none; d=google.com; s=arc-20160816; b=GL1lSfuOXkgpM7RCjqu1aH1pJgAdSkf0Wm/9+GxLjqzDmuFjEL0xbydfwG3Rmw2yjh mKeYQz/YrCu1qvKUbpkrGrkkDMQmkZBGtAh3bIXHoiVgzTVxKmn9NyGd+iTXKsc+5nN8 wEyzhMi6WWNMDRjh5WsXSwz9xdNpYSMZpANoRG91YqKr1xc/AyqY07r+K3rsw9dq8GzO a53YX0RL9gU8su/XZRE9mQCg2NRMwVn8LrtN/VqHs6RmBoxQmYQULs7Mu2jXhl5NSW0I 7MMQJwaQoB9RcwKc5+Mz1jZssIlramcDnwotCg6CkbINnQn8XEp6ilKliy/6HQZCHmge iq4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=76vcPv2r9CdASlN2TgaoXk1O8gv7hK5cwNss1TmWJNY=; fh=4h2n32rS/QTVLHkSl86VTm16hqnAMuCXWV/jhovneZg=; b=MkCHdOlWYB6yPZ4QhiOXHGaHCOtpImg8RJBo2c7YF82NpOk1kUZAHRXiZAlC/fwtcb QrHYyQhvOYIF2fB8cfbc0SETTQs3KSpgmE4zQhPi5SvYrYleoWs8txBh/oLJcSQIuSGX 3DqWzIxNwoxA121+4Owz9+1Jcpk75cvKM6O5V2aC5iR8UKiEbZQIUYB4K65OwqEr0I9w LYI9jM6rdGU1AjjimNeBtcv9MK6cMvVpTq29j11s4IIYPClHhf7DK3HDDp4mMUyPMXeg osqDo5FXWD7seSN22Zuyo8Q6Nbku6IUcfJRgpUuDhzNle8FofW02b+w/RjJqxMdk931z QeMw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DsbGbR2q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Message-Id: <20231212123401.37493-12-philmd@linaro.org> Reviewed-by: Richard Henderson --- accel/tcg/tcg-accel-ops.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 9c957f421c..2c7b0cc09e 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -37,6 +37,8 @@ #include "exec/tb-flush.h" #include "exec/gdbstub.h" +#include "hw/core/cpu.h" + #include "tcg-accel-ops.h" #include "tcg-accel-ops-mttcg.h" #include "tcg-accel-ops-rr.h" From patchwork Wed Apr 17 18:28:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 789325 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp173140wrm; Wed, 17 Apr 2024 11:30:32 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXbckOvIlqyNy/2otBjycCztuja5QfDjHqcVYqWFgZ8ILmf0NfE/rzUklVzUTH0QSVlu8TLcWmcSa0mXk/G7xHK X-Google-Smtp-Source: AGHT+IH7pMOO3KiglT8SbumZQ+t4Ho2hvNznt3LWN4RTpwk6EBuRIyFHuTcbau2cq1pBwCHcKfua X-Received: by 2002:a05:622a:30a:b0:434:a5c9:b8e3 with SMTP id q10-20020a05622a030a00b00434a5c9b8e3mr369787qtw.17.1713378632376; Wed, 17 Apr 2024 11:30:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713378632; cv=none; d=google.com; s=arc-20160816; b=CoDO6wm83U7AJe7438Zq7Bps2B4yIJ0PpOl1rWGOdbv1Vs/b2GLft65xN+XquBFxQ6 cy+E39GidYCYMENPJXOsdSDzWpkyxSvVHizYd5g2kwTMbvCypXErOpv0UmeluOF+R6j0 1J5Wc1aawGORg4oIzZvKWzNmwNcg5e8sxIiRhbiT7UNkh0VVzK5CI4AbVULKoT7EB4qB CWXvSp13rsCG5mTqv8bEOV50dc4eK0RJBIa1sJZsIH3RVzjBYjPRx6MwlLaCtGh4VJko crE7QiBQWxWZEGCiNIiGaY7Mw8tWsyhVAxik8OMw9fl78VJgo3w8USpBEV4jmvryTOvY e+7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ksGtnbhVlkkzbu1KHQ/46hqlmcPyNdFy0jfCVGKxgOI=; fh=4h2n32rS/QTVLHkSl86VTm16hqnAMuCXWV/jhovneZg=; b=oPEvAw0OSmQDWp0x2jDXUVoUNhCsiPOGftmHK420e4FQ2y3+hNuzUYC/Ja27F7segO yvo/2MGDANnA4PZHOzMy9TL34z3RQyYIZdtkwdGGYE4JiO2tqcmDO9z2minCiyWzV9AY wn0pH4KPoQfupEdOXsg/kU0c2PePTBd0dM7GWJfcRzGceL+Mxe9gqTwRpzjc000ilXDc hLqdmpJN7VlhAmd8YpwDRXetRkJRcqmphx4Fm7ZWor3kDbguP8/bIJwDxyeat5ADw9q8 xhm4oT3LncT4yy6nsnZKKWohtLS89hw1CAJKbj53NWHRzWyGq4fnlMykq6Je7V4q6Nzl oDUA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tedQrk27; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Message-Id: <20231212123401.37493-13-philmd@linaro.org> Reviewed-by: Richard Henderson --- include/exec/cpu-all.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 586dc56d9e..4de0d5a0d7 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -22,7 +22,6 @@ #include "exec/cpu-common.h" #include "exec/memory.h" #include "exec/tswap.h" -#include "qemu/thread.h" #include "hw/core/cpu.h" /* some important defines: From patchwork Wed Apr 17 18:28:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 789324 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp172907wrm; Wed, 17 Apr 2024 11:30:06 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXu6tf8WaUp5s2Qt75HTH7mz756YMHQ8vcINN1NSSzjS7q1OqzlUwKxhTsWW8Bqvtewb4SrUnO2B93MRZvjpXjl X-Google-Smtp-Source: AGHT+IFAafdBJMHq9dMSy4We+PkmKyPSbnxYRVLltZ9bBzJKKsgUzdb2323GZK4mGsm2Qxq/piVY X-Received: by 2002:a25:361c:0:b0:dcc:744d:b485 with SMTP id d28-20020a25361c000000b00dcc744db485mr183484yba.33.1713378605645; Wed, 17 Apr 2024 11:30:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713378605; cv=none; d=google.com; s=arc-20160816; b=0X6T6aCnVDC6OX86mhIMQA/0Weo063PoHV/V1oRajvJtJSFi5NgtlAfElyLmaOt9ar rlnTsqL7YkITv/R9qH0Nrzp1ESJQ9qmtT0snw59/uanxQOpK4Dx7pRMaCvVi959tnfBZ AUFp3Ptqd/uULcCBtuAPi2lN/7AHyO2cEc14VrexagJdyEOdiZW8/YunqSDfiF2UgLFu euSPF09WBbGChKgsrR3Hz+gdHLXC1g7IHYzqNs8t/Lm6crhVfcUy+QmO5WBhEo5aZzIO JHUyYg+lgPmjPBavxxpU0YXp/2Jr82TAxJj2xi5TXq7F4wDv0y5N9IzddHo0D7lyJyZ3 iNiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=NHZqwbv+wjH/HmWZ9HfsbsxWvnOGugUAYDu3jydEASY=; fh=4h2n32rS/QTVLHkSl86VTm16hqnAMuCXWV/jhovneZg=; b=AawmEr1cDzF7mtk+aDw1kRgC9amGLbCzHFzM7hpCL7orZqcWKX8Re8AyVE7lZXifWg H64p6KxbQ5qPsYeRPeZ6g9vy5ngefcHRKaKiCquaMXM2qnz4Soh0e29UeCbSKoeQrRL+ HnE0kmSF+BlIGFT3BDUtfZFPMqZALu6muh5TIg4IKthMeBc8tie11ZrJ/sY6ieaXQ0AI J7Rf+eeVZnPIoaHj6mNIFeTmGVF8LEnI78h4TH2hJqLXEUIifpyI/nI3shbywDqzL7RT M7Cp3Acu7dM4n6xCgyd4Wt+T6pBt4JJhsGp8QqW1Vn7XdiCOcK1g9icQCrPHQkklCHQX b1QA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UWShZDht; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Message-Id: <20231212123401.37493-15-philmd@linaro.org> Reviewed-by: Richard Henderson --- include/exec/cpu-all.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 4de0d5a0d7..7c44ffb3af 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -38,11 +38,9 @@ #if TARGET_LONG_SIZE == 4 #define tswapl(s) tswap32(s) -#define tswapls(s) tswap32s((uint32_t *)(s)) #define bswaptls(s) bswap32s(s) #else #define tswapl(s) tswap64(s) -#define tswapls(s) tswap64s((uint64_t *)(s)) #define bswaptls(s) bswap64s(s) #endif From patchwork Wed Apr 17 18:28:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 789333 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp173658wrm; Wed, 17 Apr 2024 11:31:43 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCURYNIQMRNYR2C4rtesrjBcnksPJaYANspGXG7YVVWgLIyZQx18KMT+UmNbzQm6NdnRs9SGMieAR5WkervH21Wr X-Google-Smtp-Source: AGHT+IEYdCX8LhFkkOuN8TLKyvrnKSOwZAM3IDQEbycVIJ5dTvt/LU/dpXfroDL4yF/0iUw1P8NC X-Received: by 2002:a05:620a:4945:b0:78e:c0f7:54fb with SMTP id vz5-20020a05620a494500b0078ec0f754fbmr230351qkn.50.1713378703399; Wed, 17 Apr 2024 11:31:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713378703; cv=none; d=google.com; s=arc-20160816; b=vfAKJEO+gRgUGycBRyxCDox+k/Q+WmP7syOSggQb/KZDdGr3Tqmrt3ri0LIj11Q3gF HECRE8nW+WM1Ws+ELYmAjuyZevcTgkZY4ZEhbbjfqyFoZj3g8xioWhHnZubXWtjLIqGd itC5zxfjc+qDmL8YdtiaGqKQUeefS5HxqV+EJpfKZb73OF1T9L0sap9x95kbxElSEg6o y1bXgjh4HhI/qojvkFL2c8Ay6AnXmGYb2hiHD4uASvwcjR3BNfw7eR0lnBHCk0thnEwp bvXFsWzCyAORcaXLYWtVICLAgzdvDPJMz/Y95mtQqHUM8X5WqVhPWU/0XifyjM0hisaV BJZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=n0UB6yYdJ7G4jV8uDJ7wPEMwbZmtBQgbO2jPSnrKT98=; fh=4h2n32rS/QTVLHkSl86VTm16hqnAMuCXWV/jhovneZg=; b=J6vtBVLSwvPdMuEyuqRFEH2UzmcGBfcWqcZMx2B2od6nfw5fmroBeMuH9t/LtUE50S WVMQS2kNv+Z0su/jUfe53lGLBdtX3AwvqlaGDXbQYyXHkAS+ADmRhKVgNzdS51WfS8C+ HU7v3i4tv2PzukX1I+wxCWgWQTKtzNyIr0UMJBWeAoQqAVF+BxbT3PLZINYGauAn07Gz wBj0/R5N8QXOArovJW4l+Md/uliJorKRmYi48RziNRPUpftQ7sYlpyAXOlUNhGMkkjOw Qbv3x5qned+y1W4LiwBZ3Cgx6yG/OKsuzCd2d7OyAEWlsI71Ckocf2ZNO4UEErkfAxkM bd0Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fSk4uxYo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Remove "hw/core/cpu.h" when it was only included to get the target_words_bigendian() declaration. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Message-Id: <20231212123401.37493-16-philmd@linaro.org> Reviewed-by: Richard Henderson --- include/exec/tswap.h | 12 +++++++++++- include/hw/core/cpu.h | 11 ----------- cpu-target.c | 1 + disas/disas.c | 1 + hw/audio/virtio-snd.c | 2 +- hw/core/cpu-sysemu.c | 2 +- hw/core/generic-loader.c | 2 +- hw/display/vga.c | 2 +- hw/virtio/virtio.c | 1 + 9 files changed, 18 insertions(+), 16 deletions(-) diff --git a/include/exec/tswap.h b/include/exec/tswap.h index 5089cd6a4c..b7a4191347 100644 --- a/include/exec/tswap.h +++ b/include/exec/tswap.h @@ -8,9 +8,19 @@ #ifndef TSWAP_H #define TSWAP_H -#include "hw/core/cpu.h" #include "qemu/bswap.h" +/** + * target_words_bigendian: + * Returns true if the (default) endianness of the target is big endian, + * false otherwise. Note that in target-specific code, you can use + * TARGET_BIG_ENDIAN directly instead. On the other hand, common + * code should normally never need to know about the endianness of the + * target, so please do *not* use this function unless you know very well + * what you are doing! + */ +bool target_words_bigendian(void); + /* * If we're in target-specific code, we can hard-code the swapping * condition, otherwise we have to do (slower) run-time checks. diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 7f037b158e..3a66d8581e 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1169,17 +1169,6 @@ bool cpu_exec_realizefn(CPUState *cpu, Error **errp); void cpu_exec_unrealizefn(CPUState *cpu); void cpu_exec_reset_hold(CPUState *cpu); -/** - * target_words_bigendian: - * Returns true if the (default) endianness of the target is big endian, - * false otherwise. Note that in target-specific code, you can use - * TARGET_BIG_ENDIAN directly instead. On the other hand, common - * code should normally never need to know about the endianness of the - * target, so please do *not* use this function unless you know very well - * what you are doing! - */ -bool target_words_bigendian(void); - const char *target_name(void); #ifdef COMPILING_PER_TARGET diff --git a/cpu-target.c b/cpu-target.c index 4c0621bf33..f88649c299 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -35,6 +35,7 @@ #endif #include "sysemu/cpus.h" #include "sysemu/tcg.h" +#include "exec/tswap.h" #include "exec/replay-core.h" #include "exec/cpu-common.h" #include "exec/exec-all.h" diff --git a/disas/disas.c b/disas/disas.c index 7e3b0bb46c..ec14715ecd 100644 --- a/disas/disas.c +++ b/disas/disas.c @@ -6,6 +6,7 @@ #include "disas/disas.h" #include "disas/capstone.h" #include "hw/core/cpu.h" +#include "exec/tswap.h" #include "exec/memory.h" /* Filled in by elfload.c. Simplistic, but will do for now. */ diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c index c80b58bf5d..6a2ee085c0 100644 --- a/hw/audio/virtio-snd.c +++ b/hw/audio/virtio-snd.c @@ -20,11 +20,11 @@ #include "qemu/log.h" #include "qemu/error-report.h" #include "include/qemu/lockable.h" +#include "exec/tswap.h" #include "sysemu/runstate.h" #include "trace.h" #include "qapi/error.h" #include "hw/audio/virtio-snd.h" -#include "hw/core/cpu.h" #define VIRTIO_SOUND_VM_VERSION 1 #define VIRTIO_SOUND_JACK_DEFAULT 0 diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index d0d6a910f9..2a9a2a4eb5 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "hw/core/cpu.h" +#include "exec/tswap.h" #include "hw/core/sysemu-cpu-ops.h" bool cpu_paging_enabled(const CPUState *cpu) diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c index d4b5c501d8..ea8628b892 100644 --- a/hw/core/generic-loader.c +++ b/hw/core/generic-loader.c @@ -31,7 +31,7 @@ */ #include "qemu/osdep.h" -#include "hw/core/cpu.h" +#include "exec/tswap.h" #include "sysemu/dma.h" #include "sysemu/reset.h" #include "hw/boards.h" diff --git a/hw/display/vga.c b/hw/display/vga.c index 77f59e8c11..d17ff4b93a 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -26,7 +26,7 @@ #include "qemu/units.h" #include "sysemu/reset.h" #include "qapi/error.h" -#include "hw/core/cpu.h" +#include "exec/tswap.h" #include "hw/display/vga.h" #include "hw/i386/x86.h" #include "hw/pci/pci.h" diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index 871674f9be..893a072c9d 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -20,6 +20,7 @@ #include "qemu/log.h" #include "qemu/main-loop.h" #include "qemu/module.h" +#include "exec/tswap.h" #include "qom/object_interfaces.h" #include "hw/core/cpu.h" #include "hw/virtio/virtio.h" From patchwork Wed Apr 17 18:28:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 789330 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp173621wrm; Wed, 17 Apr 2024 11:31:38 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXpJsZ3zr/HmSmRuCCow2YO15h3zXT0/hccETIRWaPVmeNsEc9c+uW7zNKL0i+HubVE0rwuDX86akyMf2VLHOTZ X-Google-Smtp-Source: AGHT+IHZuH53Vt/o0IUt8aiRipq0WKM36m4Ro3Rc6b0K5CVJY+ao9HVIKu66fHNfft/ZfFrJ6nGf X-Received: by 2002:a0c:dc8f:0:b0:69b:71f8:b3fe with SMTP id n15-20020a0cdc8f000000b0069b71f8b3femr199728qvk.42.1713378698476; Wed, 17 Apr 2024 11:31:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713378698; cv=none; d=google.com; s=arc-20160816; b=r6tzLykBY1yRZeiw/bWMxyrbJq/V54GxzOCRTWepnAG8rV78ONT3qBIoIqhVBwwbvd s/ddZOGq8SPdgvo3LSa9s6ow37/SsEg5Zv1B9jNFoDj1HexsaL8laY7sDvTDqxGOX+9c Jctmhe1xQdp6czwbEyydE/UuB4DtQvAat3itxaigebPkMTzm5uER7SBWArK4Ir/h9WBb oCYR81pt7MWE9NFiXhT+STR0PYQszgllMFx+SjSNvGo4PfFHsCPEzlZf8OggNbY3ovza IOrWQqsi1xAjNV929xL5Amk0mKLff4mlBMtgfQt0tDQbF7dftKXjDjhJwRICDVD6+6tg 9KQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=J8eo2jSvcn1ZSvG3FSu+38gN1aTmZ4jM+1lXBXdjpkc=; fh=4h2n32rS/QTVLHkSl86VTm16hqnAMuCXWV/jhovneZg=; b=MDGZEKAcVdjff5IJrUze+FWLaP74e4FvG8w+jtRT2ujRlsvm9/Q/hHfeCBs/t9bcvP H3OGvzjpiPsUsviktnH9sMmghyXmKL3U0bdZCHT/RUuedoT1Z/T8J8HOy+gL7b6guXfi WbnUCNOFhENSxqaWWRTZ0QNkVuQOn9F2V1kgoq9IVFsgmfvhCVOBE/zRjBZZrkVPipJ9 3zOxEAI6Cr3JWYqozx163PfhgGjmzPq1C6IHUPWq+0AGrjHt7R8e3QweopIFBzobeU+Q 2azxvraCUAVHLDg1GsculVRVn6YG1+u2KSTB5iuwq3z5DZGsaakuI15Ss99bqJGVHVGX F/kA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Dl4YDuDn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Move their definitions to a new header: "exec/user/tswap-target.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Message-Id: <20231212123401.37493-17-philmd@linaro.org> Reviewed-by: Richard Henderson --- MAINTAINERS | 1 + bsd-user/freebsd/target_os_elf.h | 1 + bsd-user/freebsd/target_os_stack.h | 1 + bsd-user/netbsd/target_os_elf.h | 1 + bsd-user/openbsd/target_os_elf.h | 1 + include/exec/cpu-all.h | 8 -------- include/exec/user/abitypes.h | 1 + include/user/tswap-target.h | 22 ++++++++++++++++++++++ bsd-user/signal.c | 1 + bsd-user/strace.c | 1 + linux-user/elfload.c | 1 + linux-user/i386/signal.c | 1 + linux-user/ppc/signal.c | 1 + 13 files changed, 33 insertions(+), 8 deletions(-) create mode 100644 include/user/tswap-target.h diff --git a/MAINTAINERS b/MAINTAINERS index f1f6922025..e85b358683 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3704,6 +3704,7 @@ Overall usermode emulation M: Riku Voipio S: Maintained F: accel/tcg/user-exec*.c +F: include/exec/user/ F: include/user/ F: common-user/ diff --git a/bsd-user/freebsd/target_os_elf.h b/bsd-user/freebsd/target_os_elf.h index 9df17d56d8..01124979f7 100644 --- a/bsd-user/freebsd/target_os_elf.h +++ b/bsd-user/freebsd/target_os_elf.h @@ -22,6 +22,7 @@ #include "target_arch_elf.h" #include "elf.h" +#include "user/tswap-target.h" #define bsd_get_ncpu() 1 /* until we pull in bsd-proc.[hc] */ diff --git a/bsd-user/freebsd/target_os_stack.h b/bsd-user/freebsd/target_os_stack.h index d15fc3263f..ac0ef22cd7 100644 --- a/bsd-user/freebsd/target_os_stack.h +++ b/bsd-user/freebsd/target_os_stack.h @@ -23,6 +23,7 @@ #include #include "target_arch_sigtramp.h" #include "qemu/guest-random.h" +#include "user/tswap-target.h" /* * The initial FreeBSD stack is as follows: diff --git a/bsd-user/netbsd/target_os_elf.h b/bsd-user/netbsd/target_os_elf.h index 2f3cb20871..9de0f290c0 100644 --- a/bsd-user/netbsd/target_os_elf.h +++ b/bsd-user/netbsd/target_os_elf.h @@ -22,6 +22,7 @@ #include "target_arch_elf.h" #include "elf.h" +#include "user/tswap-target.h" /* this flag is uneffective under linux too, should be deleted */ #ifndef MAP_DENYWRITE diff --git a/bsd-user/openbsd/target_os_elf.h b/bsd-user/openbsd/target_os_elf.h index 6dca9c5a85..4cf5747dcd 100644 --- a/bsd-user/openbsd/target_os_elf.h +++ b/bsd-user/openbsd/target_os_elf.h @@ -22,6 +22,7 @@ #include "target_arch_elf.h" #include "elf.h" +#include "user/tswap-target.h" /* this flag is uneffective under linux too, should be deleted */ #ifndef MAP_DENYWRITE diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 7c44ffb3af..78848f018c 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -36,14 +36,6 @@ #define BSWAP_NEEDED #endif -#if TARGET_LONG_SIZE == 4 -#define tswapl(s) tswap32(s) -#define bswaptls(s) bswap32s(s) -#else -#define tswapl(s) tswap64(s) -#define bswaptls(s) bswap64s(s) -#endif - /* Target-endianness CPU memory access functions. These fit into the * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h. */ diff --git a/include/exec/user/abitypes.h b/include/exec/user/abitypes.h index 6178453d94..56e96fcb99 100644 --- a/include/exec/user/abitypes.h +++ b/include/exec/user/abitypes.h @@ -2,6 +2,7 @@ #define EXEC_USER_ABITYPES_H #include "cpu.h" +#include "user/tswap-target.h" #ifdef TARGET_ABI32 #define TARGET_ABI_BITS 32 diff --git a/include/user/tswap-target.h b/include/user/tswap-target.h new file mode 100644 index 0000000000..4719330dbb --- /dev/null +++ b/include/user/tswap-target.h @@ -0,0 +1,22 @@ +/* + * target-specific swap() definitions + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#ifndef USER_TSWAP_H +#define USER_TSWAP_H + +#include "exec/cpu-defs.h" +#include "exec/tswap.h" + +#if TARGET_LONG_SIZE == 4 +#define tswapl(s) tswap32(s) +#define bswaptls(s) bswap32s(s) +#else +#define tswapl(s) tswap64(s) +#define bswaptls(s) bswap64s(s) +#endif + +#endif diff --git a/bsd-user/signal.c b/bsd-user/signal.c index e5a773ddde..b2faf1d0dd 100644 --- a/bsd-user/signal.c +++ b/bsd-user/signal.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu.h" +#include "user/tswap-target.h" #include "gdbstub/user.h" #include "signal-common.h" #include "trace.h" diff --git a/bsd-user/strace.c b/bsd-user/strace.c index 96499751eb..6dc01d3be7 100644 --- a/bsd-user/strace.c +++ b/bsd-user/strace.c @@ -22,6 +22,7 @@ #include #include "qemu.h" +#include "user/tswap-target.h" #include "os-strace.h" /* OS dependent strace print functions */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 60cf55b36c..28d9e8a9a5 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -7,6 +7,7 @@ #include #include "qemu.h" +#include "user/tswap-target.h" #include "user-internals.h" #include "signal-common.h" #include "loader.h" diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c index cfe70fc5cf..990048f42a 100644 --- a/linux-user/i386/signal.c +++ b/linux-user/i386/signal.c @@ -21,6 +21,7 @@ #include "user-internals.h" #include "signal-common.h" #include "linux-user/trace.h" +#include "user/tswap-target.h" /* from the Linux kernel - /arch/x86/include/uapi/asm/sigcontext.h */ diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c index 652038a53c..a1d8c0bccc 100644 --- a/linux-user/ppc/signal.c +++ b/linux-user/ppc/signal.c @@ -21,6 +21,7 @@ #include "user-internals.h" #include "signal-common.h" #include "linux-user/trace.h" +#include "user/tswap-target.h" #include "vdso-asmoffset.h" /* See arch/powerpc/include/asm/ucontext.h. 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Assert this user-specific header is only included from user emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Message-Id: <20231212123401.37493-20-philmd@linaro.org> Reviewed-by: Richard Henderson --- include/exec/user/abitypes.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/exec/user/abitypes.h b/include/exec/user/abitypes.h index 56e96fcb99..b5c7ad4d1a 100644 --- a/include/exec/user/abitypes.h +++ b/include/exec/user/abitypes.h @@ -1,7 +1,12 @@ #ifndef EXEC_USER_ABITYPES_H #define EXEC_USER_ABITYPES_H -#include "cpu.h" +#ifndef CONFIG_USER_ONLY +#error Cannot include this header from system emulation +#endif + +#include "exec/cpu-defs.h" +#include "exec/tswap.h" #include "user/tswap-target.h" #ifdef TARGET_ABI32 From patchwork Wed Apr 17 18:28:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 789329 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp173507wrm; Wed, 17 Apr 2024 11:31:22 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVz2QFBumPGh5oIJVScN5qZppQDEFfg3me0j2fywnuDv6VwZyYDdf0GllRSSGaisfvNcae0o9LoNaTocLHlc5ie X-Google-Smtp-Source: AGHT+IHGc35qT/Oex31meYOEh9l8alv47ID5MzdRgkOOCSP+kaWAbqZPZkqvuxW9VDIP6JW8X+9b X-Received: by 2002:a05:620a:2197:b0:78e:f809:8f8e with SMTP id g23-20020a05620a219700b0078ef8098f8emr209014qka.55.1713378682126; Wed, 17 Apr 2024 11:31:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713378682; cv=none; d=google.com; s=arc-20160816; b=lI/stChEEWp5KrvyDGJRPQSg16JZmiAYNXYDKKkNalAIsFHq3ZLfPsQ8bUghZFeRVI 7e/toAtVY08pv4kbVyoCGdcJ3lscs9HtafYIZTwfMoyzopXJg1pAGMyXL+eOuTb2MM7o L1IQFK3Gxt9N/n+TCJUYs1svBycZIoG9RMvUhbKq61PlvoO4VBR/Nda8myI4nr6LuThV fbryN2hxBQICKGpplPXLsSUQNsF5GoYun9/ewEbBxVOl9rLoCdLd6ZMVIRfDVXkVo43D aw2Bn755JpG1hJUihou3Th2wydSjljP+OGrMX11NS4QS5sN9uzpW3ND4HXEy0fb+mLhQ HaWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=T2iJJmV+2DNCV1vqfBBGFjheXtYtlaqsPcXM/OBu1Kk=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=SuXbsgkqG9noD0MOWOYRLTdTYnq08u3fYpjgTwNmU893KHAbYIzewrxE7XucdsN6hY GisZLd4NQ5qMB8edwXI4fcdt2ET7NLHTKfLoTDQW0HqKAyUxDgem2R6xk6I6AVtdB1VD t2Aerhm0PjdB8ZvvQgMO2JCuxmtM9ZYeEhLiklKKAQAqWxzePQYElMLbztpDHU0ti5n4 KpfIkFox/i4XhwpCVXFb44r/wteFVSlqWJAhCPy4YGFXJ6DTfvbm+Wbw4HckGGhmsI0N gkuo1KEypC2AwMuG4LS2F7MshaK4Q3xa6WXbGbxZH5w8iFtduNMligF7BaLOC3DvSpl2 CqHA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jo5u4ce0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t26-20020a05620a0b1a00b0078ec905414asi13518274qkg.19.2024.04.17.11.31.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 Apr 2024 11:31:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jo5u4ce0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rxA3I-0005bd-H5; Wed, 17 Apr 2024 14:30:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rxA2w-0004jT-Ek for qemu-devel@nongnu.org; Wed, 17 Apr 2024 14:30:15 -0400 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rxA2s-00040w-9j for qemu-devel@nongnu.org; Wed, 17 Apr 2024 14:30:13 -0400 Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-56e37503115so13264a12.1 for ; Wed, 17 Apr 2024 11:30:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1713378608; x=1713983408; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T2iJJmV+2DNCV1vqfBBGFjheXtYtlaqsPcXM/OBu1Kk=; b=jo5u4ce0FeUMneV8F7Ls0Nr5gNiJBFbSFRCVyrNPdSA7cze0BKBEhlBw7xLF1uTgFZ oPk64MQ2ob6IiUYs2uUu3Oz5TjWJS2wkPriK6OGbX1Xe2a4ngYaBZJqimgnkZEVIy6zK B36n/huHLt/O5ruc3rxqByWbD5202UuCt4QtSZwmriTSjGSPUQrgV+uqD+lQjHRV0e0h KE8eiDXUpizjiC4K5N4/VB+F6ON9jTprp+RW41OgqOBR4zp6jk9w9w4Pd9zypGRYxqqe VYiio/wyZrqhnkep4fCqub8HKsjyVWD+V5V9jhv/ee8sFNEPkSf7BuSfZmigNDdnorvI X/ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713378608; x=1713983408; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T2iJJmV+2DNCV1vqfBBGFjheXtYtlaqsPcXM/OBu1Kk=; b=Q1oikTpoW7k3+4AKmXLq0hbJsW42FTgPeFzGEl5jcqNAcStzoVG9KFrzo2NUef2ZM8 17fn2Xfgiu/iHGUzq++uGBNW7tib8KWxPWMqvD6J6y+u+5yHqICraTwjW+v30OIppKjl O7LUD7IeHD+2gQvD75IvQxLeimjNCsOd/q3gbTCX5zA3A9XgOcWdE/bUXfHvc/pjaxoo AOh/I1DtXDNzP7nct3JpQlFnAg0VRJjkPERg3b2NISMznZqJgVq8uoDta98T/2DYnHJ8 9RO5++gE166QD8BRIuIyc/rMDRpVM5MU2wQVQU47HKBHD3AJ8YDcsBoT8u0YP3xcW389 6rhQ== X-Gm-Message-State: AOJu0YzqcMWdY8wEImKLBBuKlny1TgL/wLyrlZuD8kot0/TdwEady6g8 072RfNlQfJL8guWti0fwCGrFMg0pJKTAkvRBRSYIq49+pMDG4q/NPnXCThkhp+Gi3ZhwUAxzBqK c X-Received: by 2002:a50:9e4e:0:b0:570:d50:e7d8 with SMTP id z72-20020a509e4e000000b005700d50e7d8mr306233ede.22.1713378608179; Wed, 17 Apr 2024 11:30:08 -0700 (PDT) Received: from m1x-phil.lan ([176.187.201.23]) by smtp.gmail.com with ESMTPSA id t6-20020a056402020600b0057030326144sm3467024edv.47.2024.04.17.11.30.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 17 Apr 2024 11:30:07 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH 21/21] exec: Declare abi_ptr type in its own 'abi_ptr.h' header Date: Wed, 17 Apr 2024 20:28:06 +0200 Message-ID: <20240417182806.69446-22-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240417182806.69446-1-philmd@linaro.org> References: <20240417182806.69446-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=philmd@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The abi_ptr type is declared in "exec/cpu_ldst.h" with all the load/store helpers. Some source files requiring abi_ptr type don't need the load/store helpers. In order to simplify, create a new "exec/abi_ptr.h" header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231212123401.37493-21-philmd@linaro.org> --- include/exec/abi_ptr.h | 33 +++++++++++++++++++++++++++++++++ include/exec/cpu_ldst.h | 17 +++-------------- include/exec/exec-all.h | 1 + include/exec/translator.h | 5 ++++- 4 files changed, 41 insertions(+), 15 deletions(-) create mode 100644 include/exec/abi_ptr.h diff --git a/include/exec/abi_ptr.h b/include/exec/abi_ptr.h new file mode 100644 index 0000000000..2aedcceb0c --- /dev/null +++ b/include/exec/abi_ptr.h @@ -0,0 +1,33 @@ +/* + * QEMU abi_ptr type definitions + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#ifndef EXEC_ABI_PTR_H +#define EXEC_ABI_PTR_H + +#include "cpu-param.h" + +#if defined(CONFIG_USER_ONLY) +/* + * sparc32plus has 64bit long but 32bit space address + * this can make bad result with g2h() and h2g() + */ +#if TARGET_VIRT_ADDR_SPACE_BITS <= 32 +typedef uint32_t abi_ptr; +#define TARGET_ABI_FMT_ptr "%x" +#else +typedef uint64_t abi_ptr; +#define TARGET_ABI_FMT_ptr "%"PRIx64 +#endif + +#else /* !CONFIG_USER_ONLY */ + +#include "exec/target_long.h" + +typedef target_ulong abi_ptr; +#define TARGET_ABI_FMT_ptr TARGET_FMT_lx + +#endif /* !CONFIG_USER_ONLY */ + +#endif diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 82690d3947..64e0319996 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -63,20 +63,11 @@ #define CPU_LDST_H #include "exec/memopidx.h" +#include "exec/abi_ptr.h" #include "qemu/int128.h" #include "cpu.h" #if defined(CONFIG_USER_ONLY) -/* sparc32plus has 64bit long but 32bit space address - * this can make bad result with g2h() and h2g() - */ -#if TARGET_VIRT_ADDR_SPACE_BITS <= 32 -typedef uint32_t abi_ptr; -#define TARGET_ABI_FMT_ptr "%x" -#else -typedef uint64_t abi_ptr; -#define TARGET_ABI_FMT_ptr "%"PRIx64 -#endif #ifndef TARGET_TAGGED_ADDRESSES static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x) @@ -120,10 +111,8 @@ static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong len) assert(h2g_valid(x)); \ h2g_nocheck(x); \ }) -#else -typedef vaddr abi_ptr; -#define TARGET_ABI_FMT_ptr VADDR_PRIx -#endif + +#endif /* CONFIG_USER_ONLY */ uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr); int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr); diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 3e53501691..e932d364b6 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -22,6 +22,7 @@ #include "cpu.h" #if defined(CONFIG_USER_ONLY) +#include "exec/abi_ptr.h" #include "exec/cpu_ldst.h" #endif #include "exec/translation-block.h" diff --git a/include/exec/translator.h b/include/exec/translator.h index 2c4fb818e7..6cd937ac5c 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -19,7 +19,10 @@ */ #include "qemu/bswap.h" -#include "exec/cpu_ldst.h" /* for abi_ptr */ +#include "exec/cpu-common.h" +#include "exec/cpu-defs.h" +#include "exec/abi_ptr.h" +#include "cpu.h" /** * gen_intermediate_code