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[209.132.180.67]) by mx.google.com with ESMTP id u8si115726edq.84.2019.10.08.13.48.56; Tue, 08 Oct 2019 13:48:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=xpMuk2LX; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731152AbfJHUsZ (ORCPT + 26 others); Tue, 8 Oct 2019 16:48:25 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:43360 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730787AbfJHUsX (ORCPT ); Tue, 8 Oct 2019 16:48:23 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x98KmJUp092460; Tue, 8 Oct 2019 15:48:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1570567699; bh=zV3cVdmjhCBXzQdA/5xCOaiT1n6XKbwdMaP1jdy4goo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xpMuk2LXulNdCJmzDpZrOEk1vHmxW+FD7Rn9RY7/3peP/TzY/v3rUxz8LAr/BRRod fURTJED8Z7jklWp2vqS+z2va5LMbKzFpr93OsJ4aZLm8kk+Rfj9vS497ohqNcEfdhP 7RhDWkizF/fpBBayFuLQFAf82WTyEJT3T52SIkgU= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x98KmJmx027690 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Oct 2019 15:48:19 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 8 Oct 2019 15:48:16 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 8 Oct 2019 15:48:19 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x98KmJUf066644; Tue, 8 Oct 2019 15:48:19 -0500 From: Dan Murphy To: , CC: , , Dan Murphy Subject: [PATCH v11 02/16] dt-bindings: leds: Add multicolor ID to the color ID list Date: Tue, 8 Oct 2019 15:47:46 -0500 Message-ID: <20191008204800.19870-3-dmurphy@ti.com> X-Mailer: git-send-email 2.22.0.214.g8dca754b1e In-Reply-To: <20191008204800.19870-1-dmurphy@ti.com> References: <20191008204800.19870-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a new color ID that is declared as MULTICOLOR as with the multicolor framework declaring a definitive color is not accurate as the node can contain multiple colors. Signed-off-by: Dan Murphy --- include/dt-bindings/leds/common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.22.0.214.g8dca754b1e diff --git a/include/dt-bindings/leds/common.h b/include/dt-bindings/leds/common.h index 9e1256a7c1bf..7006d15f71e8 100644 --- a/include/dt-bindings/leds/common.h +++ b/include/dt-bindings/leds/common.h @@ -29,7 +29,8 @@ #define LED_COLOR_ID_VIOLET 5 #define LED_COLOR_ID_YELLOW 6 #define LED_COLOR_ID_IR 7 -#define LED_COLOR_ID_MAX 8 +#define LED_COLOR_ID_MULTI 8 +#define LED_COLOR_ID_MAX 9 /* Standard LED functions */ #define LED_FUNCTION_ACTIVITY "activity" From patchwork Tue Oct 8 20:47:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 175569 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp6206908ill; Tue, 8 Oct 2019 13:49:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqxWNQhPPmEtblZQmJSmLhTBaRB35bl7toJKhyY86OEzEfNfcNuU4bn2kMan8734Hk9ZFeNx X-Received: by 2002:a17:906:5284:: with SMTP id c4mr30565455ejm.39.1570567743459; Tue, 08 Oct 2019 13:49:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570567743; cv=none; d=google.com; s=arc-20160816; b=ipADKenX8A9mHonfPTp6u/NJYIWtJCepdoPZGjk22ocounKCwwhBPLFrp+ZpRD2RrY NwkEEzhXXC6JSGXWl3glOSiHNKYQpDxEmFAwuOPTi+Mf2BcgL1m38U9nVX2jVaAIyuy9 tKXdC3hMzU4vLjq1r3uhM9YSZ5jblb+3O9/gaeUtJfG8Wy9Et8cnq9nah3YiJWOZ9U+A g6oMhIcS2tAowuqRbu/PjChYsZ1+3Auu8W1Tmgr9zNPmzRdqx/7+opRw4zCll+XXPMiX wiRFz7mTMYjeszj0SToz83APX2Hp3sypI+7W2YhOWCxJ81/4OyMjZC3jnijNvW0yR7nh pa9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vNLixCA7rV3r89geVpDyZT2afzJln66pkNhtKdigswM=; b=ZnaWElvt9oiy/hlBJeGHgBPqiAYo5AspbaEZ9qz8mxEoXd/Wq0dDfyCr0Q46G95HJ0 5HLcg9aTq0oc+6wo0+ksq5V/dtyoppFDOHL3cp+dtZO6LunT5YhT9+ykPZIrkEb4nSVx bjB8rUYoFbgyPFKG4f/tT16yMsVpvhHFwm4igP5rk3EcvsrKIgYT1RnisyZpvH1tZVgg ScSg0ZKEqoY1Z2uyNatwv4yNG8O32ZT3Q8DUzsm3kK/TdfQR/i5xcQLnSdrBXzxW63MM jpkl2mokpA1ZhLuAExqsYKrvJrDorunLe+uGjLjMJOKMqT2TO4xJopNsC/oy/aOjOmd9 IE7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=KoqvbU74; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dan Murphy --- drivers/leds/led-core.c | 1 + 1 file changed, 1 insertion(+) -- 2.22.0.214.g8dca754b1e diff --git a/drivers/leds/led-core.c b/drivers/leds/led-core.c index f1f718dbe0f8..846248a0693d 100644 --- a/drivers/leds/led-core.c +++ b/drivers/leds/led-core.c @@ -34,6 +34,7 @@ const char * const led_colors[LED_COLOR_ID_MAX] = { [LED_COLOR_ID_VIOLET] = "violet", [LED_COLOR_ID_YELLOW] = "yellow", [LED_COLOR_ID_IR] = "ir", + [LED_COLOR_ID_MULTI] = "multicolor", }; EXPORT_SYMBOL_GPL(led_colors); From patchwork Tue Oct 8 20:47:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 175573 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp6207066ill; Tue, 8 Oct 2019 13:49:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqyYDMF8nEK2tRUhx70goG2CP+p0BOv7U+ltKXThhhMCdpfOALXlWYUIkoVkRiB8nCRpO4/m X-Received: by 2002:a50:ed82:: with SMTP id h2mr36018414edr.206.1570567752605; Tue, 08 Oct 2019 13:49:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570567752; cv=none; d=google.com; s=arc-20160816; b=qHKk9WTvnZgx6UDKq/XRi8rpBSHLRUboKxrV8w3bmdDDZTbVp4THBHRCjEh6RIFgis oxViSIimOHNLpexN8rul4W0e/G82YVNYVM02b3xUOkqaiEdV3Go1s42fkquQbRCH1HUk gkY4bhHPY1GR0BCwlH1hBeCpiUYe4S8/lGC0uiZEx67VGAC3PcCwQ6eqttLt1BGdjeLw OFIoKF8goEq+1YdrCEEZiLcJPFNWsEpiAI+zUJ7crUqsKALze4Y4E13IlAqOeMLrpFCi sqRqvTbVuVGvbM169fr+e8YGakWgnq3/mxOeqX39D0Qtz8buUc0qeZqJ1roYblPug2hI gNGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LFJY/sk3vbxhRSCXMQMK8Y5qMhwQ/+YV7Aj17cmTfjg=; b=bnPVj9iuNfhIi/i11oguPlAkA8YvSg0vJlVEP2WG9qCqPP4H7A3j18dJ2DWOxE3dXX nQVb/zwXevoWnJdsjBC4O0a/rMgDc9VquoFR+HzNV2WGeoxX9TZ6ok3o8ejxJNShTDT+ pKmhDj5meif2ch9x6Bn2qI5rI4+sSp+nyMsY1okNQXc6wyPsT1VbEeTgMp3oQOFGOarb 3xXBO/i/1RfjsjRasgN6j4pEIJPxZZtdNrIrKwnk/MyruQ5fkEV6IPtlBI9CErhVxBMN Gr0Fk5Kt5pWAssLMo+nce80qOJg462juAC1zq4ouO623aJzhh+/Ig128W5qMy6w9aX1A MGKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="iBaa+A/j"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p1si98921eda.406.2019.10.08.13.49.12; Tue, 08 Oct 2019 13:49:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="iBaa+A/j"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731113AbfJHUsY (ORCPT + 26 others); Tue, 8 Oct 2019 16:48:24 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:43482 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730888AbfJHUsX (ORCPT ); Tue, 8 Oct 2019 16:48:23 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x98KmK4d114889; Tue, 8 Oct 2019 15:48:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1570567700; bh=LFJY/sk3vbxhRSCXMQMK8Y5qMhwQ/+YV7Aj17cmTfjg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=iBaa+A/j4PpiA7r0Z16UG+2WF+/LnapiN4kjpfdWOe++cpN1OEXocb6cdp9ySZTRx KcKpc63X9xB6snRKXhKjixiKOduU63Z8dPL1TyLrlOy79IQGxmF4rUZ5w8QHwwv5ak j3J1q7MuuLKOUVgnY/6JwoctMk5G3ckKMe4R6aPc= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x98KmKpt042350 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Oct 2019 15:48:20 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 8 Oct 2019 15:48:19 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 8 Oct 2019 15:48:17 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x98KmJvX066659; Tue, 8 Oct 2019 15:48:19 -0500 From: Dan Murphy To: , CC: , , Dan Murphy Subject: [PATCH v11 05/16] dt: bindings: lp50xx: Introduce the lp50xx family of RGB drivers Date: Tue, 8 Oct 2019 15:47:49 -0500 Message-ID: <20191008204800.19870-6-dmurphy@ti.com> X-Mailer: git-send-email 2.22.0.214.g8dca754b1e In-Reply-To: <20191008204800.19870-1-dmurphy@ti.com> References: <20191008204800.19870-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Introduce the bindings for the Texas Instruments LP5036, LP5030, LP5024, LP5018, LP5012 and LP5009 RGB LED device driver. The LP5036/30/24/18/12/9 can control RGB LEDs individually or as part of a control bank group. These devices have the ability to adjust the mixing control for the RGB LEDs to obtain different colors independent of the overall brightness of the LED grouping. Datasheet: http://www.ti.com/lit/ds/symlink/lp5012.pdf http://www.ti.com/lit/ds/symlink/lp5024.pdf http://www.ti.com/lit/ds/symlink/lp5036.pdf Signed-off-by: Dan Murphy --- .../devicetree/bindings/leds/leds-lp50xx.txt | 148 ++++++++++++++++++ 1 file changed, 148 insertions(+) create mode 100644 Documentation/devicetree/bindings/leds/leds-lp50xx.txt -- 2.22.0.214.g8dca754b1e diff --git a/Documentation/devicetree/bindings/leds/leds-lp50xx.txt b/Documentation/devicetree/bindings/leds/leds-lp50xx.txt new file mode 100644 index 000000000000..8a0a21f1056c --- /dev/null +++ b/Documentation/devicetree/bindings/leds/leds-lp50xx.txt @@ -0,0 +1,148 @@ +* Texas Instruments - LP5009/12/18/24/30/36 RGB LED driver + +The LP50XX is multi-channel, I2C RGB LED Drivers that can group RGB LEDs into +a LED group or control them individually. + +The difference in these RGB LED drivers is the number of supported RGB modules. + +Required parent properties: + - compatible: + "ti,lp5009" + "ti,lp5012" + "ti,lp5018" + "ti,lp5024" + "ti,lp5030" + "ti,lp5036" + - reg : I2C slave address + lp5009/12 - 0x14, 0x15, 0x16, 0x17 + lp5018/24 - 0x28, 0x29, 0x2a, 0x2b + lp5030/36 - 0x30, 0x31, 0x32, 0x33 + - #address-cells : 1 + - #size-cells : 0 + +Optional parent properties: + - enable-gpios : gpio pin to enable/disable the device. + - vled-supply : LED supply + +Required child properties: + - #address-cells : 1 + - #size-cells : 0 + - reg : This is the LED module number. + - color : Must be LED_COLOR_ID_MULTI + - function : see Documentation/devicetree/bindings/leds/common.txt + +Required child properties only is LED modules will be banked: + - ti,led-bank : This property denotes the LED module numbers that will + be controlled as a single RGB cluster. Each LED module + number will be controlled by a single LED class instance. + There can only be one instance of the ti,led-bank + property for each device node. + +Required grandchildren properties: + - reg : A single entry denoting the LED output that controls + the monochrome LED. + - color : see Documentation/devicetree/bindings/leds/common.txt + - led-sources : see Documentation/devicetree/bindings/leds/common.txt + +The LED outputs associated with the LED modules are defined in Table 1 of the +corresponding data sheets. + +LP5009 - 3 Total RGB cluster LED outputs 0-2 +LP5012 - 4 Total RGB cluster LED outputs 0-3 +LP5018 - 6 Total RGB cluster LED outputs 0-5 +LP5024 - 8 Total RGB cluster LED outputs 0-7 +LP5030 - 10 Total RGB cluster LED outputs 0-9 +LP5036 - 12 Total RGB cluster LED outputs 0-11 + +Optional child properties: + - label : see Documentation/devicetree/bindings/leds/common.txt + - linux,default-trigger : + see Documentation/devicetree/bindings/leds/common.txt + +Examples: +led-controller@29 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,lp5024"; + reg = <0x29>; + enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + vled-supply = <&vmmcsd_fixed>; + + multi-led@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + color = ; + function = LED_FUNCTION_STATUS; + + led@3 { + reg = <3>; + color = ; + }; + + led@4 { + reg = <4>; + color = ; + }; + + led@5 { + reg = <5>; + color = ; + }; + }; + + multi-led@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + color = ; + function = LED_FUNCTION_STANDBY; + ti,led-bank = <2 3 5>; + + led@6 { + reg = <0x6>; + color = ; + led-sources = <6 9 15>; + }; + + led@7 { + reg = <0x7>; + color = ; + led-sources = <7 10 16>; + }; + + led@8 { + reg = <0x8>; + color = ; + led-sources = <8 11 17>; + }; + }; + + multi-led@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + color = ; + function = LED_FUNCTION_ACTIVITY; + + led@12 { + reg = <12>; + color = ; + }; + + led@13 { + reg = <13>; + color = ; + }; + + led@14 { + reg = <14>; + color = ; + }; + }; +}; + +For more product information please see the link below: +http://www.ti.com/lit/ds/symlink/lp5012.pdf +http://www.ti.com/lit/ds/symlink/lp5024.pdf +http://www.ti.com/lit/ds/symlink/lp5036.pdf From patchwork Tue Oct 8 20:47:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 175563 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp6206559ill; Tue, 8 Oct 2019 13:48:39 -0700 (PDT) X-Google-Smtp-Source: APXvYqydYlfOg1Lep09a5vusVN3rE/tw2T7ZpNrEaoJU6flJAw5pZ3V+DK0AmHGFMgo5GdZgJX5h X-Received: by 2002:a05:6402:2d2:: with SMTP id b18mr22276664edx.214.1570567719087; Tue, 08 Oct 2019 13:48:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570567719; cv=none; d=google.com; s=arc-20160816; b=QCMqfIs0k6vKG7heLVJzt+soB0nIALvUo9IkfRfHF10ZiyomzhiIC3SwSETLgzBzOI LT6jsh8S2l0U0bFYBZQaGxhPKQL+GkqaqK8ClPTHaNaImhb3Gjh5nNz/G+godvAfr5Ni 0Ptgb5xd6fFfYZZX7+FZqhdkAuvkDbnJY0yREA6p2a9gHatTi27ZjTt7XKG9mAOGktwH FjpnlM5hZxa/3cDliESQKc3LqDjQYhKsKqTfFpzK5oUar8joAqH6Voy8QG/D57/ofbp+ 708kvVYv/m/TrSQn3mQMeHFq+p1KO2JmlZIRN9t9Z6FYKdXtzLAo7abj8FRqJgLdBGED HvKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6UWgz23CDy17POPE5Hneyq07VrEtxsZJZNBkIzFTCfM=; b=ZzIi8nTAR9JI10ikQ3+6JZCNBt8J+oGUOaPQVXA5DmJOp0BmEU6rydKosPgLg1+M4v IJ4g19ktQHLcAU0hHRiuI1FW8H4JMwN3TzH5VxIw2lQzhj9pjLFLsXU3HPWrUrj9jYK1 9cqv8McBK7GWJ+Vfp0jHBpkZH0T+NicsQkGjnYCPdd5nD4j0FlOnK2E+ZhW5pE7IIpTN ahdHf/SVtJ6k8JNMYvIYB1rQFRYx15dvvTo5vjEaih5Gqizy3pid4mSECOg37kU8E7KF 8fgeQY3sbA7qnyZWsCCUB2f7TABjNGOgkg2fk+bMQPfDaBxJnQ4jO1UGFOdXxdfZKUIo +SHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=LmUYw03Z; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s27si115462edm.226.2019.10.08.13.48.38; Tue, 08 Oct 2019 13:48:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=LmUYw03Z; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731260AbfJHUsi (ORCPT + 26 others); Tue, 8 Oct 2019 16:48:38 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:45078 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731135AbfJHUsc (ORCPT ); Tue, 8 Oct 2019 16:48:32 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x98KmSMj092733; Tue, 8 Oct 2019 15:48:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1570567708; bh=6UWgz23CDy17POPE5Hneyq07VrEtxsZJZNBkIzFTCfM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LmUYw03Zd0VLYYNF4Fh7LKddVHXyRiDirE0geAjJF/gZWQmkSnUvHoHyD/eHth4Oz vx9INHaLpSbCXnjfnsCX9CaHNY1Y2Af3eVPVT/WYrsw4BJTDr9kGoK176rpZJC3yJa nGprHErdDTHwHBhJ3nWOP64LDk/hvNaXmP1m2bCA= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x98KmS2W062334 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Oct 2019 15:48:28 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 8 Oct 2019 15:48:17 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 8 Oct 2019 15:48:20 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x98KmKU7022753; Tue, 8 Oct 2019 15:48:20 -0500 From: Dan Murphy To: , CC: , , Dan Murphy Subject: [PATCH v11 06/16] leds: lp50xx: Add the LP50XX family of the RGB LED driver Date: Tue, 8 Oct 2019 15:47:50 -0500 Message-ID: <20191008204800.19870-7-dmurphy@ti.com> X-Mailer: git-send-email 2.22.0.214.g8dca754b1e In-Reply-To: <20191008204800.19870-1-dmurphy@ti.com> References: <20191008204800.19870-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Introduce the LP5036/30/24/18/12/9 RGB LED driver. The difference in these parts are the number of LED outputs where the: LP5036 can control 36 LEDs LP5030 can control 30 LEDs LP5024 can control 24 LEDs LP5018 can control 18 LEDs LP5012 can control 12 LEDs LP5009 can control 9 LEDs The device has the ability to group LED output into control banks so that multiple LED banks can be controlled with the same mixing and brightness. Inversely the LEDs can also be controlled independently. Signed-off-by: Dan Murphy --- drivers/leds/Kconfig | 11 + drivers/leds/Makefile | 1 + drivers/leds/leds-lp50xx.c | 799 +++++++++++++++++++++++++++++++++++++ 3 files changed, 811 insertions(+) create mode 100644 drivers/leds/leds-lp50xx.c -- 2.22.0.214.g8dca754b1e diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index a1ede89afc9e..fb614a6b9afa 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -363,6 +363,17 @@ config LEDS_LP3952 To compile this driver as a module, choose M here: the module will be called leds-lp3952. +config LEDS_LP50XX + tristate "LED Support for TI LP5036/30/24/18/12/9 LED driver chip" + depends on LEDS_CLASS && REGMAP_I2C + depends on LEDS_CLASS_MULTI_COLOR + help + If you say yes here you get support for the Texas Instruments + LP5036, LP5030, LP5024, LP5018, LP5012 and LP5009 LED driver. + + To compile this driver as a module, choose M here: the + module will be called leds-lp50xx. + config LEDS_LP55XX_COMMON tristate "Common Driver for TI/National LP5521/5523/55231/5562/8501" depends on LEDS_LP5521 || LEDS_LP5523 || LEDS_LP5562 || LEDS_LP8501 diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile index 841038cfe35b..7a208a0f7b84 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_LEDS_GPIO_REGISTER) += leds-gpio-register.o obj-$(CONFIG_LEDS_GPIO) += leds-gpio.o obj-$(CONFIG_LEDS_LP3944) += leds-lp3944.o obj-$(CONFIG_LEDS_LP3952) += leds-lp3952.o +obj-$(CONFIG_LEDS_LP50XX) += leds-lp50xx.o obj-$(CONFIG_LEDS_LP55XX_COMMON) += leds-lp55xx-common.o obj-$(CONFIG_LEDS_LP5521) += leds-lp5521.o obj-$(CONFIG_LEDS_LP5523) += leds-lp5523.o diff --git a/drivers/leds/leds-lp50xx.c b/drivers/leds/leds-lp50xx.c new file mode 100644 index 000000000000..6a042f973a83 --- /dev/null +++ b/drivers/leds/leds-lp50xx.c @@ -0,0 +1,799 @@ +// SPDX-License-Identifier: GPL-2.0 +// TI LP50XX LED chip family driver +// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define LP50XX_DEV_CFG0 0x00 +#define LP50XX_DEV_CFG1 0x01 +#define LP50XX_LED_CFG0 0x02 + +/* LP5009 and LP5012 registers */ +#define LP5012_BNK_BRT 0x03 +#define LP5012_BNKA_CLR 0x04 +#define LP5012_BNKB_CLR 0x05 +#define LP5012_BNKC_CLR 0x06 +#define LP5012_LED0_BRT 0x07 +#define LP5012_LED1_BRT 0x08 +#define LP5012_LED2_BRT 0x09 +#define LP5012_LED3_BRT 0x0a +#define LP5012_OUT0_CLR 0x0b +#define LP5012_OUT1_CLR 0x0c +#define LP5012_OUT2_CLR 0x0d +#define LP5012_OUT3_CLR 0x0e +#define LP5012_OUT4_CLR 0x0f +#define LP5012_OUT5_CLR 0x10 +#define LP5012_OUT6_CLR 0x11 +#define LP5012_OUT7_CLR 0x12 +#define LP5012_OUT8_CLR 0x13 +#define LP5012_OUT9_CLR 0x14 +#define LP5012_OUT10_CLR 0x15 +#define LP5012_OUT11_CLR 0x16 +#define LP5012_RESET 0x17 + +/* LP5018 and LP5024 registers */ +#define LP5024_BNK_BRT 0x03 +#define LP5024_BNKA_CLR 0x04 +#define LP5024_BNKB_CLR 0x05 +#define LP5024_BNKC_CLR 0x06 +#define LP5024_LED0_BRT 0x07 +#define LP5024_LED1_BRT 0x08 +#define LP5024_LED2_BRT 0x09 +#define LP5024_LED3_BRT 0x0a +#define LP5024_LED4_BRT 0x0b +#define LP5024_LED5_BRT 0x0c +#define LP5024_LED6_BRT 0x0d +#define LP5024_LED7_BRT 0x0e + +#define LP5024_OUT0_CLR 0x0f +#define LP5024_OUT1_CLR 0x10 +#define LP5024_OUT2_CLR 0x11 +#define LP5024_OUT3_CLR 0x12 +#define LP5024_OUT4_CLR 0x13 +#define LP5024_OUT5_CLR 0x14 +#define LP5024_OUT6_CLR 0x15 +#define LP5024_OUT7_CLR 0x16 +#define LP5024_OUT8_CLR 0x17 +#define LP5024_OUT9_CLR 0x18 +#define LP5024_OUT10_CLR 0x19 +#define LP5024_OUT11_CLR 0x1a +#define LP5024_OUT12_CLR 0x1b +#define LP5024_OUT13_CLR 0x1c +#define LP5024_OUT14_CLR 0x1d +#define LP5024_OUT15_CLR 0x1e +#define LP5024_OUT16_CLR 0x1f +#define LP5024_OUT17_CLR 0x20 +#define LP5024_OUT18_CLR 0x21 +#define LP5024_OUT19_CLR 0x22 +#define LP5024_OUT20_CLR 0x23 +#define LP5024_OUT21_CLR 0x24 +#define LP5024_OUT22_CLR 0x25 +#define LP5024_OUT23_CLR 0x26 +#define LP5024_RESET 0x27 + +/* LP5030 and LP5036 registers */ +#define LP5036_LED_CFG1 0x03 +#define LP5036_BNK_BRT 0x04 +#define LP5036_BNKA_CLR 0x05 +#define LP5036_BNKB_CLR 0x06 +#define LP5036_BNKC_CLR 0x07 +#define LP5036_LED0_BRT 0x08 +#define LP5036_LED1_BRT 0x09 +#define LP5036_LED2_BRT 0x0a +#define LP5036_LED3_BRT 0x0b +#define LP5036_LED4_BRT 0x0c +#define LP5036_LED5_BRT 0x0d +#define LP5036_LED6_BRT 0x0e +#define LP5036_LED7_BRT 0x0f +#define LP5036_LED8_BRT 0x10 +#define LP5036_LED9_BRT 0x11 +#define LP5036_LED10_BRT 0x12 +#define LP5036_LED11_BRT 0x13 + +#define LP5036_OUT0_CLR 0x14 +#define LP5036_OUT1_CLR 0x15 +#define LP5036_OUT2_CLR 0x16 +#define LP5036_OUT3_CLR 0x17 +#define LP5036_OUT4_CLR 0x18 +#define LP5036_OUT5_CLR 0x19 +#define LP5036_OUT6_CLR 0x1a +#define LP5036_OUT7_CLR 0x1b +#define LP5036_OUT8_CLR 0x1c +#define LP5036_OUT9_CLR 0x1d +#define LP5036_OUT10_CLR 0x1e +#define LP5036_OUT11_CLR 0x1f +#define LP5036_OUT12_CLR 0x20 +#define LP5036_OUT13_CLR 0x21 +#define LP5036_OUT14_CLR 0x22 +#define LP5036_OUT15_CLR 0x23 +#define LP5036_OUT16_CLR 0x24 +#define LP5036_OUT17_CLR 0x25 +#define LP5036_OUT18_CLR 0x26 +#define LP5036_OUT19_CLR 0x27 +#define LP5036_OUT20_CLR 0x28 +#define LP5036_OUT21_CLR 0x29 +#define LP5036_OUT22_CLR 0x2a +#define LP5036_OUT23_CLR 0x2b +#define LP5036_OUT24_CLR 0x2c +#define LP5036_OUT25_CLR 0x2d +#define LP5036_OUT26_CLR 0x2e +#define LP5036_OUT27_CLR 0x2f +#define LP5036_OUT28_CLR 0x30 +#define LP5036_OUT29_CLR 0x31 +#define LP5036_OUT30_CLR 0x32 +#define LP5036_OUT31_CLR 0x33 +#define LP5036_OUT32_CLR 0x34 +#define LP5036_OUT33_CLR 0x35 +#define LP5036_OUT34_CLR 0x36 +#define LP5036_OUT35_CLR 0x37 +#define LP5036_RESET 0x38 + +#define LP50XX_SW_RESET 0xff +#define LP50XX_CHIP_EN BIT(6) + +/* There are 3 LED outputs per bank */ +#define LP50XX_LEDS_PER_MODULE 3 + +#define LP5009_MAX_LED_MODULES 2 +#define LP5012_MAX_LED_MODULES 4 +#define LP5018_MAX_LED_MODULES 6 +#define LP5024_MAX_LED_MODULES 8 +#define LP5030_MAX_LED_MODULES 10 +#define LP5036_MAX_LED_MODULES 12 + +#define LP5009_MAX_LEDS (LP5009_MAX_LED_MODULES * LP50XX_LEDS_PER_MODULE) +#define LP5012_MAX_LEDS (LP5012_MAX_LED_MODULES * LP50XX_LEDS_PER_MODULE) +#define LP5018_MAX_LEDS (LP5018_MAX_LED_MODULES * LP50XX_LEDS_PER_MODULE) +#define LP5024_MAX_LEDS (LP5024_MAX_LED_MODULES * LP50XX_LEDS_PER_MODULE) +#define LP5030_MAX_LEDS (LP5030_MAX_LED_MODULES * LP50XX_LEDS_PER_MODULE) +#define LP5036_MAX_LEDS (LP5036_MAX_LED_MODULES * LP50XX_LEDS_PER_MODULE) + +static const struct reg_default lp5012_reg_defs[] = { + {LP50XX_DEV_CFG0, 0x0}, + {LP50XX_DEV_CFG1, 0x3c}, + {LP50XX_LED_CFG0, 0x0}, + {LP5012_BNK_BRT, 0xff}, + {LP5012_BNKA_CLR, 0x0f}, + {LP5012_BNKB_CLR, 0x0f}, + {LP5012_BNKC_CLR, 0x0f}, + {LP5012_LED0_BRT, 0x0f}, + {LP5012_LED1_BRT, 0xff}, + {LP5012_LED2_BRT, 0xff}, + {LP5012_LED3_BRT, 0xff}, + {LP5012_OUT0_CLR, 0x0f}, + {LP5012_OUT1_CLR, 0x00}, + {LP5012_OUT2_CLR, 0x00}, + {LP5012_OUT3_CLR, 0x00}, + {LP5012_OUT4_CLR, 0x00}, + {LP5012_OUT5_CLR, 0x00}, + {LP5012_OUT6_CLR, 0x00}, + {LP5012_OUT7_CLR, 0x00}, + {LP5012_OUT8_CLR, 0x00}, + {LP5012_OUT9_CLR, 0x00}, + {LP5012_OUT10_CLR, 0x00}, + {LP5012_OUT11_CLR, 0x00}, + {LP5012_RESET, 0x00} +}; + +static const struct reg_default lp5024_reg_defs[] = { + {LP50XX_DEV_CFG0, 0x0}, + {LP50XX_DEV_CFG1, 0x3c}, + {LP50XX_LED_CFG0, 0x0}, + {LP5024_BNK_BRT, 0xff}, + {LP5024_BNKA_CLR, 0x0f}, + {LP5024_BNKB_CLR, 0x0f}, + {LP5024_BNKC_CLR, 0x0f}, + {LP5024_LED0_BRT, 0x0f}, + {LP5024_LED1_BRT, 0xff}, + {LP5024_LED2_BRT, 0xff}, + {LP5024_LED3_BRT, 0xff}, + {LP5024_LED4_BRT, 0xff}, + {LP5024_LED5_BRT, 0xff}, + {LP5024_LED6_BRT, 0xff}, + {LP5024_LED7_BRT, 0xff}, + {LP5024_OUT0_CLR, 0x0f}, + {LP5024_OUT1_CLR, 0x00}, + {LP5024_OUT2_CLR, 0x00}, + {LP5024_OUT3_CLR, 0x00}, + {LP5024_OUT4_CLR, 0x00}, + {LP5024_OUT5_CLR, 0x00}, + {LP5024_OUT6_CLR, 0x00}, + {LP5024_OUT7_CLR, 0x00}, + {LP5024_OUT8_CLR, 0x00}, + {LP5024_OUT9_CLR, 0x00}, + {LP5024_OUT10_CLR, 0x00}, + {LP5024_OUT11_CLR, 0x00}, + {LP5024_OUT12_CLR, 0x00}, + {LP5024_OUT13_CLR, 0x00}, + {LP5024_OUT14_CLR, 0x00}, + {LP5024_OUT15_CLR, 0x00}, + {LP5024_OUT16_CLR, 0x00}, + {LP5024_OUT17_CLR, 0x00}, + {LP5024_OUT18_CLR, 0x00}, + {LP5024_OUT19_CLR, 0x00}, + {LP5024_OUT20_CLR, 0x00}, + {LP5024_OUT21_CLR, 0x00}, + {LP5024_OUT22_CLR, 0x00}, + {LP5024_OUT23_CLR, 0x00}, + {LP5024_RESET, 0x00} +}; + +static const struct reg_default lp5036_reg_defs[] = { + {LP50XX_DEV_CFG0, 0x0}, + {LP50XX_DEV_CFG1, 0x3c}, + {LP50XX_LED_CFG0, 0x0}, + {LP5036_LED_CFG1, 0x0}, + {LP5036_BNK_BRT, 0xff}, + {LP5036_BNKA_CLR, 0x0f}, + {LP5036_BNKB_CLR, 0x0f}, + {LP5036_BNKC_CLR, 0x0f}, + {LP5036_LED0_BRT, 0x0f}, + {LP5036_LED1_BRT, 0xff}, + {LP5036_LED2_BRT, 0xff}, + {LP5036_LED3_BRT, 0xff}, + {LP5036_LED4_BRT, 0xff}, + {LP5036_LED5_BRT, 0xff}, + {LP5036_LED6_BRT, 0xff}, + {LP5036_LED7_BRT, 0xff}, + {LP5036_OUT0_CLR, 0x0f}, + {LP5036_OUT1_CLR, 0x00}, + {LP5036_OUT2_CLR, 0x00}, + {LP5036_OUT3_CLR, 0x00}, + {LP5036_OUT4_CLR, 0x00}, + {LP5036_OUT5_CLR, 0x00}, + {LP5036_OUT6_CLR, 0x00}, + {LP5036_OUT7_CLR, 0x00}, + {LP5036_OUT8_CLR, 0x00}, + {LP5036_OUT9_CLR, 0x00}, + {LP5036_OUT10_CLR, 0x00}, + {LP5036_OUT11_CLR, 0x00}, + {LP5036_OUT12_CLR, 0x00}, + {LP5036_OUT13_CLR, 0x00}, + {LP5036_OUT14_CLR, 0x00}, + {LP5036_OUT15_CLR, 0x00}, + {LP5036_OUT16_CLR, 0x00}, + {LP5036_OUT17_CLR, 0x00}, + {LP5036_OUT18_CLR, 0x00}, + {LP5036_OUT19_CLR, 0x00}, + {LP5036_OUT20_CLR, 0x00}, + {LP5036_OUT21_CLR, 0x00}, + {LP5036_OUT22_CLR, 0x00}, + {LP5036_OUT23_CLR, 0x00}, + {LP5036_OUT24_CLR, 0x00}, + {LP5036_OUT25_CLR, 0x00}, + {LP5036_OUT26_CLR, 0x00}, + {LP5036_OUT27_CLR, 0x00}, + {LP5036_OUT28_CLR, 0x00}, + {LP5036_OUT29_CLR, 0x00}, + {LP5036_OUT30_CLR, 0x00}, + {LP5036_OUT31_CLR, 0x00}, + {LP5036_OUT32_CLR, 0x00}, + {LP5036_OUT33_CLR, 0x00}, + {LP5036_OUT34_CLR, 0x00}, + {LP5036_OUT35_CLR, 0x00}, + {LP5036_RESET, 0x00} +}; + +static const struct regmap_config lp5012_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + + .max_register = LP5012_RESET, + .reg_defaults = lp5012_reg_defs, + .num_reg_defaults = ARRAY_SIZE(lp5012_reg_defs), + .cache_type = REGCACHE_RBTREE, +}; + +static const struct regmap_config lp5024_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + + .max_register = LP5024_RESET, + .reg_defaults = lp5024_reg_defs, + .num_reg_defaults = ARRAY_SIZE(lp5024_reg_defs), + .cache_type = REGCACHE_RBTREE, +}; + +static const struct regmap_config lp5036_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + + .max_register = LP5036_RESET, + .reg_defaults = lp5036_reg_defs, + .num_reg_defaults = ARRAY_SIZE(lp5036_reg_defs), + .cache_type = REGCACHE_RBTREE, +}; + +enum lp50xx_model { + LP5009, + LP5012, + LP5018, + LP5024, + LP5030, + LP5036, +}; + +/* + * struct lp50xx_chip_info - + * @num_leds: number of LED outputs available on the device + * @led_brightness0_reg: first brightness register of the device + * @mix_out0_reg: first color mix register of the device + * @bank_brt_reg: bank brightness register + * @bank_mix_reg: color mix register + * @reset_reg: device reset register + */ +struct lp50xx_chip_info { + const struct regmap_config lp50xx_regmap_config; + int model_id; + u8 max_modules; + u8 num_leds; + u8 led_brightness0_reg; + u8 mix_out0_reg; + u8 bank_brt_reg; + u8 bank_mix_reg; + u8 reset_reg; +}; + +static const struct lp50xx_chip_info lp50xx_chip_info_tbl[] = { + [LP5009] = { + .model_id = LP5009, + .max_modules = LP5009_MAX_LED_MODULES, + .num_leds = LP5009_MAX_LEDS, + .led_brightness0_reg = LP5012_LED0_BRT, + .mix_out0_reg = LP5012_OUT0_CLR, + .bank_brt_reg = LP5012_BNK_BRT, + .bank_mix_reg = LP5012_BNKA_CLR, + .reset_reg = LP5012_RESET, + .lp50xx_regmap_config = lp5012_regmap_config, + }, + [LP5012] = { + .model_id = LP5012, + .max_modules = LP5012_MAX_LED_MODULES, + .num_leds = LP5012_MAX_LEDS, + .led_brightness0_reg = LP5012_LED0_BRT, + .mix_out0_reg = LP5012_OUT0_CLR, + .bank_brt_reg = LP5012_BNK_BRT, + .bank_mix_reg = LP5012_BNKA_CLR, + .reset_reg = LP5012_RESET, + .lp50xx_regmap_config = lp5012_regmap_config, + }, + [LP5018] = { + .model_id = LP5018, + .max_modules = LP5018_MAX_LED_MODULES, + .num_leds = LP5018_MAX_LEDS, + .led_brightness0_reg = LP5024_LED0_BRT, + .mix_out0_reg = LP5024_OUT0_CLR, + .bank_brt_reg = LP5024_BNK_BRT, + .bank_mix_reg = LP5024_BNKA_CLR, + .reset_reg = LP5024_RESET, + .lp50xx_regmap_config = lp5024_regmap_config, + }, + [LP5024] = { + .model_id = LP5024, + .max_modules = LP5024_MAX_LED_MODULES, + .num_leds = LP5024_MAX_LEDS, + .led_brightness0_reg = LP5024_LED0_BRT, + .mix_out0_reg = LP5024_OUT0_CLR, + .bank_brt_reg = LP5024_BNK_BRT, + .bank_mix_reg = LP5024_BNKA_CLR, + .reset_reg = LP5024_RESET, + .lp50xx_regmap_config = lp5024_regmap_config, + }, + [LP5030] = { + .model_id = LP5030, + .max_modules = LP5030_MAX_LED_MODULES, + .num_leds = LP5030_MAX_LEDS, + .led_brightness0_reg = LP5036_LED0_BRT, + .mix_out0_reg = LP5036_OUT0_CLR, + .bank_brt_reg = LP5036_BNK_BRT, + .bank_mix_reg = LP5036_BNKA_CLR, + .reset_reg = LP5036_RESET, + .lp50xx_regmap_config = lp5036_regmap_config, + }, + [LP5036] = { + .model_id = LP5036, + .max_modules = LP5036_MAX_LED_MODULES, + .num_leds = LP5036_MAX_LEDS, + .led_brightness0_reg = LP5036_LED0_BRT, + .mix_out0_reg = LP5036_OUT0_CLR, + .bank_brt_reg = LP5036_BNK_BRT, + .bank_mix_reg = LP5036_BNKA_CLR, + .reset_reg = LP5036_RESET, + .lp50xx_regmap_config = lp5036_regmap_config, + }, +}; + +struct lp50xx_led { + struct led_classdev led_dev; + struct led_classdev_mc mc_cdev; + struct lp50xx *priv; + unsigned long bank_modules; + int led_intensity[LP50XX_LEDS_PER_MODULE]; + u8 ctrl_bank_enabled; + int led_number; +}; + +/** + * struct lp50xx - + * @enable_gpio: hardware enable gpio + * @regulator: LED supply regulator pointer + * @client: pointer to the I2C client + * @regmap: device register map + * @dev: pointer to the devices device struct + * @lock: lock for reading/writing the device + * @chip_info: chip specific information (ie num_leds) + * @num_of_banked_leds: holds the number of banked LEDs + * @leds: array of LED strings + */ +struct lp50xx { + struct gpio_desc *enable_gpio; + struct regulator *regulator; + struct i2c_client *client; + struct regmap *regmap; + struct device *dev; + struct mutex lock; + const struct lp50xx_chip_info *chip_info; + int num_of_banked_leds; + + /* This needs to be at the end of the struct */ + struct lp50xx_led leds[]; +}; + +static int lp50xx_brightness_set(struct led_classdev *cdev, + enum led_brightness brightness) +{ + struct lp50xx_led *led = container_of(cdev, struct lp50xx_led, led_dev); + const struct lp50xx_chip_info *led_chip = led->priv->chip_info; + struct led_mc_color_entry *color_data; + u8 led_offset, reg_val, reg_color_offset; + int ret = 0; + + mutex_lock(&led->priv->lock); + + if (led->ctrl_bank_enabled) + reg_val = led_chip->bank_brt_reg; + else + reg_val = led_chip->led_brightness0_reg + + led->led_number; + + ret = regmap_write(led->priv->regmap, reg_val, brightness); + if (ret) { + dev_err(&led->priv->client->dev, + "Cannot write brightness value %d\n", ret); + goto out; + } + + list_for_each_entry(color_data, &led->mc_cdev.color_list, list) { + if (color_data->led_color_id == LED_COLOR_ID_RED) { + reg_color_offset = 0; + } else if (color_data->led_color_id == LED_COLOR_ID_GREEN) { + reg_color_offset = 1; + } else if (color_data->led_color_id == LED_COLOR_ID_BLUE) { + reg_color_offset = 2; + } else { + dev_err(&led->priv->client->dev, + "LED color not found\n"); + ret = -EINVAL; + goto out; + } + + if (led->ctrl_bank_enabled) { + reg_val = led_chip->bank_mix_reg + reg_color_offset; + } else { + led_offset = (led->led_number * 3) + reg_color_offset; + reg_val = led_chip->mix_out0_reg + led_offset; + } + + ret = regmap_write(led->priv->regmap, reg_val, + color_data->intensity); + if (ret) { + dev_err(&led->priv->client->dev, + "Cannot write intensity value %d\n", ret); + goto out; + } + } +out: + mutex_unlock(&led->priv->lock); + return ret; +} + +static enum led_brightness lp50xx_brightness_get(struct led_classdev *cdev) +{ + struct lp50xx_led *led = container_of(cdev, struct lp50xx_led, led_dev); + const struct lp50xx_chip_info *led_chip = led->priv->chip_info; + unsigned int brt_val; + u8 reg_val; + int ret; + + mutex_lock(&led->priv->lock); + + if (led->ctrl_bank_enabled) + reg_val = led_chip->bank_brt_reg; + else + reg_val = led_chip->led_brightness0_reg + led->led_number; + + ret = regmap_read(led->priv->regmap, reg_val, &brt_val); + + mutex_unlock(&led->priv->lock); + + return brt_val; +} + +static int lp50xx_set_banks(struct lp50xx *priv, u32 led_banks[]) +{ + u8 led_config_lo, led_config_hi; + u32 bank_enable_mask = 0; + int ret; + int i; + + for (i = 0; i < priv->chip_info->num_leds; i++) + bank_enable_mask |= (1 << led_banks[i]); + + led_config_lo = (u8)(bank_enable_mask & 0xff); + led_config_hi = (u8)(bank_enable_mask >> 8) & 0xff; + + ret = regmap_write(priv->regmap, LP50XX_LED_CFG0, led_config_lo); + if (ret) + return ret; + + if (priv->chip_info->model_id >= LP5030) + ret = regmap_write(priv->regmap, LP5036_LED_CFG1, + led_config_hi); + + return ret; +} + +static int lp50xx_reset(struct lp50xx *priv) +{ + if (priv->enable_gpio) + return gpiod_direction_output(priv->enable_gpio, 1); + else + return regmap_write(priv->regmap, priv->chip_info->reset_reg, + LP50XX_SW_RESET); +} + +static int lp50xx_enable_disable(struct lp50xx *priv, u8 enable_disable) +{ + return regmap_write(priv->regmap, LP50XX_DEV_CFG0, enable_disable); +} + +static int lp50xx_probe_dt(struct lp50xx *priv) +{ + u32 led_banks[LP5036_MAX_LED_MODULES]; + struct fwnode_handle *child = NULL; + struct fwnode_handle *led_node = NULL; + struct led_init_data init_data; + struct lp50xx_led *led; + int num_colors; + u32 color_id; + int led_number; + size_t i = 0; + int ret; + + priv->enable_gpio = devm_gpiod_get_optional(&priv->client->dev, + "enable", GPIOD_OUT_LOW); + if (IS_ERR(priv->enable_gpio)) { + ret = PTR_ERR(priv->enable_gpio); + dev_err(&priv->client->dev, "Failed to get enable gpio: %d\n", + ret); + return ret; + } + + priv->regulator = devm_regulator_get(&priv->client->dev, "vled"); + if (IS_ERR(priv->regulator)) + priv->regulator = NULL; + + device_for_each_child_node(&priv->client->dev, child) { + led = &priv->leds[i]; + if (fwnode_property_present(child, "ti,led-bank")) { + ret = fwnode_property_read_u32_array(child, + "ti,led-bank", + NULL, 0); + priv->num_of_banked_leds = ret; + if (priv->num_of_banked_leds > + priv->chip_info->max_modules) { + dev_err(&priv->client->dev, + "led-bank property is invalid\n"); + ret = -EINVAL; + fwnode_handle_put(child); + goto child_out; + } + + ret = fwnode_property_read_u32_array(child, + "ti,led-bank", + led_banks, + ret); + if (ret) { + dev_err(&priv->client->dev, + "led-bank property is missing\n"); + fwnode_handle_put(child); + goto child_out; + } + + ret = lp50xx_set_banks(priv, led_banks); + if (ret) { + dev_err(&priv->client->dev, + "Cannot setup banked LEDs\n"); + fwnode_handle_put(child); + goto child_out; + } + led->ctrl_bank_enabled = 1; + + } else { + ret = fwnode_property_read_u32(child, "reg", + &led_number); + if (ret) { + dev_err(&priv->client->dev, + "led reg property missing\n"); + fwnode_handle_put(child); + goto child_out; + } + + if (led_number > priv->chip_info->num_leds) { + dev_err(&priv->client->dev, + "led-sources property is invalid\n"); + ret = -EINVAL; + fwnode_handle_put(child); + goto child_out; + } + + led->led_number = led_number; + } + + init_data.fwnode = child; + fwnode_property_read_string(child, "linux,default-trigger", + &led->led_dev.default_trigger); + num_colors = 0; + + fwnode_for_each_child_node(child, led_node) { + ret = fwnode_property_read_u32(led_node, "color", + &color_id); + if (ret) + dev_err(&priv->client->dev, + "Cannot read color\n"); + + set_bit(color_id, &led->mc_cdev.available_colors); + num_colors++; + + } + + led->priv = priv; + led->mc_cdev.num_leds = num_colors; + led->mc_cdev.led_cdev = &led->led_dev; + led->led_dev.brightness_set_blocking = lp50xx_brightness_set; + led->led_dev.brightness_get = lp50xx_brightness_get; + ret = led_classdev_multicolor_register_ext(&priv->client->dev, + &led->mc_cdev, + &init_data); + if (ret) { + dev_err(&priv->client->dev, "led register err: %d\n", + ret); + fwnode_handle_put(child); + goto child_out; + } + i++; + } + +child_out: + return ret; +} + +static int lp50xx_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct lp50xx *led; + int count; + int ret; + + count = device_get_child_node_count(&client->dev); + if (!count) { + dev_err(&client->dev, "LEDs are not defined in device tree!"); + return -ENODEV; + } + + led = devm_kzalloc(&client->dev, struct_size(led, leds, count), + GFP_KERNEL); + if (!led) + return -ENOMEM; + + mutex_init(&led->lock); + led->client = client; + led->dev = &client->dev; + led->chip_info = &lp50xx_chip_info_tbl[id->driver_data]; + i2c_set_clientdata(client, led); + + led->regmap = devm_regmap_init_i2c(client, + &led->chip_info->lp50xx_regmap_config); + if (IS_ERR(led->regmap)) { + ret = PTR_ERR(led->regmap); + dev_err(&client->dev, "Failed to allocate register map: %d\n", + ret); + return ret; + } + + ret = lp50xx_reset(led); + if (ret) + return ret; + + ret = lp50xx_probe_dt(led); + if (ret) + return ret; + + return lp50xx_enable_disable(led, LP50XX_CHIP_EN); +} + +static int lp50xx_remove(struct i2c_client *client) +{ + struct lp50xx *led = i2c_get_clientdata(client); + int ret; + + ret = lp50xx_enable_disable(led, LP50XX_CHIP_EN); + if (ret) { + dev_err(&led->client->dev, "Failed to disable regulator\n"); + return ret; + } + + if (led->enable_gpio) + gpiod_direction_output(led->enable_gpio, 0); + + if (led->regulator) { + ret = regulator_disable(led->regulator); + if (ret) + dev_err(&led->client->dev, + "Failed to disable regulator\n"); + } + + mutex_destroy(&led->lock); + + return 0; +} + +static const struct i2c_device_id lp50xx_id[] = { + { "lp5009", LP5009 }, + { "lp5012", LP5012 }, + { "lp5018", LP5018 }, + { "lp5024", LP5024 }, + { "lp5030", LP5030 }, + { "lp5036", LP5036 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, lp50xx_id); + +static const struct of_device_id of_lp50xx_leds_match[] = { + { .compatible = "ti,lp5009", .data = (void *)LP5009 }, + { .compatible = "ti,lp5012", .data = (void *)LP5012 }, + { .compatible = "ti,lp5018", .data = (void *)LP5018 }, + { .compatible = "ti,lp5024", .data = (void *)LP5024 }, + { .compatible = "ti,lp5030", .data = (void *)LP5030 }, + { .compatible = "ti,lp5036", .data = (void *)LP5036 }, + {}, +}; +MODULE_DEVICE_TABLE(of, of_lp50xx_leds_match); + +static struct i2c_driver lp50xx_driver = { + .driver = { + .name = "lp50xx", + .of_match_table = of_lp50xx_leds_match, + }, + .probe = lp50xx_probe, + .remove = lp50xx_remove, + .id_table = lp50xx_id, +}; +module_i2c_driver(lp50xx_driver); + +MODULE_DESCRIPTION("Texas Instruments LP50XX LED driver"); +MODULE_AUTHOR("Dan Murphy "); +MODULE_LICENSE("GPL v2"); From patchwork Tue Oct 8 20:47:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 175574 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp6207239ill; Tue, 8 Oct 2019 13:49:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqxAZnmIzIyVi/kdXZ0V7iLiUNsU9snTI132e42FgHtI8cAw4ngPC5Sw5eCVLjqawlpR6nvw X-Received: by 2002:a17:906:19d3:: with SMTP id h19mr31099721ejd.121.1570567762305; Tue, 08 Oct 2019 13:49:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570567762; cv=none; d=google.com; s=arc-20160816; b=MO7nvcSvLeY+jU2NVmlLgQRIGLZVt8wTSMNA2ZFP8WEur6lwER7WcjLtEH64izGfOk QUlumhd68ZXyF2K/l2J3xytaszkQP6hA7BI8MOACBnkTAEvbPR1VB9/+ehTumXkGhoa4 ZMvgB0S58lB6+4eUQFRvo4fGRKAzAlCvxWUBaj0iWa3MBLY6PO2qdWknVVowDCeHUX36 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This acronym should be capital throughout the document. Signed-off-by: Dan Murphy --- Documentation/devicetree/bindings/leds/leds-lp55xx.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.22.0.214.g8dca754b1e diff --git a/Documentation/devicetree/bindings/leds/leds-lp55xx.txt b/Documentation/devicetree/bindings/leds/leds-lp55xx.txt index 1b66a413fb9d..bfe2805c5534 100644 --- a/Documentation/devicetree/bindings/leds/leds-lp55xx.txt +++ b/Documentation/devicetree/bindings/leds/leds-lp55xx.txt @@ -1,4 +1,4 @@ -Binding for TI/National Semiconductor LP55xx Led Drivers +Binding for TI/National Semiconductor LP55xx LED Drivers Required properties: - compatible: one of @@ -12,8 +12,8 @@ Required properties: - clock-mode: Input clock mode, (0: automode, 1: internal, 2: external) Each child has own specific current settings -- led-cur: Current setting at each led channel (mA x10, 0 if led is not connected) -- max-cur: Maximun current at each led channel. +- led-cur: Current setting at each LED channel (mA x10, 0 if LED is not connected) +- max-cur: Maximun current at each LED channel. Optional properties: - enable-gpio: GPIO attached to the chip's enable pin From patchwork Tue Oct 8 20:47:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 175564 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp6206627ill; Tue, 8 Oct 2019 13:48:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqx2kKjfCqbZY2rvg8IayWYK4DjW41Z6idgXqeruH/JhpxQ9xQih4wEBcJSbVccMQZQ81+T2 X-Received: by 2002:a50:cc43:: with SMTP id n3mr36426192edi.250.1570567724044; Tue, 08 Oct 2019 13:48:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570567724; cv=none; d=google.com; s=arc-20160816; b=zUixWayIVDTTXCcug4DA2BSurpl63GHpqoHjI4g9jw6EdOC+MelXf9Ax1lFBXglGCp kmy/Wm2y3WsdcbeIJIr3uSmMxJjKjdUZAcO7M/u/Io+TZ25NqNygB9rQb/Tr0XheWFEj 9Qvrae2BsIqLNk/I0CocUwdd2HTzly1yvVRYfkwMbKx4bJ9veGNsiFLf1AyWFrmfTfLy z4V0xcBNSAlgumr+B7UDOPYfnF54Mix+dk1FbexSMhsx51qiu9J79SCGu1ykPsJbfykv 5znLrFV2sqY3bYkhzdIJl1kPT2RAIpIWsd/dvC+XtnTiaOULwYuYpZOlc4KbOWLU2/Au wq1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JLAX1GO8r1BPAaQSP8nT877GyOWJiBCNm5vdl8bnxYc=; b=ttbPUPBsfqyXKM2wKCNVrQLILdAmQV9lm/1poTNX7UNuse7iCKDNuC8PQaJZnQRuE8 h5QqtNAafOiYX6qoEzTEZIKkUikNmULDnILN9KC2/3+Fk/vVqktUd0c+//TLkJXV8aZQ kOpe2wQrgNwiSxqztyGresLfUPOqs4EeGVt3d35Ac33hMLAaD8Nf/AtRiJafCfkYPzUJ HnVwwzADYyTC8PWq3i4VJ3LbNmGKUlrBHyurz++m/xmCJECGzOBU3vVBSCvlzmkmkiib Qjw/IqmBm2mBd/BddnMEYxpnRce4Y4n0don9GLsDcOWQJ7zoQSc8460pg7BPwD39EwPh tRbA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=vE8jV+Ce; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dan Murphy CC: Tony Lindgren CC: "Benoît Cousson" CC: Linus Walleij CC: Shawn Guo CC: Sascha Hauer CC: Pengutronix Kernel Team CC: Fabio Estevam CC: NXP Linux Team --- .../devicetree/bindings/leds/leds-lp55xx.txt | 149 +++++++++++++++--- 1 file changed, 124 insertions(+), 25 deletions(-) -- 2.22.0.214.g8dca754b1e diff --git a/Documentation/devicetree/bindings/leds/leds-lp55xx.txt b/Documentation/devicetree/bindings/leds/leds-lp55xx.txt index bfe2805c5534..736a2e1538be 100644 --- a/Documentation/devicetree/bindings/leds/leds-lp55xx.txt +++ b/Documentation/devicetree/bindings/leds/leds-lp55xx.txt @@ -1,6 +1,8 @@ Binding for TI/National Semiconductor LP55xx LED Drivers Required properties: +- #address-cells: 1 +- #size-cells: 0 - compatible: one of national,lp5521 national,lp5523 @@ -14,6 +16,18 @@ Required properties: Each child has own specific current settings - led-cur: Current setting at each LED channel (mA x10, 0 if LED is not connected) - max-cur: Maximun current at each LED channel. +- reg: Output channel for the LED. This is zero based channel identifier and + the data sheet is a one based channel identifier. + reg value to output to LED output number + D1 = reg value is 0 + D2 = reg value is 1 + D3 = reg value is 2 + D4 = reg value is 3 + D5 = reg value is 4 + D6 = reg value is 5 + D7 = reg value is 6 + D8 = reg value is 7 + D9 = reg value is 8 Optional properties: - enable-gpio: GPIO attached to the chip's enable pin @@ -35,23 +49,28 @@ example 1) LP5521 on channel 0. lp5521@32 { + #address-cells = <1>; + #size-cells = <0>; compatible = "national,lp5521"; reg = <0x32>; label = "lp5521_pri"; clock-mode = /bits/ 8 <2>; - chan0 { + chan@0 { + reg = <0>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; linux,default-trigger = "heartbeat"; }; - chan1 { + chan@1 { + reg = <1>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; }; - chan2 { + chan@2 { + reg = <2>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; }; @@ -70,59 +89,70 @@ ASEL1 ASEL0 Address VEN VEN 35h lp5523@32 { + #address-cells = <1>; + #size-cells = <0>; compatible = "national,lp5523"; reg = <0x32>; clock-mode = /bits/ 8 <1>; - chan0 { + chan@0 { + reg = <0>; chan-name = "d1"; led-cur = /bits/ 8 <0x14>; max-cur = /bits/ 8 <0x20>; }; - chan1 { + chan@1 { + reg = <1>; chan-name = "d2"; led-cur = /bits/ 8 <0x14>; max-cur = /bits/ 8 <0x20>; }; - chan2 { + chan@2 { + reg = <2>; chan-name = "d3"; led-cur = /bits/ 8 <0x14>; max-cur = /bits/ 8 <0x20>; }; - chan3 { + chan@3 { + reg = <3>; chan-name = "d4"; led-cur = /bits/ 8 <0x14>; max-cur = /bits/ 8 <0x20>; }; - chan4 { + chan@4 { + reg = <4>; chan-name = "d5"; led-cur = /bits/ 8 <0x14>; max-cur = /bits/ 8 <0x20>; }; - chan5 { + chan@5 { + reg = <5>; chan-name = "d6"; led-cur = /bits/ 8 <0x14>; max-cur = /bits/ 8 <0x20>; }; - chan6 { + chan@6 { + reg = <6>; chan-name = "d7"; led-cur = /bits/ 8 <0x14>; max-cur = /bits/ 8 <0x20>; }; - chan7 { + chan@7 { + reg = <7>; chan-name = "d8"; led-cur = /bits/ 8 <0x14>; max-cur = /bits/ 8 <0x20>; }; - chan8 { + chan@8 { + reg = <8>; chan-name = "d9"; led-cur = /bits/ 8 <0x14>; max-cur = /bits/ 8 <0x20>; @@ -133,29 +163,35 @@ example 3) LP5562 4 channels are defined. lp5562@30 { + #address-cells = <1>; + #size-cells = <0>; compatible = "ti,lp5562"; reg = <0x30>; clock-mode = /bits/8 <2>; - chan0 { + chan@0 { + reg = <0>; chan-name = "R"; led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; }; - chan1 { + chan@1 { + reg = <1>; chan-name = "G"; led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; }; - chan2 { + chan@2 { + reg = <2>; chan-name = "B"; led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; }; - chan3 { + chan@3 { + reg = <3>; chan-name = "W"; led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; @@ -167,62 +203,125 @@ example 4) LP8501 Others are same as LP5523. lp8501@32 { + #address-cells = <1>; + #size-cells = <0>; compatible = "ti,lp8501"; reg = <0x32>; clock-mode = /bits/ 8 <2>; pwr-sel = /bits/ 8 <3>; /* D1~9 connected to VOUT */ - chan0 { + chan@0 { + reg = <0>; chan-name = "d1"; led-cur = /bits/ 8 <0x14>; max-cur = /bits/ 8 <0x20>; }; - chan1 { + chan@1 { + reg = <1>; chan-name = "d2"; led-cur = /bits/ 8 <0x14>; max-cur = /bits/ 8 <0x20>; }; - chan2 { + chan@2 { + reg = <2>; chan-name = "d3"; led-cur = /bits/ 8 <0x14>; max-cur = /bits/ 8 <0x20>; }; - chan3 { + chan@3 { + reg = <3>; chan-name = "d4"; led-cur = /bits/ 8 <0x14>; max-cur = /bits/ 8 <0x20>; }; - chan4 { + chan@4 { + reg = <4>; chan-name = "d5"; led-cur = /bits/ 8 <0x14>; max-cur = /bits/ 8 <0x20>; }; - chan5 { + chan@5 { + reg = <5>; chan-name = "d6"; led-cur = /bits/ 8 <0x14>; max-cur = /bits/ 8 <0x20>; }; - chan6 { + chan@6 { + reg = <6>; chan-name = "d7"; led-cur = /bits/ 8 <0x14>; max-cur = /bits/ 8 <0x20>; }; - chan7 { + chan@7 { + reg = <7>; chan-name = "d8"; led-cur = /bits/ 8 <0x14>; max-cur = /bits/ 8 <0x20>; }; - chan8 { + chan@8 { + reg = <8>; chan-name = "d9"; led-cur = /bits/ 8 <0x14>; max-cur = /bits/ 8 <0x20>; }; }; + +Multicolor Framework Support +In addition to the nodes and properties defined above for device support the +properties below are needed for multicolor framework support as defined in +Documentation/devicetree/bindings/leds/leds-class-multicolor.txt + +Required child properties for multicolor framework + - color : Must be LED_COLOR_ID_MULTI + - function : see Documentation/devicetree/bindings/leds/common.txt + +Required grandchildren properties + - reg : This is the LED output of the device + - color : see Documentation/devicetree/bindings/leds/common.txt + +Multicolor LED example: +lp5523: lp5523@32 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "national,lp5523"; + reg = <0x32>; + clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ + + multi-led@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + color = ; + function = LED_FUNCTION_STANDBY; + linux,default-trigger = "heartbeat"; + + led@0 { + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + reg = <0x0>; + color = ; + }; + + led@1 { + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + reg = <0x1>; + color = ; + }; + + led@6 { + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + reg = <0x6>; + color = ; + }; + }; +}; From patchwork Tue Oct 8 20:47:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 175561 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp6206430ill; Tue, 8 Oct 2019 13:48:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqy2UubUEWnxNczhtiJgXfZhdP9FFR/QtRrD6p9wg94vbLrw6uIfyi2tivhz5PD0E7IU5S9s X-Received: by 2002:a05:6402:290:: with SMTP id l16mr35945509edv.178.1570567711919; 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[209.132.180.67]) by mx.google.com with ESMTP id s27si115462edm.226.2019.10.08.13.48.31; Tue, 08 Oct 2019 13:48:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="XOJv/Zsn"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731184AbfJHUs2 (ORCPT + 26 others); Tue, 8 Oct 2019 16:48:28 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:45060 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730720AbfJHUs0 (ORCPT ); Tue, 8 Oct 2019 16:48:26 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x98KmLYb092695; Tue, 8 Oct 2019 15:48:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1570567701; bh=0CPOm8eM1uD8XbD6J4VdzkHXSOBHZ4mtmjsY/tl59e8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=XOJv/ZsnSMX3NlOxuZFEV7vdaLwJ4QTAINlRrbBmV3R+bxZXda2FvAX7VKch9nkFT 7pyB/vrnn4lmTTucnphGQU5i4WhqW6zcuPzi6AX1hK3/CK5LwQOD1lv6fdVcEcjaD0 lMuoYZODiMG9j+V3XVyrpwXi8wwGMRtUi3wxpeE4= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x98KmL6K027706 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Oct 2019 15:48:21 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 8 Oct 2019 15:48:20 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 8 Oct 2019 15:48:18 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id x98KmK5j095745; Tue, 8 Oct 2019 15:48:20 -0500 From: Dan Murphy To: , CC: , , Dan Murphy , Tony Lindgren , =?utf-8?q?Beno?= =?utf-8?q?=C3=AEt_Cousson?= Subject: [PATCH v11 09/16] ARM: dts: n900: Add reg property to the LP5523 channel node Date: Tue, 8 Oct 2019 15:47:53 -0500 Message-ID: <20191008204800.19870-10-dmurphy@ti.com> X-Mailer: git-send-email 2.22.0.214.g8dca754b1e In-Reply-To: <20191008204800.19870-1-dmurphy@ti.com> References: <20191008204800.19870-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the reg property to each channel node. This update is to accomodate the multicolor framework. In addition to the accomodation this allows the LEDs to be placed on any channel and allow designs to skip channels as opposed to requiring sequential order. Signed-off-by: Dan Murphy CC: Tony Lindgren CC: "Benoît Cousson" k# interactive rebase in progress; onto ae89cc6d4a8c --- arch/arm/boot/dts/omap3-n900.dts | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) -- 2.22.0.214.g8dca754b1e diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 84a5ade1e865..643f35619246 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -607,63 +607,74 @@ }; lp5523: lp5523@32 { + #address-cells = <1>; + #size-cells = <0>; compatible = "national,lp5523"; reg = <0x32>; clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */ - chan0 { + chan@0 { chan-name = "lp5523:kb1"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + reg = <0>; }; - chan1 { + chan@1 { chan-name = "lp5523:kb2"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + reg = <1>; }; - chan2 { + chan@2 { chan-name = "lp5523:kb3"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + reg = <2>; }; - chan3 { + chan@3 { chan-name = "lp5523:kb4"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + reg = <3>; }; - chan4 { + chan@4 { chan-name = "lp5523:b"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + reg = <4>; }; - chan5 { + chan@5 { chan-name = "lp5523:g"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + reg = <5>; }; - chan6 { + chan@6 { chan-name = "lp5523:r"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + reg = <6>; }; - chan7 { + chan@7 { chan-name = "lp5523:kb5"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + reg = <7>; }; - chan8 { + chan@8 { chan-name = "lp5523:kb6"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + reg = <8>; }; }; From patchwork Tue Oct 8 20:47:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 175562 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp6206480ill; Tue, 8 Oct 2019 13:48:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqxz+wWpn78wctl79ru7RmzCpP5RP36l7QTkl4/iWiVNKlxcFKehidHIJ58ToG/0lu3KuV2M X-Received: by 2002:a50:b7ed:: with SMTP id i42mr34822844ede.52.1570567715061; Tue, 08 Oct 2019 13:48:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570567715; cv=none; d=google.com; s=arc-20160816; b=ZIladBnPzzMz0zcpGYxHGFY44cPq4vSrBBF4f5PMe/Y6+9w9BtuwJTHTft3PgW9/f+ gTUM4mY5V4V4luB/vh5xtExxCbUjUaoBDho1tMoDkqY63yUmgD1Ga80Y1eNrErAy4Pfk 6xl5NBJhxl8rwAu7CThjIuR14+Ib88UolqpYn1YLsUHLRByJgir2ebpK01ifep5XfE/T HVLDbc5NwrhtGR2TgkGC1ydG8vvSsAGIuA0jypEGviWz4nucegLxkUt3QilejrXnl9Mi 8QnsVLp00Ejv59wbroRekeMJmJ+N+w6OeUGJPZy6TULA0GAgFBKEbXWUZbU7XPuYkWSH Yb2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Q6v3ZsELVVFaq45xRxLW4voHJAlhEXxHc1kVNsr3mZg=; b=IP0FLsJsG6v/rLsXxni8A0TdSydJh/3LUn8tYdbPZBPnjcKybHqsLRoKRYxxV4IJxR XGMieEgH+5/SHyJFDEJ5/lhpg8nsc7/SXjjiM8FnCtTVbOvlpzL4AR2dHQQwEfsDStrR agLVGgSZuoEAun6r0wLppEQ7o55hgsckdUAJwL97BLQyx0L6difS5Yj10AbgOSGugFoT oNDaZW4LbP72Tug7oPdX6MClHa4oK5+0DCh4BFHD738H7bp4cU2I1fazULMV2BMoErmC g74t3BlVe+ZCYYddqwA17Nb7ELAIC4BFHDrR7HaO0oDcpnP+uxfU7cclh/9fbPOTHwer hx3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="O6TWtE/A"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s27si115462edm.226.2019.10.08.13.48.34; Tue, 08 Oct 2019 13:48:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="O6TWtE/A"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731229AbfJHUsd (ORCPT + 26 others); Tue, 8 Oct 2019 16:48:33 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:43394 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731214AbfJHUsc (ORCPT ); Tue, 8 Oct 2019 16:48:32 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x98KmLx7092487; Tue, 8 Oct 2019 15:48:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1570567701; bh=Q6v3ZsELVVFaq45xRxLW4voHJAlhEXxHc1kVNsr3mZg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=O6TWtE/AfSr/Kk9AisDUL86VVBfXbzMkWIgnDn44HEFNiZ5lwgzto4aFABMjPePrd XODG7Xw4v+yuDzY7J4EwFEnZzCYn7eCNu7ueW6nq8QkdUq/ZPYr9ObafjnkpY8/p3Z RwemZD+idfNvilrmISB9WjJz0geuWGNiRah4kRQk= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x98KmLvS110731; Tue, 8 Oct 2019 15:48:21 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 8 Oct 2019 15:48:18 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 8 Oct 2019 15:48:18 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x98KmKqG066679; Tue, 8 Oct 2019 15:48:21 -0500 From: Dan Murphy To: , CC: , , Dan Murphy , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team Subject: [PATCH v11 10/16] ARM: dts: imx6dl-yapp4: Add reg property to the lp5562 channel node Date: Tue, 8 Oct 2019 15:47:54 -0500 Message-ID: <20191008204800.19870-11-dmurphy@ti.com> X-Mailer: git-send-email 2.22.0.214.g8dca754b1e In-Reply-To: <20191008204800.19870-1-dmurphy@ti.com> References: <20191008204800.19870-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the reg property to each channel node. This update is to accomodate the multicolor framework. In addition to the accomodation this allows the LEDs to be placed on any channel and allow designs to skip channels as opposed to requiring sequential order. Signed-off-by: Dan Murphy CC: Shawn Guo CC: Sascha Hauer CC: Pengutronix Kernel Team CC: Fabio Estevam CC: NXP Linux Team --- arch/arm/boot/dts/imx6dl-yapp4-common.dtsi | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) -- 2.22.0.214.g8dca754b1e diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi index e8d800fec637..efc466ed1fea 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -257,29 +257,35 @@ reg = <0x30>; clock-mode = /bits/ 8 <1>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; - chan0 { + chan@0 { chan-name = "R"; led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; + reg = <0>; }; - chan1 { + chan@1 { chan-name = "G"; led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; + reg = <1>; }; - chan2 { + chan@2 { chan-name = "B"; led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; + reg = <2>; }; - chan3 { + chan@3 { chan-name = "W"; led-cur = /bits/ 8 <0x0>; max-cur = /bits/ 8 <0x0>; + reg = <3>; }; }; From patchwork Tue Oct 8 20:47:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 175571 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp6207035ill; Tue, 8 Oct 2019 13:49:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqyJJocHtP+2TN4bK3Gi7k0hWytZZbUmH2himHYxhtF1j/EasHV6W1vowv3EOB8lep8Gvm0x X-Received: by 2002:a17:906:1c06:: with SMTP id k6mr30042648ejg.217.1570567751453; Tue, 08 Oct 2019 13:49:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570567751; cv=none; d=google.com; s=arc-20160816; b=DC6UcmOgD1KG+pM0wpjmpTpp9GFWZzAfILkoXAmAk3AofG3BL7Xh9gWbG6zhnQqlUr fIg3Rye4MhCYH4sfD394wcXSLxLsnoh4g8QotxSUiOSUm4cefdzXcpfxuabo2Fe/mfop 2itmAoTs8+g2gHCjrqAfL9Y9MW4hWXTDThGrjwD/9OlqFVBm4D03rxBhuIfjchCk8gYw M8lJM4qs08cEOh6o7LLTo4y7T+SCxdqGDw5q9jasdTRR9NH/iJdWTQyqD23uqgMGWvWb mWcl4KP9ZrLlGWtcsQ0zp0yWUKVtcRk02bomJulOk9gT9+f/5x4ly7FqiFoTyjJ/oF9F HhhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=95PMofJsyIEn3NAsJyz9IppOg+cVPNREQZwHO7yf3yY=; b=JWfdugAn3Epsw5gFfl9wJgM1XJ+nIuJntwK3Ki1uIoK0/EYPvFWmC9oQ2Qgg4XGRB1 JvThwrFqcTC7qLB4X+Pl38HibAWfkFTmBXvSzAqZOqz4dDF2DLejBTOFZSDOZvcboseL xHpBBnD9jlbQMu/11vNaNBkXkGrfKuSBThmmtidPRp+p5JA2SdLLslHzAVJ8o8Hk4Apj xsDIGzjoJBQ/8rVRaqLNmgl3sWRNdhkDgab43+n4+xYpy+VU7vE3cSuOKS61/F2Eh9+0 Jyj5WK2358eLYUGTMNREzw+5FHt4qS+JrHL44niYmSxpQzDaHZ/4iaqrfgARqa3KdsBW avBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=tdg+eEAo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p1si98921eda.406.2019.10.08.13.49.11; Tue, 08 Oct 2019 13:49:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=tdg+eEAo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731329AbfJHUtH (ORCPT + 26 others); Tue, 8 Oct 2019 16:49:07 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:45794 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731110AbfJHUsY (ORCPT ); Tue, 8 Oct 2019 16:48:24 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x98KmLkx097365; Tue, 8 Oct 2019 15:48:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1570567701; bh=95PMofJsyIEn3NAsJyz9IppOg+cVPNREQZwHO7yf3yY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tdg+eEAoVlv1lN9wqyu4XmZvEHmihS3xCSYxRp2RXjYeF2+Ocl04Gta9AD9jkzvjP BcdxCUEoqWRxco5+4D0tMB3f2AU4hqcP3dhG4Yv0Tlu3ls9eNPQhaVizISjcLw0iAS 4q7lnU7WAtJGsJn03iWTNJs0paWs/uZexlAwJidQ= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x98KmLvO062210 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Oct 2019 15:48:21 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 8 Oct 2019 15:48:18 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 8 Oct 2019 15:48:18 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x98KmLrt073119; Tue, 8 Oct 2019 15:48:21 -0500 From: Dan Murphy To: , CC: , , Dan Murphy , Linus Walleij Subject: [PATCH v11 11/16] ARM: dts: ste-href: Add reg property to the LP5521 channel nodes Date: Tue, 8 Oct 2019 15:47:55 -0500 Message-ID: <20191008204800.19870-12-dmurphy@ti.com> X-Mailer: git-send-email 2.22.0.214.g8dca754b1e In-Reply-To: <20191008204800.19870-1-dmurphy@ti.com> References: <20191008204800.19870-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the reg property to each channel node. This update is to accomodate the multicolor framework. In addition to the accomodation this allows the LEDs to be placed on any channel and allow designs to skip channels as opposed to requiring sequential order. Signed-off-by: Dan Murphy CC: Linus Walleij --- arch/arm/boot/dts/ste-href.dtsi | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) -- 2.22.0.214.g8dca754b1e diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 4f6acbd8c040..8a873da102d3 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -56,16 +56,21 @@ reg = <0x33>; label = "lp5521_pri"; clock-mode = /bits/ 8 <2>; - chan0 { + #address-cells = <1>; + #size-cells = <0>; + chan@0 { + reg = <0>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; linux,default-trigger = "heartbeat"; }; - chan1 { + chan@1 { + reg = <1>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; }; - chan2 { + chan@2 { + reg = <2>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; }; @@ -75,15 +80,20 @@ reg = <0x34>; label = "lp5521_sec"; clock-mode = /bits/ 8 <2>; - chan0 { + #address-cells = <1>; + #size-cells = <0>; + chan@0 { + reg = <0>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; }; - chan1 { + chan@1 { + reg = <1>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; }; - chan2 { + chan@2 { + reg = <2>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; };