From patchwork Thu Apr 11 20:25:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parker Newman X-Patchwork-Id: 788208 Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B04AF17C9B; Thu, 11 Apr 2024 20:26:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.208.4.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712867166; cv=none; b=dU3vGsQ4D5I48RqFI5aPX5h47TUCtwjg1aJjFm4dPjGDEECnMuOHp7m2Mn6rsp/1mzttf4Z20mGJlYhwnTbKS9Cv5JDqyUJ9uys3VGbn3+Xv56FYEPm9HHEkSyxyGD8uaRmTI/i3PJ/+Pwes5FhHJmloNJ/U4K2M98JAXHJidD8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712867166; c=relaxed/simple; bh=ZIhUJYvk/wOqSM1Ia5ds5H6P5YLEAb5YuO7xaYAFlVI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sUbxzTca63pCMvbnZ4tbc3N43/CtjHYLsoF9zCV6JLVZoPWHvzLPmXWmcoL0OgF23Eg5FGLlK22iu+w/qNS+RR0UX45niFs3LuWaRFNEHJ0tsDbQzsJcj1ua27xS3XYfc6jpnPlv3I6KtfxCXwmdSYV4TUMneAhxn+Ame1h4Sq0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=finest.io; spf=pass smtp.mailfrom=finest.io; dkim=pass (2048-bit key) header.d=finest.io header.i=parker@finest.io header.b=kk1nSTVt; arc=none smtp.client-ip=74.208.4.196 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=finest.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=finest.io Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=finest.io header.i=parker@finest.io header.b="kk1nSTVt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=finest.io; s=s1-ionos; t=1712867157; x=1713471957; i=parker@finest.io; bh=/pMNEblpoORPGqBosh2QqloC4JBppA9VbN2iUpBE/p8=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:Message-ID:In-Reply-To: References:MIME-Version:Content-Transfer-Encoding:cc: content-transfer-encoding:content-type:date:from:message-id: mime-version:reply-to:subject:to; b=kk1nSTVtVfu2ynp1qOzpLu0CuH3B53XzvIyrqnB4GbOoREOIeraU2mSbqF6n5Wam nRgrT81pUR82Dc6iNqAtD5s41LoZ49Z34TUFMvQ1c9RLDn4cyDw0oj5as6URXYHVU 67xk8oYRO/uC4PuF6Jc6Hr207es1qXt90qmBjYbVHS8qlADm/lxAKyC+0MAG3RtV6 hNjrUZWl6HCp+pZVJDy6N/25yKJzERxzGuOZsMcO1uzuhof3u7wOsQsCQWwzoZCMO jjY3c6rN1d0e1C0SLnjOYaL4LtYRXouYn3kw/UfvrUQ5kUbdbCZ0xtQp0vXTcsZnr gNzhvsBf/4Cjat9Spg== X-UI-Sender-Class: 55c96926-9e95-11ee-ae09-1f7a4046a0f6 Received: from finest.io ([98.159.241.229]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPSA (Nemesis) id 0MbODK-1sDdlx0u9s-00QmTM; Thu, 11 Apr 2024 22:25:57 +0200 From: parker@finest.io To: Greg Kroah-Hartman , Jiri Slaby , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Parker Newman Subject: [PATCH v2 1/7] serial: exar: adding missing CTI and Exar PCI ids Date: Thu, 11 Apr 2024 16:25:39 -0400 Message-ID: <0a62e3c831ab93a583e5f29affdea87bd27ae9d6.1712863999.git.pnewman@connecttech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Provags-ID: V03:K1:cXmJLp/tzSoLCUkKqfmuM1UaagLN2AmJ3EvkXEYcSB4NZCiUkS6 z2BzbyJBI0yCNNW3lWT1iwTuGWvyRM5bXE1G0EYh8xJ0YE5+dAa+vtdZZc9zgaZq992n15C 2Ss8g3nIqKe2Igse2VwIZ1aodDn971BT8KLu6R2T9uOyYTJIBCDiIT0J8nl0Gx2venDCuwK SK6DIaXqDJezgFlbqOE6A== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:BSekdH7t9NU=;d2x6hKxVTe4Zt81uKmdZWJUoHSw 0f8n5RgM+gXguAGFedwRNFXg4IAgyCXxdiXLw6a/MZAy1KygShEf8FSwQlxwZ+LUtkZ4xfAI6 p2f3bv+nzR8g4BpIP54GuIXSpDdKj0zlVsoBOK3uBO/mFmdR7TxCrw5ZLshmnBMD0ydX3iKJ2 INC+ic/LslRPLez4ReHZfTPTUsrnMB+FDThw4iPWLWU9Y1AjE3rUeLnmtgshyhvTMrlfqn4z7 UvuroCghhadEl3o6tPaOEvjUzGrIntQs71s/jWZ06mqNCtlr3jp6a26lqzOKhZIHeEiaMUAwO J4VneNVSnPjoQJ2u6edQycygCE0ToQ2mh/ixHe5gdjhxOMVn0RRl9oeAqqCrsShmZ7ER7+2So WsngorxHc22nIB67nYe9CigfftWdaNFB8C7UHR5uJBmtK1zCDeqXGV61Avp8af/FAap8vsGqP GZN2YOBd2bfEyytBE3lSD9vD2/mCTwP245WSc5pSpnmG/D3FwQEMD+4QT6qsQzSu8dkHZ0396 gCLHgpDnkmkHBFbW0plQSElln//wYNv3tUd5n8cv/ZuYtq2wDY+U6imCC0CECfDhFi4QEfcG2 cCNxS7W24OrgCXt5lF2PvHD2fKr1kVf3mLjJgkFmmdUpSW6/rzskj2ns1QmucIeQ1eNc+alDd C8UywUF7Q6VQxgxHkxI/fTnzYUZyUywJZDHacaWIUcCiIVH1tZuqOIIbXdxrjGQ1x8X2IFjZa 5MsfJ92cmhTjIaUnWim083Rtls6avDRBYbCdxUmci4aPHLhU+79uHs= From: Parker Newman - Added Connect Tech and Exar IDs not already in pci_ids.h Signed-off-by: Parker Newman --- drivers/tty/serial/8250/8250_exar.c | 42 +++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) -- 2.43.2 diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/8250_exar.c index 0440df7de1ed..4d1e07343d0b 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -46,8 +46,50 @@ #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 +#define PCI_VENDOR_ID_CONNECT_TECH 0x12c4 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_SP_OPTO 0x0340 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_A 0x0341 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_B 0x0342 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS 0x0350 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A 0x0351 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B 0x0352 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS 0x0353 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A 0x0354 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B 0x0355 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO 0x0360 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A 0x0361 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B 0x0362 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP 0x0370 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232 0x0371 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485 0x0372 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP 0x0373 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP 0x0374 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP 0x0375 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232_NS 0x0376 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT 0x0380 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT 0x0381 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO 0x0382 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO 0x0392 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP 0x03A0 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232 0x03A1 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485 0x03A2 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232_NS 0x03A3 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XEG001 0x0602 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_BASE 0x1000 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_2 0x1002 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_4 0x1004 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_8 0x1008 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_12 0x100C +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_16 0x1010 +#define PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG00X 0x110c +#define PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG01X 0x110d +#define PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_16 0x1110 + #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358 +#define PCI_DEVICE_ID_EXAR_XR17V252 0x0252 +#define PCI_DEVICE_ID_EXAR_XR17V254 0x0254 +#define PCI_DEVICE_ID_EXAR_XR17V258 0x0258 #define PCI_SUBDEVICE_ID_USR_2980 0x0128 #define PCI_SUBDEVICE_ID_USR_2981 0x0129 From patchwork Thu Apr 11 20:25:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parker Newman X-Patchwork-Id: 788210 Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA83C17C6A; Thu, 11 Apr 2024 20:26:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.208.4.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712867164; cv=none; b=OY9nNew8rvDe2UXmFjHs7D701mse/RXBqxWDVImACtkMB95eqGN6lcQJsRrq3cVNADYYi1lCABCDNL88mh8i4pKM2YhorQh+/tbLo6CXkEgFCVM6fy0WrUNLf7fSU7I+LQlht8H0LUOqVjB41/qzCxWPjy0qbnjqulmqdqH4gxY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712867164; c=relaxed/simple; bh=XoApVgnrMaufCiheBxdu3E9GYzATKwq4UZrsxBcGihY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=j6ay3ACy4qtH4Qlxhm+l9hUiE5hPbAeHugJX6tILNOtL8UBxtukQnZM87MvchzzKLHtwzBiIhonQrotT4TfKSJKnyHN+HtZhz68aZDXqb/n3rnj9dfRTrrEviREGXa4i4UPtUUDL2L/OLDwGCxMu1FG/RlSaeLd4X4MQcGsmUAQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=finest.io; spf=pass smtp.mailfrom=finest.io; dkim=pass (2048-bit key) header.d=finest.io header.i=parker@finest.io header.b=i6iH4hiR; arc=none smtp.client-ip=74.208.4.196 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=finest.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=finest.io Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=finest.io header.i=parker@finest.io header.b="i6iH4hiR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=finest.io; s=s1-ionos; t=1712867157; x=1713471957; i=parker@finest.io; bh=jDtycroHBuO6M79KMq7clDQ2cxUyLfrUzN08PqttkGg=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:Message-ID:In-Reply-To: References:MIME-Version:Content-Transfer-Encoding:cc: content-transfer-encoding:content-type:date:from:message-id: mime-version:reply-to:subject:to; b=i6iH4hiRs01wemE31sWZqXm9UzqsGXcoMWH40UXGf87cxkc4vgpIlSVCD5w33i9m dbQ94CkdYq+SHgQMAXS8gScBsPVIws82OklIJ2P1AaiV8tPJk0baVSEv6bogmRhu+ sLQZ8uugaJQMvhTQnnB5GEim7xdlukv4DMw5u4ajDN90HKkNxZ9e2DAZFOg5DCMk8 ecPVGmdWGwXdtiQ7hp03WuItPd/Acy42+Eet4Btcoz1r67LPRqxteKbfofqPDR7i3 LgUaneB2sDr84RJA89zB/4XVWVhI0sqnI2X7rtsRjr3FJERT7dsde11k4ffWv57D1 6GkuvLO5+puSYpmqyA== X-UI-Sender-Class: 55c96926-9e95-11ee-ae09-1f7a4046a0f6 Received: from finest.io ([98.159.241.229]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPSA (Nemesis) id 0M9IQC-1s3Ijb2DOw-0032Yw; Thu, 11 Apr 2024 22:25:57 +0200 From: parker@finest.io To: Greg Kroah-Hartman , Jiri Slaby , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Parker Newman Subject: [PATCH v2 2/7] serial: exar: add support for reading from Exar EEPROM Date: Thu, 11 Apr 2024 16:25:40 -0400 Message-ID: X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Provags-ID: V03:K1:Y4RPmjxQqQ4vafUt1kFgZGKHOYLk7BwGDAxQV2jDQxdTtiQcTRO jvRby1j2c6/Af1yc47C6LccmwT122stXSxmqbTNJNn2nm0a5DDuKlKRYE00rQahWTVbczBc dXRwLDjhGFFBZWA8PHZq/xju+DgjcKQctbyWObDTTg+0X2/NL4cLxorIDOyNDr3oPPnXKNV 8p4ZcyyChahMvX1BOv6eA== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:upnVXHs+xiY=;fYUxVut5gLhHQy/JpxbZcD7qSbs 4cbk4AK2b1I5gwNvVC+EeRHtKx14bxGJHpt0WQ0vG5Qt+jGTIR1dj7eWdSZMCTDXv5NDS/2is 6PR2GsZLUI/Qag0jzBa3FGDfs9tnIyjy+5fk62fEHtKru5yz1ICGnm8F04PwId4/kqxAGMbyU Wfr2RJ2vHKv/ttcTiuz65gzLRe3TFKjxOenjz3C7sd59tAG9EJf9YTPwSR4qedk6ihKUIk0ka EbbP1gCXUMdFid0HHrPGn5VtqxJqdxdYDG4zTtKJ1qo/JTpDRc60wyWGraygSwFjY/mi5oOhS jNZ70TZR0fe6E99PVjHaD8COPBWQ6C25zTjn6JgTyiA/9TlQhKD2LancAH10s4WK4E+FjcLGy 3iZdNDsGS21OVZwPbCxtRu3UxsopzOWm3GT8/N8DnnuVpRvVRPdvBCCtzbWFwWFidMHhU3a61 4waDD5zen4HIu80vqrVs2fSDRh9NWoEQnXvpeHDdw4r4ZlBCjB9tIGPwiibjY6EpgK//32jmz otdicFyp9ZZRwifxuduQPF0caLXEiKqLZXfZGqrIbV3teoQ05XtX5gRhMboFlAXQToBggrNi7 T4qq8aN3pwdbIB1waQfRfUUCgUzkgsDe9QW1mYlxQmqA7efWd54FTf6s8GvxTXBe3K+u/kou+ b9pFs3ahCHv6rfYbl3s8wA7UmSdS39+euk89JsdY20lGtRw1MWHqg3AMFdQvhpLwP+TIwAgWp 0KcBYk/CU/JokSjUBshOKaHiK2I6xt9xPrm/VBS0jCb0zbZ4Q8F/3s= From: Parker Newman - Adds support for reading a word from the Exar EEPROM. - Adds exar_write_reg/exar_read_reg for reading and writing to the UART's config registers. Signed-off-by: Parker Newman --- drivers/tty/serial/8250/8250_exar.c | 110 ++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) -- 2.43.2 diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/8250_exar.c index 4d1e07343d0b..49d690344e65 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -128,6 +128,16 @@ #define UART_EXAR_DLD 0x02 /* Divisor Fractional */ #define UART_EXAR_DLD_485_POLARITY 0x80 /* RS-485 Enable Signal Polarity */ +/* EEPROM registers */ +#define UART_EXAR_REGB 0x8e +#define UART_EXAR_REGB_EECK BIT(4) +#define UART_EXAR_REGB_EECS BIT(5) +#define UART_EXAR_REGB_EEDI BIT(6) +#define UART_EXAR_REGB_EEDO BIT(7) +#define UART_EXAR_REGB_EE_ADDR_SIZE 6 +#define UART_EXAR_REGB_EE_DATA_SIZE 16 + + /* * IOT2040 MPIO wiring semantics: * @@ -195,6 +205,106 @@ struct exar8250 { int line[]; }; +static inline void exar_write_reg(struct exar8250 *priv, + unsigned int reg, uint8_t value) +{ + if (!priv || !priv->virt) + return; + + writeb(value, priv->virt + reg); +} + +static inline uint8_t exar_read_reg(struct exar8250 *priv, unsigned int reg) +{ + if (!priv || !priv->virt) + return 0; + + return readb(priv->virt + reg); +} + +static inline void exar_ee_select(struct exar8250 *priv, bool enable) +{ + uint8_t value = 0x00; + + if (enable) + value |= UART_EXAR_REGB_EECS; + + exar_write_reg(priv, UART_EXAR_REGB, value); + udelay(2); +} + +static inline void exar_ee_write_bit(struct exar8250 *priv, int bit) +{ + uint8_t value = UART_EXAR_REGB_EECS; + + if (bit) + value |= UART_EXAR_REGB_EEDI; + + //Clock out the bit on the i2c interface + exar_write_reg(priv, UART_EXAR_REGB, value); + udelay(2); + + value |= UART_EXAR_REGB_EECK; + + exar_write_reg(priv, UART_EXAR_REGB, value); + udelay(2); +} + +static inline uint8_t exar_ee_read_bit(struct exar8250 *priv) +{ + uint8_t regb; + uint8_t value = UART_EXAR_REGB_EECS; + + //Clock in the bit on the i2c interface + exar_write_reg(priv, UART_EXAR_REGB, value); + udelay(2); + + value |= UART_EXAR_REGB_EECK; + + exar_write_reg(priv, UART_EXAR_REGB, value); + udelay(2); + + regb = exar_read_reg(priv, UART_EXAR_REGB); + + return (regb & UART_EXAR_REGB_EEDO ? 1 : 0); +} + +/** + * exar_ee_read() - Read a word from the EEPROM + * @priv: Device's private structure + * @ee_addr: Offset of EEPROM to read word from + * + * Read a single 16bit word from an Exar UART's EEPROM + * + * Return: EEPROM word on success, negative error code on failure + */ +static int exar_ee_read(struct exar8250 *priv, uint8_t ee_addr) +{ + int i; + int data = 0; + + exar_ee_select(priv, true); + + //Send read command (opcode 110) + exar_ee_write_bit(priv, 1); + exar_ee_write_bit(priv, 1); + exar_ee_write_bit(priv, 0); + + //Send address to read from + for (i = 1 << (UART_EXAR_REGB_EE_ADDR_SIZE - 1); i; i >>= 1) + exar_ee_write_bit(priv, (ee_addr & i)); + + //Read data 1 bit at a time + for (i = 0; i <= UART_EXAR_REGB_EE_DATA_SIZE; i++) { + data <<= 1; + data |= exar_ee_read_bit(priv); + } + + exar_ee_select(priv, false); + + return data; +} + static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old) { /* From patchwork Thu Apr 11 20:25:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parker Newman X-Patchwork-Id: 788209 Received: from mout.perfora.net (mout.perfora.net [74.208.4.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCE5E17C7F; Thu, 11 Apr 2024 20:26:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.208.4.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712867165; cv=none; b=JPiOuWSQOz2u095d6xULQxCsdT/bKDzFncMm51DhfzrysZKnxikx3JZg6rsqJrs1EFIRGrUunDuKvyG1tMC6u7Mx2P+Cv88PmklNh3ryCv60jNLaPtN23+hO+/IpWEjUKcAjBTJJRzKCmz3GPzTC7V1Ah0VykY5dnLqSBYofFFA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712867165; c=relaxed/simple; bh=+2XwDQ6lAn4Bx7+V6jX/KojsTWOswymbTXhB7XkGjWw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cHQ1l7H73QFN6e9zJgf9GMbj2iTCpZ6Y1EEOH3TIh93RGgn9Kv/+cWy70kOkmM7mg2fQQoSoR8WF4qmmNaD/oHh+8T3fOJq1cWmXnPo7ufff5EJEP2qPv59j81m4cx0YIona9FoJFu3gCB9A/309hNjICZrM0eArcozTaXYrRA4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=finest.io; spf=pass smtp.mailfrom=finest.io; dkim=pass (2048-bit key) header.d=finest.io header.i=parker@finest.io header.b=TtlHFyvR; arc=none smtp.client-ip=74.208.4.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=finest.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=finest.io Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=finest.io header.i=parker@finest.io header.b="TtlHFyvR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=finest.io; s=s1-ionos; t=1712867158; x=1713471958; i=parker@finest.io; bh=uAlKCcZd53Dk25E1mU4G5eUWhLwVSNKWLZARPx1Vd/k=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To: References; b=TtlHFyvRI6Kr9lAjljKBLlf7S2jloEqhkZQZzEI5SpolyfIMupBf4tzDmaVQ5E8m QHjuh1T/rLHQqkLJfOY5nMnnKSCnd1OSU7howzSWncicMBDxxJBzuRjkb42UD9AJR u0tBwfNOsyEUY1G+ZCDF25/hSiYaE1kHoG10MtTACMTWznOGm8JDDuYZgW64oxjl2 C6Wo/VRHl8j2xCz2BzbWc5aLMXYciYgsgjQnsD52Ay/GPITW/+h6ccVS0KiQg2n4I oRtGMLiLjmJ9tSqu3pGx+hhsT+9euELnv1eyuqKGVLsU4YDxU0yDQ/ci1JxssGZ9t i6fpttzP/ymK4S6Ydg== X-UI-Sender-Class: 55c96926-9e95-11ee-ae09-1f7a4046a0f6 Received: from finest.io ([98.159.241.229]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPSA (Nemesis) id 0LaEeW-1scdYJ3bTi-00cNNe; Thu, 11 Apr 2024 22:25:57 +0200 From: parker@finest.io To: Greg Kroah-Hartman , Jiri Slaby , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Parker Newman Subject: [PATCH v2 3/7] serial: exar: add support for config/set single MPIO Date: Thu, 11 Apr 2024 16:25:41 -0400 Message-ID: <3e671b6c0d11a2d0c292947675ed087eaaa5445e.1712863999.git.pnewman@connecttech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Provags-ID: V03:K1:yXBxXgdcJalhXxtH8gjTeGnupsP1RKxLCVurqpPIXIFf7CIdcfr JHmai1w/JQ4yp+ktShW+hu+yi6m/RhETynrnoNxAv61gBEgDoX7e5GPicA9QG0KyY5lJIjr cI5II2tdeo3Cj3E/x3xoQ01Yq7g+fNHKbcK02Ux7eJgIch9J/N5pA9zufh0HseGV6O50Aej i7TBIbMJ1PYrOKvpIKMuA== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:DpKvsfJhqzk=;cG+QJzw+y/TjMJhI+R3NDMhHo38 Y05pfv2h7JRdf5o0S2/lBKtExZrYB8u5RDuePCwDFg2i98IlKFyzcHMos1wLWK416LdxSvMOH YNoPmi3W1MOg1nxzUy4lhe/yprLb00yiXknghTKU9AS45NBLJSrMjym75pH54+uqOn4fxGakr nUo1dhy3YY53VpnC1FNLz8VNE+ShsFGPX9qGnWcBUCZ8xMf+ZACNF8lOx9GZA8HhGLfNCNgq4 xRFnOcRXcfCm5TbTJ50qd6oLRKHkbmIiqmX+qLMI11ijmqMHaywA7pAY2HkcRQcUQsU4VQG+v LU2OEAS93k3jNqppG6aop3s2jCIwYjc83MleaYUrLHPo3ZHXcwGimy4yV9CZjxt7+zO3M/NSq SmPRHMUT09mvLAoT6I6kMb5mclFREinMoX/tarxaMYMeGdAecQ3Aj2aqsYPbEyOvngb88EmDr QELkO6c/7jwVtC71vgfL4TB17TDG2cxEsnJIjA5z9dtzyWo7Wr9BVnJLqicltZODgiHnaCi37 UyAsQ4GA1yV4GS+dQ63Q5alql9klj6Wj7V8Q/TmH2lp9+5WQv/+udfTwpoS8HI2VoNALz7mU+ /kO6DyO1dSVkbzdn8sjO41NmR4JY4/0P3vUNAPYfQ2Csj267Av55uLXCwMFyxM/jaSvTLGUjC uu5aP/YT5mwTJ3GBcw6CbEcD1DID0BcQ6X3cbduonI5F4XP2+YrBUfmU9LTb7ajrItJCEK1dw w7kA8PKRKcUUg263CEMkKJ+7SCnXCSHmfXWBZGEVBSXoy+LbD/JiLc= From: Parker Newman Adds support for configuring and setting a single MPIO Signed-off-by: Parker Newman --- drivers/tty/serial/8250/8250_exar.c | 88 +++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) -- 2.43.2 diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/8250_exar.c index 49d690344e65..9915a99cb7c6 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -305,6 +305,94 @@ static int exar_ee_read(struct exar8250 *priv, uint8_t ee_addr) return data; } +/** + * exar_mpio_config() - Configure an EXar MPIO as input or output + * @priv: Device's private structure + * @mpio_num: MPIO number/offset to configure + * @output: Configure as output if true, inout if false + * + * Configure a single MPIO as an input or output and disable trisate. + * If configuring as output it is reccomended to set value with + * exar_mpio_set prior to calling this function to ensure default state. + * + * Return: 0 on success, negative error code on failure + */ +static int exar_mpio_config(struct exar8250 *priv, + unsigned int mpio_num, bool output) +{ + uint8_t sel_reg; //MPIO Select register (input/output) + uint8_t tri_reg; //MPIO Tristate register + uint8_t value; + unsigned int bit; + + if (mpio_num < 8) { + sel_reg = UART_EXAR_MPIOSEL_7_0; + tri_reg = UART_EXAR_MPIO3T_7_0; + bit = mpio_num; + } else if (mpio_num >= 8 && mpio_num < 16) { + sel_reg = UART_EXAR_MPIOSEL_15_8; + tri_reg = UART_EXAR_MPIO3T_15_8; + bit = mpio_num - 8; + } else { + return -EINVAL; + } + + //Disable MPIO pin tri-state + value = exar_read_reg(priv, tri_reg); + value &= ~(BIT(bit)); + exar_write_reg(priv, tri_reg, value); + + value = exar_read_reg(priv, sel_reg); + //Set MPIO as input (1) or output (0) + if (output) + value &= ~(BIT(bit)); + else + value |= BIT(bit); + + exar_write_reg(priv, sel_reg, value); + + return 0; +} +/** + * exar_mpio_set() - Set an Exar MPIO output high or low + * @priv: Device's private structure + * @mpio_num: MPIO number/offset to set + * @high: Set MPIO high if true, low if false + * + * Set a single MPIO high or low. exar_mpio_config must also be called + * to configure the pin as an output. + * + * Return: 0 on success, negative error code on failure + */ +static int exar_mpio_set(struct exar8250 *priv, + unsigned int mpio_num, bool high) +{ + uint8_t reg; + uint8_t value; + unsigned int bit; + + if (mpio_num < 8) { + reg = UART_EXAR_MPIOSEL_7_0; + bit = mpio_num; + } else if (mpio_num >= 8 && mpio_num < 16) { + reg = UART_EXAR_MPIOSEL_15_8; + bit = mpio_num - 8; + } else { + return -EINVAL; + } + + value = exar_read_reg(priv, reg); + + if (high) + value |= BIT(bit); + else + value &= ~(BIT(bit)); + + exar_write_reg(priv, reg, value); + + return 0; +} + static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old) { /* From patchwork Thu Apr 11 20:25:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parker Newman X-Patchwork-Id: 788951 Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D57D17C6D; Thu, 11 Apr 2024 20:26:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.208.4.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712867165; cv=none; b=H51favclpXV0QrYcyZ47tuRydkZEP8DHdlPF9+kbE4IpVIMNFS0XkA9mfpS9mJN9PLLYLNK72DKFJLsvQeEEne6ifknyYfx2oU7gcrB4tub95YFlR2FWVf8Q0kVxFCUOw/Boiiyhq+3ANZSjJUtnE7+OZXLrpABQTeCKeQUrJH8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712867165; c=relaxed/simple; bh=TkhjnlvjFGVhpEGIBO9ktab1bjtXa/Gww45F0qnwaGw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IYPNgHeNSp+knz318rJ6z2e/qvi4sGbmM21n+jSIyFI2Jg0hYNhZDBFVyjX0UdddXfUtQgaIcJtKJh/zHRulGtRLrXLjM0YwAjXZEnFVVMyb1ZQljMTg76SGk5hHJ+vU+3XBKr4ft6NJTRhdkw+zkeCiJc/vy4FUo4uw+5pBpDI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=finest.io; spf=pass smtp.mailfrom=finest.io; dkim=pass (2048-bit key) header.d=finest.io header.i=parker@finest.io header.b=SwLrta9o; arc=none smtp.client-ip=74.208.4.196 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=finest.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=finest.io Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=finest.io header.i=parker@finest.io header.b="SwLrta9o" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=finest.io; s=s1-ionos; t=1712867158; x=1713471958; i=parker@finest.io; bh=iyYbMwbsoalW7f0BZDynP1kALXT2YHy5NY0+s2Dr6Fs=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:Message-ID:In-Reply-To: References:MIME-Version:Content-Transfer-Encoding:cc: content-transfer-encoding:content-type:date:from:message-id: mime-version:reply-to:subject:to; b=SwLrta9oqLc9LjSfpwh6cf9yGX5e6RutuK+e7NSaECXA1tR8nidYQ4eDR2JU2ywI 1+iAixV9+bo2dipTkSsGtG9e6uom7qPLU+t06XWr30yAAkJXucoaGIj1HbETbxDoj C8zQP0gpfgU6ywkitJEcSZ4FzlaWQ8eVBdilo4ZxH86cNNsdMc8CHvaDA8+FAAFw+ uz0cD+NxYY23FeCjuvnfQoCb9H14PSEkWqu6ePqjZHrk1wHFgSlhow0Ikj5Dfdi4i AWaq8dDKZX5BxhoirIm48XnIN7HyPhT12kLIuZZWaQ5whptM2UYhY2sxYZVLfaID3 Dw/xDWihgdz/36wndw== X-UI-Sender-Class: 55c96926-9e95-11ee-ae09-1f7a4046a0f6 Received: from finest.io ([98.159.241.229]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPSA (Nemesis) id 0MStu7-1sMkSZ0m6n-00HffZ; Thu, 11 Apr 2024 22:25:58 +0200 From: parker@finest.io To: Greg Kroah-Hartman , Jiri Slaby , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Parker Newman Subject: [PATCH v2 4/7] serial: exar: add optional board_setup function Date: Thu, 11 Apr 2024 16:25:42 -0400 Message-ID: <69677365f4c753cbe6b5c028f530db49e6712ab3.1712863999.git.pnewman@connecttech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Provags-ID: V03:K1:cGlYfgxUzp/dk+YlF7OoGo/8PXhPAY+qB3wIDrtCULnQKHcJ2Ey zVfZISSB7kE3OunQRk0o4w0I72C90WOpchanDUIj7YBMukIsHjt7dkYLoT1vmaMUTgm+YEb EgkjbDWk7a2WXhduxd0BTq43qseMJBtCb5E9rDq4o4+PEV+GrEFQFD1a6/rCdOgmAqythds d30hTd+raE42y2dWhNH8Q== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:CeSaNtNqE98=;cEBVWnOpTBRRd8aBZe4JWF9WmQo MgA8fU/bkfIwDJrj/+mpW3WHwRY4KvnU7TiAga5ss1MWVK5k84tHNwy1jAg1wOJ+bp8FMnMHZ RRvaGQFMJNxTvMXl1L7OPHJvaQ48bElfzv/a0NWMHBKLVZ6vF23SUsb5zICFo8IItCSWVX7OB 8mx5MQ6hNEkWSRA6qu9J0N6Hc6wl5YRn6Kgk+bJEgW6XZsihJa6RnPBpyey1mHMx1KCCyzoNc dQhQ4NfDQ5b2Vsx1JYzkXit+Dze7sJ5juec1Qx1m3fcClNrx+AtEvisbKKCQxD1ezeZhq27Da 62Qh2XfAgVJyzltkuirKcKBsDeVp3VDA2y1oum+ha2EdbaUl9UnodGR75KOCL0XIRXqcRtO0p BamuNZ0LF5yFXHBuiVWMRF7AvR2JsHvQuAwWfwiBomzaC/mDWRDoMJdPJIavitbHboiulJ1on 0+qO7NFvX3w2OWjubwpBYiGcRxcWoShjxh3R1T9BZPWstTLYEG+zXJgsrVqkwu5rg9VoyBm5v 8VJEE9gKsQ9LkrtpQgaQezUjh7ZvCxYNeqzjruX8SWdno+rPfIkMFACscyHw86J2PWgTlCeaB ZNYXR6NQa60Fg1eKiRcg3ByypxaEThPWF+M09TBX5ZzYSKHXgBwymhPcnjbuoSttF4LcBOcYi 5GA031wGNJ9hrqry0AUI4xM/OAbd2lmsyp//6zsQ/drzfusPUB4m8lXc1CYQdu85hQPwOZpYg GXlZTZrDyJ1iBHR2Xr0oXXNjyeGHf1S9G2jYGa3GUEk9GR6KbS0QdY= From: Parker Newman Adds an optional "board_setup" function pointer to struct exar8250_board. This gets called once during probe prior to setting up the ports. Signed-off-by: Parker Newman --- drivers/tty/serial/8250/8250_exar.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) -- 2.43.2 diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/8250_exar.c index 9915a99cb7c6..b30f3855652a 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -143,7 +143,7 @@ * * MPIO Port Function * ---- ---- -------- - * 0 2 Mode bit 0 + * 0 2 Mode bit 0 * 1 2 Mode bit 1 * 2 2 Terminate bus * 3 - @@ -179,22 +179,24 @@ struct exar8250_platform { int (*rs485_config)(struct uart_port *port, struct ktermios *termios, struct serial_rs485 *rs485); const struct serial_rs485 *rs485_supported; - int (*register_gpio)(struct pci_dev *, struct uart_8250_port *); - void (*unregister_gpio)(struct uart_8250_port *); + int (*register_gpio)(struct pci_dev *pcidev, struct uart_8250_port *port); + void (*unregister_gpio)(struct uart_8250_port *port); }; /** * struct exar8250_board - board information * @num_ports: number of serial ports * @reg_shift: describes UART register mapping in PCI memory - * @setup: quirk run at ->probe() stage + * @board_setup: quirk run once at ->probe() stage before setting up ports + * @setup: quirk run at ->probe() stage for each port * @exit: quirk run at ->remove() stage */ struct exar8250_board { unsigned int num_ports; unsigned int reg_shift; - int (*setup)(struct exar8250 *, struct pci_dev *, - struct uart_8250_port *, int); + int (*board_setup)(struct exar8250 *priv); + int (*setup)(struct exar8250 *priv, struct pci_dev *pcidev, + struct uart_8250_port *port, int idx); void (*exit)(struct pci_dev *pcidev); }; @@ -966,6 +968,15 @@ exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent) if (rc) return rc; + if (board->board_setup) { + rc = board->board_setup(priv); + if (rc) { + pci_err(pcidev, + "failed to setup serial board: %d\n", rc); + return rc; + } + } + for (i = 0; i < nr_ports && i < maxnr; i++) { rc = board->setup(priv, pcidev, &uart, i); if (rc) { From patchwork Thu Apr 11 20:25:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parker Newman X-Patchwork-Id: 788948 Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8664524A03; Thu, 11 Apr 2024 20:26:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.208.4.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712867168; cv=none; b=LiRUISjsZF6vJ1uxpFz1P3zDnzXHJbJ7Jo/dGN2TIr4AR0aOtkNrUAzXL9n6Z/FTGocIVBRr0K0jj7vtYUnmvcwwG3xcag+cazPyC2muZMyhQU1aJJQ4peZRPgZ/wS79Z07rJXuXGTsqUVEpB6EJVMR2W4KovHXLK5QK4Ql1C9U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712867168; c=relaxed/simple; bh=D2glbP7cm0TmfFFPGqKUcqu4qF4AR8nZgHoZ7dH9Yj0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZwOfhWcPYuOn/2cVs5ZNhCSyOM+iXu7mQfj3RYKfh4AR+OBxJHLjGa85I4PpYX3Qj8SSAEEYjQDujPJ6BxlfsdG8qdxd8iPsQEoxKixWpovpffLZEMP1RC0nTj9nQ/fAAO7zOibzborNvQqTRHISJhXf85HkCJK4LOcgpXN795Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=finest.io; spf=pass smtp.mailfrom=finest.io; dkim=pass (2048-bit key) header.d=finest.io header.i=parker@finest.io header.b=dTfP+P6H; arc=none smtp.client-ip=74.208.4.196 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=finest.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=finest.io Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=finest.io header.i=parker@finest.io header.b="dTfP+P6H" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=finest.io; s=s1-ionos; t=1712867158; x=1713471958; i=parker@finest.io; bh=zGQMmuknO7H4DJSGj8qu3qo3rQdck9vuC74qN0BKFcU=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:Message-ID:In-Reply-To: References:MIME-Version:Content-Transfer-Encoding:cc: content-transfer-encoding:content-type:date:from:message-id: mime-version:reply-to:subject:to; b=dTfP+P6HSU78bTJCP4BFePeVHMdDRJ1EoXqBt67U/dtZfOvn00zdtw7Boiv5sjyf UGbrOg8Y+g2J4B2RHLZvtFHfyX++ctDOtPq2+q86lFq2YVBj9+lNFff35Z/YzRn4r 3w/BP7Tu4IZ9jKCRXim1VGXU1a7gqEkUvIZQDBkKF6dvRaJTcKd5IeWhdRo17MZFn oeFZeeIuzHr52QHa0IuMW3MbNESXBwsIpSbipNidjOcvQYdXaKIMe9F8tVj7VInO7 seq1TNtpfMZGv5DRcctoixHBYX58XsrfwjCldBQlZ4NBi40DAWO4v7NbOWD7OJmT+ o8q9olcBrAp0b0md7g== X-UI-Sender-Class: 55c96926-9e95-11ee-ae09-1f7a4046a0f6 Received: from finest.io ([98.159.241.229]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPSA (Nemesis) id 0M4oTz-1sgfzn22iz-016Swv; Thu, 11 Apr 2024 22:25:58 +0200 From: parker@finest.io To: Greg Kroah-Hartman , Jiri Slaby , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Parker Newman Subject: [PATCH v2 5/7] serial: exar: add some CTI helper functions Date: Thu, 11 Apr 2024 16:25:43 -0400 Message-ID: X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Provags-ID: V03:K1:G8KyqjAnDXTvX433vE0YOEvvWG9V3POi5snH3U7eXwdL4rS5k58 AGHssuToSCSdvBkU5/Iat6i7Oue8+KDS5iQpxvT07rcr/Xtznt9V0O+AJmXymVWZtdkseeI d4ghQppfCam/ylkZ1yHuCNonDvmFfJo+XfI+y0X3sIV3KlCoOJsrdCgMsE266zz4m5LCgEF eJtvY4G2MBgyv9H2ZH2hw== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:yQRd95HKEdQ=;uBBGFxvJX/vFGu7XBrBjxDdVOCM +96aFLBOKeh8YFeow/t2iebzML158DYHQpjbDZ4YdZaevM9JzZBj483XexIpx7duTQXGUrigC M/azsSDhP2zIOr36cSY0C4Gefwxd/CaJUxaeSVOhCj0JAmVGrAQFnsPYkygcHEhfzAZmucFJY jFUt8JNIO7TefplGuTS2a67kcXSu2eC3O47VpxxvFj9AQWG4WQ2//M9FU7RVJ2HcjjuOYgM8l ft/qeYdukE7Gu48LUS3dwT55OfZuEcBYvY14efzq4aewjRLzDQqIxkY0TitKSAYSGKNjt6eGI 80KGfOSoz6RtFmT0oTW8VNsaLPMDiHbAmwcvqZRafTvAd5Ecp7y5ohWYAKXS+safEkzYqRm8H naHowAa548CT1ApNm0Mz9sYCzdKz0Qk+pIM1IM0SPwrDVRY4AyNGd8+9ZgXAkKhoe2SheY+s5 WAtRW5XZGJmi889ZwGdoKeEdSccKtoLWn3mRWc9rlBjYJGNXgoihv8lBJoaTn4rI/LT5NbXsn vA2UfiZ4K1Y5bxsnrZZod1Xncw1adZTAwCumSVGW6N4FzRtxpFAJfnW07BOcfh8ILHy1RM0Qq zs0ZidIBf1uUx/f3Ic0MO523jVVRuWT3M8YJT3p5V9umVNbF4PnlgfVDCNZ5tiQMPYvMU45Yb ye88QcBoYq4P4ldP3YZubIPrOg91jHA63vSWZeQUYn4SUE5C1XLaFh9Ka51goLZtCIYoh60gr U39MPXQhTVmVojIKuiTqjEr9UOeUIztsh6lmSdztGRrNDHCMWbXoR4= From: Parker Newman - Adds various helper functions for CTI boards. - Add osc_freq and pcidev to struct exar8250 - Added a exar_get_nr_ports function Signed-off-by: Parker Newman --- drivers/tty/serial/8250/8250_exar.c | 363 +++++++++++++++++++++++++++- 1 file changed, 357 insertions(+), 6 deletions(-) -- 2.43.2 diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/8250_exar.c index b30f3855652a..6f3697e34722 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -137,6 +137,9 @@ #define UART_EXAR_REGB_EE_ADDR_SIZE 6 #define UART_EXAR_REGB_EE_DATA_SIZE 16 +#define UART_EXAR_XR17C15X_PORT_OFFSET 0x200 +#define UART_EXAR_XR17V25X_PORT_OFFSET 0x200 +#define UART_EXAR_XR17V35X_PORT_OFFSET 0x400 /* * IOT2040 MPIO wiring semantics: @@ -173,6 +176,46 @@ #define IOT2040_UARTS_ENABLE 0x03 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */ +/* CTI EEPROM offsets */ +#define CTI_EE_OFF_XR17C15X_OSC_FREQ 0x04 /* 2 words (4 bytes) */ +#define CTI_EE_OFF_XR17V25X_OSC_FREQ 0x08 /* 2 words (4 bytes) */ +#define CTI_EE_OFF_XR17C15X_PART_NUM 0x0A /* 4 words (8 bytes) */ +#define CTI_EE_OFF_XR17V25X_PART_NUM 0x0E /* 4 words (8 bytes) */ +#define CTI_EE_OFF_XR17C15X_SERIAL_NUM 0x0E /* 1 word (2 bytes) */ +#define CTI_EE_OFF_XR17V25X_SERIAL_NUM 0x12 /* 1 word (2 bytes) */ +#define CTI_EE_OFF_XR17V35X_SERIAL_NUM 0x11 /* 2 word (4 bytes) */ +#define CTI_EE_OFF_XR17V35X_BOARD_FLAGS 0x13 /* 1 word (2 bytes) */ +#define CTI_EE_OFF_XR17V35X_PORT_FLAGS 0x14 /* 1 word (per port) */ + +#define CTI_FPGA_RS485_IO_REG 0x2008 + +#define CTI_DEFAULT_PCI_OSC_FREQ 29491200 +#define CTI_DEFAULT_PCIE_OSC_FREQ 125000000 +#define CTI_DEFAULT_FPGA_OSC_FREQ 33333333 + +/* + * CTI Serial port line types. These match the values stored in the first + * nibble of the CTI EEPROM port_flags word. + */ +enum cti_port_type { + CTI_PORT_TYPE_NONE = 0, + CTI_PORT_TYPE_RS232, //RS232 ONLY + CTI_PORT_TYPE_RS422_485, //RS422/RS485 ONLY + CTI_PORT_TYPE_RS232_422_485_HW, //RS232/422/485 HW ONLY Switchable + CTI_PORT_TYPE_RS232_422_485_SW, //RS232/422/485 SW ONLY Switchable + CTI_PORT_TYPE_RS232_422_485_4B, //RS232/422/485 HW/SW (4bit ex. BCG004) + CTI_PORT_TYPE_RS232_422_485_2B, //RS232/422/485 HW/SW (2bit ex. BBG008) + CTI_PORT_TYPE_MAX, +}; + +#define CTI_PORT_TYPE_VALID(_port_type) \ + (((_port_type) > CTI_PORT_TYPE_NONE) && \ + ((_port_type) < CTI_PORT_TYPE_MAX)) + +#define CTI_PORT_TYPE_RS485(_port_type) \ + (((_port_type) > CTI_PORT_TYPE_RS232) && \ + ((_port_type) < CTI_PORT_TYPE_MAX)) + struct exar8250; struct exar8250_platform { @@ -202,6 +245,8 @@ struct exar8250_board { struct exar8250 { unsigned int nr; + unsigned int osc_freq; + struct pci_dev *pcidev; struct exar8250_board *board; void __iomem *virt; int line[]; @@ -557,6 +602,279 @@ pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev, return 0; } +/** + * cti_set_tristate() - Enable/Disable RS485 transciever tristate + * @priv: Device's private structure + * @port_num: Port number to set tristate on/off + * @enable: Enable tristate if true, disable if false + * + * Most RS485 capable cards have a power on tristate jumper/switch that ensures + * the RS422/RS485 transciever does not drive a multi-drop RS485 bus when it is + * not the master. When this jumper is installed the user must set the RS485 + * mode to disable tristate prior to using the port. + * + * Some Exar UARTs have an auto-tristate feature while others require setting + * an MPIO to disable the tristate. + * + * Return: 0 on success, negative error code on failure + */ +static int cti_set_tristate(struct exar8250 *priv, + unsigned int port_num, bool enable) +{ + int ret = 0; + + if (!priv || (port_num >= priv->nr)) + return -EINVAL; + + //Only Exar based cards use MPIO, return 0 otherwise + if (priv->pcidev->vendor != PCI_VENDOR_ID_EXAR) + return 0; + + pci_dbg(priv->pcidev, "%s tristate for port %u\n", + (enable ? "enabling" : "disabling"), port_num); + + ret = exar_mpio_set(priv, port_num, !enable); + if (ret) + return ret; + + //ensure MPIO is an output + ret = exar_mpio_config(priv, port_num, true); + + return ret; +} + +/** + * cti_set_plx_int_enable() - Enable/Disable PCI interrupts + * @priv: Device's private structure + * @enable: Enable interrupts if true, disable if false + * + * Some older CTI cards require MPIO_0 to be set low to enable the PCI + * interupts from the UART to the PLX PCI->PCIe bridge. + * + * Return: 0 on success, negative error code on failure + */ +static int cti_set_plx_int_enable(struct exar8250 *priv, bool enable) +{ + int ret = 0; + + if (!priv) + return -EINVAL; + + //Only Exar based cards use MPIO, return 0 otherwise + if (priv->pcidev->vendor != PCI_VENDOR_ID_EXAR) + return 0; + + pci_dbg(priv->pcidev, "%s plx fix\n", + (enable ? "enabling" : "disabling")); + + //INT enabled when MPIO0 is LOW + ret = exar_mpio_set(priv, 0, !enable); + if (ret) + return ret; + + //ensure MPIO is an output + ret = exar_mpio_config(priv, 0, true); + + return ret; +} + +/** + * cti_read_osc_freq() - Read the UART oscillator frequency from EEPROM + * @priv: Device's private structure + * + * CTI XR17x15X and XR17V25X cards have the serial boards oscillator frequency + * stored in the EEPROM. FPGA and XR17V35X based cards use the PCI/PCIe clock. + * + * Return: frequency on success, negative error code on failure + */ +static int cti_read_osc_freq(struct exar8250 *priv, uint8_t eeprom_offset) +{ + int osc_freq; + + if (!priv) + return -EINVAL; + + osc_freq = (exar_ee_read(priv, eeprom_offset)); + osc_freq |= (exar_ee_read(priv, (eeprom_offset + 1)) << 16); + + //check if EEPROM word was blank + if ((osc_freq == 0xFFFF) || (osc_freq == 0x0000)) + return -EIO; + + pci_dbg(priv->pcidev, "osc_freq from EEPROM %d\n", osc_freq); + + return osc_freq; +} + +/** + * cti_get_port_type_xr17c15x_xr17v25x() - Get the port type of a xr17c15x + * or xr17v25x card + * + * @priv: Device's private structure + * @port_num: Port to get type of + * + * CTI xr17c15x and xr17v25x based cards port types are based on PCI IDs + * + * Return: port type on success, CTI_PORT_TYPE_NONE on failure + */ +static enum cti_port_type cti_get_port_type_xr17c15x_xr17v25x(struct exar8250 *priv, + unsigned int port_num) +{ + enum cti_port_type port_type; + + if (!priv) + return CTI_PORT_TYPE_NONE; + + switch (priv->pcidev->subsystem_device) { + //RS232 only cards + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232_NS: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232_NS: + port_type = CTI_PORT_TYPE_RS232; + break; + //1x RS232, 1x RS422/RS485 + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1: + port_type = (port_num == 0) ? + CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485; + break; + //2x RS232, 2x RS422/RS485 + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2: + port_type = (port_num < 2) ? + CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485; + break; + //4x RS232, 4x RS422/RS485 + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP: + port_type = (port_num < 4) ? + CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485; + break; + //RS232/RS422/RS485 HW (jumper) selectable + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_SP_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_B: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP: + port_type = CTI_PORT_TYPE_RS232_422_485_HW; + break; + //RS422/RS485 HW (jumper) selectable + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485: + port_type = CTI_PORT_TYPE_RS422_485; + break; + //6x RS232, 2x RS422/RS485 + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP: + port_type = (port_num < 6) ? + CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485; + break; + //2x RS232, 6x RS422/RS485 + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP: + port_type = (port_num < 2) ? + CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485; + break; + default: + pci_err(priv->pcidev, "unknown/unsupported device\n"); + port_type = CTI_PORT_TYPE_NONE; + } + + return port_type; +} + +/** + * cti_get_port_type_fpga() - Get the port type of a CTI FPGA card + * @priv: Device's private structure + * @port_num: Port to get type of + * + * FPGA based cards port types are based on PCI IDs + * + * Return: port type on success, CTI_PORT_TYPE_NONE on failure + */ +static enum cti_port_type cti_get_port_type_fpga(struct exar8250 *priv, + unsigned int port_num) +{ + enum cti_port_type port_type; + + if (!priv) + return CTI_PORT_TYPE_NONE; + + switch (priv->pcidev->device) { + case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG00X: + case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG01X: + case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_16: + port_type = CTI_PORT_TYPE_RS232_422_485_HW; + break; + default: + pci_err(priv->pcidev, "unknown/unsupported device\n"); + return CTI_PORT_TYPE_NONE; + } + + return port_type; +} + +/** + * cti_get_port_type_xr17v35x() - Read port type from the EEPROM + * @priv: Device's private structure + * @port_num: port offset + * + * CTI XR17V35X based cards have the port types stored in the EEPROM. + * This function reads the port type for a single port. + * + * Return: port type on success, CTI_PORT_TYPE_NONE on failure + */ +static enum cti_port_type cti_get_port_type_xr17v35x(struct exar8250 *priv, + unsigned int port_num) +{ + uint16_t port_flags; + uint8_t offset; + enum cti_port_type port_type; + + if (!priv) + return CTI_PORT_TYPE_NONE; + + offset = CTI_EE_OFF_XR17V35X_PORT_FLAGS + port_num; + port_flags = exar_ee_read(priv, offset); + + port_type = (port_flags & 0x00FF); + + if (!CTI_PORT_TYPE_VALID(port_type)) { + /* + * If the port type is missing the card assume it is a + * RS232/RS422/RS485 card to be safe. + * + * There is one known board (BEG013) that only has + * 3 of 4 port types written to the EEPROM so this + * acts as a work around. + */ + pci_warn(priv->pcidev, + "failed to get port %d type from EEPROM\n", port_num); + port_type = CTI_PORT_TYPE_RS232_422_485_HW; + } + + return port_type; +} + static int pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev, struct uart_8250_port *port, int idx) @@ -914,6 +1232,39 @@ static irqreturn_t exar_misc_handler(int irq, void *data) return IRQ_HANDLED; } +static unsigned int exar_get_nr_ports(struct exar8250_board *board, + struct pci_dev *pcidev) +{ + unsigned int nr_ports = 0; + + if (!board || !pcidev) + return 0; + + if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO) { + nr_ports = BIT(((pcidev->device & 0x38) >> 3) - 1); + } else if (board->num_ports > 0) { + //Check if board struct overrides number of ports + nr_ports = board->num_ports; + } else if (pcidev->vendor == PCI_VENDOR_ID_EXAR) { + //Exar encodes # ports in last nibble of PCI Device ID ex. 0358 + nr_ports = pcidev->device & 0x0f; + } else if (pcidev->vendor == PCI_VENDOR_ID_CONNECT_TECH) { + //Handle CTI FPGA cards + switch (pcidev->device) { + case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG00X: + case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG01X: + nr_ports = 12; + break; + case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_16: + nr_ports = 16; + default: + break; + } + } + + return nr_ports; +} + static int exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent) { @@ -933,18 +1284,18 @@ exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent) maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3); - if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO) - nr_ports = BIT(((pcidev->device & 0x38) >> 3) - 1); - else if (board->num_ports) - nr_ports = board->num_ports; - else - nr_ports = pcidev->device & 0x0f; + nr_ports = exar_get_nr_ports(board, pcidev); + if (nr_ports == 0) { + pci_err(pcidev, "failed to get number of ports\n"); + return -ENODEV; + } priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL); if (!priv) return -ENOMEM; priv->board = board; + priv->pcidev = pcidev; priv->virt = pcim_iomap(pcidev, bar, 0); if (!priv->virt) return -ENOMEM; From patchwork Thu Apr 11 20:25:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parker Newman X-Patchwork-Id: 788207 Received: from mout.perfora.net (mout.perfora.net [74.208.4.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 612E421105; Thu, 11 Apr 2024 20:26:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.208.4.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712867168; cv=none; b=Tq8dcIN8PK8QH9Mu3j7PlvUnwSeQdC+Zjw1YRW8gNFpk6nZrXX37zfcPDfoZdQj7n/j3WNua75nKbEJ+HvISb4kYL+e/ZY7VPCQj0lvFAnRYT+48DJ+nWvzf2uVDvqtPJrlWVvKF7qZDl8tidDbzwmV++D7S6ggl2B/QUgoSy8A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712867168; c=relaxed/simple; bh=vMRkyS/nU3uMmQ0YX45/F5RdIM2oxYF6Fbc7JHqcG3w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HkNgnJ9AsXzEsFOgUIJhilrSQNISdjJ6TUmk+OGduKiqoSuKSjqDZDZrtT5bQNpxinUW3ypf7dm4IOd3Ai53fTgx9+dlnAGhDX1Q2KOCiLr0Wl0Kj+iH1P3wzIZRPhbQ/r48QZv00PnPq+NVCdib7AfN41uFzjpIlGdMtu4/wfs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=finest.io; spf=pass smtp.mailfrom=finest.io; dkim=pass (2048-bit key) header.d=finest.io header.i=parker@finest.io header.b=bULBQNhe; arc=none smtp.client-ip=74.208.4.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=finest.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=finest.io Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=finest.io header.i=parker@finest.io header.b="bULBQNhe" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=finest.io; s=s1-ionos; t=1712867159; x=1713471959; i=parker@finest.io; bh=pKbKQ5Mt2Wd95+QbmtpBW0rcpjwWKIHjnsw/dZ/hMZA=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To: References; b=bULBQNhe7FVJZGFDFn7vyr1FyNjRtpCHkce7CcBpFrhLBj3DEiQ2hVWcSiwQqbxj AcKL9w5ozFH1r0+cCUvqVc/crH+NVGw7ViVis0x+lb3K9LcVhX4MO99Jq9tFy71Gd cSQnaCovIwdkWvnW636F5iJB+YqBIcQe9Z7yVfQYO0Z8KtLI65VDihrEc6pXBtUV7 2flTSRkvl4fcAyTqUhGJYUa2ut057LtavXl51Y3hRFdAM7K3IYpZGz+PSlCnxBYvN LyYd6qKTe7IB5tHAI5aMY9KnvUAIRc9D0qwnQge3HuTXmUGmNQi7xp/2OqTtzyDc5 gdlfoXtB6fIXNWrjMQ== X-UI-Sender-Class: 55c96926-9e95-11ee-ae09-1f7a4046a0f6 Received: from finest.io ([98.159.241.229]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPSA (Nemesis) id 0MfWg9-1s6nDJ3NP9-00YmI7; Thu, 11 Apr 2024 22:25:58 +0200 From: parker@finest.io To: Greg Kroah-Hartman , Jiri Slaby , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Parker Newman Subject: [PATCH v2 6/7] serial: exar: add CTI board and port setup functions Date: Thu, 11 Apr 2024 16:25:44 -0400 Message-ID: X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Provags-ID: V03:K1:PuX4ZS5iXPbMFe9bDBhe2tElBc3yuus6SpjeF8+ywaH4HTsBdLK fPR+0DVLwsRtF26zRFpi44Fpu76SSLizqJacWBL9/LsFsFoGTk447jHwUmJ4uQ3xClEX3RW 2S9t4aOTF3Ooe94zEDFzwNkf/yDDRNqe9EakHz/T9D2o4q9J0a/jBWUMzq7OiTCvOpa4a6T 31K9IruQP1n1IVO0Hd6Bg== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:P1iin8ZiPWo=;BkVVieI7Dmbrb0IV/vWwDTCzDHJ gCD9HMMnReIti58n1UaB0nRPXczFzu5VY7wm6WULGOylhZkxj8Ev9NWVT0I+ePuwoouURIGIJ d3D/UHkYLX6DpN5fxZfY2dYss4cz2+yWJNomel9U2nztHktTYLsuKqAW2jiNneMabyWS0eCcC MJizDvqfstVer949HQt8+f8jvRuoXkFpIUV/OAmu82JSMZnpd8CZBlXCqid57rtn3qpWF9rok fPRwYCdwGyO9QOJrzBu1G8ukB3zLYpaQJ2/qVS6unS9UjoEyu8soih+WX4C28UA9DS0y2x97z T8IXoO75xK2gBSCQMax5d+ZjUx/WU13dqIbQiSDQrFhatE6hCxrAYtvRAcS5e2+Nu3YgTy68E X+KYPSN2ZVJxg3CBNyzLH4WYqOlAN8YlekfG/zJiyibjITsoqFIalH1UEgDAU3+IueuDmesFQ 5Gp2YiZlF9wlYFpUtyh0LGMXo8L9ODdqiPcOEFSEJRm76mG/qfI/z8zx4wWM08QQGY2I2CxU5 xtFq1T9znqCVHOLoZiIvW7xphX4MAT+C3x6NHfpKtT6RvrWqS3NBA12ZaVw3UEPkFJN+9Plig gZsxvJKhjItHkaT8klykN8uTbfVaM6kT0i93fNTpE63dX+HoO1KrK4UNakFcMzqypb59HmTef hiMgWqIH9KfmGhpBhU8gJu8H1ImF+quNLEXOORz2LGjCryKoZem1U0T3fiNOWqqwU7JK8dKiQ yiM1Ogu9f44/5s7Gbp/zC3vLGo0Sa0DXjxAya8lHkY6w5TCgY4RZbc= From: Parker Newman - Removed old port setup function and replaced with UART specific ones - Added board setup functions for CTI boards - Replaced CONNECT_DEVICE macro with CTI_EXAR_DEVICE and CTI_PCI_DEVICE - Moved "generic rs485" support up in the file Signed-off-by: Parker Newman --- drivers/tty/serial/8250/8250_exar.c | 454 ++++++++++++++++++++++++---- 1 file changed, 401 insertions(+), 53 deletions(-) -- 2.43.2 diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/8250_exar.c index 6f3697e34722..d8425113a9f1 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -440,6 +440,31 @@ static int exar_mpio_set(struct exar8250 *priv, return 0; } +static int generic_rs485_config(struct uart_port *port, struct ktermios *termios, + struct serial_rs485 *rs485) +{ + bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED); + u8 __iomem *p = port->membase; + u8 value; + + value = readb(p + UART_EXAR_FCTR); + if (is_rs485) + value |= UART_FCTR_EXAR_485; + else + value &= ~UART_FCTR_EXAR_485; + + writeb(value, p + UART_EXAR_FCTR); + + if (is_rs485) + writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR); + + return 0; +} + +static const struct serial_rs485 generic_rs485_supported = { + .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND, +}; + static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old) { /* @@ -875,15 +900,332 @@ static enum cti_port_type cti_get_port_type_xr17v35x(struct exar8250 *priv, return port_type; } -static int -pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev, - struct uart_8250_port *port, int idx) +static int cti_rs485_config_mpio_tristate(struct uart_port *port, + struct ktermios *termios, + struct serial_rs485 *rs485) { - unsigned int offset = idx * 0x200; - unsigned int baud = 1843200; + struct exar8250 *priv; + int ret; - port->port.uartclk = baud * 16; - return default_setup(priv, pcidev, idx, offset, port); + priv = (struct exar8250 *)port->private_data; + if (!priv) + return -EINVAL; + + ret = generic_rs485_config(port, termios, rs485); + if (ret) + return ret; + + //disable power-on tri-state via MPIO + return cti_set_tristate(priv, port->port_id, false); +} + +static int cti_port_setup_common(struct exar8250 *priv, + int idx, unsigned int offset, + struct uart_8250_port *port) +{ + int ret; + + if (!priv || !port) + return -EINVAL; + + if (priv->osc_freq == 0) + return -EINVAL; + + port->port.port_id = idx; + port->port.uartclk = priv->osc_freq; + + ret = serial8250_pci_setup_port(priv->pcidev, port, 0, offset, 0); + if (ret) { + pci_err(priv->pcidev, + "failed to setup pci for port %d err: %d\n", idx, ret); + return ret; + } + + port->port.private_data = (void *)priv; + port->port.pm = exar_pm; + port->port.shutdown = exar_shutdown; + + return 0; +} + +static int cti_port_setup_fpga(struct exar8250 *priv, + struct pci_dev *pcidev, + struct uart_8250_port *port, + int idx) +{ + enum cti_port_type port_type; + unsigned int offset; + + port_type = cti_get_port_type_fpga(priv, idx); + + //FPGA shares port offests with XR17C15X + offset = idx * UART_EXAR_XR17C15X_PORT_OFFSET; + port->port.type = PORT_XR17D15X; + + port->port.get_divisor = xr17v35x_get_divisor; + port->port.set_divisor = xr17v35x_set_divisor; + port->port.startup = xr17v35x_startup; + + if (CTI_PORT_TYPE_RS485(port_type)) { + port->port.rs485_config = generic_rs485_config; + port->port.rs485_supported = generic_rs485_supported; + } + + return cti_port_setup_common(priv, idx, offset, port); +} + +static int cti_port_setup_xr17v35x(struct exar8250 *priv, + struct pci_dev *pcidev, + struct uart_8250_port *port, + int idx) +{ + enum cti_port_type port_type; + unsigned int offset; + int ret; + + port_type = cti_get_port_type_xr17v35x(priv, idx); + + offset = idx * UART_EXAR_XR17V35X_PORT_OFFSET; + port->port.type = PORT_XR17V35X; + + port->port.get_divisor = xr17v35x_get_divisor; + port->port.set_divisor = xr17v35x_set_divisor; + port->port.startup = xr17v35x_startup; + + switch (port_type) { + case CTI_PORT_TYPE_RS422_485: + case CTI_PORT_TYPE_RS232_422_485_HW: + port->port.rs485_config = cti_rs485_config_mpio_tristate; + port->port.rs485_supported = generic_rs485_supported; + break; + case CTI_PORT_TYPE_RS232_422_485_SW: + case CTI_PORT_TYPE_RS232_422_485_4B: + case CTI_PORT_TYPE_RS232_422_485_2B: + port->port.rs485_config = generic_rs485_config; + port->port.rs485_supported = generic_rs485_supported; + break; + default: + break; + } + + ret = cti_port_setup_common(priv, idx, offset, port); + if (ret) + return ret; + + exar_write_reg(priv, (offset + UART_EXAR_8XMODE), 0x00); + exar_write_reg(priv, (offset + UART_EXAR_FCTR), UART_FCTR_EXAR_TRGD); + exar_write_reg(priv, (offset + UART_EXAR_TXTRG), 128); + exar_write_reg(priv, (offset + UART_EXAR_RXTRG), 128); + + return 0; +} + +static int cti_port_setup_xr17v25x(struct exar8250 *priv, + struct pci_dev *pcidev, + struct uart_8250_port *port, + int idx) +{ + enum cti_port_type port_type; + unsigned int offset; + int ret; + + port_type = cti_get_port_type_xr17c15x_xr17v25x(priv, idx); + + offset = idx * UART_EXAR_XR17V25X_PORT_OFFSET; + port->port.type = PORT_XR17D15X; + + //xr17v25x supports fractional baudrates + port->port.get_divisor = xr17v35x_get_divisor; + port->port.set_divisor = xr17v35x_set_divisor; + port->port.startup = xr17v35x_startup; + + if (CTI_PORT_TYPE_RS485(port_type)) { + switch (priv->pcidev->subsystem_device) { + //These cards support power on 485 tri-state via MPIO + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485: + port->port.rs485_config = cti_rs485_config_mpio_tristate; + break; + //Otherwise auto or no power on 485 tri-state support + default: + port->port.rs485_config = generic_rs485_config; + break; + } + + port->port.rs485_supported = generic_rs485_supported; + } + + ret = cti_port_setup_common(priv, idx, offset, port); + if (ret) + return ret; + + exar_write_reg(priv, (offset + UART_EXAR_8XMODE), 0x00); + exar_write_reg(priv, (offset + UART_EXAR_FCTR), UART_FCTR_EXAR_TRGD); + exar_write_reg(priv, (offset + UART_EXAR_TXTRG), 32); + exar_write_reg(priv, (offset + UART_EXAR_RXTRG), 32); + + return 0; +} + +static int cti_port_setup_xr17c15x(struct exar8250 *priv, + struct pci_dev *pcidev, + struct uart_8250_port *port, + int idx) +{ + enum cti_port_type port_type; + unsigned int offset; + + port_type = cti_get_port_type_xr17c15x_xr17v25x(priv, idx); + + offset = idx * UART_EXAR_XR17C15X_PORT_OFFSET; + port->port.type = PORT_XR17D15X; + + if (CTI_PORT_TYPE_RS485(port_type)) { + switch (priv->pcidev->subsystem_device) { + //These cards support power on 485 tri-state via MPIO + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485: + port->port.rs485_config = cti_rs485_config_mpio_tristate; + break; + //Otherwise auto or no power on 485 tri-state support + default: + port->port.rs485_config = generic_rs485_config; + break; + } + + port->port.rs485_supported = generic_rs485_supported; + } + + return cti_port_setup_common(priv, idx, offset, port); +} + +static int cti_board_setup_xr17v35x(struct exar8250 *priv) +{ + if (!priv) + return -EINVAL; + + //XR17V35X use the PCIe clock rather than crystal + priv->osc_freq = CTI_DEFAULT_PCIE_OSC_FREQ; + + return 0; +} + +static int cti_board_setup_xr17v25x(struct exar8250 *priv) +{ + int osc_freq; + + if (!priv) + return -EINVAL; + + osc_freq = cti_read_osc_freq(priv, CTI_EE_OFF_XR17V25X_OSC_FREQ); + if (osc_freq < 0) { + pci_warn(priv->pcidev, + "failed to read osc freq from EEPROM, using default\n"); + osc_freq = CTI_DEFAULT_PCI_OSC_FREQ; + } + + priv->osc_freq = osc_freq; + + /* enable interupts on cards that need the "PLX fix" */ + switch (priv->pcidev->subsystem_device) { + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B: + cti_set_plx_int_enable(priv, true); + break; + default: + break; + } + + return 0; +} + +static int cti_board_setup_xr17c15x(struct exar8250 *priv) +{ + int osc_freq; + + if (!priv) + return -EINVAL; + + osc_freq = cti_read_osc_freq(priv, CTI_EE_OFF_XR17C15X_OSC_FREQ); + if (osc_freq <= 0) { + pci_warn(priv->pcidev, + "failed to read osc freq from EEPROM, using default\n"); + osc_freq = CTI_DEFAULT_PCI_OSC_FREQ; + } + + priv->osc_freq = osc_freq; + + /* enable interrupts on cards that need the "PLX fix" */ + switch (priv->pcidev->subsystem_device) { + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B: + cti_set_plx_int_enable(priv, true); + break; + default: + break; + } + + return 0; +} + +static int cti_board_setup_fpga(struct exar8250 *priv) +{ + int ret; + uint16_t cfg_val; + + if (!priv) + return -EINVAL; + + //FPGA OSC is fixed to the 33MHz PCI clock + priv->osc_freq = CTI_DEFAULT_FPGA_OSC_FREQ; + + //Enable external interrupts in special cfg space register + ret = pci_read_config_word(priv->pcidev, 0x48, &cfg_val); + if (ret) + return ret; + + cfg_val |= BIT(15); + + ret = pci_write_config_word(priv->pcidev, 0x48, cfg_val); + if (ret) + return ret; + + //RS485 gate needs to be enabled; otherwise RTS/CTS will not work + exar_write_reg(priv, CTI_FPGA_RS485_IO_REG, 0x01); + + return 0; } static int @@ -985,27 +1327,6 @@ static void xr17v35x_unregister_gpio(struct uart_8250_port *port) port->port.private_data = NULL; } -static int generic_rs485_config(struct uart_port *port, struct ktermios *termios, - struct serial_rs485 *rs485) -{ - bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED); - u8 __iomem *p = port->membase; - u8 value; - - value = readb(p + UART_EXAR_FCTR); - if (is_rs485) - value |= UART_FCTR_EXAR_485; - else - value &= ~UART_FCTR_EXAR_485; - - writeb(value, p + UART_EXAR_FCTR); - - if (is_rs485) - writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR); - - return 0; -} - static int sealevel_rs485_config(struct uart_port *port, struct ktermios *termios, struct serial_rs485 *rs485) { @@ -1044,10 +1365,6 @@ static int sealevel_rs485_config(struct uart_port *port, struct ktermios *termio return 0; } -static const struct serial_rs485 generic_rs485_supported = { - .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND, -}; - static const struct exar8250_platform exar8250_default_platform = { .register_gpio = xr17v35x_register_gpio, .unregister_gpio = xr17v35x_unregister_gpio, @@ -1408,8 +1725,24 @@ static const struct exar8250_board pbn_fastcom335_8 = { .setup = pci_fastcom335_setup, }; -static const struct exar8250_board pbn_connect = { - .setup = pci_connect_tech_setup, +static const struct exar8250_board pbn_cti_xr17c15x = { + .board_setup = cti_board_setup_xr17c15x, + .setup = cti_port_setup_xr17c15x, +}; + +static const struct exar8250_board pbn_cti_xr17v25x = { + .board_setup = cti_board_setup_xr17v25x, + .setup = cti_port_setup_xr17v25x, +}; + +static const struct exar8250_board pbn_cti_xr17v35x = { + .board_setup = cti_board_setup_xr17v35x, + .setup = cti_port_setup_xr17v35x, +}; + +static const struct exar8250_board pbn_cti_fpga = { + .board_setup = cti_board_setup_fpga, + .setup = cti_port_setup_fpga, }; static const struct exar8250_board pbn_exar_ibm_saturn = { @@ -1456,15 +1789,27 @@ static const struct exar8250_board pbn_exar_XR17V8358 = { .exit = pci_xr17v35x_exit, }; -#define CONNECT_DEVICE(devid, sdevid, bd) { \ - PCI_DEVICE_SUB( \ - PCI_VENDOR_ID_EXAR, \ - PCI_DEVICE_ID_EXAR_##devid, \ - PCI_SUBVENDOR_ID_CONNECT_TECH, \ - PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \ - (kernel_ulong_t)&bd \ +//For Connect Tech cards with Exar vendor/device PCI IDs +#define CTI_EXAR_DEVICE(devid, bd) { \ + PCI_DEVICE_SUB( \ + PCI_VENDOR_ID_EXAR, \ + PCI_DEVICE_ID_EXAR_##devid, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_ANY_ID), 0, 0, \ + (kernel_ulong_t)&bd \ + } + +//For Connect Tech cards with Connect Tech vendor/device PCI IDs (FPGA based) +#define CTI_PCI_DEVICE(devid, bd) { \ + PCI_DEVICE_SUB( \ + PCI_VENDOR_ID_CONNECT_TECH, \ + PCI_DEVICE_ID_CONNECT_TECH_PCI_##devid, \ + PCI_ANY_ID, \ + PCI_ANY_ID), 0, 0, \ + (kernel_ulong_t)&bd \ } + #define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) } #define IBM_DEVICE(devid, sdevid, bd) { \ @@ -1494,18 +1839,21 @@ static const struct pci_device_id exar_pci_tbl[] = { EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x), EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x), - CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect), - CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect), - CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect), - CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect), - CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect), - CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect), - CONNECT_DEVICE(XR17C152, UART_2, pbn_connect), - CONNECT_DEVICE(XR17C154, UART_4, pbn_connect), - CONNECT_DEVICE(XR17C158, UART_8, pbn_connect), - CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect), - CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect), - CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect), + CTI_EXAR_DEVICE(XR17C152, pbn_cti_xr17c15x), + CTI_EXAR_DEVICE(XR17C154, pbn_cti_xr17c15x), + CTI_EXAR_DEVICE(XR17C158, pbn_cti_xr17c15x), + + CTI_EXAR_DEVICE(XR17V252, pbn_cti_xr17v25x), + CTI_EXAR_DEVICE(XR17V254, pbn_cti_xr17v25x), + CTI_EXAR_DEVICE(XR17V258, pbn_cti_xr17v25x), + + CTI_EXAR_DEVICE(XR17V352, pbn_cti_xr17v35x), + CTI_EXAR_DEVICE(XR17V354, pbn_cti_xr17v35x), + CTI_EXAR_DEVICE(XR17V358, pbn_cti_xr17v35x), + + CTI_PCI_DEVICE(XR79X_12_XIG00X, pbn_cti_fpga), + CTI_PCI_DEVICE(XR79X_12_XIG01X, pbn_cti_fpga), + CTI_PCI_DEVICE(XR79X_16, pbn_cti_fpga), IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn), From patchwork Thu Apr 11 20:25:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parker Newman X-Patchwork-Id: 788949 Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F30DA18030; Thu, 11 Apr 2024 20:26:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.208.4.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712867167; cv=none; b=T/HENZC5bmKA+GU055elSgMUypfbVmFVYc0pgpbfW8rK6C6MJHSPohsVbbq5UPTN3++uM72IJr6QqYQJL+ErX2qoRA6F8XkcEc2+6BwfEN/eKUX5gSmGNFAN46XgLq8FaWJ/ey9WSFx0p6ca9HXwvDHGw6N47e0K3J8xMdUMKqY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712867167; c=relaxed/simple; bh=OyiwdrslugF9xn2I0IrJDXL7cDDj3UpTmiAZkhP4QoQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=V9Eh0kDJPr5fewNFqic7Za3eGfoJbOyHL5S1AKfyEmerJH4B8CyK9LelIcZ7zCSXfEuZ2kVcjRkcAU8SZ23Rk+UrTfuxPs2vhY+vLpTX52fGFZ7SvoBiw5hvZaBOvxc+TkcnDcPZnnNGOmax60K6QLPHG0eCfvtPmmmJMzvOfEw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=finest.io; spf=pass smtp.mailfrom=finest.io; dkim=pass (2048-bit key) header.d=finest.io header.i=parker@finest.io header.b=ix8tw4bK; arc=none smtp.client-ip=74.208.4.196 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=finest.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=finest.io Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=finest.io header.i=parker@finest.io header.b="ix8tw4bK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=finest.io; s=s1-ionos; t=1712867159; x=1713471959; i=parker@finest.io; bh=vaELCzZnSbZPiv+n/DYJ9hiAKVejhtPPQdvjQgpLFGM=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:Message-ID:In-Reply-To: References:MIME-Version:Content-Transfer-Encoding:cc: content-transfer-encoding:content-type:date:from:message-id: mime-version:reply-to:subject:to; b=ix8tw4bKi/WKkO7/oGnNp19593x3C8aBKaf4+ueWgCm1jgBHZlc0Rx1cYDMx7zEO K0C+A3ydGzuhCpB4DoejnwLY6vzvfBiVXzLt7MTWq6uZfj2k8Xm7j4QTOXWUWx0WN zG2Mxy3A7gX0KI36QzSmHQFAK4essD6SERYwOAyHMZwT0PET1Srj7fvzwKFAgxnR2 pzTCZu4NPsAHpz1tsNLalG0q0UND6Ul/dOC3plgbn5Gc1T2cL5NE2VIlhIeGp5aoA f44XBiQJsF0NRQfOM2V2MlpsUurM/8kawdeXgSSSVzHvRBwwSu8VqBzPEwnM4xnC7 5mnzWar1BZqx8kMFtw== X-UI-Sender-Class: 55c96926-9e95-11ee-ae09-1f7a4046a0f6 Received: from finest.io ([98.159.241.229]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPSA (Nemesis) id 0MXriD-1sIuhc0Yzf-00Mdkl; Thu, 11 Apr 2024 22:25:59 +0200 From: parker@finest.io To: Greg Kroah-Hartman , Jiri Slaby , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Parker Newman Subject: [PATCH v2 7/7] serial: exar: fix: fix crash during shutdown if setup fails Date: Thu, 11 Apr 2024 16:25:45 -0400 Message-ID: <9af149b983592a7b8763132c64ca269909b4b8d3.1712863999.git.pnewman@connecttech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Provags-ID: V03:K1:s1qZqYeeCh/p55n0hx6/aal+F/Q4pAG+Wd3llXFjndMKaBsI6W7 Qhes136f0gHDTPSamEW9VgEwV9Vk5kGq06drYjuPtHmKimt3LZUTWWI7zQML2URCGJwZn86 07PD0QSb4ddP/TlJqqvQi//4ZMuXgfY5AujJSMzuX+JBv3zbNTtETBflaPr39v4FoxBfIyX tWJ9KBqy3yimxtK6dHmgQ== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:kyFkFkRSoq0=;eeDmdpPDU1OJ7YPEsz61CCfLQFe zwVOh3DvjJoO6wJkHveiEkrZg+D/CF/Df2JKSIeMZh3TOmADpzfSp+HpQxX2YqmIzL0/KUCM/ qewwFjewvrHNcVmDBrLL1kXKcb0WWkHNWoj5SN6foAFfN/WagtWS3743O/4u8XcAUsrCOQAjg Lhz5I9cIj6fPHi0i2Z/TICA9ifKDH4UHBM2Y+X2GsfkD4H4daY3346NAC6xkBqmeU4MtXnsXs 3LU/ORoCgBkgjVYnn5KaDbDToeN7j8UJ3D6QRJXRBIMyiH1WUvZWedTBTzLXARwyKCrPCYc/9 vIyT8XCPtyEKNc9qJqbx5Nw23WUbIE8RCaS2TC3dYH9h4o50O5JINfTiGro4Q0R3vb3bdA2nY 8d0BjrSWYaR1z0fn8vcAXHtDIkdPUGTEdZC/9zEuiOQ0z+o8qV67G4vf/bB53JwXtcWUC7Inq J+dZJ1fwmif0UJul3v1LkK8oTu1oFjYp91IbKfI/RIZQ7r6gihYeuH6wJ+n8y0FG3OZkUTARN 6mNaj8F6KO+YOVPyEPIlSU0Xuilwx5dznAcAEEuc0xwcxL8wUju3hwKS6AY7JDDq3/KOg2d8Y sObNF4plZQjOIV3lvLRaZ9bR3ZmjpUP1HOrCi4Axwiv25qtGxaVh9um7f+mc7iuZxfN04kaHo esJYhcpI4fVxDaTLIvJbvjsiJdQ/6xZjrEqP+14ckltGm8Huuq420VEoSs6B1xQgx6m0q4xSa hX6Mud+2fBLwxtVQkmJZDKbdm8IHXifHdwtYOcR9uz8rEfsu0QR6dU= From: Parker Newman If a port fails to register with serial8250_register_8250_port the kernel can crash when shutting down or module removal. This is because "priv->line[i]" will be set to a negative error code andin the exar_pci_remove function serial8250_unregister_port is called without checking if the "priv->line[i]" value is valid. Signed-off-by: Parker Newman --- drivers/tty/serial/8250/8250_exar.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.43.2 diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/8250_exar.c index d8425113a9f1..1c6343ed76e9 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -1675,7 +1675,8 @@ static void exar_pci_remove(struct pci_dev *pcidev) unsigned int i; for (i = 0; i < priv->nr; i++) - serial8250_unregister_port(priv->line[i]); + if (priv->line[i] >= 0) + serial8250_unregister_port(priv->line[i]); /* Ensure that every init quirk is properly torn down */ if (priv->board->exit)