From patchwork Wed Apr 10 07:21:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 787475 Delivered-To: patch@linaro.org Received: by 2002:adf:fdd2:0:b0:346:15ad:a2a with SMTP id i18csp566482wrs; Wed, 10 Apr 2024 00:24:10 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWgkOrync5DiyYqBBBrV9Y73vlh9vHD3Mj3TEM0E2OUNOroQxBV2BO1Oe5Y9Yrs3LEtdYdO0G4ekWzElRqCAy33 X-Google-Smtp-Source: AGHT+IHOcnhN1nRqnhTiA7/kX3mcKeij0eWgD7QFF2tySgLyeSMuFX3u1I7D1dRPIY3upz043ESG X-Received: by 2002:a05:620a:8ca:b0:78d:645c:bc37 with SMTP id z10-20020a05620a08ca00b0078d645cbc37mr1842479qkz.32.1712733850672; Wed, 10 Apr 2024 00:24:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712733850; cv=none; d=google.com; s=arc-20160816; b=n0jCNs2cdE6W5Q3sVSHGm0Hpactm4u1BrFCg8hli6V2MZ8RielWEW2RXO1dIWWnaoB +IicUMz1CUsEMBRvgxSwYK1rIKAyyBP8H/CYwIf7m7Mc1u24IWk4FPeEzfvrhdrLgsqb gOUDuw7P0QQC+IWp3LHLHvB2x56RINi6RRd81kRz64mRmP91KyWmrPs9DsGmg0+OvG7Q t942zNXgwcyBIEly26nIlb0qzRghqfeI6RIR9s8qg36gDS+v/vupDWe6KNyqAf6KpHZA qh5szd3T6oh2OwDnJK/MU+yhAVaEUCoVN6cwKjf7bDzrbf3+E2G2UYr9ufpWTHbFaNCz cCRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=bQiaPh82Puf5Cn+3gSpOd84zptlbwJz/VKNuzpfP8hg=; fh=K4abbxCgZAPvqzOXA+PZ7RIZh+KufMVJze7rXLOwES0=; b=O4T+CyMJw/ZOwpptIHimpi8dn5pNSM+MihsNbURQI9Yc04l6HVa5V+4BHeWxkxsSI4 uc5oWz1mRNB1StnAxPglbPUc+lkAKM1vB8TfNfy7BDu36gnjgmvejI2fF6BR5zBGHaEi JW7+gWaZ6dKqZVX/K444u4d606yV09wRKCGIBVNRB8AEisKp+X5RhWdz2UfLxoc5wEin O/Tk+WDHAsa62tOWxjQ4avAsJfBG1HuWs/Ce8eAoVgOECO5J/2pMrsISRzCWnZmNX6iq LQv+G1hqQr9mb2wP7XRY6GU36Br6AxOyNPwGb1RSqM7Li6hQ19P4b6hBkckycY29PM/V iC/w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id dt33-20020a05620a47a100b0078d5ce73e60si8439960qkb.498.2024.04.10.00.24.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 10 Apr 2024 00:24:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ruSIq-0007aR-1i; Wed, 10 Apr 2024 03:23:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruSIg-0007Qb-Uv; Wed, 10 Apr 2024 03:23:19 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruSIa-0003re-1l; Wed, 10 Apr 2024 03:23:17 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 8CFDE5D672; Wed, 10 Apr 2024 10:25:02 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 324C1B02B3; Wed, 10 Apr 2024 10:23:04 +0300 (MSK) Received: (nullmailer pid 4191653 invoked by uid 1000); Wed, 10 Apr 2024 07:23:03 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Michael Tokarev Subject: [Stable-8.2.3 03/87] tcg/aarch64: Apple does not align __int128_t in even registers Date: Wed, 10 Apr 2024 10:21:36 +0300 Message-Id: <20240410072303.4191455-3-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson >From https://developer.apple.com/documentation/xcode/writing-arm64-code-for-apple-platforms When passing an argument with 16-byte alignment in integer registers, Apple platforms allow the argument to start in an odd-numbered xN register. The standard ABI requires it to begin in an even-numbered xN register. Cc: qemu-stable@nongnu.org Fixes: 5427a9a7604 ("tcg: Add TCG_TARGET_CALL_{RET,ARG}_I128") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2169 Signed-off-by: Richard Henderson Message-Id: <9fc0c2c7-dd57-459e-aecb-528edb74b4a7@linaro.org> Reviewed-by: Philippe Mathieu-Daudé (cherry picked from commit 7f89fdf8ebe6ef8df48f0a05f44e1020c713a94e) Signed-off-by: Michael Tokarev diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 33f15a564a..d6da7ec0f6 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -55,7 +55,11 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL -#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN +#ifdef CONFIG_DARWIN +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#else +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN +#endif #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL #define have_lse (cpuinfo & CPUINFO_LSE) From patchwork Wed Apr 10 07:21:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 787476 Delivered-To: patch@linaro.org Received: by 2002:adf:fdd2:0:b0:346:15ad:a2a with SMTP id i18csp566946wrs; Wed, 10 Apr 2024 00:25:50 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVSKllJcOPgSUavM2tj7blhhHhfcSHGTGUczFOyKhwuZf+bgLO2O3F0U6An5Zvs2BeOrBP15XNJNo49HSGinDB4 X-Google-Smtp-Source: AGHT+IGFe/YZmBCZ2VLHUmFNr24yDNPF0tICJqpM69/JZMU6thWNpTwNmkPXXo51X/9BdGGh9kjC X-Received: by 2002:a05:6214:e61:b0:69b:14ed:f0db with SMTP id jz1-20020a0562140e6100b0069b14edf0dbmr1713168qvb.59.1712733950621; Wed, 10 Apr 2024 00:25:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712733950; cv=none; d=google.com; s=arc-20160816; b=IlTGg6jgQQMqTgMMsrODeTlbtsu5xfP8R349YyUzx3Uvx3L5yOgCicH8eAaaxzZ+0K 7QtfcLYEBU7HJ5NpACMQBSDMjt6WarjPG7kSrkBPxUdWE/Dw8VIaTxWc7hW5YlC4H9Gb nQ7IedF23mAYbKuNLHBHp0BePAvRqXDB9kEsbfblE5jihFX7+16kRL3XjRN89sx3M7dh X0rf70gyrdbef5FoM0Uel6KY41o/ZHzDMJujks1cCRYld3Qo4eTw9FXxUZt+QFw5i/Hi vfAKndDA0vqxqsSUNB44Gy90WKXEBp5fHiUvphXYLX89YqYGmF3foisAA5IoVWrAILs8 uNqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=0IBSA7d2yFuY5RiiVHA+FFeIIFjGvAg8+fl7SZXgyp4=; fh=pNPzA2klLwkTa9wB0TH4HdzIuaYqvoyobZ1rUSsbmbA=; b=rdy3zvWyXv4o3VMebSz3g1nQylP6k/kQtvBH3EEHZUxdvE0vlN40H0bICMXr+dvdR5 MmyXchmLVOluyzGIF9G6VWQvBabps5IBrsZs5UFAnuym746lM9BxvvWALcAFtvpiQrLg Keg4KsKfAynsTA7tu0ES4gV+eomzudBLCs0fidQWDQ/MuxfRLH8HFGm3Lla9j77vsmZt E0t6WaBG4kCIXDZrFRBfHJc9g1FNIT7A/6d3yKonYVxXbV8JA40TuIU+zOFCgbbrx4e9 XAl8DdN5+7s2NjThJ9J0Wq8cPYN0R/gmTvVWDR4l96cLb/2DgEH42YYiNl/P7gmFmnIv O00w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ct14-20020a056214178e00b0069b1efa1029si5014000qvb.167.2024.04.10.00.25.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 10 Apr 2024 00:25:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ruSIp-0007Zk-D8; Wed, 10 Apr 2024 03:23:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruSIh-0007R2-LL; Wed, 10 Apr 2024 03:23:20 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruSIe-0003s2-SS; Wed, 10 Apr 2024 03:23:19 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 9DFE85D673; Wed, 10 Apr 2024 10:25:02 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 41E1BB02B4; Wed, 10 Apr 2024 10:23:04 +0300 (MSK) Received: (nullmailer pid 4191656 invoked by uid 1000); Wed, 10 Apr 2024 07:23:04 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Richard Henderson , Alexey Sheplyakov , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Michael Tokarev Subject: [Stable-8.2.3 04/87] linux-user: Remove pgb_dynamic alignment assertion Date: Wed, 10 Apr 2024 10:21:37 +0300 Message-Id: <20240410072303.4191455-4-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson The assertion was never correct, because the alignment is a composite of the image alignment and SHMLBA. Even if the image alignment didn't match the image address, an assertion would not be correct -- more appropriate would be an error message about an ill formed image. But the image cannot be held to SHMLBA under any circumstances. Fixes: ee94743034b ("linux-user: completely re-write init_guest_space") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2157 Signed-off-by: Richard Henderson Reported-by: Alexey Sheplyakov Reviewed-by: Philippe Mathieu-Daudé (cherry picked from commit b816e1b5ba58a986b10cd830d6617f351979ab91) Signed-off-by: Michael Tokarev diff --git a/linux-user/elfload.c b/linux-user/elfload.c index cf9e74468b..7cc8d9685e 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -3016,8 +3016,6 @@ static void pgb_dynamic(const char *image_name, uintptr_t guest_loaddr, uintptr_t brk, ret; PGBAddrs ga; - assert(QEMU_IS_ALIGNED(guest_loaddr, align)); - /* Try the identity map first. */ if (pgb_addr_set(&ga, guest_loaddr, guest_hiaddr, true)) { brk = (uintptr_t)sbrk(0); From patchwork Wed Apr 10 07:21:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 787477 Delivered-To: patch@linaro.org Received: by 2002:adf:fdd2:0:b0:346:15ad:a2a with SMTP id i18csp567157wrs; Wed, 10 Apr 2024 00:26:34 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV5yQ78ZsW8mOCAGrAQxrs6yvmy6i1B/UOcOnhwrYmc6vwzo4A9+8pgIBRxFzNiMmiT1FQXFJU3T8n6kXceK5Ay X-Google-Smtp-Source: AGHT+IE0+HM8D4xxLjukAKsylIsWSOxrd1sUy7KZKvS+WIPv8OjZifTlzX5PnZjG+vj6KZb3wTYQ X-Received: by 2002:a37:e209:0:b0:78d:6377:33a6 with SMTP id g9-20020a37e209000000b0078d637733a6mr1979680qki.66.1712733993909; Wed, 10 Apr 2024 00:26:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712733993; cv=none; d=google.com; s=arc-20160816; b=qZy5RKrCo9EFtKNHP9ESUgJ7GiQRPZ9foELgxRfvdzcEFgHR6xfkVJLT0nBACvLmYB OV5jhftB2+XjMduMWlYN8Ixn1hvOGg5KbuCg+3hd/2s1s9Ne+K0liTE/APfL0GWEgo38 XPyZRSZ9SocPYrBxzAMSM0R9Jt2i5VY84yTnUZqu5oEUvKJfMFciIhDF8BEQPNnR6zsd bdT+8uWXifA9fgqQl3j7er0gez12YoLoMiTX5LJORmjDjdxzukgxuLFj307oRsA8J4MQ hIRs/K2l2MKLoxJzPM/fFg96CQrrz9/V1/wPhFoLV7H4OZLb5NLUEk5Psy9JD8SiH3cf cOiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=XZZtESjNtunFLVtA8+mgvoZdvSpzlXOdv36BlQ9obbc=; fh=TbI2pklXwlJGmj6m7lZZgI+jTnI/L5qcZuxsjME8SeI=; b=TjXqkJomLbt03ZLy1m+0Tusob+eXwO7YbXbXxdJhErPUlbXEViJn/JLIEMCqJNqU/R JfQlg/K2pFLIzS5cHbcHdbbhlyFRFJfct/sMaKSkzLnTte9M53T1aY/bcCKFrzoK2lCS +2Y72wA7kKiC8s0+TgLBnABSAVpAOTP21Wt0e45LIvq47YfTRM6fXJOThY3jhx0s4rsT ktCI9AVR11s+rnymd5IoH7TvlfCgBYTl9VHFCY3onCUVU/z6lKDjKzjwkSUj5zI+K+OL /RFD3UO13dJlWbSfioibJIZ52lOfGh7jEc63cblz+mz9FhBW85EMApDxj6QJubZAEeHN mgGw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id op5-20020a05620a534500b0078a45519e35si11458263qkn.329.2024.04.10.00.26.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 10 Apr 2024 00:26:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ruSIt-0007fG-1e; Wed, 10 Apr 2024 03:23:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruSIo-0007Ye-GT; Wed, 10 Apr 2024 03:23:26 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruSIl-0003uA-Jl; Wed, 10 Apr 2024 03:23:26 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id D00B55D676; Wed, 10 Apr 2024 10:25:02 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 72C36B02B7; Wed, 10 Apr 2024 10:23:04 +0300 (MSK) Received: (nullmailer pid 4191665 invoked by uid 1000); Wed, 10 Apr 2024 07:23:04 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Michael Tokarev Subject: [Stable-8.2.3 07/87] target/arm: Fix 32-bit SMOPA Date: Wed, 10 Apr 2024 10:21:40 +0300 Message-Id: <20240410072303.4191455-7-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson While the 8-bit input elements are sequential in the input vector, the 32-bit output elements are not sequential in the output matrix. Do not attempt to compute 2 32-bit outputs at the same time. Cc: qemu-stable@nongnu.org Fixes: 23a5e3859f5 ("target/arm: Implement SME integer outer product") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2083 Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240305163931.242795-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell (cherry picked from commit d572bcb222010b38b382871a23b2f38e2c3f4d2d) Signed-off-by: Michael Tokarev diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 904bfdac43..e2e0575039 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -1083,11 +1083,32 @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, } } -typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool); +typedef uint32_t IMOPFn32(uint32_t, uint32_t, uint32_t, uint8_t, bool); +static inline void do_imopa_s(uint32_t *za, uint32_t *zn, uint32_t *zm, + uint8_t *pn, uint8_t *pm, + uint32_t desc, IMOPFn32 *fn) +{ + intptr_t row, col, oprsz = simd_oprsz(desc) / 4; + bool neg = simd_data(desc); + + for (row = 0; row < oprsz; ++row) { + uint8_t pa = (pn[H1(row >> 1)] >> ((row & 1) * 4)) & 0xf; + uint32_t *za_row = &za[tile_vslice_index(row)]; + uint32_t n = zn[H4(row)]; -static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm, - uint8_t *pn, uint8_t *pm, - uint32_t desc, IMOPFn *fn) + for (col = 0; col < oprsz; ++col) { + uint8_t pb = pm[H1(col >> 1)] >> ((col & 1) * 4); + uint32_t *a = &za_row[H4(col)]; + + *a = fn(n, zm[H4(col)], *a, pa & pb, neg); + } + } +} + +typedef uint64_t IMOPFn64(uint64_t, uint64_t, uint64_t, uint8_t, bool); +static inline void do_imopa_d(uint64_t *za, uint64_t *zn, uint64_t *zm, + uint8_t *pn, uint8_t *pm, + uint32_t desc, IMOPFn64 *fn) { intptr_t row, col, oprsz = simd_oprsz(desc) / 8; bool neg = simd_data(desc); @@ -1107,25 +1128,16 @@ static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm, } #define DEF_IMOP_32(NAME, NTYPE, MTYPE) \ -static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \ +static uint32_t NAME(uint32_t n, uint32_t m, uint32_t a, uint8_t p, bool neg) \ { \ - uint32_t sum0 = 0, sum1 = 0; \ + uint32_t sum = 0; \ /* Apply P to N as a mask, making the inactive elements 0. */ \ n &= expand_pred_b(p); \ - sum0 += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \ - sum0 += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \ - sum0 += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \ - sum0 += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \ - sum1 += (NTYPE)(n >> 32) * (MTYPE)(m >> 32); \ - sum1 += (NTYPE)(n >> 40) * (MTYPE)(m >> 40); \ - sum1 += (NTYPE)(n >> 48) * (MTYPE)(m >> 48); \ - sum1 += (NTYPE)(n >> 56) * (MTYPE)(m >> 56); \ - if (neg) { \ - sum0 = (uint32_t)a - sum0, sum1 = (uint32_t)(a >> 32) - sum1; \ - } else { \ - sum0 = (uint32_t)a + sum0, sum1 = (uint32_t)(a >> 32) + sum1; \ - } \ - return ((uint64_t)sum1 << 32) | sum0; \ + sum += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \ + sum += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \ + sum += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \ + sum += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \ + return neg ? a - sum : a + sum; \ } #define DEF_IMOP_64(NAME, NTYPE, MTYPE) \ @@ -1151,16 +1163,17 @@ DEF_IMOP_64(umopa_d, uint16_t, uint16_t) DEF_IMOP_64(sumopa_d, int16_t, uint16_t) DEF_IMOP_64(usmopa_d, uint16_t, int16_t) -#define DEF_IMOPH(NAME) \ - void HELPER(sme_##NAME)(void *vza, void *vzn, void *vzm, void *vpn, \ - void *vpm, uint32_t desc) \ - { do_imopa(vza, vzn, vzm, vpn, vpm, desc, NAME); } - -DEF_IMOPH(smopa_s) -DEF_IMOPH(umopa_s) -DEF_IMOPH(sumopa_s) -DEF_IMOPH(usmopa_s) -DEF_IMOPH(smopa_d) -DEF_IMOPH(umopa_d) -DEF_IMOPH(sumopa_d) -DEF_IMOPH(usmopa_d) +#define DEF_IMOPH(NAME, S) \ + void HELPER(sme_##NAME##_##S)(void *vza, void *vzn, void *vzm, \ + void *vpn, void *vpm, uint32_t desc) \ + { do_imopa_##S(vza, vzn, vzm, vpn, vpm, desc, NAME##_##S); } + +DEF_IMOPH(smopa, s) +DEF_IMOPH(umopa, s) +DEF_IMOPH(sumopa, s) +DEF_IMOPH(usmopa, s) + +DEF_IMOPH(smopa, d) +DEF_IMOPH(umopa, d) +DEF_IMOPH(sumopa, d) +DEF_IMOPH(usmopa, d) diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index cded1d01fc..ea3e232e65 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -67,7 +67,7 @@ endif # SME Tests ifneq ($(CROSS_AS_HAS_ARMV9_SME),) -AARCH64_TESTS += sme-outprod1 +AARCH64_TESTS += sme-outprod1 sme-smopa-1 sme-smopa-2 endif # System Registers Tests diff --git a/tests/tcg/aarch64/sme-smopa-1.c b/tests/tcg/aarch64/sme-smopa-1.c new file mode 100644 index 0000000000..c62d5e0007 --- /dev/null +++ b/tests/tcg/aarch64/sme-smopa-1.c @@ -0,0 +1,47 @@ +#include +#include + +int main() +{ + static const int cmp[4][4] = { + { 110, 134, 158, 182 }, + { 390, 478, 566, 654 }, + { 670, 822, 974, 1126 }, + { 950, 1166, 1382, 1598 } + }; + int dst[4][4]; + int *tmp = &dst[0][0]; + + asm volatile( + ".arch armv8-r+sme\n\t" + "smstart\n\t" + "index z0.b, #0, #1\n\t" + "movprfx z1, z0\n\t" + "add z1.b, z1.b, #16\n\t" + "ptrue p0.b\n\t" + "smopa za0.s, p0/m, p0/m, z0.b, z1.b\n\t" + "ptrue p0.s, vl4\n\t" + "mov w12, #0\n\t" + "st1w { za0h.s[w12, #0] }, p0, [%0]\n\t" + "add %0, %0, #16\n\t" + "st1w { za0h.s[w12, #1] }, p0, [%0]\n\t" + "add %0, %0, #16\n\t" + "st1w { za0h.s[w12, #2] }, p0, [%0]\n\t" + "add %0, %0, #16\n\t" + "st1w { za0h.s[w12, #3] }, p0, [%0]\n\t" + "smstop" + : "+r"(tmp) : : "memory"); + + if (memcmp(cmp, dst, sizeof(dst)) == 0) { + return 0; + } + + /* See above for correct results. */ + for (int i = 0; i < 4; ++i) { + for (int j = 0; j < 4; ++j) { + printf("%6d", dst[i][j]); + } + printf("\n"); + } + return 1; +} diff --git a/tests/tcg/aarch64/sme-smopa-2.c b/tests/tcg/aarch64/sme-smopa-2.c new file mode 100644 index 0000000000..c9f48c3bfc --- /dev/null +++ b/tests/tcg/aarch64/sme-smopa-2.c @@ -0,0 +1,54 @@ +#include +#include + +int main() +{ + static const long cmp[4][4] = { + { 110, 134, 158, 182 }, + { 390, 478, 566, 654 }, + { 670, 822, 974, 1126 }, + { 950, 1166, 1382, 1598 } + }; + long dst[4][4]; + long *tmp = &dst[0][0]; + long svl; + + /* Validate that we have a wide enough vector for 4 elements. */ + asm(".arch armv8-r+sme-i64\n\trdsvl %0, #1" : "=r"(svl)); + if (svl < 32) { + return 0; + } + + asm volatile( + "smstart\n\t" + "index z0.h, #0, #1\n\t" + "movprfx z1, z0\n\t" + "add z1.h, z1.h, #16\n\t" + "ptrue p0.b\n\t" + "smopa za0.d, p0/m, p0/m, z0.h, z1.h\n\t" + "ptrue p0.d, vl4\n\t" + "mov w12, #0\n\t" + "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t" + "add %0, %0, #32\n\t" + "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t" + "mov w12, #2\n\t" + "add %0, %0, #32\n\t" + "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t" + "add %0, %0, #32\n\t" + "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t" + "smstop" + : "+r"(tmp) : : "memory"); + + if (memcmp(cmp, dst, sizeof(dst)) == 0) { + return 0; + } + + /* See above for correct results. */ + for (int i = 0; i < 4; ++i) { + for (int j = 0; j < 4; ++j) { + printf("%6ld", dst[i][j]); + } + printf("\n"); + } + return 1; +} From patchwork Wed Apr 10 07:21:41 2024 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id w8-20020ac857c8000000b004315e4f196asi12243535qta.664.2024.04.10.00.27.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 10 Apr 2024 00:27:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ruSIy-0007vU-EC; Wed, 10 Apr 2024 03:23:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruSIp-0007aM-E5; Wed, 10 Apr 2024 03:23:27 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruSIm-0003ub-RB; Wed, 10 Apr 2024 03:23:27 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id E66FE5D677; Wed, 10 Apr 2024 10:25:02 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 84D19B02B8; Wed, 10 Apr 2024 10:23:04 +0300 (MSK) Received: (nullmailer pid 4191668 invoked by uid 1000); Wed, 10 Apr 2024 07:23:04 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Peter Maydell , Paolo Bonzini , Artyom Tarasenko , Markus Armbruster , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= , =?utf-8?q?Daniel_P_=2E_B?= =?utf-8?q?errang=C3=A9?= , Michael Tokarev Subject: [Stable-8.2.3 08/87] hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later Date: Wed, 10 Apr 2024 10:21:41 +0300 Message-Id: <20240410072303.4191455-8-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell The sun4v RTC device model added under commit a0e893039cf2ce0 in 2016 was unfortunately added with a license of GPL-v3-or-later, which is not compatible with other QEMU code which has a GPL-v2-only license. Relicense the code in the .c and the .h file to GPL-v2-or-later, to make it compatible with the rest of QEMU. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Signed-off-by: Paolo Bonzini (for Red Hat) Signed-off-by: Artyom Tarasenko Signed-off-by: Markus Armbruster Signed-off-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Daniel P. Berrangé Acked-by: Alex Bennée Message-id: 20240223161300.938542-1-peter.maydell@linaro.org Signed-off-by: Peter Maydell (cherry picked from commit fd7f95f23d6fe485332c1d4b489eb719fcb7c225) Signed-off-by: Michael Tokarev diff --git a/hw/rtc/sun4v-rtc.c b/hw/rtc/sun4v-rtc.c index e037acd1b5..ffcc0aa25d 100644 --- a/hw/rtc/sun4v-rtc.c +++ b/hw/rtc/sun4v-rtc.c @@ -5,7 +5,7 @@ * * Copyright (c) 2016 Artyom Tarasenko * - * This code is licensed under the GNU GPL v3 or (at your option) any later + * This code is licensed under the GNU GPL v2 or (at your option) any later * version. */ diff --git a/include/hw/rtc/sun4v-rtc.h b/include/hw/rtc/sun4v-rtc.h index fc54dfcba4..26a9eb6196 100644 --- a/include/hw/rtc/sun4v-rtc.h +++ b/include/hw/rtc/sun4v-rtc.h @@ -5,7 +5,7 @@ * * Copyright (c) 2016 Artyom Tarasenko * - * This code is licensed under the GNU GPL v3 or (at your option) any later + * This code is licensed under the GNU GPL v2 or (at your option) any later * version. */ From patchwork Wed Apr 10 07:22:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 787482 Delivered-To: patch@linaro.org Received: by 2002:adf:fdd2:0:b0:346:15ad:a2a with SMTP id i18csp570186wrs; Wed, 10 Apr 2024 00:37:41 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX2k9M9VBW8K7mXn/iQZ7r5lkgHn0M8tYX8iHOab65uMP1p/T5tbgWu+lmcgJvYIrVQ37P5V4fae6GXibDZTjLZ X-Google-Smtp-Source: AGHT+IFer4sjDb4ENGe12iXFOTWNtYfFIT+9QseI7gnSexFecAmhNRzMncJ3pRB/czSgqv4mQrdL X-Received: by 2002:a05:6808:201b:b0:3c6:b55:8acc with SMTP id q27-20020a056808201b00b003c60b558accmr1072063oiw.14.1712734661490; Wed, 10 Apr 2024 00:37:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712734661; cv=none; d=google.com; s=arc-20160816; b=CZWRcjLxp/dDdvsVh2+gpR46V/6OvNjqewtlNu6xo4sJtUK+J2A5ot8R+CUvvTo67P IXRuuIlPLIhpUbdN8kGq+sszlOLMtmULafzPIDvl2Ku/S+uF01butT/l7rmCZrkuNyd+ quKClZ8ptAE+i10+Nz8eVoJxNF3DCSaPOqhrzi13QT8sV/MX2mCNptn7doU/+3UTHdSM UoMWkhReY4AvolA61Bn/3RICCk2m1NOK8f6VRDV8x352+ipgXaSpBmwrqXxc+08BAynG jzFXnxD7+YHmH3WseTi+UQo+CGeLUCeI7om4V3dgV1Lrg+J4vJ0G99Q3ILhAy2wXB3c7 1tcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=HLUUr7BAmeMGzlFTWwdxehIP5/p+vUN/6xOR4DiO2FY=; fh=XPr16z7k4qYUwnp7MFr0Z2i5quBDvtkdSzZufoMjA6c=; b=mQQmmYOaf+1xF9HmwsFQbPrKypjn5Mm4NCFirM9xuEFzOumHfGx/DLxIRr/lNnobHB y71cppV4wBQ0xWYFeaxPRLoFjwXt/i0zL7Y2pma+oL1CT20j2URHrHN/UPUoBWPgNFEW 8r9ERsogRpmcoQ4MczQYW7VFH15YjVVxQx2EnW+WeaJThOhSRiBe679U0BFXw6V+Py6I dvlyW0+2wSMo/Z1BOhzUzlSI61ES63dfRBrdiqoaNxM4VT7/mEe4zasU0/qL3vz/YzH6 tDc6a3XRn+Lca63aVm5iKG0DoeERB7Y5nRxozzl2MN9zKb4R/VJkVz2I59IJ7AvYMLST yulg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Wed, 10 Apr 2024 03:26:46 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 6A2265D699; Wed, 10 Apr 2024 10:25:05 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 025D6B02D9; Wed, 10 Apr 2024 10:23:07 +0300 (MSK) Received: (nullmailer pid 4191771 invoked by uid 1000); Wed, 10 Apr 2024 07:23:04 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Richard Henderson , Sven Schnelle , Helge Deller , Michael Tokarev Subject: [Stable-8.2.3 41/87] target/hppa: Fix assemble_16 insns for wide mode Date: Wed, 10 Apr 2024 10:22:14 +0300 Message-Id: <20240410072303.4191455-41-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Reported-by: Sven Schnelle Reviewed-by: Helge Deller Signed-off-by: Richard Henderson (cherry picked from commit 72bace2d13cb427fde3bb50ae1a71a2abe9acc0f) Signed-off-by: Michael Tokarev diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index f5a3f02fd1..0d9f8159ec 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -27,13 +27,14 @@ %assemble_11a 0:s1 4:10 !function=expand_shl3 %assemble_12 0:s1 2:1 3:10 !function=expand_shl2 %assemble_12a 0:s1 3:11 !function=expand_shl2 +%assemble_16 0:16 !function=expand_16 %assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2 %assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2 +%assemble_sp 14:2 !function=sp0_if_wide %assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11 %lowsign_11 0:s1 1:10 -%lowsign_14 0:s1 1:13 %sm_imm 16:10 !function=expand_sm_imm @@ -221,7 +222,7 @@ sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d ldil 001000 t:5 ..................... i=%assemble_21 addil 001010 r:5 ..................... i=%assemble_21 -ldo 001101 b:5 t:5 -- .............. i=%lowsign_14 +ldo 001101 b:5 t:5 ................ i=%assemble_16 addi 101101 ..... ..... .... 0 ........... @rri_cf addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf @@ -306,10 +307,12 @@ fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi @ldstim11 ...... b:5 t:5 sp:2 .............. \ &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3 -@ldstim14 ...... b:5 t:5 sp:2 .............. \ - &ldst disp=%lowsign_14 x=0 scale=0 m=0 -@ldstim14m ...... b:5 t:5 sp:2 .............. \ - &ldst disp=%lowsign_14 x=0 scale=0 m=%neg_to_m +@ldstim14 ...... b:5 t:5 ................ \ + &ldst sp=%assemble_sp disp=%assemble_16 \ + x=0 scale=0 m=0 +@ldstim14m ...... b:5 t:5 ................ \ + &ldst sp=%assemble_sp disp=%assemble_16 \ + x=0 scale=0 m=%neg_to_m @ldstim12m ...... b:5 t:5 sp:2 .............. \ &ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3ef39b1bd7..5d9f448acd 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -144,6 +144,28 @@ static int assemble_6(DisasContext *ctx, int val) return (val ^ 31) + 1; } +/* Expander for assemble_16(s,im14). */ +static int expand_16(DisasContext *ctx, int val) +{ + /* + * @val is bits [0:15], containing both im14 and s. + * Swizzle thing around depending on PSW.W. + */ + int s = extract32(val, 14, 2); + int i = (-(val & 1) << 13) | extract32(val, 1, 13); + + if (ctx->tb_flags & PSW_W) { + i ^= s << 13; + } + return i; +} + +/* The sp field is only present with !PSW_W. */ +static int sp0_if_wide(DisasContext *ctx, int sp) +{ + return ctx->tb_flags & PSW_W ? 0 : sp; +} + /* Translate CMPI doubleword conditions to standard. */ static int cmpbid_c(DisasContext *ctx, int val) { From patchwork Wed Apr 10 07:22:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 787479 Delivered-To: patch@linaro.org Received: by 2002:adf:fdd2:0:b0:346:15ad:a2a with SMTP id i18csp567897wrs; Wed, 10 Apr 2024 00:29:46 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWoDw6qOF0t1LET7me4e26ildcRCucJBWcN0Z+P+lWqH5XCyRbCqqnSz1OSRTe5hkfQ2yACUAGpWUpsMxDDqT6h X-Google-Smtp-Source: AGHT+IEBNam2+iVTTGvQhw49FzYD18xy01vqpn3a+r5vIPHGjBeuJFMB9BUWwLcOyshTqwnMUwc1 X-Received: by 2002:a05:620a:1215:b0:78d:6a6b:414d with SMTP id u21-20020a05620a121500b0078d6a6b414dmr3169389qkj.17.1712734186199; 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Wed, 10 Apr 2024 03:26:46 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 7AB5D5D69A; Wed, 10 Apr 2024 10:25:05 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 1EC8FB02DA; Wed, 10 Apr 2024 10:23:07 +0300 (MSK) Received: (nullmailer pid 4191774 invoked by uid 1000); Wed, 10 Apr 2024 07:23:04 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Richard Henderson , Helge Deller , Sven Schnelle , Michael Tokarev Subject: [Stable-8.2.3 42/87] target/hppa: Fix assemble_11a insns for wide mode Date: Wed, 10 Apr 2024 10:22:15 +0300 Message-Id: <20240410072303.4191455-42-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Tested-by: Helge Deller Reviewed-by: Helge Deller Reported-by: Sven Schnelle Signed-off-by: Richard Henderson (cherry picked from commit 4768c28edd4097ebef42822e15b4a43026b15376) Signed-off-by: Michael Tokarev diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 0d9f8159ec..9c6f92444c 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -24,7 +24,7 @@ %assemble_sr3 13:1 14:2 %assemble_sr3x 13:1 14:2 !function=expand_sr3x -%assemble_11a 0:s1 4:10 !function=expand_shl3 +%assemble_11a 4:12 0:1 !function=expand_11a %assemble_12 0:s1 2:1 3:10 !function=expand_shl2 %assemble_12a 0:s1 3:11 !function=expand_shl2 %assemble_16 0:16 !function=expand_16 @@ -305,8 +305,9 @@ fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi # Offset Mem #### -@ldstim11 ...... b:5 t:5 sp:2 .............. \ - &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3 +@ldstim11 ...... b:5 t:5 ................ \ + &ldst sp=%assemble_sp disp=%assemble_11a \ + m=%ma2_to_m x=0 scale=0 size=3 @ldstim14 ...... b:5 t:5 ................ \ &ldst sp=%assemble_sp disp=%assemble_16 \ x=0 scale=0 m=0 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 5d9f448acd..8c7a2fd331 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -121,12 +121,6 @@ static int expand_shl2(DisasContext *ctx, int val) return val << 2; } -/* Used for fp memory ops. */ -static int expand_shl3(DisasContext *ctx, int val) -{ - return val << 3; -} - /* Used for assemble_21. */ static int expand_shl11(DisasContext *ctx, int val) { @@ -144,6 +138,23 @@ static int assemble_6(DisasContext *ctx, int val) return (val ^ 31) + 1; } +/* Expander for assemble_16a(s,cat(im10a,0),i). */ +static int expand_11a(DisasContext *ctx, int val) +{ + /* + * @val is bit 0 and bits [4:15]. + * Swizzle thing around depending on PSW.W. + */ + int im10a = extract32(val, 1, 10); + int s = extract32(val, 11, 2); + int i = (-(val & 1) << 13) | (im10a << 3); + + if (ctx->tb_flags & PSW_W) { + i ^= s << 13; + } + return i; +} + /* Expander for assemble_16(s,im14). */ static int expand_16(DisasContext *ctx, int val) { From patchwork Wed Apr 10 07:22:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 787484 Delivered-To: patch@linaro.org Received: by 2002:adf:fdd2:0:b0:346:15ad:a2a with SMTP id i18csp570652wrs; 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Wed, 10 Apr 2024 03:27:09 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 977925D69B; Wed, 10 Apr 2024 10:25:05 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 2F8EBB02DB; Wed, 10 Apr 2024 10:23:07 +0300 (MSK) Received: (nullmailer pid 4191777 invoked by uid 1000); Wed, 10 Apr 2024 07:23:04 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Richard Henderson , Helge Deller , Sven Schnelle , Michael Tokarev Subject: [Stable-8.2.3 43/87] target/hppa: Fix assemble_12a insns for wide mode Date: Wed, 10 Apr 2024 10:22:16 +0300 Message-Id: <20240410072303.4191455-43-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Tested-by: Helge Deller Reported-by: Sven Schnelle Signed-off-by: Richard Henderson (cherry picked from commit 46174e140d274385b1255bc7f16a5a711853053f) Signed-off-by: Michael Tokarev diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 9c6f92444c..5412ff9836 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -26,7 +26,7 @@ %assemble_11a 4:12 0:1 !function=expand_11a %assemble_12 0:s1 2:1 3:10 !function=expand_shl2 -%assemble_12a 0:s1 3:11 !function=expand_shl2 +%assemble_12a 3:13 0:1 !function=expand_12a %assemble_16 0:16 !function=expand_16 %assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2 %assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2 @@ -314,8 +314,9 @@ fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi @ldstim14m ...... b:5 t:5 ................ \ &ldst sp=%assemble_sp disp=%assemble_16 \ x=0 scale=0 m=%neg_to_m -@ldstim12m ...... b:5 t:5 sp:2 .............. \ - &ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m +@ldstim12m ...... b:5 t:5 ................ \ + &ldst sp=%assemble_sp disp=%assemble_12a \ + x=0 scale=0 m=%pos_to_m # LDB, LDH, LDW, LDWM ld 010000 ..... ..... .. .............. @ldstim14 size=0 @@ -331,15 +332,19 @@ st 011010 ..... ..... .. .............. @ldstim14 size=2 st 011011 ..... ..... .. .............. @ldstim14m size=2 st 011111 ..... ..... .. ...........10. @ldstim12m size=2 -fldw 010110 b:5 ..... sp:2 .............. \ - &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2 -fldw 010111 b:5 ..... sp:2 ...........0.. \ - &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2 - -fstw 011110 b:5 ..... sp:2 .............. \ - &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2 -fstw 011111 b:5 ..... sp:2 ...........0.. \ - &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2 +fldw 010110 b:5 ..... ................ \ + &ldst disp=%assemble_12a sp=%assemble_sp \ + t=%rm64 m=%a_to_m x=0 scale=0 size=2 +fldw 010111 b:5 ..... .............0.. \ + &ldst disp=%assemble_12a sp=%assemble_sp \ + t=%rm64 m=0 x=0 scale=0 size=2 + +fstw 011110 b:5 ..... ................ \ + &ldst disp=%assemble_12a sp=%assemble_sp \ + t=%rm64 m=%a_to_m x=0 scale=0 size=2 +fstw 011111 b:5 ..... .............0.. \ + &ldst disp=%assemble_12a sp=%assemble_sp \ + t=%rm64 m=0 x=0 scale=0 size=2 ld 010100 ..... ..... .. ............0. @ldstim11 fldd 010100 ..... ..... .. ............1. @ldstim11 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8c7a2fd331..23ff14c39b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -155,6 +155,23 @@ static int expand_11a(DisasContext *ctx, int val) return i; } +/* Expander for assemble_16a(s,im11a,i). */ +static int expand_12a(DisasContext *ctx, int val) +{ + /* + * @val is bit 0 and bits [3:15]. + * Swizzle thing around depending on PSW.W. + */ + int im11a = extract32(val, 1, 11); + int s = extract32(val, 12, 2); + int i = (-(val & 1) << 13) | (im11a << 2); + + if (ctx->tb_flags & PSW_W) { + i ^= s << 13; + } + return i; +} + /* Expander for assemble_16(s,im14). */ static int expand_16(DisasContext *ctx, int val) { From patchwork Wed Apr 10 07:22:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 787485 Delivered-To: patch@linaro.org Received: by 2002:adf:fdd2:0:b0:346:15ad:a2a with SMTP id i18csp571027wrs; Wed, 10 Apr 2024 00:41:11 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX10mnZhZJR2ViRkwj+AgfB2zmSrxqFPxpGZv+5kClk1UwcdseffTiEmJi1xwR95GKcH5Bxj8ZaxSg+iaLv5VJM X-Google-Smtp-Source: AGHT+IG602eE8aTg4GNDGnQJVArEFuLAt0PmfpfFL0p4D2mgA7V8T+ZEqyuchK55f4IATwFUf23B X-Received: by 2002:a05:6214:2021:b0:69b:9a1:b9bb with SMTP id 1-20020a056214202100b0069b09a1b9bbmr1923336qvf.50.1712734871299; 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[209.51.188.17]) by mx.google.com with ESMTPS id e9-20020a0cf349000000b0069b2068681csi5006657qvm.495.2024.04.10.00.41.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 10 Apr 2024 00:41:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ruSPq-00037b-4Q; Wed, 10 Apr 2024 03:30:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruSPZ-0002wR-30; Wed, 10 Apr 2024 03:30:26 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruSPW-00055p-FR; Wed, 10 Apr 2024 03:30:23 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id DF6835D6BA; Wed, 10 Apr 2024 10:25:07 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 84E07B02FA; Wed, 10 Apr 2024 10:23:09 +0300 (MSK) Received: (nullmailer pid 4191873 invoked by uid 1000); Wed, 10 Apr 2024 07:23:04 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Michael Tokarev Subject: [Stable-8.2.3 74/87] tcg/optimize: Fix sign_mask for logical right-shift Date: Wed, 10 Apr 2024 10:22:47 +0300 Message-Id: <20240410072303.4191455-74-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson The 'sign' computation is attempting to locate the sign bit that has been repeated, so that we can test if that bit is known zero. That computation can be zero if there are no known sign repetitions. Cc: qemu-stable@nongnu.org Fixes: 93a967fbb57 ("tcg/optimize: Propagate sign info for shifting") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2248 Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé (cherry picked from commit 2911e9b95f3bb03783ae5ca3e2494dc3b44a9161) Signed-off-by: Michael Tokarev diff --git a/tcg/optimize.c b/tcg/optimize.c index f2d01654c5..6fcdda68ef 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2123,7 +2123,7 @@ static bool fold_shift(OptContext *ctx, TCGOp *op) * will not reduced the number of input sign repetitions. */ sign = (s_mask & -s_mask) >> 1; - if (!(z_mask & sign)) { + if (sign && !(z_mask & sign)) { ctx->s_mask = s_mask; } break; diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index ea3e232e65..0efd565f05 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -10,6 +10,7 @@ VPATH += $(AARCH64_SRC) # Base architecture tests AARCH64_TESTS=fcvt pcalign-a64 lse2-fault +AARCH64_TESTS += test-2248 fcvt: LDFLAGS+=-lm diff --git a/tests/tcg/aarch64/test-2248.c b/tests/tcg/aarch64/test-2248.c new file mode 100644 index 0000000000..aac2e17836 --- /dev/null +++ b/tests/tcg/aarch64/test-2248.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* See https://gitlab.com/qemu-project/qemu/-/issues/2248 */ + +#include + +__attribute__((noinline)) +long test(long x, long y, long sh) +{ + long r; + asm("cmp %1, %2\n\t" + "cset x12, lt\n\t" + "and w11, w12, #0xff\n\t" + "cmp w11, #0\n\t" + "csetm x14, ne\n\t" + "lsr x13, x14, %3\n\t" + "sxtb %0, w13" + : "=r"(r) + : "r"(x), "r"(y), "r"(sh) + : "x11", "x12", "x13", "x14"); + return r; +} + +int main() +{ + long r = test(0, 1, 2); + assert(r == -1); + return 0; +} From patchwork Wed Apr 10 07:22:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 787480 Delivered-To: patch@linaro.org Received: by 2002:adf:fdd2:0:b0:346:15ad:a2a with SMTP id i18csp568712wrs; Wed, 10 Apr 2024 00:32:14 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV5rK4zh/qYLU/+S4FACjxGYUR8jHX5+16p8+etDRkpp8AiJYzLC4zpa7/kqAGTqHviVvTrYWwYzCEfhtHKmKsf X-Google-Smtp-Source: AGHT+IG1pTMcYVwDZNNd/132cwqu+MP/kIPergqoFrERSG+yzDnStJ3Vch9GSCrQjAdzkwGcwxHA X-Received: by 2002:a05:620a:4009:b0:78d:65a3:173b with SMTP id h9-20020a05620a400900b0078d65a3173bmr7866678qko.1.1712734333860; Wed, 10 Apr 2024 00:32:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712734333; cv=none; d=google.com; s=arc-20160816; b=lPKGZFNdDaKKeJl3SPKAKsp0X5nYYt5Nar5bO68cyjk95j7X+adW/ulX3zTI93Rrrc G7d7cIIHIPUMt0gTs+as/RQ8Fdnw6Wjt86bwHHbBLFKNJmBdtJSQwCsc8gcva6GUgBE8 3rkNGpSeWv5W/XBjO78yftkqtvPZno6Yhr1CTwEuBSVWZwkIwBz5gKug3mD6NZ4PzHew KLpuQmAzTapAltGT2vSJ+D/6X87AcqitmjbUIJ51HcYCCAJnU8vvkex0Xd7qPt5AtW5d 4EGUvEAFbdQN7/6Mb90FEamJ281cvZs/ioreIbxgwmKzUAgryyZInanpqgxMDBdvwV3e CnNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=nI4fB85FATRCcAJ8aAvbasdMbZEi9ryi+S3AaFTSkaA=; fh=kdk60BKfZ5DgEBtWXo3DTw7OzkP+TNgwcG6z+nAOi8Y=; b=LKtQih4OANjG9sJVNpauFgSF4IOUKUeIWN408dpbzuoeccdTgYVgJd0YSmglirq6fz CxyrffxydP1yjOiHq8q+24+y5MGjZ2/+LSvIItiSlKWPgRC3EspO1QwuCvDXhF/6tela 0tMkifDlHtb1RIAuPIygqr+N29OtGB9n8+zLmSJwvjeITT57pk643LCdAkrPYSdn1nAn zuMDixy0Vad6KuihFPskOAgdVS6teDsGJot5T9sc+rZFCNoTyu8JvI9w+5IltI7WcVhW dBM+YuBpvjkXxrNC8yWHKEjaO07HG0vs05ScHmHEwblLkZQr1EOokGBdvovhP7qhoz7+ Wjow==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ou9-20020a05620a620900b0078a49e0d95esi11817558qkn.665.2024.04.10.00.32.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 10 Apr 2024 00:32:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ruSPq-0003CR-Fj; Wed, 10 Apr 2024 03:30:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruSPa-0002zr-CN; Wed, 10 Apr 2024 03:30:28 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruSPY-0005D8-SK; Wed, 10 Apr 2024 03:30:26 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id F0B7B5D6BB; Wed, 10 Apr 2024 10:25:07 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 952C4B02FB; Wed, 10 Apr 2024 10:23:09 +0300 (MSK) Received: (nullmailer pid 4191876 invoked by uid 1000); Wed, 10 Apr 2024 07:23:04 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Richard Henderson , Sven Schnelle , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Michael Tokarev Subject: [Stable-8.2.3 75/87] target/hppa: Clear psw_n for BE on use_nullify_skip path Date: Wed, 10 Apr 2024 10:22:48 +0300 Message-Id: <20240410072303.4191455-75-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Along this path we have already skipped the insn to be nullified, so the subsequent insn should be executed. Cc: qemu-stable@nongnu.org Reported-by: Sven Schnelle Tested-by: Sven Schnelle Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson (cherry picked from commit 4a3aa11e1fb25c28c24a43fd2835c429b00a463d) Signed-off-by: Michael Tokarev diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 19c4df8960..d82d3c8748 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3819,6 +3819,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp); tcg_gen_mov_i64(cpu_iasq_f, new_spc); tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f); + nullify_set(ctx, 0); } else { copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); if (ctx->iaoq_b == -1) { From patchwork Wed Apr 10 07:22:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 787486 Delivered-To: patch@linaro.org Received: by 2002:adf:fdd2:0:b0:346:15ad:a2a with SMTP id i18csp571585wrs; Wed, 10 Apr 2024 00:43:15 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX1Tptt/9tkAevpDNFRgFuVNipaF3Z1s7j7WVJxtNa91zPRsJsHkhYTSqJU1e6NJ4NpYBMnkQTkDU6gGAXN3Cgw X-Google-Smtp-Source: AGHT+IEa7cCCYITNgweemPX6NI9kYTFZ7KWN7z+B2jyK0KYz5CBS0UVbF3v31k58U/KP2zM9pVbT X-Received: by 2002:a05:622a:11d3:b0:434:e30b:2cf8 with SMTP id n19-20020a05622a11d300b00434e30b2cf8mr1954667qtk.30.1712734995537; Wed, 10 Apr 2024 00:43:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712734995; cv=none; d=google.com; s=arc-20160816; b=UJC6DEVgPY6mGQPlAlqRa+WWn7z6W9b4OWJDILjQ2BArVhe48Cau3+XobsOWPr8Wi/ lmeQQyk7GPVPMSAx+5bUwOm5/xrACLDjrAQFPY9KeY37MAKXKupBfO6FcJGRMNQebBT4 hF+BiyEf4d68bPMDV1dcmx13+EIRh8S6BSHnRqzW4cp+i9DHuAVeTPVJatwYkEuVxfpA u90mRdiNR9jcqjl5Yz7xe5QV1ESKC9MHSlm1VIeMeSwBbYWz//gEFOvzN8STl0emTI+X vU187NILWt/Y9kezox3Hq6gVRK5MhmOiI0rIxyfkfuxATQOG5qPUPqN5Oz7ahqlxVb9H Rkvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=NEyzqnL1srbnZU95s9tfMinTyWn9xDPViewoW5k1wRQ=; fh=xJ1URYKcMN3TM0/XAv5v+aCN+5tIbzAdcfBx5UNgoLw=; b=WC/GyA8kbsHmHfBhf4T4Y8GSOpCqLNRi0Htr29J+E+HaxEktLOlcls7YN44cffUrsL ldOWMnxd+EaEwf3gq0BAbfrK+s/jtyJNn+Yb/kH7ULWGM18Gdce6LBG5iXHG91whxV68 sGqv+bOvULJSk3oAHjdKz4EEksSGq+OA+1LitXHiuN4WGPaRm1Rnyt9raKe/gBIottQG 28upyeDSjGqRDSBvRLYCtGsZkt0ZcwA1wmYREVHaPYDu5LSRq1sfo95qA+NMKUl9SMbt mUfX4sfKhLIJiJdy0ePgNYW/QDx2mVsF0+GPdxRvbbQTPo+CmVUOVYs5LcVlQO3hPJX9 GuJQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c5-20020a05622a024500b00434ebb49e2asi2308958qtx.138.2024.04.10.00.43.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 10 Apr 2024 00:43:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ruSPr-0003MI-Rz; Wed, 10 Apr 2024 03:30:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruSPg-00033w-H3; Wed, 10 Apr 2024 03:30:34 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruSPe-0005NP-AL; Wed, 10 Apr 2024 03:30:31 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 2B27C5D6BE; Wed, 10 Apr 2024 10:25:08 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id C505CB02FE; Wed, 10 Apr 2024 10:23:09 +0300 (MSK) Received: (nullmailer pid 4191885 invoked by uid 1000); Wed, 10 Apr 2024 07:23:04 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Peter Maydell , Richard Henderson , Michael Tokarev Subject: [Stable-8.2.3 78/87] hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled Date: Wed, 10 Apr 2024 10:22:51 +0300 Message-Id: <20240410072303.4191455-78-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell If the group of the highest priority pending interrupt is disabled via ICC_IGRPEN*, the ICC_HPPIR* registers should return INTID_SPURIOUS, not the interrupt ID. (See the GIC architecture specification pseudocode functions ICC_HPPIR1_EL1[] and HighestPriorityPendingInterrupt().) Make HPPIR reads honour the group disable, the way we already do when determining whether to preempt in icc_hppi_can_preempt(). Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240328153333.2522667-1-peter.maydell@linaro.org (cherry picked from commit 44e25fbc1900c99c91a44e532c5bd680bc403459) Signed-off-by: Michael Tokarev diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 258dee1b80..3364f6b706 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -1067,7 +1067,7 @@ static uint64_t icc_hppir0_value(GICv3CPUState *cs, CPUARMState *env) */ bool irq_is_secure; - if (cs->hppi.prio == 0xff) { + if (icc_no_enabled_hppi(cs)) { return INTID_SPURIOUS; } @@ -1104,7 +1104,7 @@ static uint64_t icc_hppir1_value(GICv3CPUState *cs, CPUARMState *env) */ bool irq_is_secure; - if (cs->hppi.prio == 0xff) { + if (icc_no_enabled_hppi(cs)) { return INTID_SPURIOUS; } From patchwork Wed Apr 10 07:22:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 787483 Delivered-To: patch@linaro.org Received: by 2002:adf:fdd2:0:b0:346:15ad:a2a with SMTP id i18csp570199wrs; Wed, 10 Apr 2024 00:37:42 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXMER1ajI/iphzP/EDo+0z2cby102eAELcGMEAXAJK/WKl3H/iMpMvCf16vSFszHtXXlqQVpHHP/7S5UV2pnZ5z X-Google-Smtp-Source: AGHT+IEVJ6zw7r+o2hP07USZF4QIWNarcVVerr9Pap5Ljj0L/bKL78D6UGIUlAuGXWg1HHS3eM25 X-Received: by 2002:ad4:5de1:0:b0:696:a490:a94f with SMTP id jn1-20020ad45de1000000b00696a490a94fmr2569272qvb.30.1712734662781; Wed, 10 Apr 2024 00:37:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712734662; cv=none; d=google.com; s=arc-20160816; b=iYirsg39/IeOEKlQk2CX55AJD0XAy3ZR2dpwRwKPLLG3sy+F7W9qqyVwadN6PKaxBr W3S0q2NauX1DcbLkp4K7Rle4vbiTbHY1wsW1udT6hV62+yrN4yn504KT9PX3OcrzbHAK 34NTDIEWazsyAoHpHAGhgvXcMx/W2Tghy4hAloH3MDTOSyU8zmPbDSj2xLx6fhpBSlCg DvwyCUjYk8Gfd9a9UPo9W8Kimu2wOv1h7KxXBcZ54BTsCfCtz3HW/pERVswyrhNJTyYX y0qlBsKUqmNL/ZY2KDtjnpSoYNZRiQg5KdN0M+nWh5npFRxL065X0GPSUIchjFPS/Wnm Asiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=omPI5ZbB80xT/Xy05t3AUNNG5qAZSkQCSw2CQDT66xU=; fh=xJ1URYKcMN3TM0/XAv5v+aCN+5tIbzAdcfBx5UNgoLw=; b=Q17eu2nwHAAWvoJuwm1ZMP6QYLG3fj54sW/Q8TPqxhdeHsWpOKWglRkuFp038MNxge gRXtKZiVwLmlEn/L7O2Ow/aWSGPyxvor3RD/gCNAbKK9IvsEeGIpJPVS4KGcJAVdBLoK +qBKnG/uCLxq9AcJvNDAVsFduzbru1Cpo2NhDu3lbctYLuXJJQhLYkhcNhpiS1DJBcoc 2o1rUPYZ7ysVanui/znHjtaHvCsvI9U7rup0RpSdonkQwSdXUZz0VQtriKdUrARH8bYF B9rm4I+3Bh3kzkB27qU/1RMpPJCVIeSk+AWSAsk1nn49ZC9iOZPeI1+4Uu/Ve6RcQ1zh O1Fw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s12-20020ad4438c000000b0069b22177e9csi4665161qvr.45.2024.04.10.00.37.42 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 10 Apr 2024 00:37:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ruSQ3-0004SU-Hk; Wed, 10 Apr 2024 03:30:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruSQ1-0004HR-Bk; Wed, 10 Apr 2024 03:30:53 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruSPz-0005NW-DG; Wed, 10 Apr 2024 03:30:53 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 3B1F45D6BF; Wed, 10 Apr 2024 10:25:08 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id D4863B02FF; Wed, 10 Apr 2024 10:23:09 +0300 (MSK) Received: (nullmailer pid 4191889 invoked by uid 1000); Wed, 10 Apr 2024 07:23:04 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Peter Maydell , Richard Henderson , Michael Tokarev Subject: [Stable-8.2.3 79/87] target/arm: take HSTR traps of cp15 accesses to EL2, not EL1 Date: Wed, 10 Apr 2024 10:22:52 +0300 Message-Id: <20240410072303.4191455-79-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell The HSTR_EL2 register allows the hypervisor to trap AArch32 EL1 and EL0 accesses to cp15 registers. We incorrectly implemented this so they trap to EL1 when we detect the need for a HSTR trap at code generation time. (The check in access_check_cp_reg() which we do at runtime to catch traps from EL0 is correctly routing them to EL2.) Use the correct target EL when generating the code to take the trap. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2226 Fixes: 049edada5e93df ("target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240325133116.2075362-1-peter.maydell@linaro.org (cherry picked from commit fbe5ac5671a9cfcc7f4aee9a5fac7720eea08876) Signed-off-by: Michael Tokarev diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index b3660173d1..e555e885a1 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -4584,7 +4584,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, tcg_gen_andi_i32(t, t, 1u << maskbit); tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label); - gen_exception_insn(s, 0, EXCP_UDEF, syndrome); + gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); /* * gen_exception_insn() will set is_jmp to DISAS_NORETURN, * but since we're conditionally branching over it, we want From patchwork Wed Apr 10 07:22:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 787481 Delivered-To: patch@linaro.org Received: by 2002:adf:fdd2:0:b0:346:15ad:a2a with SMTP id i18csp568714wrs; Wed, 10 Apr 2024 00:32:14 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXfyFR9mitTnM9ExFX3G27ldCtdyKWHweUDPk4v4mexnze32aPGp9q++LGt2FH9ideu2Vyq2NLjDh4o1nuCHIAy X-Google-Smtp-Source: AGHT+IHIc+5OUnGmurj0FhOzyP2qmZOuGDfjTJZqKS5XNUCkQMXhj0rqV8jmQCMESDGhu85OsF05 X-Received: by 2002:ac8:138b:0:b0:434:fd7d:636f with SMTP id h11-20020ac8138b000000b00434fd7d636fmr2992771qtj.4.1712734334291; Wed, 10 Apr 2024 00:32:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712734334; cv=none; d=google.com; s=arc-20160816; b=GG1R72fflnSHhQ/EmKhBoSGBWs40paq8mARjyPrI0/BREjZCBuxCYZrgAFUVE6CceS o9beo3v5eMh3Q8Bifmjko9f743SCJfkez/t5htfmgb5uSCZ57arJqrZqQrkLjRLL08my jnfSExl3+Nn6sRoNfpSdh9LZH7MFIw98si+1qtrrbMuFGrBck6MsFUPiS+5wcM4uZGsL ADQVmGhENyT1SWNHYOqnM4jTB293VH4YwNrL3ItxjaOjsN+a5t9OBcAfX6QmDCRtUTaE WAlBsVRB+kJ2FrUrddGn1CmQ/SOE6KFb4Sn1ryP0Gn5UPySCBXrgubETOHO2RTWNTs4v Za6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=Iu2iKOxaxxOCVlBupUr1F9RLVwCRf2NJ3Y/NCahQvAI=; fh=xJ1URYKcMN3TM0/XAv5v+aCN+5tIbzAdcfBx5UNgoLw=; b=02T5SA1sJEtzgvW66JEXu0MDWPSaG06QXxXJESinovbS4ITxInpVs1tY0voOUg/tCo 63u+3h+5SypQdTDUNuILA3UiFnFftsF1ZMKTV2vMc5jlzHKxuJJzgLzr6I/szZsO9m+n RUPYj6xNbbce5zBC57pHm7hXMGNK6RJPfXyWeccyQXxgJR1FBeaP/aMleB+dpyYVNh+s gNJ/XWMGtCWppb8094UzZDtxK9siWndNu8A4BeGQD6xXCoU2BVHqAWJxdUCL4s1IKGJt +g6UrB3gvVUHamg6Gt/p1OlT5vbzbqkoVBWKz5Nzg7aaf05Kb769nW1LG8ylc8ZqeHT9 ZTkQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v9-20020a05622a188900b00434f39edd11si2142943qtc.660.2024.04.10.00.32.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 10 Apr 2024 00:32:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ruSQu-0005bt-Tm; Wed, 10 Apr 2024 03:31:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruSQU-0005J0-Ph; Wed, 10 Apr 2024 03:31:23 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruSQR-0005QD-RE; Wed, 10 Apr 2024 03:31:21 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 89AA45D6C3; Wed, 10 Apr 2024 10:25:08 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 2E992B0303; Wed, 10 Apr 2024 10:23:10 +0300 (MSK) Received: (nullmailer pid 4191901 invoked by uid 1000); Wed, 10 Apr 2024 07:23:04 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Peter Maydell , Richard Henderson , Michael Tokarev Subject: [Stable-8.2.3 83/87] target/arm: Use correct SecuritySpace for AArch64 AT ops at EL3 Date: Wed, 10 Apr 2024 10:22:56 +0300 Message-Id: <20240410072303.4191455-83-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell When we do an AT address translation operation, the page table walk is supposed to be performed in the context of the EL we're doing the walk for, so for instance an AT S1E2R walk is done for EL2. In the pseudocode an EL is passed to AArch64.AT(), which calls SecurityStateAtEL() to find the security state that we should be doing the walk with. In ats_write64() we get this wrong, instead using the current security space always. This is fine for AT operations performed from EL1 and EL2, because there the current security state and the security state for the lower EL are the same. But for AT operations performed from EL3, the current security state is always either Secure or Root, whereas we want to use the security state defined by SCR_EL3.{NS,NSE} for the walk. This affects not just guests using FEAT_RME but also ones where EL3 is Secure state and the EL3 code is trying to do an AT for a NonSecure EL2 or EL1. Use arm_security_space_below_el3() to get the SecuritySpace to pass to do_ats_write() for all AT operations except the AT S1E3* operations. Cc: qemu-stable@nongnu.org Fixes: e1ee56ec2383 ("target/arm: Pass security space rather than flag for AT instructions") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2250 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240405180232.3570066-1-peter.maydell@linaro.org (cherry picked from commit 19b254e86a900dc5ee332e3ac0baf9c521301abf) Signed-off-by: Michael Tokarev diff --git a/target/arm/helper.c b/target/arm/helper.c index df1646de3a..ca2c6e9732 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3703,6 +3703,8 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, ARMMMUIdx mmu_idx; uint64_t hcr_el2 = arm_hcr_el2_eff(env); bool regime_e20 = (hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE); + bool for_el3 = false; + ARMSecuritySpace ss; switch (ri->opc2 & 6) { case 0: @@ -3720,6 +3722,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx = ARMMMUIdx_E3; + for_el3 = true; break; default: g_assert_not_reached(); @@ -3738,8 +3741,8 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, g_assert_not_reached(); } - env->cp15.par_el[1] = do_ats_write(env, value, access_type, - mmu_idx, arm_security_space(env)); + ss = for_el3 ? arm_security_space(env) : arm_security_space_below_el3(env); + env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx, ss); #else /* Handled by hardware accelerator. */ g_assert_not_reached();