From patchwork Mon Apr 8 11:47:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 787017 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D4D569DFE for ; Mon, 8 Apr 2024 11:47:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712576835; cv=none; b=K5sa18xkgWzZQGvgrjArCskMzTkeIEQr0tAngBdgKrO52LUl8/QynNL5QMwyzfrOpUiC9CuIX4rUz1fWD4E3bmtGNoz0EcEyMXAJI4qsMyAZPJr/OkG4VVxf82ucRkfIFPanmsTHDTiwMIvoAjKdgHvoeU434ab/hce8u+AQ/r4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712576835; c=relaxed/simple; bh=JEEcZ7GT4m842B7HDSa1gs6t5sncwlWhVy9ppSIiaIw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UmP95oJOvC1XWFVxdUMPjasTadc7lgsstwuw48hA7WWw9Lvo6tWdmZYEyKwWTbeC9sqIH+A7pvqmApn86vtTvtqboJr5vAJitOCowAuVPwA36/BucvBfAMZcEkTi203b44m8Y7nsVLNCO0JE20/f1fRUt8z/WhbLQd+PvYMmSZs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=S/G4QX02; arc=none smtp.client-ip=209.85.167.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="S/G4QX02" Received: by mail-lf1-f48.google.com with SMTP id 2adb3069b0e04-516d04fc04bso6367331e87.2 for ; Mon, 08 Apr 2024 04:47:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712576831; x=1713181631; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=64cuR2i1dQD0IH225310OR1c+tox9VMCKmc6hrJvTAA=; b=S/G4QX02wZnjOpjv8gK6fehWyj6iTtzWtOJzh0M5jCGnfQkGPp9gUsnwEUpkSY0xer trtjfnxtVVoj4DXI0mdRCEouOjY2tyJeR4NPg1If9orQ8e5YunJWUqlpfnmklyn1iX+/ TrZYnKg/hpX4j38oH6zTWG3dhPEY4sZKeq416M3/C0uXhqqcXqIn8xwCmgtO8ahcPFni 0t/2uXd+WeQM/ig8H+jN5Vy+4AS8iT1ByA54fsR/F/dxNHntjQ4UQ4obnr7Sus0N8xT+ K9fPKaTOj7UdJKSjNkXn6FqnCQKFCZOUNeaZ71sF018IeNjwlrM0qkuz+hdqqokdsnrO N/9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712576831; x=1713181631; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=64cuR2i1dQD0IH225310OR1c+tox9VMCKmc6hrJvTAA=; b=EPHQyhOBFZH7tZIv0eIwW1hFm0JqMwd/XvLH2CTCXdxEuSgunctSVioGiLuDkU7C4K z1VfHGvlx3VrP5Fkoj4o0DKp031QX/R0CjmoRXHzsjoBE5yjGY7LKHoLzTeTkObpIV+Q rboDHrHho6lyE32wqI+EsID+P4YR4JIveYQNfSi53/044c8+WefmiVe/gJeF7M3eBxfw pUTSof3Mt7KEacMiynpjfoZYpEUn2X6Qgsgfb+mJOw6fdYPoQJPR9PI7qmt97UaPTv7V rWZQgatxtl2fDPEuMnM81ZmnvsYOPMqHK7f2fc4sIonmp+W/qzHl6TJqruptwg5BAnto QDDQ== X-Gm-Message-State: AOJu0Yyw7BOAwwQRBiIEMMSG7KSkJPAsXTqvlalZCyh6pI7TU3hhUmjp C1MA/p/P8o9ETXmDpxY/aeccKK0kgkJMEIH+wsH4CxT6a0GNeXHWOEy0fWJaWks= X-Google-Smtp-Source: AGHT+IE1RRgf0MEyF18A0T8NT3YmtSCMr0fSfeTqjN58nIVz22Wj9SjCxFiRSSb3akCmh1cUTwTUHg== X-Received: by 2002:a19:6446:0:b0:513:7e83:b3f2 with SMTP id b6-20020a196446000000b005137e83b3f2mr7832191lfj.45.1712576831520; Mon, 08 Apr 2024 04:47:11 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id g17-20020a19e051000000b005158ddab172sm1175549lfj.19.2024.04.08.04.47.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Apr 2024 04:47:11 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 08 Apr 2024 14:47:04 +0300 Subject: [PATCH 1/4] clk: qcom: dispcc-sm8450: fix DisplayPort clocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240408-dispcc-dp-clocks-v1-1-f9e44902c28d@linaro.org> References: <20240408-dispcc-dp-clocks-v1-0-f9e44902c28d@linaro.org> In-Reply-To: <20240408-dispcc-dp-clocks-v1-0-f9e44902c28d@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Konrad Dybcio , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3066; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=JEEcZ7GT4m842B7HDSa1gs6t5sncwlWhVy9ppSIiaIw=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmE9k9tcMAUMKUHJNNPHZnqDs/qTZ3VWTBd0n2i fafY7QDhhqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZhPZPQAKCRCLPIo+Aiko 1XIfB/4kyD9Ash8QTxO2U1slDgEC6Zst91dV2SrsOfjSQfodYgvtIi0DIYikJyMoNSEf2j5pH7z AmsrZuna+oYnHu93FXhbYBeXGE19J5BKrhKgfy2eKUsZo1sA2c15HXrdGOOeIGAi9o/rE26LwWj Ifg9g5154EOEPVsUxx59wgDYCOQ+0+S9PXHGtGoDRq33Da1IHOGfIuSjlu78mnvqDHyldV/xDL6 omC7299WD21kaB5nEQ5x+CDKGs3MoHZ2W+a6JmxPWu4nppLjb+WEjM0yU7sDTbPz0HwGj/yJ0Pq ZdBgwj+64oxGAVrQfKSD6ujPWp4QZNv8K5sP0ieS4/P0vOkL X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On SM8450 DisplayPort link clocks use frequency tables inherited from the vendor kernel, it is not applicable in the upstream kernel. Drop frequency tables and use clk_byte2_ops for those clocks. Fixes: 16fb89f92ec4 ("clk: qcom: Add support for Display Clock Controller on SM8450") Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong --- drivers/clk/qcom/dispcc-sm8450.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c index 92e9c4e7b13d..49bb4f58c391 100644 --- a/drivers/clk/qcom/dispcc-sm8450.c +++ b/drivers/clk/qcom/dispcc-sm8450.c @@ -309,26 +309,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { }, }; -static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = { - F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - { } -}; - static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { .cmd_rcgr = 0x819c, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx0_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; @@ -382,13 +373,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx1_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; @@ -442,13 +432,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx2_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; @@ -502,13 +491,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx3_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; From patchwork Mon Apr 8 11:47:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 787620 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35E8169E0D for ; Mon, 8 Apr 2024 11:47:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712576836; cv=none; b=jQ3TF5GgAtOUZxqCtmmLZS6Bwt6oCfSgBd6//siuzrvp/1pNTk7X0F3ofHuahNCMp7Xu32WVS84uvcJbRQmT6+ngREwcSSkzQ5dhz65mN3hncuNselkmg6hKTz5Bw47xpdpzYowwpdGcUFjpFOiWt27uIcXTTLPhKtZaJ858nQ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712576836; c=relaxed/simple; bh=OsDfVmwigHiKLQONHsnbey3y8n9mOJj5tZKTmOviAn4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FBzHNg379sibMnxfSlmkxIJeg0SmL81RP2JkipeeFKRsgGJLDnKGQ3s47b51ll4ojj+gqDbdZMhHiFaVv191xZgVQn5SrQgnollVgrQTSaEa7q2M5qxEH1G4Sk7cZ06Coz+yB2CX3eQIT0diFExlSkBIOrgJNmrOzwv0BlwIRTk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=MmnZ18Fw; arc=none smtp.client-ip=209.85.167.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="MmnZ18Fw" Received: by mail-lf1-f48.google.com with SMTP id 2adb3069b0e04-516d756eb74so3045723e87.3 for ; Mon, 08 Apr 2024 04:47:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712576832; x=1713181632; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=9iTV4QYo3hma+PsA0jLP4qJZguBY70D1nyyF3au1lSI=; b=MmnZ18FwnEyEwiZFdyEqmoj1UrC6Cf/Yy3qDxmrS5OkpBbr4lRfx9AxvCRbkc478Yv vDyRUYereZuJxVsJABD9U0N43juvNKA9OihYUHGGj+zyC8HLXsMgCgYnb96mdjirdyBo dTIRz22L7jL7S4sZHAQE5ywZYKZT2qj3C/k/zWddzXszO6J6eMeQfIxMrv5rT1nKrT+H ag8P4/GivpRDXkDmX7iGf1m/3m3qCE2CKFPwAbwDzBxLc1sPdt/4Bc6ctMZcA5QbLcX7 ZAz9rjD2UtHK2XOj/7tWdxj0bRV0Sxbfd0CkGFlSinFYCO5pgtTLG1xBMpWmcQXsvVVM hQkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712576832; x=1713181632; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9iTV4QYo3hma+PsA0jLP4qJZguBY70D1nyyF3au1lSI=; b=X4EW+BtcvWIScMJkwP8HNK0UFBRomJSKW6Opcpn9E0k2psUK/Bhov7mftSvgbS58Uf ayTkP9zWIDwNo4Zww7gUB+dHsj9KB1rhZLZoRqE8uzUbPkJ6K4DQSQ203fbR3ekbi/qI OEp/aMprAfA7p+Ohao7qfdYM8JYfEVH1OhS/sSVIqbhFWsK/gxpbyaWV4uxHLoK57juH HbF6b9r02Rm2ZOoynWjaZRVndB3yMDnFNX8JaX64z0OwVBgOEAn30YdWShgljuedz4O4 gx5HVPh/KJmfogmn8Fj8+BdbdLBqBRLG0f+ZODSh7Px645GR06ar8PUc8rI8mzODI/rT pjWA== X-Gm-Message-State: AOJu0YzbOxTH0zfMywEP5Ui6Bx4+yRA5GUAZSJMm0GXAqmFXCcHWJI97 F8i+/H7FIYjKitzgsktTWKPLCMfTlYEQc11PS0+RsF1naOsoMilo1LiqGOjOQsY= X-Google-Smtp-Source: AGHT+IHqPwzhcmiM/FFm6l5Gaq1CDWR1urthcYvPs25MRFKeLPNrQy0Zb66y8K1jwvGHKkPMjZAXPw== X-Received: by 2002:a19:8c58:0:b0:515:9783:938d with SMTP id i24-20020a198c58000000b005159783938dmr5304212lfj.63.1712576832419; Mon, 08 Apr 2024 04:47:12 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id g17-20020a19e051000000b005158ddab172sm1175549lfj.19.2024.04.08.04.47.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Apr 2024 04:47:11 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 08 Apr 2024 14:47:05 +0300 Subject: [PATCH 2/4] clk: qcom: dispcc-sm6350: fix DisplayPort clocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240408-dispcc-dp-clocks-v1-2-f9e44902c28d@linaro.org> References: <20240408-dispcc-dp-clocks-v1-0-f9e44902c28d@linaro.org> In-Reply-To: <20240408-dispcc-dp-clocks-v1-0-f9e44902c28d@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Konrad Dybcio , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1555; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=OsDfVmwigHiKLQONHsnbey3y8n9mOJj5tZKTmOviAn4=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmE9k9H5X8yWLigKleQcptLAkRmAVjhc0DUmetS t6V2YwGWdWJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZhPZPQAKCRCLPIo+Aiko 1VinCACL15UdGiAHHUzISh3SClQ/NVhj0nL6bIOISNQbcB/Y3jfnqOkEIdiL6uXtknAihDBevZq /N2gZ2INDcXqZDpYaMTwz7PB+w8qulCbwGuKHG9rrXlJSaqtvKBNv/wi2OYkRRA+KyXhGGewOA7 uWxcy/gtGLWqpucxCGaJJu3cEOCe0XiPMDXhOaJd6OXZW00rSu/rX1ioc6NPSAdz2ow+Wz83tQ5 txyqMynPFC1xcUv/1no3jrkkkHurBxz3SN8a3ZMfjBznYpMG317IlPTkSW9bsG7XqRj5aRZP3re 8oxcL6744FUt2kPjn1RFC0LTu7n/HlR/w6aIavhSjS+q2mrg X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On SM6350 DisplayPort link clocks use frequency tables inherited from the vendor kernel, it is not applicable in the upstream kernel. Drop frequency tables and use clk_byte2_ops for those clocks. Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM6350") Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Tested-by: Luca Weiss --- drivers/clk/qcom/dispcc-sm6350.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm6350.c b/drivers/clk/qcom/dispcc-sm6350.c index 839435362010..e4b7464c4d0e 100644 --- a/drivers/clk/qcom/dispcc-sm6350.c +++ b/drivers/clk/qcom/dispcc-sm6350.c @@ -221,26 +221,17 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { }, }; -static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { - F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - { } -}; - static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { .cmd_rcgr = 0x10f8, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_0, - .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link_clk_src", .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; From patchwork Mon Apr 8 11:47:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 787016 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE2C669DF5 for ; Mon, 8 Apr 2024 11:47:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712576836; cv=none; b=q2IWtArI4ZFiwMS7lJMKDZtOlJI3ykT8B36nX/5C8pfZw7fWTr2V1f1jxSIK5550USHR8weH4yMZ+qhAThvmrYawZoUo+0rmKCXUHtQoIs3N0BzMTwPa39veobasUhTHfWlA7Esuj8M7LYwOMTEwyiXbGu1/K4bESfdjZIK43UI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712576836; c=relaxed/simple; bh=FhQoTr0AvrLk6QoJyJABfGJzAUBSTtD195jvIOJBmlk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HDnrmsqVK3l84rgQur/iM59iBjAFoj4SijTJhzE6CDPjfxox7ULgIXky6EB6dNdRuqXIJLKhezLIhaRgA2fIL+tk2zzlqUuL8tExm6cPEHN8FUnK5udSo73ApOSeApUwP09uSP7KOp6JDbrL3+FV8OZqDfaa5vciUnev45/QAok= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=d+izmYXK; arc=none smtp.client-ip=209.85.167.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="d+izmYXK" Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-516d487659bso3975362e87.2 for ; Mon, 08 Apr 2024 04:47:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712576833; x=1713181633; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=cfh+IFGGFO50cagmdMAMy2wvELw0DUI2fSJUlsAEF90=; b=d+izmYXKe/iZeQ21Aka/4JDA1Qpa3H2PBuWSQjgyouCe4U7pfi7Izu9O4jwHnu95hW a03i1m6voL83pQiqJElPztguUGxnxuPhqov3O9U94wDIeO5nAtNQLpnhSYjs93RTBLiV COd6P6R1BFN81GIKo9+5b2EJ8/wcf8O4KwD+vBe+/udvu/+CwT49PTZsc+Ncy8NCn1iJ 4XNzXX/UQuzCZtZFbZ0acWmByZg/zkAtr8r3Y2EPSCOpF8W1bu4L7P8c/45nPMmj8DY7 7dM6rGCjVgb9mz2DhRZ91SkEy9waiG/RI1f9TVOt8jrFn42a3FL5f7zoYUpEMs+8dasy 9nEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712576833; x=1713181633; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cfh+IFGGFO50cagmdMAMy2wvELw0DUI2fSJUlsAEF90=; b=nb27ENLBZcElB/A+NoZN7Yh09fzeR/F9DEK/xbayCOFfXDo1AzTeO9sRXyp2d/47On 0y6xBakbmjASqhynuRhzd8rfqI/LwAQMj8v6DFFLD5vX8PJ9D1vGr3r20YDYQeuVhHZ7 SCNLx7t9+6sJJHQJxnzDmjQrAd5o/uSx16J1u/Oz3xKqVsNazikOpXsY9BNQyw2OsGxP RYHLqTQroIdgUca+6ra4PEmg3yI2qrRSf4yNex84fIRWDZOva4n0fnAKajsD1A4cO4Wu OIr7qTJQFWkmA6d4mRdDvFTn8hm4U4fRfELpwYcScNwKKKl+NIe97QYcmDnFt7q4n4Ab TXJQ== X-Gm-Message-State: AOJu0YzR1Djk6P3zUGpYgq9+LXtsT8JRXiycLfIqrVMfskCki/Ra9Eob S9B9zDW9DOxOPqGgEv8KEek+4xRb5KtNrR77m2SwXwTxx+moLuKgGwYGvO2StAKAUwDNmDfq6c+ g X-Google-Smtp-Source: AGHT+IFXUVN/VS8k+F/6ACOo9SxvRvCzqxWsfE59GivhPlSyoOrlRRZN5re/crSCy843/biTKnYZnA== X-Received: by 2002:a05:6512:3134:b0:516:b148:6d8 with SMTP id p20-20020a056512313400b00516b14806d8mr6215011lfd.50.1712576833060; Mon, 08 Apr 2024 04:47:13 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id g17-20020a19e051000000b005158ddab172sm1175549lfj.19.2024.04.08.04.47.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Apr 2024 04:47:12 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 08 Apr 2024 14:47:06 +0300 Subject: [PATCH 3/4] clk: qcom: dispcc-sm8550: fix DisplayPort clocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240408-dispcc-dp-clocks-v1-3-f9e44902c28d@linaro.org> References: <20240408-dispcc-dp-clocks-v1-0-f9e44902c28d@linaro.org> In-Reply-To: <20240408-dispcc-dp-clocks-v1-0-f9e44902c28d@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Konrad Dybcio , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3040; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=FhQoTr0AvrLk6QoJyJABfGJzAUBSTtD195jvIOJBmlk=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmE9k9wFt9eN1/J0kZNA4RledruJ4qqlYwBoldH 66kpS1s4B6JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZhPZPQAKCRCLPIo+Aiko 1cMUB/9weyhr1QSQlO12vN8YefYoycnkjThsV7v5ONcRuOBjr37FeLtdRjyjeTs9CNkV3NaQpeE eL6rptscrOy1xgpmiAnKt9B7w38fZaHx/psoM0nwED/Jx0ROTlFOG89j6b4ZbrjtG4ChKOOn7oj K1sdjYuB739rdQSF8wmVxMoNQ333uc3naBRssgQmK3TFdzNp3pR9/6qGiZMNfSqN03Ko23sEdXZ es8k/pjATXBRp11MKz0pSxY2JekxtWzqjsHiYEOk3AXHbaOSDNZvF04UREovmZvfZbYQCH8/npJ LbueZm+lI3gkBqPqEFwI2gx4MB8Kc4PKZX8TR35LBb4OdDp7 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On SM8550 DisplayPort link clocks use frequency tables inherited from the vendor kernel, it is not applicable in the upstream kernel. Drop frequency tables and use clk_byte2_ops for those clocks. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Tested-by: Neil Armstrong # on SM8550-HDK --- drivers/clk/qcom/dispcc-sm8550.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c index 3672c73ac11c..38ecea805503 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -345,26 +345,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { }, }; -static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = { - F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - { } -}; - static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { .cmd_rcgr = 0x8170, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_7, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx0_link_clk_src", .parent_data = disp_cc_parent_data_7, .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; @@ -418,13 +409,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx1_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; @@ -478,13 +468,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx2_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; @@ -538,13 +527,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx3_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; From patchwork Mon Apr 8 11:47:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 787619 Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C2DD6A329 for ; Mon, 8 Apr 2024 11:47:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712576837; cv=none; b=q6b4xZcK4hxdZH01APy3nS/eoH656VNMSBo4rMZvv+4kuZshttCQ++l7XzRwLgLR9A/+x3Il4mHmJlLmeGqfE9utAugcveTJTgbVESwIDiLWCpJ0d5SfmtHENceLx78BNeX5ul5YQnBTyCPUf6XQItx0BLmgtN+Tx617sivCk60= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712576837; c=relaxed/simple; bh=IKtUHbqglcvzb700IveFFW+Q8Qyh3/7h1q+qa+Dlnpg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rww0F+inGiUlxVEfTFdUuc4UPyTd2MRfRyZHxOO0OVe7C0ibRrqdeduXOm0oN9pkufDeX/DbqmmzWGjqIkx+CXya3Ml84hG2kcN8pzzBqjA+tvkFzN17ReBpwvb+n6kUm8h7xlQp0/+xyUIGPPRE5a/A1NxIFjw/QaP5shb/toc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=aC3TH4m9; arc=none smtp.client-ip=209.85.167.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="aC3TH4m9" Received: by mail-lf1-f42.google.com with SMTP id 2adb3069b0e04-51381021af1so6901286e87.0 for ; Mon, 08 Apr 2024 04:47:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712576834; x=1713181634; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=CN1hLTpzqQmwOO4CNeIWzvBcYoI/2klJca3uhjxthOE=; b=aC3TH4m98bL6luMYSOJPqsvbLz7bOYvQ9G/9lI+dPbkt8BUy/9daGrQzFfCpW25Xy8 x94G8KDbcfzxxbm0U3PRuW1/MUGqbI67Fy3lCyQtiGN8Q6UHWfCGOeEMc0m036r+gPYa RVH5qiB0xU+qX2iDX0PCRLWosIQ+4X3f525yNjsQuEtFk0KdEjyZHouT4FgJXlI3vPf6 rlZ4NrVGHt6D0sIZPVkhlDIYxtpGhZcnHHBlWPknOzvYFrF6rDq2CfDZCbcNz7COdvby TBXv6cffOVlc7oLXN01nBpI/yikJQ6wTfSYnczq9x8+2DUcQTJwue+EDiD73JGS11tfZ PX7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712576834; x=1713181634; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CN1hLTpzqQmwOO4CNeIWzvBcYoI/2klJca3uhjxthOE=; b=cS6gi1mwdxPExAXOGzASCHxqKZIQHNh22N+ioGgi9kh0jCxCFJU8iB4lqf8+dNP0h3 OCONSkG25geXg/LnPNZZEprxE0GmGg1WYK8SzTxx4CgOMUqwHoZLVlinCacAb0nK9pDp OdkHNcMpdum9eNRrazP02qzXoFKlkVp+UaPeRal5NTIACAdoc+pzFOfsIzk6vwJ4IVI4 ekW4FnLB9Bhnn5ZrkCMhLuS5oryeuy5SpvRF6g++92R9WdmOJE3uu4UplyxbStonpArO BjcgZFtc9Rxc3ZvqmE/SiYfMi7OPX5D61ryPVFhF8aJ21CHGZDnkfDHrk7kU6NN/ATou nxQQ== X-Gm-Message-State: AOJu0YyYRIA9QYbPTcrBY5SvKxVT7EtNbfGW5My9a+MYpvM4aSXzyJQh M1REUyHWHxD2t5QFdkOlTb5bYyxm2+H1R/5Ugbqqt9vY2nJ9Rc6ZPpMQIjyN3Rg= X-Google-Smtp-Source: AGHT+IGCm9bgFbhczRAIueF/v2N27cqAlm/rh8j3x6HKsHAKQr4mlMzDwMWZGS3pMDxQ7sfFiN4qAA== X-Received: by 2002:a19:700c:0:b0:516:cbca:5c9a with SMTP id h12-20020a19700c000000b00516cbca5c9amr7461316lfc.9.1712576833913; Mon, 08 Apr 2024 04:47:13 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id g17-20020a19e051000000b005158ddab172sm1175549lfj.19.2024.04.08.04.47.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Apr 2024 04:47:13 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 08 Apr 2024 14:47:07 +0300 Subject: [PATCH 4/4] clk: qcom: dispcc-sm8650: fix DisplayPort clocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240408-dispcc-dp-clocks-v1-4-f9e44902c28d@linaro.org> References: <20240408-dispcc-dp-clocks-v1-0-f9e44902c28d@linaro.org> In-Reply-To: <20240408-dispcc-dp-clocks-v1-0-f9e44902c28d@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Konrad Dybcio , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3086; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=IKtUHbqglcvzb700IveFFW+Q8Qyh3/7h1q+qa+Dlnpg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmE9k+tfTJFbid+O44LrGG5OcDG+49XUQpLvoEc OH1gSW1GiWJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZhPZPgAKCRCLPIo+Aiko 1cKqCACei1rb7cgkzuppGz5EJiZ/ALBWOZza6WybcZXJtvDt6MuYNZuWKLlKByjkASGOqR8InSM fUeY7rLiIhJObbk8e6UwjRBLqoVJp/+S6X5jLaud5zLizXfSUK/BSQd/hmdnLFbIUAuaw+xsQ8w aPNYskOxSp3HyuB6qmyfC9rNatdicPvOfc5d/lYJ7Z4woa8hSKHBIUCNwjQucB1tCPOJ0xF5Kn1 wZUmoElq7CwAi926gNqoPcithV+U1EjdvpOaxsd0BZlyr4xhUQKKg64c7tnk22MCDFpz9EQzuV5 thpvqUS22cf3ZFNME5JbnZXHYZ9IaMMsS8P+Y4W2JWnGVOTc X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On SM8650 DisplayPort link clocks use frequency tables inherited from the vendor kernel, it is not applicable in the upstream kernel. Drop frequency tables and use clk_byte2_ops for those clocks. Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver") Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8650.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c index 9539db0d9114..3eb64bcad487 100644 --- a/drivers/clk/qcom/dispcc-sm8650.c +++ b/drivers/clk/qcom/dispcc-sm8650.c @@ -343,26 +343,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { }, }; -static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = { - F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - { } -}; - static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { .cmd_rcgr = 0x8170, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_7, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx0_link_clk_src", .parent_data = disp_cc_parent_data_7, .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; @@ -416,13 +407,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx1_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; @@ -476,13 +466,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx2_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; @@ -536,13 +525,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx3_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, };