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a=openpgp-sha256; l=2202; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=GwVgZdE26NDUHVKCdQIs4DldqMTJkpU3Pk/WgyxXJjg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmEzIOsWZE0K6uxILhzHgEr/EN647OWFab82UmR AyrlutwlYCJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZhMyDgAKCRCLPIo+Aiko 1cfEB/9qTNSpJTLxEWDO34OifP37mWXh2knrveFUXkNPOwZnHoUWkEILGgPqYqazzTe3OuH6umb pydAY9tIgE+K9P8+dnKNxHOoL4glYzY3UBc3Y9mnbYmMC8avnPvzmZUYGmEuVlM5DtEC9zNJfdQ ap/+i87+GYqE+zyPmK1vKsuFf+ez2Z/LSmgt2jbCSEHkQ1wKhNMwCEYBzvmORhHWosl824MEOCO wU/NYpatsxsPS+B1K4xt+wjROTH9iU1buyX99DKQX2Bn6GyQ8GBo4Y/j/V31WQuPghZW0SNYPQv z1z+v6cYP/a6OxQ04iIpiW7Hl55SUgtCEj/tR4Ba4gobAJg8 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A From: Sumit Semwal LG SW43408 is 1080x2160, 4-lane MIPI-DSI panel present on Google Pixel 3 phones. Signed-off-by: Vinod Koul Signed-off-by: Sumit Semwal [caleb: convert to yaml] Signed-off-by: Caleb Connolly Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../bindings/display/panel/lg,sw43408.yaml | 62 ++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml b/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml new file mode 100644 index 000000000000..1e08648f5bc7 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/lg,sw43408.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LG SW43408 1080x2160 DSI panel + +maintainers: + - Caleb Connolly + +description: + This panel is used on the Pixel 3, it is a 60hz OLED panel which + required DSC (Display Stream Compression) and has rounded corners. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - const: lg,sw43408 + + reg: true + port: true + vddi-supply: true + vpnl-supply: true + reset-gpios: true + +required: + - compatible + - vddi-supply + - vpnl-supply + - reset-gpios + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "lg,sw43408"; + reg = <0>; + + vddi-supply = <&vreg_l14a_1p88>; + vpnl-supply = <&vreg_l28a_3p0>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + port { + endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; + }; +... 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a=openpgp-sha256; l=2601; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Jn//Iw9esRD8TM8P085ElFyT7MDokBKCt93Vkd/VJlo=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ5qwER+vpasEz4a1AuuUvyk/ClxTNZ9XrWfPkpYzrNpn7 ly+eWl/J6MxCwMjF4OsmCKLT0HL1JhNyWEfdkythxnEygQyhYGLUwAmYmrL/leumqn/090ehhMb Vl2yDBa4cWavqbey7s/rqycqn7jPJvcpo+jfw+hXBTstnTzTFp0MYPWKdPZhiV53S0CM3S8ie3G ltprHZHkH+YdCTlzHni2xP/hlqn3e9NklJ88EHJy04ZJMdNXzuvr/v1xOhdvvnDgl+HcuW/H04I MywfXXrDeum613xVtLRjzV41zvWSNdmxOTFn9i8XrncTeB85+raztbJdOb7W9mB/TOnGZ48MIJj kj7iIC4Xdm9U8u1Lni12Mk9TEkILVe5UH71pJjCqlcsZ9N4Z/xZoBbqf1h+Mlf1JsHopFfNdmqW DyKM/Sxuugv29XptVHg0ZWdVnWEcx29eN9k1Mw2CObRSAA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The functions mipi_dsi_compression_mode() and mipi_dsi_picture_parameter_set() return 0-or-error rather than a buffer size. Follow example of other similar MIPI DSI functions and use int return type instead of size_t. Fixes: f4dea1aaa9a1 ("drm/dsi: add helpers for DSI compression mode and PPS packets") Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/drm_mipi_dsi.c | 6 +++--- include/drm/drm_mipi_dsi.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c index ef6e416522f8..9874ff6d4718 100644 --- a/drivers/gpu/drm/drm_mipi_dsi.c +++ b/drivers/gpu/drm/drm_mipi_dsi.c @@ -654,7 +654,7 @@ EXPORT_SYMBOL(mipi_dsi_set_maximum_return_packet_size); * * Return: 0 on success or a negative error code on failure. */ -ssize_t mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable) +int mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable) { /* Note: Needs updating for non-default PPS or algorithm */ u8 tx[2] = { enable << 0, 0 }; @@ -679,8 +679,8 @@ EXPORT_SYMBOL(mipi_dsi_compression_mode); * * Return: 0 on success or a negative error code on failure. */ -ssize_t mipi_dsi_picture_parameter_set(struct mipi_dsi_device *dsi, - const struct drm_dsc_picture_parameter_set *pps) +int mipi_dsi_picture_parameter_set(struct mipi_dsi_device *dsi, + const struct drm_dsc_picture_parameter_set *pps) { struct mipi_dsi_msg msg = { .channel = dsi->channel, diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index c0aec0d4d664..3011d33eccbd 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -241,9 +241,9 @@ int mipi_dsi_shutdown_peripheral(struct mipi_dsi_device *dsi); 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It provides a way to specify the algorithm and PPS selector. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten --- drivers/gpu/drm/drm_mipi_dsi.c | 41 ++++++++++++++++++++++++++++++++++------- include/drm/drm_mipi_dsi.h | 9 +++++++++ 2 files changed, 43 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c index 9874ff6d4718..795001bb7ff1 100644 --- a/drivers/gpu/drm/drm_mipi_dsi.c +++ b/drivers/gpu/drm/drm_mipi_dsi.c @@ -645,29 +645,56 @@ int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi, EXPORT_SYMBOL(mipi_dsi_set_maximum_return_packet_size); /** - * mipi_dsi_compression_mode() - enable/disable DSC on the peripheral + * mipi_dsi_compression_mode_ext() - enable/disable DSC on the peripheral * @dsi: DSI peripheral device * @enable: Whether to enable or disable the DSC + * @algo: Selected compression algorithm + * @pps_selector: Select PPS from the table of pre-stored or uploaded PPS entries * - * Enable or disable Display Stream Compression on the peripheral using the - * default Picture Parameter Set and VESA DSC 1.1 algorithm. + * Enable or disable Display Stream Compression on the peripheral. * * Return: 0 on success or a negative error code on failure. */ -int mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable) +int mipi_dsi_compression_mode_ext(struct mipi_dsi_device *dsi, bool enable, + enum mipi_dsi_compression_algo algo, + unsigned int pps_selector) { - /* Note: Needs updating for non-default PPS or algorithm */ - u8 tx[2] = { enable << 0, 0 }; + u8 tx[2] = { }; struct mipi_dsi_msg msg = { .channel = dsi->channel, .type = MIPI_DSI_COMPRESSION_MODE, .tx_len = sizeof(tx), .tx_buf = tx, }; - int ret = mipi_dsi_device_transfer(dsi, &msg); + int ret; + + if (algo > 3 || pps_selector > 3) + return -EINVAL; + + tx[0] = (enable << 0) | + (algo << 1) | + (pps_selector << 4); + + ret = mipi_dsi_device_transfer(dsi, &msg); return (ret < 0) ? ret : 0; } +EXPORT_SYMBOL(mipi_dsi_compression_mode_ext); + +/** + * mipi_dsi_compression_mode() - enable/disable DSC on the peripheral + * @dsi: DSI peripheral device + * @enable: Whether to enable or disable the DSC + * + * Enable or disable Display Stream Compression on the peripheral using the + * default Picture Parameter Set and VESA DSC 1.1 algorithm. + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable) +{ + return mipi_dsi_compression_mode_ext(dsi, enable, MIPI_DSI_COMPRESSION_DSC, 0); +} EXPORT_SYMBOL(mipi_dsi_compression_mode); /** diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index 3011d33eccbd..82b1cc434ea3 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -226,6 +226,12 @@ static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt) return -EINVAL; } +enum mipi_dsi_compression_algo { + MIPI_DSI_COMPRESSION_DSC = 0, + MIPI_DSI_COMPRESSION_VENDOR = 3, + /* other two values are reserved, DSI 1.3 */ +}; + struct mipi_dsi_device * mipi_dsi_device_register_full(struct mipi_dsi_host *host, const struct mipi_dsi_device_info *info); @@ -242,6 +248,9 @@ int mipi_dsi_turn_on_peripheral(struct mipi_dsi_device *dsi); int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi, u16 value); int mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable); +int mipi_dsi_compression_mode_ext(struct mipi_dsi_device *dsi, bool enable, + enum mipi_dsi_compression_algo algo, + unsigned int pps_selector); int mipi_dsi_picture_parameter_set(struct mipi_dsi_device *dsi, const struct drm_dsc_picture_parameter_set *pps); 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a=openpgp-sha256; l=12311; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=rBO0yC8UpgMVwvLTQTxZhiafy7u8OGxH1e/YYI9RoRg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmEzIPVSR9B6y/jl9SjHHOD6e1y+5UOJtLZGSGE meJBTYYLU6JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZhMyDwAKCRCLPIo+Aiko 1crWB/0c/JWNIrhM/3rJ8TpqKfuBOX5Ax4nmpJbllKt4HwF+rqaV88KP7T3TNVJ3m0ldFDwJI+A 1PvXReP1ttFEVQBP+4zvIqyzgP1t6xkQmRjU5BA/CoNkd7bXQa4fZv1ckXuwbarQxT9mh9ATq/H iBbq7AeHdEVOUJ13Mb8wXipLLC3Dw5rXmLF5efIXQW7uxy5aYwyZ1aztb8XUowcLpqGgmeykVQE VCxVTNdzNOAQHRcijy1NMmim3ShqhGleyIh6oSqIOVOSxLJTR6UnC/qW1T6WCT998RnMejCWEpn Vr37VHvuOxak5wyLN17EHFEUtHUAi3Mtd3Lkn05qhyczpjbT X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A From: Sumit Semwal LG SW43408 is 1080x2160@60Hz, 4-lane MIPI-DSI panel, used in some Google Pixel-3 phones. Signed-off-by: Sumit Semwal [vinod: Add DSC support] Signed-off-by: Vinod Koul [caleb: cleanup and support turning off the panel] Signed-off-by: Caleb Connolly [DB: partially rewrote the driver and fixed DSC programming] Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- MAINTAINERS | 8 + drivers/gpu/drm/panel/Kconfig | 11 ++ drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-lg-sw43408.c | 323 +++++++++++++++++++++++++++++++ 4 files changed, 343 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d36c19c1bf81..4cc43c16e07e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6789,6 +6789,14 @@ S: Maintained F: Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml F: drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +DRM DRIVER FOR LG SW43408 PANELS +M: Sumit Semwal +M: Caleb Connolly +S: Maintained +T: git git://anongit.freedesktop.org/drm/drm-misc +F: Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml +F: drivers/gpu/drm/panel/panel-lg-sw43408.c + DRM DRIVER FOR LOGICVC DISPLAY CONTROLLER M: Paul Kocialkowski S: Supported diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 6dc451f58a3e..4dc435fd9a44 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -335,6 +335,17 @@ config DRM_PANEL_LG_LG4573 Say Y here if you want to enable support for LG4573 RGB panel. To compile this driver as a module, choose M here. +config DRM_PANEL_LG_SW43408 + tristate "LG SW43408 panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for LG sw43408 panel. + The panel has a 1080x2160@60Hz resolution and uses 24 bit RGB per + pixel. It provides a MIPI DSI interface to the host and has a + built-in LED backlight. + config DRM_PANEL_MAGNACHIP_D53E6EA8966 tristate "Magnachip D53E6EA8966 DSI panel" depends on OF && SPI diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 24a02655d726..0b40b010e8e7 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W) += panel-leadtek-ltk050h3146w.o obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829) += panel-leadtek-ltk500hd1829.o obj-$(CONFIG_DRM_PANEL_LG_LB035Q02) += panel-lg-lb035q02.o obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o +obj-$(CONFIG_DRM_PANEL_LG_SW43408) += panel-lg-sw43408.o obj-$(CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966) += panel-magnachip-d53e6ea8966.o obj-$(CONFIG_DRM_PANEL_NEC_NL8048HL11) += panel-nec-nl8048hl11.o obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3051D) += panel-newvision-nv3051d.o diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c b/drivers/gpu/drm/panel/panel-lg-sw43408.c new file mode 100644 index 000000000000..bd9706ae7615 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-2024 Linaro Ltd + * Author: Sumit Semwal + * Dmitry Baryshkov + */ + +#include +#include +#include +#include +#include +#include + +#include