From patchwork Thu Apr 4 04:59:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 786148 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AF98B286A6; Thu, 4 Apr 2024 05:10:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=153.127.30.23 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712207430; cv=none; b=k/UaKLjhHvUJCkGFKVDQsq5roFjamacuGXV/4tB+HQ/XjmAIljIZ7v58x1BWQ8p8NlEiSQh9JkzEVUd3UAgBreyP2O8e2I7n1yh0Nr96tbbXrAKhUQ7N8T+xf7KoxuIYhOGA9F+zsOfFIBWlPATwHA0DDL7VoBgyXI6YvnsjZPI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712207430; c=relaxed/simple; bh=X5xhUmYdUi/YHxJqfjY+z9LAkIgLaCslllhJ8YzjKP4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iGLkFxzXHQD7pmXC80f6z6wZuKqd+9U/ZjWus38ocAb08ghp3Os6C6QwQUiuK0cuLPKb0J3po0WhWaXVUHisz+MN3L49DgmAVp6YRBSlHFvFXDHXRLRoQk5cHsYW6EqWyFO/WqRNuYJFukQeTh/mWXIAWlQwa2GcbeZZIpUswOE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp; spf=fail smtp.mailfrom=users.sourceforge.jp; arc=none smtp.client-ip=153.127.30.23 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=users.sourceforge.jp Received: from SIOS1075.ysato.name (al128006.dynamic.ppp.asahi-net.or.jp [111.234.128.6]) by sakura.ysato.name (Postfix) with ESMTPSA id C98F21C022E; Thu, 4 Apr 2024 14:00:36 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Damien Le Moal , Niklas Cassel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Thomas Gleixner , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Daniel Lezcano , Rich Felker , John Paul Adrian Glaubitz , Lee Jones , Helge Deller , Heiko Stuebner , Shawn Guo , Sebastian Reichel , Chris Morgan , Linus Walleij , Arnd Bergmann , David Rientjes , Hyeonggon Yoo <42.hyeyoo@gmail.com>, Vlastimil Babka , Baoquan He , Andrew Morton , Guenter Roeck , Kefeng Wang , Stephen Rothwell , Javier Martinez Canillas , Guo Ren , Azeem Shaikh , Max Filippov , Jonathan Corbet , Jacky Huang , Herve Codina , Manikanta Guntupalli , Anup Patel , Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Sam Ravnborg , Sergey Shtylyov , Laurent Pinchart , linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, linux-fbdev@vger.kernel.org Subject: [PATCH v7 01/37] sh: passing FDT address to kernel startup. Date: Thu, 4 Apr 2024 13:59:26 +0900 Message-Id: <58ead9bb7def6e12a46dd7ad2fee716dc17e44f7.1712205900.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 R4 is caller saved in SH ABI. Save it so it doesn't get corrupted until it's needed for initialization. Signed-off-by: Yoshinori Sato Reviewed-by: Geert Uytterhoeven --- arch/sh/boot/compressed/head_32.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/sh/boot/compressed/head_32.S b/arch/sh/boot/compressed/head_32.S index 7bb168133dbb..6be59851122e 100644 --- a/arch/sh/boot/compressed/head_32.S +++ b/arch/sh/boot/compressed/head_32.S @@ -15,7 +15,8 @@ startup: /* Load initial status register */ mov.l init_sr, r1 ldc r1, sr - + /* Save FDT address */ + mov r4, r13 /* Move myself to proper location if necessary */ mova 1f, r0 mov.l 1f, r2 @@ -84,7 +85,7 @@ l1: /* Jump to the start of the decompressed kernel */ mov.l kernel_start_addr, r0 jmp @r0 - nop + mov r13, r4 .align 2 bss_start_addr: From patchwork Thu Apr 4 04:59:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 786147 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B731729CF1; Thu, 4 Apr 2024 05:10:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=153.127.30.23 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712207431; cv=none; b=Nz4iTPoPY8UgoW8rG7n/M8M8IK+OM2ukTB+zf6SK3v01O9CQ1t5PIRALIeJqHqRHdXkfDa2G/Ck53jVAL2vdgvr2Kax0DU8WdmgAs/dF4FYgekwbWQzWWU+ayyUUwqrwiidmMe/N/b5tvVWeo337nqkdbkfALs+2Y15xK/YBCwo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712207431; c=relaxed/simple; bh=Mlar4k36vsGupOpHsgffs9x7mHFF2T26ers8FFl0RyI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UkLGdXMavcUNxmNZNs7zWsSARSEaqh07LxlUDj+e9g2igAo1xT2aFC+3n6EH5RwjSK3n5BNwbm6IjX2yg5UPJYd7Kx0GNRf57E2F+yKJRgwaFZ8TukLiG8uuxBbPFHXTWBpMp7wpw6yU49RHfub6Jtt+eOgW8HvHXfgW6jn0pJ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp; spf=fail smtp.mailfrom=users.sourceforge.jp; arc=none smtp.client-ip=153.127.30.23 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=users.sourceforge.jp Received: from SIOS1075.ysato.name (al128006.dynamic.ppp.asahi-net.or.jp [111.234.128.6]) by sakura.ysato.name (Postfix) with ESMTPSA id 9BB021C0242; Thu, 4 Apr 2024 14:00:38 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Damien Le Moal , Niklas Cassel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Thomas Gleixner , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Daniel Lezcano , Rich Felker , John Paul Adrian Glaubitz , Lee Jones , Helge Deller , Heiko Stuebner , Shawn Guo , Sebastian Reichel , Chris Morgan , Linus Walleij , Arnd Bergmann , David Rientjes , Hyeonggon Yoo <42.hyeyoo@gmail.com>, Vlastimil Babka , Baoquan He , Andrew Morton , Guenter Roeck , Kefeng Wang , Stephen Rothwell , Javier Martinez Canillas , Guo Ren , Azeem Shaikh , Max Filippov , Jonathan Corbet , Jacky Huang , Herve Codina , Manikanta Guntupalli , Anup Patel , Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Sam Ravnborg , Sergey Shtylyov , Laurent Pinchart , linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, linux-fbdev@vger.kernel.org Subject: [PATCH v7 02/37] sh: Kconfig unified OF supported targets. Date: Thu, 4 Apr 2024 13:59:27 +0900 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Targets that support OF should be treated as one board. Signed-off-by: Yoshinori Sato --- arch/sh/Kconfig | 1 + arch/sh/boards/Kconfig | 23 +++++++++++++---------- 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 2ad3e29f0ebe..cbf48e69ad74 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -711,6 +711,7 @@ choice prompt "Kernel command line" optional default CMDLINE_OVERWRITE + depends on !OF || USE_BUILTIN_DTB help Setting this option allows the kernel command line arguments to be set. diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index 109bec4dad94..46387fd040ad 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -19,16 +19,9 @@ config SH_DEVICE_TREE select TIMER_OF select COMMON_CLK select GENERIC_CALIBRATE_DELAY - -config SH_JCORE_SOC - bool "J-Core SoC" - select SH_DEVICE_TREE - select CLKSRC_JCORE_PIT - select JCORE_AIC - depends on CPU_J2 - help - Select this option to include drivers core components of the - J-Core SoC, including interrupt controllers and timers. + select GENERIC_IRQ_CHIP + select SYS_SUPPORTS_PCI + select GENERIC_PCI_IOMAP if PCI config SH_SOLUTION_ENGINE bool "SolutionEngine" @@ -293,6 +286,7 @@ config SH_LANDISK bool "LANDISK" depends on CPU_SUBTYPE_SH7751R select HAVE_PCI + select SYS_SUPPORTS_PCI help I-O DATA DEVICE, INC. "LANDISK Series" support. @@ -369,6 +363,15 @@ config SH_APSH4AD0A help Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A. +config SH_OF_BOARD + bool "General Open Firmware boards" + select SH_DEVICE_TREE + select CLKSRC_JCORE_PIT if CPU_J2 + select JCORE_AIC if CPU_J2 + select HAVE_PCI if CPU_SUBTYPE_SH7751R + help + This board means general OF supported targets. + source "arch/sh/boards/mach-r2d/Kconfig" source "arch/sh/boards/mach-highlander/Kconfig" source "arch/sh/boards/mach-sdk7780/Kconfig" From patchwork Thu Apr 4 04:59:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 786157 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 722991CFA0; Thu, 4 Apr 2024 05:00:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=153.127.30.23 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712206850; cv=none; b=bjMswcDdcfDLugt4moes0qxAlOgE3Fil13/nTXvxCgAUvtxSLQIQF9ufT2PI8p/ThvGL5L0st2maW+sDj8pwPIeJpkWxHuAWO1JfydlNtgzDbVuTbz/Lg9dz8KMrpR2JOXHMpwIt8MN8ud//flWIqjdnw61LaUaSi64ShEgGbwA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712206850; c=relaxed/simple; bh=YdVR5VR9Dwt1XuaGLTGtEYBwDqKsBqzuokkPY3rn9Qc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VUI3zR09usuDM4atXJzSZfFN9QIzBtPTnM8/bIv/cxdbmDzJHWpqavTbk/6tDQ8BckmnSdbCfQQ0MEGaGxGQqJsfm6oYj+o6OPekRvbVQufl6WdCjR9ZSNfRB8LlH/K0+JWthtLh5Dm+o2IBKawdWVnmjMeXMJUEzCN/8UwlbEA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp; spf=fail smtp.mailfrom=users.sourceforge.jp; arc=none smtp.client-ip=153.127.30.23 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=users.sourceforge.jp Received: from SIOS1075.ysato.name (al128006.dynamic.ppp.asahi-net.or.jp [111.234.128.6]) by sakura.ysato.name (Postfix) with ESMTPSA id A98A31C04AD; Thu, 4 Apr 2024 14:00:45 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Damien Le Moal , Niklas Cassel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Thomas Gleixner , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Daniel Lezcano , Rich Felker , John Paul Adrian Glaubitz , Lee Jones , Helge Deller , Heiko Stuebner , Shawn Guo , Sebastian Reichel , Chris Morgan , Linus Walleij , Arnd Bergmann , David Rientjes , Hyeonggon Yoo <42.hyeyoo@gmail.com>, Vlastimil Babka , Baoquan He , Andrew Morton , Guenter Roeck , Kefeng Wang , Stephen Rothwell , Javier Martinez Canillas , Guo Ren , Azeem Shaikh , Max Filippov , Jonathan Corbet , Jacky Huang , Herve Codina , Manikanta Guntupalli , Anup Patel , Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Sam Ravnborg , Sergey Shtylyov , Laurent Pinchart , linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, linux-fbdev@vger.kernel.org Subject: [PATCH v7 06/37] sh: kernel/setup Update DT support. Date: Thu, 4 Apr 2024 13:59:31 +0900 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Fix extrnal fdt initialize and bootargs. Signed-off-by: Yoshinori Sato --- arch/sh/Kconfig | 23 +++++++++++------------ arch/sh/include/asm/setup.h | 1 + arch/sh/kernel/setup.c | 36 +++++++++++++++++++++++------------- 3 files changed, 35 insertions(+), 25 deletions(-) diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 6711cde0d973..242cf30e704d 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -708,17 +708,22 @@ config ROMIMAGE_MMCIF first part of the romImage which in turn loads the rest the kernel image to RAM using the MMCIF hardware block. +config CMDLINE + string "Kernel command line arguments string" + default "console=ttySC1,115200" + choice prompt "Kernel command line" - optional - default CMDLINE_OVERWRITE - depends on !OF || USE_BUILTIN_DTB + default CMDLINE_BOOTLOADER + +config CMDLINE_BOOTLOADER + bool "Use bootloader kernel arguments" help - Setting this option allows the kernel command line arguments - to be set. + Uses the command-line options passed by the boot loader. + If boot loader dosen't provide kernel argments, Use built-in argments. config CMDLINE_OVERWRITE - bool "Overwrite bootloader kernel arguments" + bool "Overwrite built-in kernel arguments" help Given string will overwrite any arguments passed in by a bootloader. @@ -730,12 +735,6 @@ config CMDLINE_EXTEND by a bootloader. endchoice - -config CMDLINE - string "Kernel command line arguments string" - depends on CMDLINE_OVERWRITE || CMDLINE_EXTEND - default "console=ttySC1,115200" - endmenu menu "Bus options" diff --git a/arch/sh/include/asm/setup.h b/arch/sh/include/asm/setup.h index fc807011187f..84bb23a771f3 100644 --- a/arch/sh/include/asm/setup.h +++ b/arch/sh/include/asm/setup.h @@ -21,5 +21,6 @@ void sh_mv_setup(void); void check_for_initrd(void); void per_cpu_trap_init(void); +void sh_fdt_init(phys_addr_t dt_phys); #endif /* _SH_SETUP_H */ diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index 620e5cf8ae1e..42e6292a40cf 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -269,8 +270,22 @@ void __ref sh_fdt_init(phys_addr_t dt_phys) void __init setup_arch(char **cmdline_p) { +#if defined(CONFIG_OF) && defined(CONFIG_OF_EARLY_FLATTREE) + if (IS_ENABLED(CONFIG_USE_BUILTIN_DTB)) { + /* Relocate Embedded DTB */ + unflatten_and_copy_device_tree(); + } else if (initial_boot_params) { + /* Reserve external DTB area */ + memblock_reserve(__pa(initial_boot_params), + fdt_totalsize(initial_boot_params)); + unflatten_device_tree(); + } + /* copy from /chosen/bootargs */ + strscpy(command_line, boot_command_line, COMMAND_LINE_SIZE); +#endif enable_mmu(); +#ifndef CONFIG_OF ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV); printk(KERN_NOTICE "Boot params:\n" @@ -299,14 +314,17 @@ void __init setup_arch(char **cmdline_p) bss_resource.start = virt_to_phys(__bss_start); bss_resource.end = virt_to_phys(__bss_stop)-1; -#ifdef CONFIG_CMDLINE_OVERWRITE - strscpy(command_line, CONFIG_CMDLINE, sizeof(command_line)); -#else - strscpy(command_line, COMMAND_LINE, sizeof(command_line)); +#endif +#if !defined(CONFIG_OF) || defined(CONFIG_USE_BUILTIN_DTB) + if (*COMMAND_LINE) + strscpy(command_line, COMMAND_LINE, sizeof(command_line)); +#endif + if (*command_line == '\0' || IS_ENABLED(CONFIG_CMDLINE_OVERWRITE)) + /* Use built-in parameter */ + strscpy(command_line, CONFIG_CMDLINE, sizeof(command_line)); #ifdef CONFIG_CMDLINE_EXTEND strlcat(command_line, " ", sizeof(command_line)); strlcat(command_line, CONFIG_CMDLINE, sizeof(command_line)); -#endif #endif /* Save unparsed command line copy for /proc/cmdline */ @@ -322,14 +340,6 @@ void __init setup_arch(char **cmdline_p) /* Let earlyprintk output early console messages */ sh_early_platform_driver_probe("earlyprintk", 1, 1); -#ifdef CONFIG_OF_EARLY_FLATTREE -#ifdef CONFIG_USE_BUILTIN_DTB - unflatten_and_copy_device_tree(); -#else - unflatten_device_tree(); -#endif -#endif - paging_init(); /* Perform the machine specific initialisation */ From patchwork Thu Apr 4 04:59:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 786156 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 303CD45C06; Thu, 4 Apr 2024 05:00:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=153.127.30.23 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712206853; cv=none; b=ON37B7/dyEBiNXHaOSp9OMXtveiAynih/pncXLY5ewCCWndZ3TQtaq7n7qh1ZQYSdtDJMKflzBXplBZTp0+pfFyOO6P2UOtnxwceWv20MKMAINrqYv8xOxP42CIotpslk1kuoPvCFQ2qzLl2zxRTOZ2Nwe2b1kGPUV+iQqpOHSE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712206853; c=relaxed/simple; bh=AS26eaglS7RJBQUnl7T6NslU0tdNz/37Vg4rHtcxbk4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SnKaSDP3pJOUufwcb9GDPjKgLRfSzWOQY+4B7aIQIVNd6SeUz3SrkQuJ6nI0uhH8sh5+w2UdGZeqg2WMUuIDm7GIIHBUzqS4whkxg3XiBgBEtrnSoFFYgZyl1dLMkWuwMta7KVfypp7RjOJUMMqYPSSlPiuaKZ7X5cHIEmHPj4c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp; spf=fail smtp.mailfrom=users.sourceforge.jp; arc=none smtp.client-ip=153.127.30.23 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=users.sourceforge.jp Received: from SIOS1075.ysato.name (al128006.dynamic.ppp.asahi-net.or.jp [111.234.128.6]) by sakura.ysato.name (Postfix) with ESMTPSA id 415841C0675; Thu, 4 Apr 2024 14:00:49 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Damien Le Moal , Niklas Cassel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Thomas Gleixner , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Daniel Lezcano , Rich Felker , John Paul Adrian Glaubitz , Lee Jones , Helge Deller , Heiko Stuebner , Shawn Guo , Sebastian Reichel , Chris Morgan , Linus Walleij , Arnd Bergmann , David Rientjes , Hyeonggon Yoo <42.hyeyoo@gmail.com>, Vlastimil Babka , Baoquan He , Andrew Morton , Guenter Roeck , Kefeng Wang , Stephen Rothwell , Javier Martinez Canillas , Guo Ren , Azeem Shaikh , Max Filippov , Jonathan Corbet , Jacky Huang , Herve Codina , Manikanta Guntupalli , Anup Patel , Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Sam Ravnborg , Sergey Shtylyov , Laurent Pinchart , linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, linux-fbdev@vger.kernel.org Subject: [PATCH v7 08/37] clocksource: sh_tmu: CLOCKSOURCE support. Date: Thu, 4 Apr 2024 13:59:33 +0900 Message-Id: <4a9b59733c7a8e7d042f3987ca6bf601eea5b30d.1712205900.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Allows initialization as CLOCKSOURCE. Signed-off-by: Yoshinori Sato --- drivers/clocksource/sh_tmu.c | 198 ++++++++++++++++++++++++----------- 1 file changed, 134 insertions(+), 64 deletions(-) diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c index beffff81c00f..59f9da7fd987 100644 --- a/drivers/clocksource/sh_tmu.c +++ b/drivers/clocksource/sh_tmu.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include #include #include #include @@ -51,6 +53,7 @@ struct sh_tmu_channel { struct sh_tmu_device { struct platform_device *pdev; + struct device_node *np; void __iomem *mapbase; struct clk *clk; @@ -65,6 +68,7 @@ struct sh_tmu_device { bool has_clockevent; bool has_clocksource; + const char *name; }; #define TSTR -1 /* shared register */ @@ -148,8 +152,8 @@ static int __sh_tmu_enable(struct sh_tmu_channel *ch) /* enable clock */ ret = clk_enable(ch->tmu->clk); if (ret) { - dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n", - ch->index); + pr_err("%s ch%u: cannot enable clock\n", + ch->tmu->name, ch->index); return ret; } @@ -174,9 +178,10 @@ static int sh_tmu_enable(struct sh_tmu_channel *ch) if (ch->enable_count++ > 0) return 0; - pm_runtime_get_sync(&ch->tmu->pdev->dev); - dev_pm_syscore_device(&ch->tmu->pdev->dev, true); - + if (ch->tmu->pdev) { + pm_runtime_get_sync(&ch->tmu->pdev->dev); + dev_pm_syscore_device(&ch->tmu->pdev->dev, true); + } return __sh_tmu_enable(ch); } @@ -202,8 +207,10 @@ static void sh_tmu_disable(struct sh_tmu_channel *ch) __sh_tmu_disable(ch); - dev_pm_syscore_device(&ch->tmu->pdev->dev, false); - pm_runtime_put(&ch->tmu->pdev->dev); + if (ch->tmu->pdev) { + dev_pm_syscore_device(&ch->tmu->pdev->dev, false); + pm_runtime_put(&ch->tmu->pdev->dev); + } } static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta, @@ -245,7 +252,7 @@ static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs) +static inline struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs) { return container_of(cs, struct sh_tmu_channel, cs); } @@ -292,7 +299,8 @@ static void sh_tmu_clocksource_suspend(struct clocksource *cs) if (--ch->enable_count == 0) { __sh_tmu_disable(ch); - dev_pm_genpd_suspend(&ch->tmu->pdev->dev); + if (ch->tmu->pdev) + dev_pm_genpd_suspend(&ch->tmu->pdev->dev); } } @@ -304,7 +312,8 @@ static void sh_tmu_clocksource_resume(struct clocksource *cs) return; if (ch->enable_count++ == 0) { - dev_pm_genpd_resume(&ch->tmu->pdev->dev); + if (ch->tmu->pdev) + dev_pm_genpd_resume(&ch->tmu->pdev->dev); __sh_tmu_enable(ch); } } @@ -324,14 +333,14 @@ static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch, cs->mask = CLOCKSOURCE_MASK(32); cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; - dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n", - ch->index); + pr_info("%s ch%u: used as clock source\n", + ch->tmu->name, ch->index); clocksource_register_hz(cs, ch->tmu->rate); return 0; } -static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced) +static inline struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced) { return container_of(ced, struct sh_tmu_channel, ced); } @@ -364,8 +373,8 @@ static int sh_tmu_clock_event_set_state(struct clock_event_device *ced, if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) sh_tmu_disable(ch); - dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n", - ch->index, periodic ? "periodic" : "oneshot"); + pr_info("%s ch%u: used for %s clock events\n", + ch->tmu->name, ch->index, periodic ? "periodic" : "oneshot"); sh_tmu_clock_event_start(ch, periodic); return 0; } @@ -417,20 +426,22 @@ static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, ced->set_state_shutdown = sh_tmu_clock_event_shutdown; ced->set_state_periodic = sh_tmu_clock_event_set_periodic; ced->set_state_oneshot = sh_tmu_clock_event_set_oneshot; - ced->suspend = sh_tmu_clock_event_suspend; - ced->resume = sh_tmu_clock_event_resume; + if (ch->tmu->pdev) { + ced->suspend = sh_tmu_clock_event_suspend; + ced->resume = sh_tmu_clock_event_resume; + } - dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n", - ch->index); + pr_info("%s ch%u: used for clock events\n", + ch->tmu->name, ch->index); clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff); ret = request_irq(ch->irq, sh_tmu_interrupt, IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, - dev_name(&ch->tmu->pdev->dev), ch); + ch->tmu->name, ch); if (ret) { - dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n", - ch->index, ch->irq); + pr_err("%s ch%u: failed to request irq %d\n", + ch->tmu->name, ch->index, ch->irq); return; } } @@ -465,28 +476,36 @@ static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index, else ch->base = tmu->mapbase + 8 + ch->index * 12; - ch->irq = platform_get_irq(tmu->pdev, index); + if (tmu->pdev) + ch->irq = platform_get_irq(tmu->pdev, index); + if (tmu->np) + ch->irq = of_irq_get(tmu->np, index); + if (ch->irq < 0) return ch->irq; ch->cs_enabled = false; ch->enable_count = 0; - return sh_tmu_register(ch, dev_name(&tmu->pdev->dev), - clockevent, clocksource); + return sh_tmu_register(ch, tmu->name, clockevent, clocksource); } static int sh_tmu_map_memory(struct sh_tmu_device *tmu) { struct resource *res; - res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&tmu->pdev->dev, "failed to get I/O memory\n"); - return -ENXIO; + if (tmu->pdev) { + res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0); + if (!res) { + pr_err("sh_tmu failed to get I/O memory\n"); + return -ENXIO; + } + + tmu->mapbase = ioremap(res->start, resource_size(res)); } + if (tmu->np) + tmu->mapbase = of_iomap(tmu->np, 0); - tmu->mapbase = ioremap(res->start, resource_size(res)); if (tmu->mapbase == NULL) return -ENXIO; @@ -495,7 +514,12 @@ static int sh_tmu_map_memory(struct sh_tmu_device *tmu) static int sh_tmu_parse_dt(struct sh_tmu_device *tmu) { - struct device_node *np = tmu->pdev->dev.of_node; + struct device_node *np; + + if (tmu->pdev) + np = tmu->pdev->dev.of_node; + if (tmu->np) + np = tmu->np; tmu->model = SH_TMU; tmu->num_channels = 3; @@ -503,45 +527,19 @@ static int sh_tmu_parse_dt(struct sh_tmu_device *tmu) of_property_read_u32(np, "#renesas,channels", &tmu->num_channels); if (tmu->num_channels != 2 && tmu->num_channels != 3) { - dev_err(&tmu->pdev->dev, "invalid number of channels %u\n", - tmu->num_channels); + pr_err("%s: invalid number of channels %u\n", + tmu->name, tmu->num_channels); return -EINVAL; } return 0; } -static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) +static int sh_tmu_setup(struct sh_tmu_device *tmu) { unsigned int i; int ret; - tmu->pdev = pdev; - - raw_spin_lock_init(&tmu->lock); - - if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { - ret = sh_tmu_parse_dt(tmu); - if (ret < 0) - return ret; - } else if (pdev->dev.platform_data) { - const struct platform_device_id *id = pdev->id_entry; - struct sh_timer_config *cfg = pdev->dev.platform_data; - - tmu->model = id->driver_data; - tmu->num_channels = hweight8(cfg->channels_mask); - } else { - dev_err(&tmu->pdev->dev, "missing platform data\n"); - return -ENXIO; - } - - /* Get hold of clock. */ - tmu->clk = clk_get(&tmu->pdev->dev, "fck"); - if (IS_ERR(tmu->clk)) { - dev_err(&tmu->pdev->dev, "cannot get clock\n"); - return PTR_ERR(tmu->clk); - } - ret = clk_prepare(tmu->clk); if (ret < 0) goto err_clk_put; @@ -557,7 +555,7 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) /* Map the memory resource. */ ret = sh_tmu_map_memory(tmu); if (ret < 0) { - dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n"); + pr_err("%s: failed to remap I/O memory\n", tmu->name); goto err_clk_unprepare; } @@ -580,8 +578,6 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) goto err_unmap; } - platform_set_drvdata(pdev, tmu); - return 0; err_unmap: @@ -594,6 +590,39 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) return ret; } +static int sh_tmu_setup_pdev(struct sh_tmu_device *tmu, struct platform_device *pdev) +{ + int ret; + + tmu->pdev = pdev; + + raw_spin_lock_init(&tmu->lock); + + if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { + ret = sh_tmu_parse_dt(tmu); + if (ret < 0) + return ret; + } else if (pdev->dev.platform_data) { + const struct platform_device_id *id = pdev->id_entry; + struct sh_timer_config *cfg = pdev->dev.platform_data; + + tmu->model = id->driver_data; + tmu->num_channels = hweight8(cfg->channels_mask); + } else { + dev_err(&tmu->pdev->dev, "missing platform data\n"); + return -ENXIO; + } + + tmu->name = dev_name(&pdev->dev); + tmu->clk = clk_get(&tmu->pdev->dev, "fck"); + if (IS_ERR(tmu->clk)) { + dev_err(&tmu->pdev->dev, "cannot get clock\n"); + return PTR_ERR(tmu->clk); + } + + return sh_tmu_setup(tmu); +} + static int sh_tmu_probe(struct platform_device *pdev) { struct sh_tmu_device *tmu = platform_get_drvdata(pdev); @@ -613,12 +642,13 @@ static int sh_tmu_probe(struct platform_device *pdev) if (tmu == NULL) return -ENOMEM; - ret = sh_tmu_setup(tmu, pdev); + ret = sh_tmu_setup_pdev(tmu, pdev); if (ret) { kfree(tmu); pm_runtime_idle(&pdev->dev); return ret; } + platform_set_drvdata(pdev, tmu); if (is_sh_early_platform_device(pdev)) return 0; @@ -632,6 +662,45 @@ static int sh_tmu_probe(struct platform_device *pdev) return 0; } +static int sh_tmu_setup_of(struct sh_tmu_device *tmu, struct device_node *np) +{ + int ret; + + tmu->np = np; + raw_spin_lock_init(&tmu->lock); + + ret = sh_tmu_parse_dt(tmu); + if (ret < 0) + return ret; + + tmu->clk = of_clk_get(np, 0); + tmu->name = of_node_full_name(np); + + if (IS_ERR(tmu->clk)) { + pr_err("%pOF: cannot get clock\n", np); + return PTR_ERR(tmu->clk); + } + + return sh_tmu_setup(tmu); +} + +static int __init sh_tmu_of_register(struct device_node *np) +{ + struct sh_tmu_device *tmu; + int ret; + + tmu = kzalloc(sizeof(*tmu), GFP_KERNEL); + if (tmu == NULL) + return -ENOMEM; + + ret = sh_tmu_setup_of(tmu, np); + if (ret) { + kfree(tmu); + pr_warn("%pOF: Timer register failed (%d)", np, ret); + } + return ret; +} + static const struct platform_device_id sh_tmu_id_table[] = { { "sh-tmu", SH_TMU }, { "sh-tmu-sh3", SH_TMU_SH3 }, @@ -665,6 +734,7 @@ static void __exit sh_tmu_exit(void) platform_driver_unregister(&sh_tmu_device_driver); } +TIMER_OF_DECLARE(sh_tmu, "renesas,tmu", sh_tmu_of_register); #ifdef CONFIG_SUPERH sh_early_platform_init("earlytimer", &sh_tmu_device_driver); #endif From patchwork Thu Apr 4 04:59:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 786155 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 52EF65473D; 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dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=users.sourceforge.jp Received: from SIOS1075.ysato.name (al128006.dynamic.ppp.asahi-net.or.jp [111.234.128.6]) by sakura.ysato.name (Postfix) with ESMTPSA id 1B6FC1C0912; Thu, 4 Apr 2024 14:00:53 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Damien Le Moal , Niklas Cassel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Thomas Gleixner , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Daniel Lezcano , Rich Felker , John Paul Adrian Glaubitz , Lee Jones , Helge Deller , Heiko Stuebner , Shawn Guo , Sebastian Reichel , Chris Morgan , Linus Walleij , Arnd Bergmann , David Rientjes , Hyeonggon Yoo <42.hyeyoo@gmail.com>, Vlastimil Babka , Baoquan He , Andrew Morton , Guenter Roeck , Kefeng Wang , Stephen Rothwell , Javier Martinez Canillas , Guo Ren , Azeem Shaikh , Max Filippov , Jonathan Corbet , Jacky Huang , Herve Codina , Manikanta Guntupalli , Anup Patel , Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Sam Ravnborg , Sergey Shtylyov , Laurent Pinchart , linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, linux-fbdev@vger.kernel.org Subject: [PATCH v7 10/37] sh: Common PCI Framework driver support. Date: Thu, 4 Apr 2024 13:59:37 +0900 Message-Id: <1dc50e154999c1cf5f13949fdd7d049fa363c34b.1712205900.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add New OF based PCI Host driver. This driver conflicts some point in legacy PCI driver. To resolve the conflict, I made some changes to the legacy driver. Signed-off-by: Yoshinori Sato --- arch/sh/include/asm/io.h | 6 ++++++ arch/sh/include/asm/pci.h | 4 ++++ arch/sh/kernel/iomap.c | 18 ++++++++++++++++++ 3 files changed, 28 insertions(+) diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h index 5c544cf5201b..29b5f996cde3 100644 --- a/arch/sh/include/asm/io.h +++ b/arch/sh/include/asm/io.h @@ -20,6 +20,7 @@ #include #include #include +#include #define __IO_PREFIX generic #include @@ -310,4 +311,9 @@ unsigned long long poke_real_address_q(unsigned long long addr, int valid_phys_addr_range(phys_addr_t addr, size_t size); int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); +#if defined(CONFIG_PCI) && !defined(CONFIG_GENERIC_IOMAP) +#define pci_remap_iospace pci_remap_iospace +int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); +#endif + #endif /* __ASM_SH_IO_H */ diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h index 54c30126ea17..92b3bd604319 100644 --- a/arch/sh/include/asm/pci.h +++ b/arch/sh/include/asm/pci.h @@ -2,6 +2,7 @@ #ifndef __ASM_SH_PCI_H #define __ASM_SH_PCI_H +#ifndef CONFIG_SH_DEVICE_TREE /* Can be used to override the logic in pci_scan_bus for skipping already-configured bus numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the loader */ @@ -88,4 +89,7 @@ static inline int pci_proc_domain(struct pci_bus *bus) return hose->need_domain_info; } +#else /* CONFIG_SH_DEVICE_TREE */ +#include +#endif #endif /* __ASM_SH_PCI_H */ diff --git a/arch/sh/kernel/iomap.c b/arch/sh/kernel/iomap.c index 0a0dff4e66de..d1b8e496ca23 100644 --- a/arch/sh/kernel/iomap.c +++ b/arch/sh/kernel/iomap.c @@ -160,3 +160,21 @@ void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count) mmio_outsl(addr, src, count); } EXPORT_SYMBOL(iowrite32_rep); + +#if defined(pci_remap_iospace) +int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) +{ + unsigned long vaddr = res->start; + + if (!(res->flags & IORESOURCE_IO)) + return -EINVAL; + + if (res->end > IO_SPACE_LIMIT) + return -EINVAL; + + __set_io_port_base(phys_addr); + return vmap_page_range(vaddr, vaddr + resource_size(res), phys_addr, + pgprot_device(PAGE_KERNEL)); +} +EXPORT_SYMBOL(pci_remap_iospace); +#endif From patchwork Thu Apr 4 04:59:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 786154 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4A6EB5810C; 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dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=users.sourceforge.jp Received: from SIOS1075.ysato.name (al128006.dynamic.ppp.asahi-net.or.jp [111.234.128.6]) by sakura.ysato.name (Postfix) with ESMTPSA id 479581C08D7; Thu, 4 Apr 2024 14:00:57 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Damien Le Moal , Niklas Cassel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Thomas Gleixner , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Daniel Lezcano , Rich Felker , John Paul Adrian Glaubitz , Lee Jones , Helge Deller , Heiko Stuebner , Shawn Guo , Sebastian Reichel , Chris Morgan , Linus Walleij , Arnd Bergmann , David Rientjes , Hyeonggon Yoo <42.hyeyoo@gmail.com>, Vlastimil Babka , Baoquan He , Andrew Morton , Guenter Roeck , Kefeng Wang , Stephen Rothwell , Javier Martinez Canillas , Guo Ren , Azeem Shaikh , Max Filippov , Jonathan Corbet , Jacky Huang , Herve Codina , Manikanta Guntupalli , Anup Patel , Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Sam Ravnborg , Sergey Shtylyov , Laurent Pinchart , linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, linux-fbdev@vger.kernel.org Subject: [PATCH v7 12/37] dt-bindings: pci: pci-sh7751: Add SH7751 PCI Date: Thu, 4 Apr 2024 13:59:41 +0900 Message-Id: <5ab3c5952b49d7998734855e2ec1ee980795a724.1712205900.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Renesas SH7751 PCI Controller json-schema. Signed-off-by: Yoshinori Sato --- .../bindings/pci/renesas,sh7751-pci.yaml | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml diff --git a/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml b/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml new file mode 100644 index 000000000000..115c2bb67339 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/renesas,sh7751-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7751 PCI Host controller + +maintainers: + - Yoshinori Sato + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: renesas,sh7751-pci + + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: PCI Controller + - const: Bus State Controller + + "#interrupt-cells": + const: 1 + + "#address-cells": + const: 3 + + "#size-cells": + const: 2 + + ranges: true + + dma-ranges: true + + interrupt-controller: true + + renesas,bus-arbit-round-robin: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set DMA bus arbitration to round robin. + +required: + - compatible + - reg + - "#interrupt-cells" + - "#address-cells" + - "#size-cells" + - ranges + - interrupt-map + - interrupt-map-mask + +unevaluatedProperties: false + +examples: + - | + #include + pci@fe200000 { + compatible = "renesas,sh7751-pci"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-controller; + device_type = "pci"; + bus-range = <0 0>; + ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>, + <0x01000000 0 0x00000000 0xfe240000 0 0x00040000>; + dma-ranges = <0x02000000 0 0xc000000 0x0c000000 0 0x04000000>; + reg = <0xfe200000 0x0400>, + <0xff800000 0x0100>; + interrupt-map = <0x0000 0 0 1 &julianintc 5 IRQ_TYPE_LEVEL_LOW>, + <0x0000 0 0 2 &julianintc 6 IRQ_TYPE_LEVEL_LOW>, + <0x0000 0 0 3 &julianintc 7 IRQ_TYPE_LEVEL_LOW>, + <0x0000 0 0 4 &julianintc 8 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 1 &julianintc 6 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 2 &julianintc 7 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 3 &julianintc 8 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 4 &julianintc 5 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 1 &julianintc 7 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 2 &julianintc 8 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 3 &julianintc 5 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 4 &julianintc 6 IRQ_TYPE_LEVEL_LOW>; + interrupt-map-mask = <0x1800 0 0 7>; + }; From patchwork Thu Apr 4 04:59:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 786153 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 35AD45FB83; Thu, 4 Apr 2024 05:01:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=153.127.30.23 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712206865; cv=none; b=S5uORbiDPDZOe5Xxv0m2KK9fnNrFJhh/VeWL9cJCvwbqHJSss8UNmM3yFfUCQW10Jg/2YtbvGIby436RhzXGYf5/kU3orlFyGgeQMEkmA6bRz6MIe8WXqtnUGFmc0SCQOWvqZqh8bFZL6prcETe6qcfUUHdJQxTstTHTqZ98Fws= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712206865; c=relaxed/simple; bh=Hz4pzC8dI8YsLdK/hgxwHgxaTjxeeWuYz5hIEbCWJbs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=I7nVFniVawrcsjMofmi7q8vB4Dirfmmu8P6XWNX95jobaXtd+ri+Tnkt4/NfgMmDSCnaqQJ9wc1snSBjiU4RDw778O+BBrBBDTKqDIPSdnFLJZQgsAiCrIMxmHFUsP+HlFnTs7JfoUkSpkXUa/aE/bRbYoAKOq4v7mwkmH8IH6U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp; spf=fail smtp.mailfrom=users.sourceforge.jp; arc=none smtp.client-ip=153.127.30.23 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=users.sourceforge.jp Received: from SIOS1075.ysato.name (al128006.dynamic.ppp.asahi-net.or.jp [111.234.128.6]) by sakura.ysato.name (Postfix) with ESMTPSA id 002BF1C0939; Thu, 4 Apr 2024 14:01:00 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Damien Le Moal , Niklas Cassel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Thomas Gleixner , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Daniel Lezcano , Rich Felker , John Paul Adrian Glaubitz , Lee Jones , Helge Deller , Heiko Stuebner , Shawn Guo , Sebastian Reichel , Chris Morgan , Linus Walleij , Arnd Bergmann , David Rientjes , Hyeonggon Yoo <42.hyeyoo@gmail.com>, Vlastimil Babka , Baoquan He , Andrew Morton , Guenter Roeck , Kefeng Wang , Stephen Rothwell , Javier Martinez Canillas , Guo Ren , Azeem Shaikh , Max Filippov , Jonathan Corbet , Jacky Huang , Herve Codina , Manikanta Guntupalli , Anup Patel , Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Sam Ravnborg , Sergey Shtylyov , Laurent Pinchart , linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, linux-fbdev@vger.kernel.org Subject: [PATCH v7 14/37] clk: Compatible with narrow registers Date: Thu, 4 Apr 2024 13:59:44 +0900 Message-Id: <9c1d56d37f5d3780d3c506ae680133b6bdaa5fdc.1712205900.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 divider and gate only support 32-bit registers. Older hardware uses narrower registers, so I want to be able to handle 8-bit and 16-bit wide registers. Seven clk_divider flags are used, and if I add flags for 8bit access and 16bit access, 8bit will not be enough, so I expanded it to u16. Signed-off-by: Yoshinori Sato --- drivers/clk/clk-divider.c | 56 +++++++++++++++++++++----------- drivers/clk/clk-gate.c | 62 ++++++++++++++++++++++++++++-------- include/linux/clk-provider.h | 22 ++++++++++--- 3 files changed, 103 insertions(+), 37 deletions(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index a2c2b5203b0a..a1b5187cd63d 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -26,20 +26,38 @@ * parent - fixed parent. No clk_set_parent support */ -static inline u32 clk_div_readl(struct clk_divider *divider) -{ - if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) - return ioread32be(divider->reg); - - return readl(divider->reg); +static inline u32 clk_div_read(struct clk_divider *divider) +{ + if (divider->flags & CLK_DIVIDER_REG_8BIT) + return readb(divider->reg); + else if (divider->flags & CLK_DIVIDER_REG_16BIT) { + if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) + return ioread16be(divider->reg); + else + return readw(divider->reg); + } else { + if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) + return ioread32be(divider->reg); + else + return readl(divider->reg); + } } -static inline void clk_div_writel(struct clk_divider *divider, u32 val) +static inline void clk_div_write(struct clk_divider *divider, u32 val) { - if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) - iowrite32be(val, divider->reg); - else - writel(val, divider->reg); + if (divider->flags & CLK_DIVIDER_REG_8BIT) + writeb(val, divider->reg); + else if (divider->flags & CLK_DIVIDER_REG_16BIT) { + if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) + iowrite16be(val, divider->reg); + else + writew(val, divider->reg); + } else { + if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) + iowrite32be(val, divider->reg); + else + writel(val, divider->reg); + } } static unsigned int _get_table_maxdiv(const struct clk_div_table *table, @@ -152,7 +170,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, struct clk_divider *divider = to_clk_divider(hw); unsigned int val; - val = clk_div_readl(divider) >> divider->shift; + val = clk_div_read(divider) >> divider->shift; val &= clk_div_mask(divider->width); return divider_recalc_rate(hw, parent_rate, val, divider->table, @@ -434,7 +452,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, if (divider->flags & CLK_DIVIDER_READ_ONLY) { u32 val; - val = clk_div_readl(divider) >> divider->shift; + val = clk_div_read(divider) >> divider->shift; val &= clk_div_mask(divider->width); return divider_ro_round_rate(hw, rate, prate, divider->table, @@ -455,7 +473,7 @@ static int clk_divider_determine_rate(struct clk_hw *hw, if (divider->flags & CLK_DIVIDER_READ_ONLY) { u32 val; - val = clk_div_readl(divider) >> divider->shift; + val = clk_div_read(divider) >> divider->shift; val &= clk_div_mask(divider->width); return divider_ro_determine_rate(hw, req, divider->table, @@ -505,11 +523,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { val = clk_div_mask(divider->width) << (divider->shift + 16); } else { - val = clk_div_readl(divider); + val = clk_div_read(divider); val &= ~(clk_div_mask(divider->width) << divider->shift); } val |= (u32)value << divider->shift; - clk_div_writel(divider, val); + clk_div_write(divider, val); if (divider->lock) spin_unlock_irqrestore(divider->lock, flags); @@ -538,7 +556,7 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, - void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, + void __iomem *reg, u8 shift, u8 width, u32 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock) { struct clk_divider *div; @@ -610,7 +628,7 @@ EXPORT_SYMBOL_GPL(__clk_hw_register_divider); struct clk *clk_register_divider_table(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, - u8 clk_divider_flags, const struct clk_div_table *table, + u32 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock) { struct clk_hw *hw; @@ -664,7 +682,7 @@ struct clk_hw *__devm_clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, - void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, + void __iomem *reg, u8 shift, u8 width, u32 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock) { struct clk_hw **ptr, *hw; diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 68e585a02fd9..65191f9684ff 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -24,20 +24,38 @@ * parent - fixed parent. No clk_set_parent support */ -static inline u32 clk_gate_readl(struct clk_gate *gate) +static inline u32 clk_gate_read(struct clk_gate *gate) { - if (gate->flags & CLK_GATE_BIG_ENDIAN) - return ioread32be(gate->reg); - - return readl(gate->reg); + if (gate->flags & CLK_GATE_REG_8BIT) + return readb(gate->reg); + else if (gate->flags & CLK_GATE_REG_16BIT) { + if (gate->flags & CLK_GATE_BIG_ENDIAN) + return ioread16be(gate->reg); + else + return readw(gate->reg); + } else { + if (gate->flags & CLK_GATE_BIG_ENDIAN) + return ioread32be(gate->reg); + else + return readl(gate->reg); + } } -static inline void clk_gate_writel(struct clk_gate *gate, u32 val) +static inline void clk_gate_write(struct clk_gate *gate, u32 val) { - if (gate->flags & CLK_GATE_BIG_ENDIAN) - iowrite32be(val, gate->reg); - else - writel(val, gate->reg); + if (gate->flags & CLK_GATE_REG_8BIT) + writeb(val, gate->reg); + else if (gate->flags & CLK_GATE_REG_16BIT) { + if (gate->flags & CLK_GATE_BIG_ENDIAN) + iowrite16be(val, gate->reg); + else + writew(val, gate->reg); + } else { + if (gate->flags & CLK_GATE_BIG_ENDIAN) + iowrite32be(val, gate->reg); + else + writel(val, gate->reg); + } } /* @@ -72,7 +90,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) if (set) reg |= BIT(gate->bit_idx); } else { - reg = clk_gate_readl(gate); + reg = clk_gate_read(gate); if (set) reg |= BIT(gate->bit_idx); @@ -80,7 +98,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) reg &= ~BIT(gate->bit_idx); } - clk_gate_writel(gate, reg); + clk_gate_write(gate, reg); if (gate->lock) spin_unlock_irqrestore(gate->lock, flags); @@ -105,7 +123,7 @@ int clk_gate_is_enabled(struct clk_hw *hw) u32 reg; struct clk_gate *gate = to_clk_gate(hw); - reg = clk_gate_readl(gate); + reg = clk_gate_read(gate); /* if a set bit disables this clk, flip it before masking */ if (gate->flags & CLK_GATE_SET_TO_DISABLE) @@ -137,12 +155,30 @@ struct clk_hw *__clk_hw_register_gate(struct device *dev, struct clk_init_data init = {}; int ret = -EINVAL; + /* validate register size option and bit_idx */ if (clk_gate_flags & CLK_GATE_HIWORD_MASK) { if (bit_idx > 15) { pr_err("gate bit exceeds LOWORD field\n"); return ERR_PTR(-EINVAL); } } + if (clk_gate_flags & CLK_GATE_REG_16BIT) { + if (bit_idx > 15) { + pr_err("gate bit exceeds 16 bits\n"); + return ERR_PTR(-EINVAL); + } + } + if (clk_gate_flags & CLK_GATE_REG_8BIT) { + if (bit_idx > 7) { + pr_err("gate bit exceeds 8 bits\n"); + return ERR_PTR(-EINVAL); + } + } + if ((clk_gate_flags & CLK_GATE_HIWORD_MASK) && + clk_gate_flags & (CLK_GATE_REG_8BIT | CLK_GATE_REG_16BIT)) { + pr_err("HIWORD_MASK required 32-bit register\n"); + return ERR_PTR(-EINVAL); + } /* allocate the gate */ gate = kzalloc(sizeof(*gate), GFP_KERNEL); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 4a537260f655..eaa6ff1d0b2e 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -508,12 +508,16 @@ void of_fixed_clk_setup(struct device_node *np); * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for * the gate register. Setting this flag makes the register accesses big * endian. + * CLK_GATE_REG_8BIT - by default 32bit register accesses are used for + * the gate register. Setting this flag makes the register accesses 8bit. + * CLK_GATE_REG_16BIT - by default 32bit register accesses are used for + * the gate register. Setting this flag makes the register accesses 16bit. */ struct clk_gate { struct clk_hw hw; void __iomem *reg; u8 bit_idx; - u8 flags; + u32 flags; spinlock_t *lock; }; @@ -522,6 +526,8 @@ struct clk_gate { #define CLK_GATE_SET_TO_DISABLE BIT(0) #define CLK_GATE_HIWORD_MASK BIT(1) #define CLK_GATE_BIG_ENDIAN BIT(2) +#define CLK_GATE_REG_8BIT BIT(3) +#define CLK_GATE_REG_16BIT BIT(4) extern const struct clk_ops clk_gate_ops; struct clk_hw *__clk_hw_register_gate(struct device *dev, @@ -675,13 +681,17 @@ struct clk_div_table { * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used * for the divider register. Setting this flag makes the register accesses * big endian. + * CLK_DIVIDER_REG_8BIT - by default 32bit register accesses are used for + * the gate register. Setting this flag makes the register accesses 8bit. + * CLK_DIVIDER_REG_16BIT - by default 32bit register accesses are used for + * the gate register. Setting this flag makes the register accesses 16bit. */ struct clk_divider { struct clk_hw hw; void __iomem *reg; u8 shift; u8 width; - u8 flags; + u16 flags; const struct clk_div_table *table; spinlock_t *lock; }; @@ -697,6 +707,8 @@ struct clk_divider { #define CLK_DIVIDER_READ_ONLY BIT(5) #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) #define CLK_DIVIDER_BIG_ENDIAN BIT(7) +#define CLK_DIVIDER_REG_8BIT BIT(8) +#define CLK_DIVIDER_REG_16BIT BIT(9) extern const struct clk_ops clk_divider_ops; extern const struct clk_ops clk_divider_ro_ops; @@ -726,18 +738,18 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, - void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, + void __iomem *reg, u8 shift, u8 width, u32 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); struct clk_hw *__devm_clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, - void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, + void __iomem *reg, u8 shift, u8 width, u32 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); struct clk *clk_register_divider_table(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, - u8 clk_divider_flags, const struct clk_div_table *table, + u32 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); /** * clk_register_divider - register a divider clock with the clock framework From patchwork Thu Apr 4 04:59:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 786152 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 36F506BFA4; Thu, 4 Apr 2024 05:01:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=153.127.30.23 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712206869; cv=none; b=eniINUvhtW/l7yRFWst4VogElE6I6HUzSHRNvnuhMnDsAHJgey28mLMJB2smHxpYeqbJ5Dy9e0r1RQceBgRw2pTCP6zPiAY5SD/tZkNQCwrGdfHEcbBU9R9HMtreqUod2KQ8TutVfcGhaCytrQUXrEvmmnthCTXlhEPzI4ztdMQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712206869; c=relaxed/simple; bh=oCrxEmk2AZZ3QAEZghfuBRaq+IhD5YVLcxnsl2qregU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cHadRRg+mKPI6FH6UN2CA0XwNdX54rDFMghQw1I0nnjJya63xpzLaBEDJD4tWlsiXnlGSSZUR6HFJzuQI5S/cO+GsUqewJcj1/MNkYSevK/82M02qd7EqeLGGgiFrdTpAeKCeVCB6SMyWiwJCCOYIcEx9HDqXw6oxRqmFdmvegY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp; spf=fail smtp.mailfrom=users.sourceforge.jp; arc=none smtp.client-ip=153.127.30.23 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=users.sourceforge.jp Received: from SIOS1075.ysato.name (al128006.dynamic.ppp.asahi-net.or.jp [111.234.128.6]) by sakura.ysato.name (Postfix) with ESMTPSA id 4855B1C075F; Thu, 4 Apr 2024 14:01:05 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Damien Le Moal , Niklas Cassel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Thomas Gleixner , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Daniel Lezcano , Rich Felker , John Paul Adrian Glaubitz , Lee Jones , Helge Deller , Heiko Stuebner , Shawn Guo , Sebastian Reichel , Chris Morgan , Linus Walleij , Arnd Bergmann , David Rientjes , Hyeonggon Yoo <42.hyeyoo@gmail.com>, Vlastimil Babka , Baoquan He , Andrew Morton , Guenter Roeck , Kefeng Wang , Stephen Rothwell , Javier Martinez Canillas , Guo Ren , Azeem Shaikh , Max Filippov , Jonathan Corbet , Jacky Huang , Herve Codina , Manikanta Guntupalli , Anup Patel , Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Sam Ravnborg , Sergey Shtylyov , Laurent Pinchart , linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, linux-fbdev@vger.kernel.org Subject: [PATCH v7 16/37] irqchip: Add SH7751 INTC driver Date: Thu, 4 Apr 2024 13:59:49 +0900 Message-Id: <82bf86c5804460fd61eb6725c6222ad1cbd7d846.1712205900.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Renesas SH7751 Internal interrupt controller driver. Signed-off-by: Yoshinori Sato --- drivers/irqchip/Kconfig | 8 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-renesas-sh7751.c | 282 +++++++++++++++++++++++++++ 3 files changed, 291 insertions(+) create mode 100644 drivers/irqchip/irq-renesas-sh7751.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 72c07a12f5e1..33badb5b4f00 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -690,4 +690,12 @@ config SUNPLUS_SP7021_INTC chained controller, routing all interrupt source in P-Chip to the primary controller on C-Chip. +config RENESAS_SH7751_INTC + bool "Renesas SH7751 Interrupt Controller" + depends on SH_DEVICE_TREE || COMPILE_TEST + select IRQ_DOMAIN_HIERARCHY + help + Support for the Renesas SH7751 On-chip interrupt controller. + And external interrupt encoder for some targets. + endmenu diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index ec4a18380998..51855034a895 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -121,3 +121,4 @@ obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o +obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o diff --git a/drivers/irqchip/irq-renesas-sh7751.c b/drivers/irqchip/irq-renesas-sh7751.c new file mode 100644 index 000000000000..91d6dc3ed04c --- /dev/null +++ b/drivers/irqchip/irq-renesas-sh7751.c @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas SH7751 interrupt controller driver + * + * Copyright 2023 Yoshinori Sato + */ + +#include +#include +#include +#include +#include +#include +#include + +struct ipr { + u16 off; + u16 idx; +}; + +struct sh7751_intc_priv { + const struct ipr *iprmap; + void __iomem *base; + void __iomem *intpri00; + bool irlm; +}; + +enum { + R_ICR = 0x00, + R_IPR = 0x04, + R_INTPRI00 = 0x00, + R_INTREQ00 = 0x20, + R_INTMSK00 = 0x40, + R_INTMSKCLR00 = 0x60, +}; + +#define ICR_IRLM BIT(7) + +/* + * SH7751 IRQ mapping + * IRQ16 - 63: Group0 - IPRA to IPRD + * IRQ16 - 31: external IRL input (ICR.IRLM is 0) + * IRQ80 - 92: Group1 - INTPRI00 + */ +#define IRQ_START 16 +#define MAX_IRL (IRQ_START + NR_IRL) +#define GRP0_IRQ_END 63 +#define GRP1_IRQ_START 80 +#define IRQ_END 92 + +#define NR_IPRMAP0 (GRP0_IRQ_END - IRQ_START + 1) +#define NR_IPRMAP1 (IRQ_END - GRP1_IRQ_START) +#define IPR_PRI_MASK 0x000f + +#define IPRA 0 +#define IPRB 4 +#define IPRC 8 +#define IPRD 12 +#define INTPRI00 256 +#define IPR_B12 12 +#define IPR_B8 8 +#define IPR_B4 4 +#define IPR_B0 0 + +/* SH7751 EVT to IPR mapping table */ +static const struct ipr sh7751_iprmap[] = { + [evt2irq(0x240)] = {IPRD, IPR_B12}, /* IRL0 (ICR.IRLM=1) */ + [evt2irq(0x2a0)] = {IPRD, IPR_B8}, /* IRL1 (ICR.IRLM=1) */ + [evt2irq(0x300)] = {IPRD, IPR_B4}, /* IRL2 (ICR.IRLM=1) */ + [evt2irq(0x360)] = {IPRD, IPR_B0}, /* IRL3 (ICR.IRLM=1) */ + [evt2irq(0x400)] = {IPRA, IPR_B12}, /* TMU0 */ + [evt2irq(0x420)] = {IPRA, IPR_B8}, /* TMU1 */ + [evt2irq(0x440)] = {IPRA, IPR_B4}, /* TMU2 TNUI */ + [evt2irq(0x460)] = {IPRA, IPR_B4}, /* TMU2 TICPI */ + [evt2irq(0x480)] = {IPRA, IPR_B0}, /* RTC ATI */ + [evt2irq(0x4a0)] = {IPRA, IPR_B0}, /* RTC PRI */ + [evt2irq(0x4c0)] = {IPRA, IPR_B0}, /* RTC CUI */ + [evt2irq(0x4e0)] = {IPRB, IPR_B4}, /* SCI ERI */ + [evt2irq(0x500)] = {IPRB, IPR_B4}, /* SCI RXI */ + [evt2irq(0x520)] = {IPRB, IPR_B4}, /* SCI TXI */ + [evt2irq(0x540)] = {IPRB, IPR_B4}, /* SCI TEI */ + [evt2irq(0x560)] = {IPRB, IPR_B12}, /* WDT */ + [evt2irq(0x580)] = {IPRB, IPR_B8}, /* REF RCMI */ + [evt2irq(0x5a0)] = {IPRB, IPR_B4}, /* REF ROVI */ + [evt2irq(0x600)] = {IPRC, IPR_B0}, /* H-UDI */ + [evt2irq(0x620)] = {IPRC, IPR_B12}, /* GPIO */ + [evt2irq(0x640)] = {IPRC, IPR_B8}, /* DMAC DMTE0 */ + [evt2irq(0x660)] = {IPRC, IPR_B8}, /* DMAC DMTE1 */ + [evt2irq(0x680)] = {IPRC, IPR_B8}, /* DMAC DMTE2 */ + [evt2irq(0x6a0)] = {IPRC, IPR_B8}, /* DMAC DMTE3 */ + [evt2irq(0x6c0)] = {IPRC, IPR_B8}, /* DMAC DMAE */ + [evt2irq(0x700)] = {IPRC, IPR_B4}, /* SCIF ERI */ + [evt2irq(0x720)] = {IPRC, IPR_B4}, /* SCIF RXI */ + [evt2irq(0x740)] = {IPRC, IPR_B4}, /* SCIF BRI */ + [evt2irq(0x760)] = {IPRC, IPR_B4}, /* SCIF TXI */ + [evt2irq(0x780)] = {IPRC, IPR_B8}, /* DMAC DMTE4 */ + [evt2irq(0x7a0)] = {IPRC, IPR_B8}, /* DMAC DMTE5 */ + [evt2irq(0x7c0)] = {IPRC, IPR_B8}, /* DMAC DMTE6 */ + [evt2irq(0x7e0)] = {IPRC, IPR_B8}, /* DMAC DMTE7 */ + [evt2irq(0xa00)] = {INTPRI00, IPR_B0}, /* PCIC PCISERR */ + [evt2irq(0xa20)] = {INTPRI00, IPR_B4}, /* PCIC PCIDMA3 */ + [evt2irq(0xa40)] = {INTPRI00, IPR_B4}, /* PCIC PCIDMA2 */ + [evt2irq(0xa60)] = {INTPRI00, IPR_B4}, /* PCIC PCIDMA1 */ + [evt2irq(0xa80)] = {INTPRI00, IPR_B4}, /* PCIC PCIDMA0 */ + [evt2irq(0xaa0)] = {INTPRI00, IPR_B4}, /* PCIC PCIPWON */ + [evt2irq(0xac0)] = {INTPRI00, IPR_B4}, /* PCIC PCIPWDWN */ + [evt2irq(0xae0)] = {INTPRI00, IPR_B4}, /* PCIC PCIERR */ + [evt2irq(0xb00)] = {INTPRI00, IPR_B8}, /* TMU3 */ + [evt2irq(0xb80)] = {INTPRI00, IPR_B12}, /* TMU4 */ +}; + +/* + * IPR registers have 4bit priority x 4 entry (16bits) + */ +static void update_ipr(struct sh7751_intc_priv *priv, unsigned int irq, u16 pri) +{ + const struct ipr *ipr = NULL; + void __iomem *ipr_base; + unsigned int offset; + u16 mask; + + ipr = priv->iprmap + irq; + if (irq < GRP1_IRQ_START) { + /* Group0 */ + ipr_base = priv->base + R_IPR; + offset = ipr->off; + } else { + /* Group1 */ + ipr_base = priv->intpri00; + offset = ipr->off - INTPRI00; + } + mask = ~(IPR_PRI_MASK << ipr->idx); + pri = (pri & IPR_PRI_MASK) << ipr->idx; + mask &= __raw_readw(ipr_base + offset); + __raw_writew(mask | pri, ipr_base + offset); +} + +static inline bool is_valid_irq(unsigned int irq) +{ + /* IRQ16 - 63 */ + if (irq >= IRQ_START && irq < IRQ_START + NR_IPRMAP0) + return true; + /* IRQ80 - 92 */ + if (irq >= GRP1_IRQ_START && irq <= IRQ_END) + return true; + return false; +} + +static inline struct sh7751_intc_priv *irq_data_to_priv(struct irq_data *data) +{ + return data->domain->host_data; +} + +/* Interrupt unmask priority is 1, mask priority is 0 */ +#define PRI_ENABLE 1 +#define PRI_DISABLE 0 +static void endisable_irq(struct irq_data *data, bool enable) +{ + struct sh7751_intc_priv *priv; + unsigned int irq; + + priv = irq_data_to_priv(data); + + irq = irqd_to_hwirq(data); + if (!is_valid_irq(irq)) { + /* IRQ out of range */ + pr_warn_once("%s: IRQ %u is out of range\n", __FILE__, irq); + return; + } + + if (irq <= MAX_IRL && !priv->irlm) { + /* IRL encoded external interrupt */ + /* enable and disable from SR.IMASK */ + update_sr_imask(irq - IRQ_START, enable); + } else { + /* Internal peripheral interrupt */ + /* enable and disable from interrupt priority */ + update_ipr(priv, irq, enable ? PRI_ENABLE : PRI_DISABLE); + } +} + +static void sh7751_mask_irq(struct irq_data *data) +{ + endisable_irq(data, false); +} + +static void sh7751_unmask_irq(struct irq_data *data) +{ + endisable_irq(data, true); +} + +static const struct irq_chip sh7751_irq_chip = { + .name = "SH7751-INTC", + .irq_unmask = sh7751_unmask_irq, + .irq_mask = sh7751_mask_irq, +}; + +static int irq_sh7751_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw_irq_num) +{ + irq_set_chip_and_handler(virq, &sh7751_irq_chip, handle_level_irq); + irq_get_irq_data(virq)->chip_data = h->host_data; + irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOPROBE); + return 0; +} + +static int irq_sh7751_xlate(struct irq_domain *d, struct device_node *ctrlr, + const u32 *intspec, unsigned int intsize, + unsigned long *out_hwirq, unsigned int *out_type) +{ + if (WARN_ON(intsize < 1)) + return -EINVAL; + *out_hwirq = evt2irq(intspec[0]); + *out_type = IRQ_TYPE_NONE; + return 0; +} + +static const struct irq_domain_ops irq_ops = { + .map = irq_sh7751_map, + .xlate = irq_sh7751_xlate, +}; + +static int __init shintc_of_init(struct device_node *intc, struct device_node *parent, + const struct ipr *iprmap) +{ + struct sh7751_intc_priv *priv; + void __iomem *base, *base2; + struct irq_domain *domain; + u16 icr; + int ret; + + priv = kzalloc(sizeof(struct sh7751_intc_priv), GFP_KERNEL); + if (priv == NULL) + return -ENOMEM; + + base = of_iomap(intc, 0); + base2 = of_iomap(intc, 1); + if (!base || !base2) { + pr_err("%pOFP: Invalid register definition\n", intc); + ret = -EINVAL; + goto error; + } + + priv->base = base; + priv->intpri00 = base2; + priv->iprmap = iprmap; + + if (of_property_read_bool(intc, "renesas,irlm")) { + priv->irlm = true; + icr = __raw_readw(priv->base + R_ICR); + icr |= ICR_IRLM; + __raw_writew(icr, priv->base + R_ICR); + } + + domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, priv); + if (domain == NULL) { + pr_err("%pOFP: cannot initialize irq domain\n", intc); + ret = -ENOMEM; + goto error; + } + + irq_set_default_host(domain); + pr_info("%pOFP: SH7751 Interrupt controller (%s external IRQ)", + intc, priv->irlm ? "4 lines" : "15 level"); + return 0; + +error: + if (base) + iounmap(base); + if (base2) + iounmap(base); + kfree(priv); + return ret; +} + +static int __init sh7751_intc_of_init(struct device_node *intc, + struct device_node *parent) +{ + return shintc_of_init(intc, parent, sh7751_iprmap); +} + +IRQCHIP_DECLARE(sh_7751_intc, "renesas,sh7751-intc", sh7751_intc_of_init); From patchwork Thu Apr 4 04:59:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 786151 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1356E6EB73; Thu, 4 Apr 2024 05:01:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=153.127.30.23 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712206873; cv=none; b=BoVDBE80kxDO27RzY3Og+fNWN0TOwRdhaXIYiMduRKG0gRaFi4VZE2WWF+coCYmycd2o0MgLfUycIrm6vh2X5jch4N0mv7YgKoZrZcv7cQaiDY4FR3JsZS88HbRRt1YisyIBcs9Nktc24r9GUuMpEGX4u9buWNkCCRt0Fbp8BvA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712206873; c=relaxed/simple; bh=UJW1y/CNqaXMUaqUfQ32jgB+zVWcGE7dF8voaeMrWZE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cUzngTiiOlVXpu9HtpKgSWZtjZXPn7sWFAGtYvlh2zIgTRY1NygGC/V06cr7RIzXL58JYs/RMUZmCTJJZO9X76ysZJ8QPTK9PuLPiHM+G3gEf1KlTiIuvtp0itTsWe1OpFHwNKTi1gIgowPNNfTEIlHLPlrBNgzZqn5OcKuRUw4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp; spf=fail smtp.mailfrom=users.sourceforge.jp; arc=none smtp.client-ip=153.127.30.23 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=users.sourceforge.jp Received: from SIOS1075.ysato.name (al128006.dynamic.ppp.asahi-net.or.jp [111.234.128.6]) by sakura.ysato.name (Postfix) with ESMTPSA id 22AC81C089C; Thu, 4 Apr 2024 14:01:09 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Damien Le Moal , Niklas Cassel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Thomas Gleixner , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Daniel Lezcano , Rich Felker , John Paul Adrian Glaubitz , Lee Jones , Helge Deller , Heiko Stuebner , Shawn Guo , Sebastian Reichel , Chris Morgan , Linus Walleij , Arnd Bergmann , David Rientjes , Hyeonggon Yoo <42.hyeyoo@gmail.com>, Vlastimil Babka , Baoquan He , Andrew Morton , Guenter Roeck , Kefeng Wang , Stephen Rothwell , Javier Martinez Canillas , Guo Ren , Azeem Shaikh , Max Filippov , Jonathan Corbet , Jacky Huang , Herve Codina , Manikanta Guntupalli , Anup Patel , Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Sam Ravnborg , Sergey Shtylyov , Laurent Pinchart , linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, linux-fbdev@vger.kernel.org Subject: [PATCH v7 18/37] irqchip: SH7751 external interrupt encoder with enable gate. Date: Thu, 4 Apr 2024 13:59:53 +0900 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 SH7751 have 15 level external interrupt. It is typically connected to the CPU through a priority encoder that can suppress requests. This driver provides a way to control those hardware with irqchip. Signed-off-by: Yoshinori Sato --- drivers/irqchip/Kconfig | 7 + drivers/irqchip/Makefile | 2 + drivers/irqchip/irq-renesas-sh7751irl.c | 221 ++++++++++++++++++++++++ 3 files changed, 230 insertions(+) create mode 100644 drivers/irqchip/irq-renesas-sh7751irl.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 33badb5b4f00..7670fcd6757d 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -698,4 +698,11 @@ config RENESAS_SH7751_INTC Support for the Renesas SH7751 On-chip interrupt controller. And external interrupt encoder for some targets. +config RENESAS_SH7751IRL_INTC + bool "Renesas SH7751 based target IRL encoder support." + depends on RENESAS_SH7751_INTC + help + Support for External Interrupt encoder + on the some Renesas SH7751 based target. + endmenu diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 51855034a895..bc21d65441f2 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -122,3 +122,5 @@ obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o +obj-$(CONFIG_RENESAS_SH7751IRL_INTC) += irq-renesas-sh7751irl.o + diff --git a/drivers/irqchip/irq-renesas-sh7751irl.c b/drivers/irqchip/irq-renesas-sh7751irl.c new file mode 100644 index 000000000000..5990f2cd9a3d --- /dev/null +++ b/drivers/irqchip/irq-renesas-sh7751irl.c @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SH7751 based board external interrupt level encoder driver + * (Renesas RTS7751R2D / IO DATA DEVICE LANDISK, USL-5P) + * + * Copyright (C) 2023 Yoshinori Sato + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct sh7751irl_intc_priv { + struct irq_domain *irq_domain; + void __iomem *base; + unsigned int width; + bool invert; + u32 enable_bit[NR_IRL]; +}; + +static inline unsigned long get_reg(void __iomem *addr, unsigned int w) +{ + switch (w) { + case 8: + return __raw_readb(addr); + case 16: + return __raw_readw(addr); + case 32: + return __raw_readl(addr); + default: + /* The size is checked when reading the properties. */ + pr_err("%s: Invalid width %d", __FILE__, w); + return 0; + } +} + +static inline void set_reg(void __iomem *addr, unsigned int w, unsigned long val) +{ + switch (w) { + case 8: + __raw_writeb(val, addr); + break; + case 16: + __raw_writew(val, addr); + break; + case 32: + __raw_writel(val, addr); + break; + default: + pr_err("%s: Invalid width %d", __FILE__, w); + } +} + +static inline struct sh7751irl_intc_priv *irq_data_to_priv(struct irq_data *data) +{ + return data->domain->host_data; +} + +static void irl_endisable(struct irq_data *data, unsigned int enable) +{ + struct sh7751irl_intc_priv *priv; + unsigned long val; + unsigned int irl; + + priv = irq_data_to_priv(data); + irl = irqd_to_hwirq(data) - IRL_BASE_IRQ; + + if (irl < NR_IRL && priv->enable_bit[irl] < priv->width) { + if (priv->invert) + enable = !enable; + + val = get_reg(priv->base, priv->width); + if (enable) + set_bit(priv->enable_bit[irl], &val); + else + clear_bit(priv->enable_bit[irl], &val); + set_reg(priv->base, priv->width, val); + } else { + pr_err("%s: Invalid register define in IRL %u", __FILE__, irl); + } +} + +static void sh7751irl_intc_disable_irq(struct irq_data *data) +{ + irl_endisable(data, 0); +} + +static void sh7751irl_intc_enable_irq(struct irq_data *data) +{ + irl_endisable(data, 1); +} + +static struct irq_chip sh7751irl_intc_chip = { + .name = "SH7751IRL-INTC", + .irq_enable = sh7751irl_intc_enable_irq, + .irq_disable = sh7751irl_intc_disable_irq, +}; + +static int sh7751irl_intc_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw_irq_num) +{ + irq_set_chip_and_handler(virq, &sh7751irl_intc_chip, handle_level_irq); + irq_get_irq_data(virq)->chip_data = h->host_data; + irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOPROBE); + return 0; +} + +static int sh7751irl_intc_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, unsigned long *hwirq, + unsigned int *type) +{ + if (fwspec->param[0] > NR_IRL) + return -EINVAL; + + switch (fwspec->param_count) { + case 2: + *type = fwspec->param[1]; + fallthrough; + case 1: + *hwirq = fwspec->param[0] + IRL_BASE_IRQ; + break; + default: + return -EINVAL; + } + return 0; +} + +static const struct irq_domain_ops sh7751irl_intc_domain_ops = { + .map = sh7751irl_intc_map, + .translate = sh7751irl_intc_translate, +}; + +static int __init load_irl_bit(struct device_node *node, struct sh7751irl_intc_priv *priv) +{ + struct property *enable_map; + const __be32 *p; + u32 nr_bits, bit; + u32 irl; + int ret; + + /* Fill in unused */ + memset(priv->enable_bit, ~0, sizeof(priv->enable_bit)); + + enable_map = of_find_property(node, "renesas,enable-reg", &nr_bits); + if (IS_ERR(enable_map)) + return PTR_ERR(enable_map); + + nr_bits /= sizeof(u32); + if (nr_bits > priv->width) + return -EINVAL; + + ret = nr_bits; + p = NULL; + for (bit = nr_bits; bit > 0; bit--) { + p = of_prop_next_u32(enable_map, p, &irl); + if (p == NULL || irl > NR_IRL) + return -EINVAL; + if (irl == NR_IRL) + /* IRL15 is unassined bit */ + continue; + priv->enable_bit[irl] = bit - 1; + } + return ret; +} + +static int __init sh7751irl_init(struct device_node *node, struct device_node *parent) +{ + struct sh7751irl_intc_priv *priv; + struct resource res; + struct irq_domain *d; + void __iomem *base; + int ret = 0; + + if (of_address_to_resource(node, 0, &res)) + return -EINVAL; + if (resource_size(&res) > 4) + return -EINVAL; + + base = ioremap(res.start, resource_size(&res)); + if (!base) + return -EINVAL; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = base; + priv->width = 8 << resource_size(&res); + + ret = load_irl_bit(node, priv); + if (ret < 0) { + pr_err("%pOFP: Invalid register define.\n", node); + goto error; + } + + d = irq_domain_add_tree(node, &sh7751irl_intc_domain_ops, priv); + if (d == NULL) { + pr_err("%pOFP: cannot initialize irq domain\n", node); + ret = -ENOMEM; + goto error; + } + + priv->irq_domain = d; + irq_domain_update_bus_token(d, DOMAIN_BUS_WIRED); + pr_info("%pOFP: SH7751 External Interrupt encoder (input=%d)", node, ret); + return 0; +error: + kfree(priv); + return ret; +} + +IRQCHIP_DECLARE(renesas_sh7751_irl, "renesas,sh7751-irl-ext", sh7751irl_init); From patchwork Thu Apr 4 04:59:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 786150 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0994271B3A; Thu, 4 Apr 2024 05:01:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=153.127.30.23 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Thu, 4 Apr 2024 14:01:13 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Damien Le Moal , Niklas Cassel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Thomas Gleixner , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Daniel Lezcano , Rich Felker , John Paul Adrian Glaubitz , Lee Jones , Helge Deller , Heiko Stuebner , Shawn Guo , Sebastian Reichel , Chris Morgan , Linus Walleij , Arnd Bergmann , David Rientjes , Hyeonggon Yoo <42.hyeyoo@gmail.com>, Vlastimil Babka , Baoquan He , Andrew Morton , Guenter Roeck , Kefeng Wang , Stephen Rothwell , Javier Martinez Canillas , Guo Ren , Azeem Shaikh , Max Filippov , Jonathan Corbet , Jacky Huang , Herve Codina , Manikanta Guntupalli , Anup Patel , Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Sam Ravnborg , Sergey Shtylyov , Laurent Pinchart , linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, linux-fbdev@vger.kernel.org Subject: [PATCH v7 20/37] serial: sh-sci: fix SH4 OF support. Date: Thu, 4 Apr 2024 13:59:57 +0900 Message-Id: <38f5834918e7e9dff023e8db970bc3c0160583ec.1712205900.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 - fix earlycon name. - fix earlyprintk hung (NULL pointer reference). - fix SERIAL_SH_SCI_EARLYCON enablement Signed-off-by: Yoshinori Sato Reviewed-by: Geert Uytterhoeven --- drivers/tty/serial/Kconfig | 2 +- drivers/tty/serial/sh-sci.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index ffcf4882b25f..dfe5fd436816 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -661,7 +661,7 @@ config SERIAL_SH_SCI_EARLYCON depends on SERIAL_SH_SCI=y select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON - default ARCH_RENESAS + default ARCH_RENESAS || SUPERH config SERIAL_SH_SCI_DMA bool "DMA support" if EXPERT diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index e512eaa57ed5..46466fb5a637 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -2717,7 +2717,7 @@ static int sci_remap_port(struct uart_port *port) if (port->membase) return 0; - if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { + if ((port->dev && port->dev->of_node) || (port->flags & UPF_IOREMAP)) { port->membase = ioremap(port->mapbase, sport->reg_size); if (unlikely(!port->membase)) { dev_err(port->dev, "can't remap port#%d\n", port->line); @@ -3545,8 +3545,8 @@ static int __init hscif_early_console_setup(struct earlycon_device *device, OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); -OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); -OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); +OF_EARLYCON_DECLARE(rzscifa, "renesas,scif-r7s9210", rzscifa_early_console_setup); +OF_EARLYCON_DECLARE(rzscifa, "renesas,scif-r9a07g044", rzscifa_early_console_setup); OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); From patchwork Thu Apr 4 05:00:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 786149 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D6BA7745C0; Thu, 4 Apr 2024 05:01:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=153.127.30.23 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712206881; cv=none; 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Received: from SIOS1075.ysato.name (al128006.dynamic.ppp.asahi-net.or.jp [111.234.128.6]) by sakura.ysato.name (Postfix) with ESMTPSA id D6DAF1C0BE5; Thu, 4 Apr 2024 14:01:16 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Damien Le Moal , Niklas Cassel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Thomas Gleixner , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Daniel Lezcano , Rich Felker , John Paul Adrian Glaubitz , Lee Jones , Helge Deller , Heiko Stuebner , Shawn Guo , Sebastian Reichel , Chris Morgan , Linus Walleij , Arnd Bergmann , David Rientjes , Hyeonggon Yoo <42.hyeyoo@gmail.com>, Vlastimil Babka , Baoquan He , Andrew Morton , Guenter Roeck , Kefeng Wang , Stephen Rothwell , Javier Martinez Canillas , Guo Ren , Azeem Shaikh , Max Filippov , Jonathan Corbet , Jacky Huang , Herve Codina , Manikanta Guntupalli , Anup Patel , Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Sam Ravnborg , Sergey Shtylyov , Laurent Pinchart , linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, linux-fbdev@vger.kernel.org Subject: [PATCH v7 22/37] dt-bindings: display: smi,sm501: SMI SM501 binding json-schema Date: Thu, 4 Apr 2024 14:00:01 +0900 Message-Id: <9858ef1c149bd27b27594b3bd388601681d83460.1712205900.git.ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Signed-off-by: Yoshinori Sato --- .../bindings/display/smi,sm501.yaml | 398 ++++++++++++++++++ 1 file changed, 398 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/smi,sm501.yaml diff --git a/Documentation/devicetree/bindings/display/smi,sm501.yaml b/Documentation/devicetree/bindings/display/smi,sm501.yaml new file mode 100644 index 000000000000..06c6af4fa4a9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/smi,sm501.yaml @@ -0,0 +1,398 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/smi,sm501.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Motion SM501 Mobile Multimedia Companion Chip + +maintainers: + - Yoshinori Sato + +description: | + These DT bindings describe the SM501. + +properties: + compatible: + const: + smi,sm501 + + reg: + maxItems: 2 + description: | + First entry: System Configuration register + Second entry: IO space (Display Controller register) + + interrupts: + description: SM501 interrupt to the cpu should be described here. + + mode: + $ref: /schemas/types.yaml#/definitions/string + description: select a video mode + + edid: + description: | + verbatim EDID data block describing attached display. + Data from the detailed timing descriptor will be used to + program the display controller. + + little-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: available on big endian systems, to set different foreign endian. + big-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: available on little endian systems, to set different foreign endian. + + swap-fb-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: swap framebuffer byteorder. + + route-crt-panel: + $ref: /schemas/types.yaml#/definitions/flag + description: Panel output merge to CRT. + + crt: + type: object + description: CRT output control + properties: + edid: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: | + verbatim EDID data block describing attached display. + Data from the detailed timing descriptor will be used to + program the display controller. + + smi,flags: + $ref: /schemas/types.yaml#/definitions/string-array + description: Display control flags. + items: + anyOf: + - const: use-init-done + - const: disable-at-exit + - const: use-hwcursor + - const: use-hwaccel + - const: panel-no-fpen + - const: panel-no-vbiasen + - const: panel-inv-fpen + - const: panel-inv-vbiasen + maxItems: 8 + + bpp: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Color depth + + panel: + type: object + description: Panel output control + properties: + edid: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: | + verbatim EDID data block describing attached display. + Data from the detailed timing descriptor will be used to + program the display controller. + + smi,flags: + $ref: /schemas/types.yaml#/definitions/string-array + description: Display control flags. + items: + anyOf: + - const: use-init-done + - const: disable-at-exit + - const: use-hwcursor + - const: use-hwaccel + - const: panel-no-fpen + - const: panel-no-vbiasen + - const: panel-inv-fpen + - const: panel-inv-vbiasen + maxItems: 8 + + bpp: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Color depth + + smi,devices: + $ref: /schemas/types.yaml#/definitions/string-array + description: Select SM501 device functions. + items: + anyOf: + - const: usb-host + - const: usb-slave + - const: ssp0 + - const: ssp1 + - const: uart0 + - const: uart1 + - const: fbaccel + - const: ac97 + - const: i2s + - const: gpio + minItems: 1 + maxItems: 10 + + smi,mclk: + $ref: /schemas/types.yaml#/definitions/uint32 + description: mclk frequency. + + smi,m1xclk: + $ref: /schemas/types.yaml#/definitions/uint32 + description: m1xclk frequency. + + misc-timing: + type: object + description: Miscellaneous Timing register values. + properties: + ex: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Extend bus holding time. + + xc: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Xscale clock input select. + + usb-over-current-detect-disable: + $ref: /schemas/types.yaml#/definitions/flag + description: USB host current detection disable (Us=0). + + usb-over-current-detect-enable: + $ref: /schemas/types.yaml#/definitions/flag + description: USB host current detection disable (Us=1). + + sdram-clock-mode1-288mhz: + $ref: /schemas/types.yaml#/definitions/flag + description: SSM1 bit is clear. + + sdram-clock-mode1-div: + $ref: /schemas/types.yaml#/definitions/flag + description: SSM1 bit is set. + + sm1: + $ref: /schemas/types.yaml#/definitions/flag + description: SDRAM clock divider for PW mode 1. + + sdram-clock-mode0-288mhz: + $ref: /schemas/types.yaml#/definitions/flag + description: SSM0 bit is clear. + + sdram-clock-mode0-div: + $ref: /schemas/types.yaml#/definitions/flag + description: SSM0 bit is set. + + sm0: + $ref: /schemas/types.yaml#/definitions/uint32 + description: SDRAM clock divider for PW mode 0. + + pll-debug-input: + $ref: /schemas/types.yaml#/definitions/flag + description: 96MHz PLL debug input reference frequency (Deb=0). + + pll-debug-output: + $ref: /schemas/types.yaml#/definitions/flag + description: 96MHz PLL debug output frequency (Deb=1). + + no-acpi-control: + $ref: /schemas/types.yaml#/definitions/flag + description: No ACPI control (A=0). + + acpi-control: + $ref: /schemas/types.yaml#/definitions/flag + description: No ACPI control (A=1). + + divider: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Second PLL output frequency. + + usb-host-normal: + $ref: /schemas/types.yaml#/definitions/flag + description: USB Host normal mode. + + usb-host-simulation: + $ref: /schemas/types.yaml#/definitions/flag + description: USB Host simulation mode. + + delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Delay time to latch read data. Set the value to 10x. + + misc-control: + type: object + description: Miscellaneous Control register values. + properties: + pad: + $ref: /schemas/types.yaml#/definitions/uint32 + description: PCI Pad drive strength. + + usbclk: + $ref: /schemas/types.yaml#/definitions/uint32 + description: USB Clcok Select. + + uart1: + $ref: /schemas/types.yaml#/definitions/flag + description: UART1 (SSP=0) + + ssp1: + $ref: /schemas/types.yaml#/definitions/flag + description: SSP1 (SSP=1) + + latch-address-disable: + $ref: /schemas/types.yaml#/definitions/flag + description: 8051 Latch disable (Lat=0). + + latch-address-enable: + $ref: /schemas/types.yaml#/definitions/flag + description: 8051 Latch enable (Lat=1). + + panel-data-18bit: + $ref: /schemas/types.yaml#/definitions/flag + description: Flat Panel data 18bit (FP=0). + + panel-data-24bit: + $ref: /schemas/types.yaml#/definitions/flag + description: Flat Panel data 24bit (FP=1). + + xtal-freq-24mhz: + $ref: /schemas/types.yaml#/definitions/flag + description: Crystal frequency 24MHz (Freq=0). + + xtal-freq-12mhz: + $ref: /schemas/types.yaml#/definitions/flag + description: Crystal frequency 12MHz (Freq=1). + + refresh: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Internal memory refresh timing. + + hold: + $ref: /schemas/types.yaml#/definitions/uint32 + description: BUS Hold time. + + sh-ready-low: + $ref: /schemas/types.yaml#/definitions/flag + description: SuperH ready polarity active low (SH=0). + + sh-ready-high: + $ref: /schemas/types.yaml#/definitions/flag + description: SuperH ready polarity active high (SH=1). + + interrupt-normal: + $ref: /schemas/types.yaml#/definitions/flag + description: Interrupt normal (II=0). + + interrupt-inverted: + $ref: /schemas/types.yaml#/definitions/flag + description: Interrupt Inverting (II=1). + + pll-clock-count-disable: + $ref: /schemas/types.yaml#/definitions/flag + description: PLL clock count disable. + + pll-clock-count-enaable: + $ref: /schemas/types.yaml#/definitions/flag + description: PLL clock count enable. + + dac-power-enable: + $ref: /schemas/types.yaml#/definitions/flag + description: DAC Power enable (DAC=0). + + dac-power-disable: + $ref: /schemas/types.yaml#/definitions/flag + description: DAC Power disable (DAC=1). + + usb-slave-cpu: + $ref: /schemas/types.yaml#/definitions/flag + description: USB slave controller cpu (MC=0). + + usb-slave-8051: + $ref: /schemas/types.yaml#/definitions/flag + description: USB slave controller 8051MCU (MC=1). + + burst-length-8: + $ref: /schemas/types.yaml#/definitions/flag + description: CPU Master burst length 8 (BL=0). + + burst-length-1: + $ref: /schemas/types.yaml#/definitions/flag + description: CPU Master burst length 1 (BL=1). + + usb-port-master: + $ref: /schemas/types.yaml#/definitions/flag + description: USB port master. + + usb-port-slave: + $ref: /schemas/types.yaml#/definitions/flag + description: USB port slave. + + vr-mmio-30mb: + $ref: /schemas/types.yaml#/definitions/flag + description: NEC VR Memory map MMIO locatedat 30MB (VR=0) + + vr-mmio-62mb: + $ref: /schemas/types.yaml#/definitions/flag + description: NEC VR Memory map MMIO locatedat 62MB (VR=1) + + gpio-pin-control: + type: object + description: GPIO control configuration. + properties: + pin: + type: object + properties: + gpio: + $ref: /schemas/types.yaml#/definitions/flag + description: pin in/out use GPIO. + function: + $ref: /schemas/types.yaml#/definitions/flag + description: pin in/out use function. + + gpio-i2c: + type: object + description: GPIO I2C definition. + properties: + i2c: + type: object + properties: + bus: + $ref: /schemas/types.yaml#/definitions/uint32 + description: I2C bus number. + + sda: + $ref: /schemas/types.yaml#/definitions/uint32 + description: I2C SDA pin port number. + + scl: + $ref: /schemas/types.yaml#/definitions/uint32 + description: I2C SCL pin port number. + + delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: bit transmission delay. + + timeout: + $ref: /schemas/types.yaml#/definitions/uint32 + description: transmission timeout. + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + + +examples: + # MPC5200 + - | + display@1,0 { + compatible = "smi,sm501"; + reg = <0x00000000 0x00800000 + 0x03e00000 0x00200000>; + interrupts = <1 1 3>; + mode = "640x480-32@60"; + edid = [00 ff ff ff ff ff ff 00 00 00 00 00 00 00 00 00 + 00 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 f0 0a 80 fb 20 e0 25 10 32 60 + 02 00 00 00 00 00 00 06 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 bd]; + };