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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Update Bhupesh's email to his new one. Reviewed-by: Neil Armstrong Signed-off-by: Caleb Connolly --- Cc: Bhupesh Sharma --- .mailmap | 1 + 1 file changed, 1 insertion(+) diff --git a/.mailmap b/.mailmap index d1f08f3eca8a..f6e0847b2168 100644 --- a/.mailmap +++ b/.mailmap @@ -29,8 +29,9 @@ Ashok Reddy Soma Atish Patra Bharat Kumar Gogada Bharat Kumar Gogada Bhargava Sreekantappa Gayathri +Bhupesh Sharma Bin Meng Boris Brezillon Boris Brezillon Christian Kohn From patchwork Wed Apr 3 12:07:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 785413 Delivered-To: patch@linaro.org Received: by 2002:adf:f001:0:b0:33e:7753:30bd with SMTP id j1csp280238wro; Wed, 3 Apr 2024 05:08:15 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXAbvK5SDoTwg2Tht9UksduhOEemKTJ2GniR7XudnCttNFcr20WwiuNFfzQuzre58RrbdOP3VZfl9NM0bHJvt4w X-Google-Smtp-Source: AGHT+IG388HN7nduQQy3gE9eNJYejxhAns/Gyofp3hmcjK0myOkyovQk9i/BvzF/8+YIN7eoBg32 X-Received: by 2002:a17:906:3605:b0:a46:fb17:8871 with SMTP id q5-20020a170906360500b00a46fb178871mr10915958ejb.76.1712146095374; Wed, 03 Apr 2024 05:08:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712146095; cv=none; d=google.com; s=arc-20160816; b=v2ABgfOrt2mLR1Gtn/NPfsFqZOEJNp+KKZtS+JuiFYksqEYOHe1cXUG12qSwk6Nh2n Ob1/+MBhWFydelFWzvlB5lupHdP5uuZJe5VQWFHIZk6B7TLEiVGYq4jiliYCcduox6PT FUdR/4HDvw1/+IUbyYt5jK8RVFFhXgqzh9LXqnAX+AZ63kymMZ7UXB4fYZextRYmh5yq rOKXbebZuvg1o8w7NxdFzDyUs8qFglr2NEzWy3hGN0qQ7FnQ4TT5mJzIS94ZIG9hl1nE YZIEl9ZuS7dMWL2J7Izn1Xpd4KwzPTq8AhEmJwZCEHhtugVpWATxEeHNVtH435f4OJK7 7kwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=aOr/sX+VlUJKn+m2ODZMVOXoyYKzp0OTGmvKS29yZIE=; fh=IUJzsJXR8tzOhtgP/Qm7FzQrRAC2ZStJPTaXNXY0swo=; b=hB4+VEpNi+EqsUuVWMIN7INAdVxfyj89Pje3erBwzbcjvkoLexiw/ghvm/JYmdS3cq Db8BQVLiGaZOwEN6J0j7XvaCDDqM3/8uR78vbrrd4K4o2oo0KyHaQe3OfL6zJH0tr6ga lwiUfxrW84ci7YxRWf4Ee6GII3CdoE5AWzdzSi+qkUcgy0/ZHcZH5oDpkuUUPS4pa3KZ X6L2FmA0bzMmDKpunto1uHx9mD3/5owQ9Invi1epWbDmj2yqUPN6wijBRIOaEgc0CnEt MdT5DzVeiom1gxkBDcMvpAqwWnY0Lpp0g59thbM7YzBLFv+/JAGujaAL1YFmmXlRq9ew yJhg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Spyhkpgh; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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a=openpgp-sha256; l=14100; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=4b2mnUOwURE79EaLZQk8U/Csv3o5Zh+Q2/iPjqCNkAI=; b=owEBbQKS/ZANAwAIAQWDMSsZX2S2AcsmYgBmDUaQV2wtFCAb6vfio4SGYBwUj5VtJ+xYlYAeG E6oxYG8geyJAjMEAAEIAB0WIQS2UaFGPGq+0GkMVc0FgzErGV9ktgUCZg1GkAAKCRAFgzErGV9k tl4vEACXXqks97/+3Mxs/jBShjttFYH/yCCBIr3QMxs1SBQfjwls+heX5Sem/JOqUKZeU+Z4i6p 2F7L7cEoQze3aacVGkD9DoGwNwyzj42lPwdMoEd3Swy+pIBx0FI3fThZMH974jSo3TO8Xeij4ud wqKlloqobOw+BfdwCCNu4vk+YJMNNgClQOfIMIQo/69nCV65h9wd/dkT+3EjSVFJTP05bRC9hNo G6TJTuMvq/AzgpB1boOLrJltL5lUFMyYzNZObTU2yxs2NxP3j5Ntot4lxspXDhXKqR75nxRoTiG oYxDS/KQ50tG8l7amd6GB0TFFfSQLolkglKXK+jKjFilrF7BDC7RrQIDsJ/mK//h+JeEqDyDMD9 0xg/pLZnfC36TsfQmG0HAZ5pFqs6A8BfpuFExXHYQfasrDcNZaQxcQhEeCt29N7hQsgLGtbvl/I ZlzLIzwv+0Fn16g6rst+CsvXkUQxK005MNe0OU7wXfkc/3dryNRAmbHje/uC8TVounY2vOGMKVR 0qCgHRW2THBVoknRFhBJDrGXgv1yavOhjJ3hekKSbts189qY8b1zj9S9++pA6goUutQSztVOMgt auO7wvRRSHIntUbvu6PGRtzO6cAl7ImDAEdcQCVdpd+CTGQXpbZBEkOhrh7rO8x+VtisA7BBPR1 RibF+gzRr4CINpQ== X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Bhupesh Sharma The Snapdragon 845 and several other Qualcomm SoCs feature this USB high-speed phy. Add a driver for it based on the Linux driver, with support for the SDM845, and the QCM2290 and SM6115 SoCs which will gain support in U-Boot in future patches. Signed-off-by: Bhupesh Sharma [code cleanup, switch to clk_bulk] Acked-by: Sumit Garg Signed-off-by: Caleb Connolly --- drivers/phy/qcom/Kconfig | 7 + drivers/phy/qcom/Makefile | 1 + drivers/phy/qcom/phy-qcom-qusb2.c | 429 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 437 insertions(+) diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index f4ca174805a4..361dfb6e1126 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -11,8 +11,15 @@ config PHY_QCOM_IPQ4019_USB depends on PHY && ARCH_IPQ40XX help Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. +config PHY_QCOM_QUSB2 + tristate "Qualcomm USB QUSB2 PHY driver" + depends on PHY && ARCH_SNAPDRAGON + help + Enable this to support the Super-Speed USB transceiver on various + Qualcomm chipsets. + config PHY_QCOM_USB_HS_28NM tristate "Qualcomm 28nm High-Speed PHY" depends on PHY && ARCH_SNAPDRAGON help diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile index 2113f178c0c7..f6af985666a4 100644 --- a/drivers/phy/qcom/Makefile +++ b/drivers/phy/qcom/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o +obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c b/drivers/phy/qcom/phy-qcom-qusb2.c new file mode 100644 index 000000000000..c91ba18c4ab1 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qusb2.c @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Bhupesh Sharma + * + * Based on Linux driver + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define QUSB2PHY_PLL 0x0 +#define QUSB2PHY_PLL_TEST 0x04 +#define CLK_REF_SEL BIT(7) + +#define QUSB2PHY_PLL_TUNE 0x08 +#define QUSB2PHY_PLL_USER_CTL1 0x0c +#define QUSB2PHY_PLL_USER_CTL2 0x10 +#define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c +#define QUSB2PHY_PLL_PWR_CTRL 0x18 + +/* QUSB2PHY_PLL_STATUS register bits */ +#define PLL_LOCKED BIT(5) + +/* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */ +#define CORE_READY_STATUS BIT(0) + +/* QUSB2PHY_PORT_POWERDOWN register bits */ +#define CLAMP_N_EN BIT(5) +#define FREEZIO_N BIT(1) +#define POWER_DOWN BIT(0) + +/* QUSB2PHY_PWR_CTRL1 register bits */ +#define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5) +#define PWR_CTRL1_CLAMP_N_EN BIT(1) + +#define QUSB2PHY_REFCLK_ENABLE BIT(0) + +#define PHY_CLK_SCHEME_SEL BIT(0) + +/* QUSB2PHY_INTR_CTRL register bits */ +#define DMSE_INTR_HIGH_SEL BIT(4) +#define DPSE_INTR_HIGH_SEL BIT(3) +#define CHG_DET_INTR_EN BIT(2) +#define DMSE_INTR_EN BIT(1) +#define DPSE_INTR_EN BIT(0) + +/* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */ +#define CORE_PLL_EN_FROM_RESET BIT(4) +#define CORE_RESET BIT(5) +#define CORE_RESET_MUX BIT(6) + +/* QUSB2PHY_IMP_CTRL1 register bits */ +#define IMP_RES_OFFSET_MASK GENMASK(5, 0) +#define IMP_RES_OFFSET_SHIFT 0x0 + +/* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */ +#define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0) +#define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0 + +/* QUSB2PHY_CHG_CONTROL_2 register bits */ +#define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4) +#define CHG_CTRL2_OFFSET_SHIFT 0x4 + +/* QUSB2PHY_PORT_TUNE1 register bits */ +#define HSTX_TRIM_MASK GENMASK(7, 4) +#define HSTX_TRIM_SHIFT 0x4 +#define PREEMPH_WIDTH_HALF_BIT BIT(2) +#define PREEMPHASIS_EN_MASK GENMASK(1, 0) +#define PREEMPHASIS_EN_SHIFT 0x0 + +/* QUSB2PHY_PORT_TUNE2 register bits */ +#define HSDISC_TRIM_MASK GENMASK(1, 0) +#define HSDISC_TRIM_SHIFT 0x0 + +#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04 +#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c +#define QUSB2PHY_PLL_CMODE 0x2c +#define QUSB2PHY_PLL_LOCK_DELAY 0x184 +#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4 +#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194 +#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198 +#define QUSB2PHY_PWR_CTRL2 0x214 +#define QUSB2PHY_IMP_CTRL1 0x220 +#define QUSB2PHY_IMP_CTRL2 0x224 +#define QUSB2PHY_CHG_CTRL2 0x23c + +struct qusb2_phy_init_tbl { + unsigned int offset; + unsigned int val; + /* + * register part of layout ? + * if yes, then offset gives index in the reg-layout + */ + int in_layout; +}; + +struct qusb2_phy_cfg { + const struct qusb2_phy_init_tbl *tbl; + /* number of entries in the table */ + unsigned int tbl_num; + /* offset to PHY_CLK_SCHEME register in TCSR map */ + unsigned int clk_scheme_offset; + + /* array of registers with different offsets */ + const unsigned int *regs; + unsigned int mask_core_ready; + unsigned int disable_ctrl; + unsigned int autoresume_en; + + /* true if PHY has PLL_TEST register to select clk_scheme */ + bool has_pll_test; + + /* true if TUNE1 register must be updated by fused value, else TUNE2 */ + bool update_tune1_with_efuse; + + /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */ + bool has_pll_override; +}; + +/* set of registers with offsets different per-PHY */ +enum qusb2phy_reg_layout { + QUSB2PHY_PLL_CORE_INPUT_OVERRIDE, + QUSB2PHY_PLL_STATUS, + QUSB2PHY_PORT_TUNE1, + QUSB2PHY_PORT_TUNE2, + QUSB2PHY_PORT_TUNE3, + QUSB2PHY_PORT_TUNE4, + QUSB2PHY_PORT_TUNE5, + QUSB2PHY_PORT_TEST1, + QUSB2PHY_PORT_TEST2, + QUSB2PHY_PORT_POWERDOWN, + QUSB2PHY_INTR_CTRL, +}; + +#define QUSB2_PHY_INIT_CFG(o, v) \ + { \ + .offset = o, .val = v, \ + } + +#define QUSB2_PHY_INIT_CFG_L(o, v) \ + { \ + .offset = o, .val = v, .in_layout = 1, \ + } + +static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = { + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x81), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x17), + + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), + + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), + + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), +}; + +static const unsigned int sm6115_regs_layout[] = { + [QUSB2PHY_PLL_STATUS] = 0x38, [QUSB2PHY_PORT_TUNE1] = 0x80, + [QUSB2PHY_PORT_TUNE2] = 0x84, [QUSB2PHY_PORT_TUNE3] = 0x88, + [QUSB2PHY_PORT_TUNE4] = 0x8c, [QUSB2PHY_PORT_TUNE5] = 0x90, + [QUSB2PHY_PORT_TEST1] = 0xb8, [QUSB2PHY_PORT_TEST2] = 0x9c, + [QUSB2PHY_PORT_POWERDOWN] = 0xb4, [QUSB2PHY_INTR_CTRL] = 0xbc, +}; + +static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = { + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21), + QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0), + QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58), + + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03), + + QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0), +}; + +static const unsigned int qusb2_v2_regs_layout[] = { + [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8, + [QUSB2PHY_PLL_STATUS] = 0x1a0, + [QUSB2PHY_PORT_TUNE1] = 0x240, + [QUSB2PHY_PORT_TUNE2] = 0x244, + [QUSB2PHY_PORT_TUNE3] = 0x248, + [QUSB2PHY_PORT_TUNE4] = 0x24c, + [QUSB2PHY_PORT_TUNE5] = 0x250, + [QUSB2PHY_PORT_TEST1] = 0x254, + [QUSB2PHY_PORT_TEST2] = 0x258, + [QUSB2PHY_PORT_POWERDOWN] = 0x210, + [QUSB2PHY_INTR_CTRL] = 0x230, +}; + +static const struct qusb2_phy_cfg sm6115_phy_cfg = { + .tbl = sm6115_init_tbl, + .tbl_num = ARRAY_SIZE(sm6115_init_tbl), + .regs = sm6115_regs_layout, + + .has_pll_test = true, + .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), + .mask_core_ready = PLL_LOCKED, + .autoresume_en = BIT(3), +}; + +static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = { + .tbl = qusb2_v2_init_tbl, + .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl), + .regs = qusb2_v2_regs_layout, + + .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN | + POWER_DOWN), + .mask_core_ready = CORE_READY_STATUS, + .has_pll_override = true, + .autoresume_en = BIT(0), + .update_tune1_with_efuse = true, +}; + +/** + * struct qusb2_phy - structure holding qusb2 phy attributes + * + * @phy: generic phy + * @base: iomapped memory space for qubs2 phy + * + * @cfg_ahb_clk: AHB2PHY interface clock + * @phy_rst: phy reset control + * + * @cfg: phy config data + * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme + */ +struct qusb2_phy { + struct phy *phy; + void __iomem *base; + + struct clk cfg_ahb_clk; + struct reset_ctl phy_rst; + + const struct qusb2_phy_cfg *cfg; + bool has_se_clk_scheme; +}; + +static inline void qusb2_phy_configure(void __iomem *base, + const unsigned int *regs, + const struct qusb2_phy_init_tbl tbl[], + int num) +{ + int i; + + for (i = 0; i < num; i++) { + if (tbl[i].in_layout) + writel(tbl[i].val, base + regs[tbl[i].offset]); + else + writel(tbl[i].val, base + tbl[i].offset); + } +} + +static int qusb2phy_do_reset(struct qusb2_phy *qphy) +{ + int ret; + + ret = reset_assert(&qphy->phy_rst); + if (ret) + return ret; + + udelay(500); + + ret = reset_deassert(&qphy->phy_rst); + if (ret) + return ret; + + return 0; +} + +static int qusb2phy_power_on(struct phy *phy) +{ + struct qusb2_phy *qphy = dev_get_priv(phy->dev); + const struct qusb2_phy_cfg *cfg = qphy->cfg; + int ret; + u32 val; + + ret = qusb2phy_do_reset(qphy); + if (ret) + return ret; + + /* Disable the PHY */ + setbits_le32(qphy->base + cfg->regs[QUSB2PHY_PORT_POWERDOWN], + qphy->cfg->disable_ctrl); + + if (cfg->has_pll_test) { + /* save reset value to override reference clock scheme later */ + val = readl(qphy->base + QUSB2PHY_PLL_TEST); + } + + qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, cfg->tbl_num); + + /* Enable the PHY */ + clrbits_le32(qphy->base + cfg->regs[QUSB2PHY_PORT_POWERDOWN], + POWER_DOWN); + + /* Required to get phy pll lock successfully */ + udelay(150); + + if (cfg->has_pll_test) { + val |= CLK_REF_SEL; + + writel(val, qphy->base + QUSB2PHY_PLL_TEST); + + /* ensure above write is through */ + readl(qphy->base + QUSB2PHY_PLL_TEST); + } + + /* Required to get phy pll lock successfully */ + udelay(100); + + val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); + if (!(val & cfg->mask_core_ready)) { + pr_err("QUSB2PHY pll lock failed: status reg = %x\n", val); + ret = -EBUSY; + return ret; + } + + return 0; +} + +static int qusb2phy_power_off(struct phy *phy) +{ + struct qusb2_phy *qphy = dev_get_priv(phy->dev); + + /* Disable the PHY */ + setbits_le32(qphy->base + qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], + qphy->cfg->disable_ctrl); + + reset_assert(&qphy->phy_rst); + + clk_disable(&qphy->cfg_ahb_clk); + + return 0; +} + +static int qusb2phy_clk_init(struct udevice *dev, struct qusb2_phy *qphy) +{ + int ret; + + /* We ignore the ref clock as we currently lack a driver for rpmcc/rpmhcc where + * it usually comes from - we assume it's always on. + */ + ret = clk_get_by_name(dev, "cfg_ahb", &qphy->cfg_ahb_clk); + if (ret == -ENOSYS || ret == -ENOENT) + return 0; + if (ret) + return ret; + + ret = clk_enable(&qphy->cfg_ahb_clk); + if (ret) + return ret; + + return 0; +} + +static int qusb2phy_probe(struct udevice *dev) +{ + struct qusb2_phy *qphy = dev_get_priv(dev); + int ret; + + qphy->base = (void __iomem *)dev_read_addr(dev); + if (IS_ERR(qphy->base)) + return PTR_ERR(qphy->base); + + ret = qusb2phy_clk_init(dev, qphy); + if (ret) { + printf("%s: Couldn't get clocks: %d\n", __func__, ret); + return ret; + } + + ret = reset_get_by_index(dev, 0, &qphy->phy_rst); + if (ret) { + printf("%s: Couldn't get resets: %d\n", __func__, ret); + return ret; + } + + qphy->cfg = (const struct qusb2_phy_cfg *)dev_get_driver_data(dev); + if (!qphy->cfg) { + printf("%s: Couldn't get driver data\n", __func__); + return -EINVAL; + } + + debug("%s success qusb phy cfg %p\n", __func__, qphy->cfg); + return 0; +} + +static struct phy_ops qusb2phy_ops = { + .power_on = qusb2phy_power_on, + .power_off = qusb2phy_power_off, +}; + +static const struct udevice_id qusb2phy_ids[] = { + { .compatible = "qcom,qusb2-phy" }, + { .compatible = "qcom,qcm2290-qusb2-phy", + .data = (ulong)&sm6115_phy_cfg }, + { .compatible = "qcom,sm6115-qusb2-phy", + .data = (ulong)&sm6115_phy_cfg }, + { .compatible = "qcom,qusb2-v2-phy", .data = (ulong)&qusb2_v2_phy_cfg }, + {} +}; + +U_BOOT_DRIVER(qcom_qusb2_phy) = { + .name = "qcom-qusb2-phy", + .id = UCLASS_PHY, + .of_match = qusb2phy_ids, + .ops = &qusb2phy_ops, + .probe = qusb2phy_probe, + .priv_auto = sizeof(struct qusb2_phy), +}; From patchwork Wed Apr 3 12:07:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 785414 Delivered-To: patch@linaro.org Received: by 2002:adf:f001:0:b0:33e:7753:30bd with SMTP id j1csp280322wro; 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Bhupesh Sharma Some Qualcomm SoCs newer than SDM845 feature a so-called "7nm phy" driver, notable the SM8250 SoC which will gain U-Boot support in upcoming patches. Introduce a driver based on the Linux driver. Signed-off-by: Bhupesh Sharma [code cleanup, align symbol names with Linux, switch to clk/reset_bulk APIs] Acked-by: Sumit Garg Signed-off-by: Caleb Connolly --- drivers/phy/qcom/Kconfig | 8 ++ drivers/phy/qcom/Makefile | 1 + drivers/phy/qcom/phy-qcom-snps-femto-v2.c | 216 ++++++++++++++++++++++++++++++ 3 files changed, 225 insertions(+) diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index 361dfb6e1126..b9fe608c2798 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -18,8 +18,16 @@ config PHY_QCOM_QUSB2 help Enable this to support the Super-Speed USB transceiver on various Qualcomm chipsets. +config PHY_QCOM_USB_SNPS_FEMTO_V2 + tristate "Qualcomm SNPS FEMTO USB HS PHY v2" + depends on PHY && ARCH_SNAPDRAGON + help + Enable this to support the Qualcomm Synopsys DesignWare Core 7nm + High-Speed PHY driver. This driver supports the Hi-Speed PHY which + is usually paired with Synopsys DWC3 USB IPs on MSM SOCs. + config PHY_QCOM_USB_HS_28NM tristate "Qualcomm 28nm High-Speed PHY" depends on PHY && ARCH_SNAPDRAGON help diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile index f6af985666a4..5f4db4a53788 100644 --- a/drivers/phy/qcom/Makefile +++ b/drivers/phy/qcom/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o +obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2) += phy-qcom-snps-femto-v2.o obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qcom/phy-qcom-snps-femto-v2.c b/drivers/phy/qcom/phy-qcom-snps-femto-v2.c new file mode 100644 index 000000000000..a1675b664e46 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-snps-femto-v2.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (C) 2023 Bhupesh Sharma + * + * Based on Linux driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c) +#define SLEEPM BIT(0) +#define OPMODE_MASK GENMASK(4, 3) +#define OPMODE_NORMAL (0x00) +#define OPMODE_NONDRIVING BIT(3) +#define TERMSEL BIT(5) + +#define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50) +#define POR BIT(1) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) +#define SIDDQ BIT(2) +#define RETENABLEN BIT(3) +#define FSEL_MASK GENMASK(6, 4) +#define FSEL_DEFAULT (0x3 << 4) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58) +#define VBUSVLDEXTSEL0 BIT(4) +#define PLLBTUNE BIT(5) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c) +#define VREGBYPASS BIT(0) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60) +#define VBUSVLDEXT0 BIT(0) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64) +#define USB2_AUTO_RESUME BIT(0) +#define USB2_SUSPEND_N BIT(2) +#define USB2_SUSPEND_N_SEL BIT(3) + +#define USB2_PHY_USB_PHY_CFG0 (0x94) +#define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0) +#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1) + +#define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0) +#define REFCLK_SEL_MASK GENMASK(1, 0) +#define REFCLK_SEL_DEFAULT (0x2 << 0) + +struct qcom_snps_hsphy { + void __iomem *base; + struct clk_bulk clks; + struct reset_ctl_bulk resets; +}; + +/* + * We should just be able to use clrsetbits_le32() here, but this results + * in crashes on some boards. This is suspected to be because of some bus + * arbitration quirks with the PHY (i.e. it takes several bus clock cycles + * for the write to actually go through). The readl_relaxed() at the end will + * block until the write is completed (and all registers updated), and thus + * ensure that we don't access the PHY registers when they're in an + * undetermined state. + */ +static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset, + u32 mask, u32 val) +{ + u32 reg; + + reg = readl_relaxed(base + offset); + + reg &= ~mask; + reg |= val & mask; + writel_relaxed(reg, base + offset); + + /* Ensure above write is completed */ + readl_relaxed(base + offset); +} + +static int qcom_snps_hsphy_usb_init(struct phy *phy) +{ + struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_CFG0, + UTMI_PHY_CMN_CTRL_OVERRIDE_EN, + UTMI_PHY_CMN_CTRL_OVERRIDE_EN); + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_UTMI_CTRL5, POR, + POR); + qcom_snps_hsphy_write_mask(priv->base, + USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, FSEL_MASK, 0); + qcom_snps_hsphy_write_mask(priv->base, + USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, + PLLBTUNE, PLLBTUNE); + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_REFCLK_CTRL, + REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK); + qcom_snps_hsphy_write_mask(priv->base, + USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, + VBUSVLDEXTSEL0, VBUSVLDEXTSEL0); + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1, + VBUSVLDEXT0, VBUSVLDEXT0); + + qcom_snps_hsphy_write_mask(priv->base, + USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, + VREGBYPASS, VREGBYPASS); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_UTMI_CTRL0, + SLEEPM, SLEEPM); + + qcom_snps_hsphy_write_mask( + priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ, 0); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_UTMI_CTRL5, POR, + 0); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL, 0); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_CFG0, + UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0); + + return 0; +} + +static int qcom_snps_hsphy_power_on(struct phy *phy) +{ + struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev); + int ret; + + clk_enable_bulk(&priv->clks); + + ret = reset_deassert_bulk(&priv->resets); + if (ret) + return ret; + + ret = qcom_snps_hsphy_usb_init(phy); + if (ret) + return ret; + + return 0; +} + +static int qcom_snps_hsphy_power_off(struct phy *phy) +{ + struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev); + + reset_assert_bulk(&priv->resets); + clk_disable_bulk(&priv->clks); + + return 0; +} + +static int qcom_snps_hsphy_phy_probe(struct udevice *dev) +{ + struct qcom_snps_hsphy *priv = dev_get_priv(dev); + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + ret = clk_get_bulk(dev, &priv->clks); + if (ret < 0 && ret != -ENOENT) { + printf("%s: Failed to get clocks %d\n", __func__, ret); + return ret; + } + + ret = reset_get_bulk(dev, &priv->resets); + if (ret < 0) { + printf("failed to get resets, ret = %d\n", ret); + return ret; + } + + clk_enable_bulk(&priv->clks); + reset_deassert_bulk(&priv->resets); + + return 0; +} + +static struct phy_ops qcom_snps_hsphy_phy_ops = { + .power_on = qcom_snps_hsphy_power_on, + .power_off = qcom_snps_hsphy_power_off, +}; + +static const struct udevice_id qcom_snps_hsphy_phy_ids[] = { + { .compatible = "qcom,sm8150-usb-hs-phy" }, + { .compatible = "qcom,usb-snps-hs-5nm-phy" }, + { .compatible = "qcom,usb-snps-hs-7nm-phy" }, + { .compatible = "qcom,usb-snps-femto-v2-phy" }, + {} +}; + +U_BOOT_DRIVER(qcom_usb_qcom_snps_hsphy) = { + .name = "qcom-snps-hsphy", + .id = UCLASS_PHY, + .of_match = qcom_snps_hsphy_phy_ids, + .ops = &qcom_snps_hsphy_phy_ops, + .probe = qcom_snps_hsphy_phy_probe, + .priv_auto = sizeof(struct qcom_snps_hsphy), +}; From patchwork Wed Apr 3 12:07:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 785415 Delivered-To: patch@linaro.org Received: by 2002:adf:f001:0:b0:33e:7753:30bd with SMTP id j1csp280415wro; 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-qcom.c | 2 ++ drivers/clk/qcom/clock-sdm845.c | 2 +- drivers/serial/serial_msm_geni.c | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 7a5938a06a34..6303dcbf8461 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -226,8 +226,9 @@ U_BOOT_DRIVER(qcom_clk) = { .id = UCLASS_CLK, .ops = &msm_clk_ops, .priv_auto = sizeof(struct msm_clk_priv), .probe = msm_clk_probe, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, }; int qcom_cc_bind(struct udevice *parent) { @@ -410,5 +411,6 @@ U_BOOT_DRIVER(qcom_power) = { .name = "qcom_power", .id = UCLASS_POWER_DOMAIN, .ops = &qcom_power_ops, .probe = qcom_power_probe, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index 36ffee79d966..babd83119e2c 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -182,6 +182,6 @@ U_BOOT_DRIVER(gcc_sdm845) = { .name = "gcc_sdm845", .id = UCLASS_NOP, .of_match = gcc_sdm845_of_match, .bind = qcom_cc_bind, - .flags = DM_FLAG_PRE_RELOC, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, }; diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index e5c3dcffc1c6..4aa0bc8c72bc 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -602,9 +602,9 @@ U_BOOT_DRIVER(serial_msm_geni) = { .of_to_plat = msm_serial_ofdata_to_platdata, .priv_auto = sizeof(struct msm_serial_data), .probe = msm_serial_probe, .ops = &msm_serial_ops, - .flags = DM_FLAG_PRE_RELOC, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, }; #ifdef CONFIG_DEBUG_UART_MSM_GENI From patchwork Wed Apr 3 12:07:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 785416 Delivered-To: patch@linaro.org Received: by 2002:adf:f001:0:b0:33e:7753:30bd with SMTP id j1csp280504wro; Wed, 3 Apr 2024 05:08:46 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVOHwNLxg2V7zGChT1kxyO74AqZaiPyLY01UhevMwLN24lph9ZvAnV/MWKhqAVcL8U9CLITNAxqNUPnTaj6dzFG X-Google-Smtp-Source: AGHT+IGH85Zz9zCMStLUZf7DQcRl0XXUW2uSuxpMy2N3/lr20Aaw4OvskMqwAQKgvt0bsOsgDrmx X-Received: by 2002:a17:906:ccc3:b0:a47:4b3e:a966 with SMTP id ot3-20020a170906ccc300b00a474b3ea966mr9735929ejb.75.1712146126034; Wed, 03 Apr 2024 05:08:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712146126; cv=none; d=google.com; s=arc-20160816; b=JBrU8TKG5o7EhmVwWZNVFAJaRwv+FT0rYCAG1RNomJX4SSskWvwH7SUumSkqAhB7B5 kJ0OaFCpSNfQlxr15p0NGq9S0OFjPb4hi9dRsRy61cnSa5swkD3p6tJuSjQuDBHP8xQP aL7SigdOT47hMnanxYjM9IPQgGeBXEX9QAOa/SRMqWZk2BoTydLQkDyUjOMgDqcwXgWH GQwDHLjAVzPrRjlDLyCQgoJdkvWGimeQSVSZdFnm/EAQpQoILEY0CCS7tVDzETf+6vl1 LPbYsoygElvhptOq+YiJwbhtf/wpQSLY6+KWDqLYhhkTSbYt9ClQI+ZugrqH+4IICVxI dJhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=juaadawQi5dtqVZYnJ+QwO1/OAexPncDaRDXhesSnrw=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=ADb+TE+oVRuzHn8/5N+2cZeRxUQXJ9L1UrAXQHJU1DePymwyU790PxyTkI2INvcSf2 juAbsJM+h1kTzh1+Zs+oSXBGCvsccpLdj7EMyjetz28IjBNYZoAAm7KzEtyEQlsm3ajg 5vUDHvDnvwRangaVbhoxv5rAewQ7bMspPSaASNon+7vxXf7cNrZTUlK2QT7Mei3q96Jg HVSq6ToIJSaVhnEXsg08QYJyURTiFhXA3Vd5smIh/5UUzlmw/tW6ZPSq4QBeC5z4nCrd TaivoYvJl5DPyfEoXc+C93LDBuysf/op2c7XIxRZ73GOlbto33ju1ds0Fscd5BAry/XX xX4w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WchRs6y0; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-apq8016.c | 39 +------------ drivers/clk/qcom/clock-apq8096.c | 28 +-------- drivers/clk/qcom/clock-qcom.c | 22 +++---- drivers/clk/qcom/clock-qcom.h | 16 +++-- drivers/clk/qcom/clock-qcs404.c | 122 +++++---------------------------------- drivers/clk/qcom/clock-sdm845.c | 16 +---- 6 files changed, 39 insertions(+), 204 deletions(-) diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index e6647f7c41dd..5a5868169c89 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -22,13 +22,9 @@ #define APCS_GPLL_ENA_VOTE (0x45000) #define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) #define SDCC_BCR(n) ((n * 0x1000) + 0x41000) -#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004) -#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008) -#define SDCC_M(n) ((n * 0x1000) + 0x4100C) -#define SDCC_N(n) ((n * 0x1000) + 0x41010) -#define SDCC_D(n) ((n * 0x1000) + 0x41014) +#define SDCC_CMD_RCGR(n) (((n + 1) * 0x1000) + 0x41004) #define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018) #define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C) /* BLSP1 AHB clock (root clock for BLSP) */ @@ -37,33 +33,12 @@ /* Uart clock control registers */ #define BLSP1_UART2_BCR (0x3028) #define BLSP1_UART2_APPS_CBCR (0x302C) #define BLSP1_UART2_APPS_CMD_RCGR (0x3034) -#define BLSP1_UART2_APPS_CFG_RCGR (0x3038) -#define BLSP1_UART2_APPS_M (0x303C) -#define BLSP1_UART2_APPS_N (0x3040) -#define BLSP1_UART2_APPS_D (0x3044) /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(17) -static const struct bcr_regs sdc_regs[] = { - { - .cfg_rcgr = SDCC_CFG_RCGR(1), - .cmd_rcgr = SDCC_CMD_RCGR(1), - .M = SDCC_M(1), - .N = SDCC_N(1), - .D = SDCC_D(1), - }, - { - .cfg_rcgr = SDCC_CFG_RCGR(2), - .cmd_rcgr = SDCC_CMD_RCGR(2), - .M = SDCC_M(2), - .N = SDCC_N(2), - .D = SDCC_D(2), - } -}; - static struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, .ena_vote = APCS_GPLL_ENA_VOTE, @@ -85,32 +60,24 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) div = 4; clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot)); /* 800Mhz/div, gpll0 */ - clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0, + clk_rcg_set_rate_mnd(priv->base, SDCC_CMD_RCGR(slot), div, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot)); return rate; } -static const struct bcr_regs uart2_regs = { - .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR, - .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR, - .M = BLSP1_UART2_APPS_M, - .N = BLSP1_UART2_APPS_N, - .D = BLSP1_UART2_APPS_D, -}; - /* UART: 115200 */ int apq8016_clk_init_uart(phys_addr_t base) { /* Enable AHB clock */ clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk); /* 7372800 uart block clock @ GPLL0 */ - clk_rcg_set_rate_mnd(base, &uart2_regs, 1, 144, 15625, + clk_rcg_set_rate_mnd(base, BLSP1_UART2_APPS_CMD_RCGR, 1, 144, 15625, CFG_CLK_SRC_GPLL0, 16); /* Vote for gpll0 clock */ clk_enable_gpll0(base, &gpll0_vote_clk); diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index a4731613c5e0..479f9771a464 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -25,33 +25,17 @@ #define SDCC2_BCR (0x14000) /* block reset */ #define SDCC2_APPS_CBCR (0x14004) /* branch control */ #define SDCC2_AHB_CBCR (0x14008) #define SDCC2_CMD_RCGR (0x14010) -#define SDCC2_CFG_RCGR (0x14014) -#define SDCC2_M (0x14018) -#define SDCC2_N (0x1401C) -#define SDCC2_D (0x14020) #define BLSP2_AHB_CBCR (0x25004) #define BLSP2_UART2_APPS_CBCR (0x29004) #define BLSP2_UART2_APPS_CMD_RCGR (0x2900C) -#define BLSP2_UART2_APPS_CFG_RCGR (0x29010) -#define BLSP2_UART2_APPS_M (0x29014) -#define BLSP2_UART2_APPS_N (0x29018) -#define BLSP2_UART2_APPS_D (0x2901C) /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(30) #define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0) -static const struct bcr_regs sdc_regs = { - .cfg_rcgr = SDCC2_CFG_RCGR, - .cmd_rcgr = SDCC2_CMD_RCGR, - .M = SDCC2_M, - .N = SDCC2_N, - .D = SDCC2_D, -}; - static const struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, .ena_vote = APCS_GPLL_ENA_VOTE, @@ -68,31 +52,23 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) { int div = 5; clk_enable_cbc(priv->base + SDCC2_AHB_CBCR); - clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0, + clk_rcg_set_rate_mnd(priv->base, SDCC2_CMD_RCGR, div, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC2_APPS_CBCR); return rate; } -static const struct bcr_regs uart2_regs = { - .cfg_rcgr = BLSP2_UART2_APPS_CFG_RCGR, - .cmd_rcgr = BLSP2_UART2_APPS_CMD_RCGR, - .M = BLSP2_UART2_APPS_M, - .N = BLSP2_UART2_APPS_N, - .D = BLSP2_UART2_APPS_D, -}; - static int clk_init_uart(struct msm_clk_priv *priv) { /* Enable AHB clock */ clk_enable_vote_clk(priv->base, &gcc_blsp2_ahb_clk); /* 7372800 uart block clock @ GPLL0 */ - clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625, + clk_rcg_set_rate_mnd(priv->base, BLSP2_UART2_APPS_CMD_RCGR, 1, 192, 15625, CFG_CLK_SRC_GPLL0, 16); /* Vote for gpll0 clock */ clk_enable_gpll0(priv->base, &gpll0_vote_clk); diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 6303dcbf8461..05e5ab7d094b 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -103,9 +103,9 @@ void clk_bcr_update(phys_addr_t apps_cmd_rcgr) /* * root set rate for clocks with half integer and MND divider * div should be pre-calculated ((div * 2) - 1) */ -void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, +void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr, int div, int m, int n, int source, u8 mnd_width) { u32 cfg; /* M value for MND divider. */ @@ -119,14 +119,14 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, debug("m %#x n %#x d %#x div %#x mask %#x\n", m_val, n_val, d_val, div, mask); /* Program MND values */ - writel(m_val & mask, base + regs->M); - writel(n_val & mask, base + regs->N); - writel(d_val & mask, base + regs->D); + writel(m_val & mask, base + cmd_rcgr + RCG_M_REG); + writel(n_val & mask, base + cmd_rcgr + RCG_N_REG); + writel(d_val & mask, base + cmd_rcgr + RCG_D_REG); /* setup src select and divider */ - cfg = readl(base + regs->cfg_rcgr); + cfg = readl(base + cmd_rcgr + RCG_CFG_REG); cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK | CFG_SRC_DIV_MASK); cfg |= source & CFG_SRC_SEL_MASK; /* Select clock source */ @@ -135,22 +135,22 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, if (n && n != m) cfg |= CFG_MODE_DUAL_EDGE; - writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ + writel(cfg, base + cmd_rcgr + RCG_CFG_REG); /* Write new clock configuration */ /* Inform h/w to start using the new config. */ - clk_bcr_update(base + regs->cmd_rcgr); + clk_bcr_update(base + cmd_rcgr); } /* root set rate for clocks with half integer and mnd_width=0 */ -void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, +void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, int source) { u32 cfg; /* setup src select and divider */ - cfg = readl(base + regs->cfg_rcgr); + cfg = readl(base + cmd_rcgr + RCG_CFG_REG); cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK); cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */ /* @@ -159,12 +159,12 @@ void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, */ if (div) cfg |= (2 * div - 1) & CFG_SRC_DIV_MASK; - writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ + writel(cfg, base + cmd_rcgr + RCG_CFG_REG); /* Write new clock configuration */ /* Inform h/w to start using the new config. */ - clk_bcr_update(base + regs->cmd_rcgr); + clk_bcr_update(base + cmd_rcgr); } const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) { diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index 12a1eaec2b2e..a7f833a4b6dd 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -11,8 +11,13 @@ #define CFG_CLK_SRC_GPLL0 (1 << 8) #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8) #define CFG_CLK_SRC_MASK (7 << 8) +#define RCG_CFG_REG 0x4 +#define RCG_M_REG 0x8 +#define RCG_N_REG 0xc +#define RCG_D_REG 0x10 + struct pll_vote_clk { uintptr_t status; int status_bit; uintptr_t ena_vote; @@ -23,15 +28,8 @@ struct vote_clk { uintptr_t cbcr_reg; uintptr_t ena_vote; int vote_bit; }; -struct bcr_regs { - uintptr_t cfg_rcgr; - uintptr_t cmd_rcgr; - uintptr_t M; - uintptr_t N; - uintptr_t D; -}; struct freq_tbl { uint freq; uint src; @@ -87,11 +85,11 @@ void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0); void clk_bcr_update(phys_addr_t apps_cmd_rgcr); void clk_enable_cbc(phys_addr_t cbcr); void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate); -void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, +void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr, int div, int m, int n, int source, u8 mnd_width); -void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, +void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, int source); static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id) { diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index 958312b88842..8a897a52bc00 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -27,37 +27,24 @@ /* Uart clock control registers */ #define BLSP1_UART2_BCR (0x3028) #define BLSP1_UART2_APPS_CBCR (0x302C) #define BLSP1_UART2_APPS_CMD_RCGR (0x3034) -#define BLSP1_UART2_APPS_CFG_RCGR (0x3038) -#define BLSP1_UART2_APPS_M (0x303C) -#define BLSP1_UART2_APPS_N (0x3040) -#define BLSP1_UART2_APPS_D (0x3044) /* I2C controller clock control registerss */ #define BLSP1_QUP0_I2C_APPS_CBCR (0x6028) #define BLSP1_QUP0_I2C_APPS_CMD_RCGR (0x602C) -#define BLSP1_QUP0_I2C_APPS_CFG_RCGR (0x6030) #define BLSP1_QUP1_I2C_APPS_CBCR (0x2008) #define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x200C) -#define BLSP1_QUP1_I2C_APPS_CFG_RCGR (0x2010) #define BLSP1_QUP2_I2C_APPS_CBCR (0x3010) #define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x3000) -#define BLSP1_QUP2_I2C_APPS_CFG_RCGR (0x3004) #define BLSP1_QUP3_I2C_APPS_CBCR (0x4020) #define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x4000) -#define BLSP1_QUP3_I2C_APPS_CFG_RCGR (0x4004) #define BLSP1_QUP4_I2C_APPS_CBCR (0x5020) #define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x5000) -#define BLSP1_QUP4_I2C_APPS_CFG_RCGR (0x5004) /* SD controller clock control registers */ #define SDCC_BCR(n) (((n) * 0x1000) + 0x41000) -#define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x41004) -#define SDCC_CFG_RCGR(n) (((n) * 0x1000) + 0x41008) -#define SDCC_M(n) (((n) * 0x1000) + 0x4100C) -#define SDCC_N(n) (((n) * 0x1000) + 0x41010) -#define SDCC_D(n) (((n) * 0x1000) + 0x41014) +#define SDCC_CMD_RCGR(n) (((n + 1) * 0x1000) + 0x41004) #define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018) #define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C) /* USB-3.0 controller clock control registers */ @@ -69,12 +56,8 @@ #define USB30_MOCK_UTMI_CBCR (0x39014) #define USB30_MOCK_UTMI_CMD_RCGR (0x3901C) #define USB30_MOCK_UTMI_CFG_RCGR (0x39020) #define USB30_MASTER_CMD_RCGR (0x39028) -#define USB30_MASTER_CFG_RCGR (0x3902C) -#define USB30_MASTER_M (0x39030) -#define USB30_MASTER_N (0x39034) -#define USB30_MASTER_D (0x39038) #define USB2A_PHY_SLEEP_CBCR (0x4102C) #define USB_HS_PHY_CFG_AHB_CBCR (0x41030) /* ETH controller clock control registers */ @@ -82,14 +65,9 @@ #define ETH_RGMII_CBCR (0x4e008) #define ETH_SLAVE_AHB_CBCR (0x4e00c) #define ETH_AXI_CBCR (0x4e010) #define EMAC_PTP_CMD_RCGR (0x4e014) -#define EMAC_PTP_CFG_RCGR (0x4e018) #define EMAC_CMD_RCGR (0x4e01c) -#define EMAC_CFG_RCGR (0x4e020) -#define EMAC_M (0x4e024) -#define EMAC_N (0x4e028) -#define EMAC_D (0x4e02c) /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(31) @@ -102,24 +80,8 @@ static struct vote_clk gcc_blsp1_ahb_clk = { .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE, .vote_bit = BIT(10) | BIT(5) | BIT(4), }; -static const struct bcr_regs uart2_regs = { - .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR, - .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR, - .M = BLSP1_UART2_APPS_M, - .N = BLSP1_UART2_APPS_N, - .D = BLSP1_UART2_APPS_D, -}; - -static const struct bcr_regs sdc_regs = { - .cfg_rcgr = SDCC_CFG_RCGR(1), - .cmd_rcgr = SDCC_CMD_RCGR(1), - .M = SDCC_M(1), - .N = SDCC_N(1), - .D = SDCC_D(1), -}; - static struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, .ena_vote = APCS_GPLL_ENA_VOTE, @@ -132,92 +94,38 @@ static struct pll_vote_clk gpll1_vote_clk = { .ena_vote = APCS_GPLL_ENA_VOTE, .vote_bit = BIT(1), }; -static const struct bcr_regs usb30_master_regs = { - .cfg_rcgr = USB30_MASTER_CFG_RCGR, - .cmd_rcgr = USB30_MASTER_CMD_RCGR, - .M = USB30_MASTER_M, - .N = USB30_MASTER_N, - .D = USB30_MASTER_D, -}; - -static const struct bcr_regs emac_regs = { - .cfg_rcgr = EMAC_CFG_RCGR, - .cmd_rcgr = EMAC_CMD_RCGR, - .M = EMAC_M, - .N = EMAC_N, - .D = EMAC_D, -}; - -static const struct bcr_regs emac_ptp_regs = { - .cfg_rcgr = EMAC_PTP_CFG_RCGR, - .cmd_rcgr = EMAC_PTP_CMD_RCGR, - .M = EMAC_M, - .N = EMAC_N, - .D = EMAC_D, -}; - -static const struct bcr_regs blsp1_qup0_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP0_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP0_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - -static const struct bcr_regs blsp1_qup1_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP1_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP1_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - -static const struct bcr_regs blsp1_qup2_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP2_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP2_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - -static const struct bcr_regs blsp1_qup3_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP3_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP3_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - -static const struct bcr_regs blsp1_qup4_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP4_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP4_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); switch (clk->id) { case GCC_BLSP1_UART2_APPS_CLK: /* UART: 1843200Hz for a fixed 115200 baudrate (19200000 * (12/125)) */ - clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125, + clk_rcg_set_rate_mnd(priv->base, BLSP1_UART2_APPS_CMD_RCGR, 0, 12, 125, CFG_CLK_SRC_CXO, 16); clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); return 1843200; case GCC_SDCC1_APPS_CLK: /* SDCC1: 200MHz */ - clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 7, 0, 0, + clk_rcg_set_rate_mnd(priv->base, SDCC_CMD_RCGR(0), 7, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1)); return rate; case GCC_ETH_RGMII_CLK: if (rate == 250000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 0, 0, CFG_CLK_SRC_GPLL1, 8); else if (rate == 125000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 7, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 7, 0, 0, CFG_CLK_SRC_GPLL1, 8); else if (rate == 50000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 19, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 19, 0, 0, CFG_CLK_SRC_GPLL1, 8); else if (rate == 5000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 1, 50, CFG_CLK_SRC_GPLL1, 8); return rate; } @@ -236,9 +144,9 @@ static int qcs404_clk_enable(struct clk *clk) switch (clk->id) { case GCC_USB30_MASTER_CLK: clk_enable_cbc(priv->base + USB30_MASTER_CBCR); - clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 7, 0, 0, + clk_rcg_set_rate_mnd(priv->base, USB30_MASTER_CMD_RCGR, 7, 0, 0, CFG_CLK_SRC_GPLL0, 8); break; case GCC_SYS_NOC_USB3_CLK: clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR); @@ -258,16 +166,16 @@ static int qcs404_clk_enable(struct clk *clk) case GCC_ETH_PTP_CLK: /* SPEED_1000: freq -> 250MHz */ clk_enable_cbc(priv->base + ETH_PTP_CBCR); clk_enable_gpll0(priv->base, &gpll1_vote_clk); - clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 3, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_PTP_CMD_RCGR, 3, 0, 0, CFG_CLK_SRC_GPLL1, 8); break; case GCC_ETH_RGMII_CLK: /* SPEED_1000: freq -> 250MHz */ clk_enable_cbc(priv->base + ETH_RGMII_CBCR); clk_enable_gpll0(priv->base, &gpll1_vote_clk); - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 0, 0, CFG_CLK_SRC_GPLL1, 8); break; case GCC_ETH_SLAVE_AHB_CLK: clk_enable_cbc(priv->base + ETH_SLAVE_AHB_CBCR); @@ -279,29 +187,29 @@ static int qcs404_clk_enable(struct clk *clk) clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk); break; case GCC_BLSP1_QUP0_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP0_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup0_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP0_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_BLSP1_QUP1_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP1_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup1_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP1_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_BLSP1_QUP2_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP2_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup2_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP2_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_BLSP1_QUP3_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP3_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup3_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP3_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_BLSP1_QUP4_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP4_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP4_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_SDCC1_AHB_CLK: clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1)); diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index babd83119e2c..ccb0cf245d33 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -18,15 +18,9 @@ #include #include "clock-qcom.h" -#define SE9_AHB_CBCR 0x25004 -#define SE9_UART_APPS_CBCR 0x29004 #define SE9_UART_APPS_CMD_RCGR 0x18148 -#define SE9_UART_APPS_CFG_RCGR 0x1814C -#define SE9_UART_APPS_M 0x18150 -#define SE9_UART_APPS_N 0x18154 -#define SE9_UART_APPS_D 0x18158 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), @@ -45,25 +39,17 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75), { } }; -static const struct bcr_regs uart2_regs = { - .cfg_rcgr = SE9_UART_APPS_CFG_RCGR, - .cmd_rcgr = SE9_UART_APPS_CMD_RCGR, - .M = SE9_UART_APPS_M, - .N = SE9_UART_APPS_N, - .D = SE9_UART_APPS_D, -}; - static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); const struct freq_tbl *freq; switch (clk->id) { case GCC_QUPV3_WRAP1_S1_CLK: /* UART9 */ freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); - clk_rcg_set_rate_mnd(priv->base, &uart2_regs, + clk_rcg_set_rate_mnd(priv->base, SE9_UART_APPS_CMD_RCGR, freq->pre_div, freq->m, freq->n, freq->src, 16); return freq->freq; default: return 0; From patchwork Wed Apr 3 12:07:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 785417 Delivered-To: patch@linaro.org Received: by 2002:adf:f001:0:b0:33e:7753:30bd with SMTP id j1csp280606wro; Wed, 3 Apr 2024 05:08:57 -0700 (PDT) X-Forwarded-Encrypted: i=2; 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Define the GDSC power domains for SDM845. Reviewed-by: Neil Armstrong Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-sdm845.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index ccb0cf245d33..b7154360894a 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -145,13 +145,31 @@ static const struct qcom_reset_map sdm845_gcc_resets[] = { [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, }; +static const struct qcom_power_map sdm845_gdscs[] = { + [PCIE_0_GDSC] = { 0x6b004 }, + [PCIE_1_GDSC] = { 0x8d004 }, + [UFS_CARD_GDSC] = { 0x75004 }, + [UFS_PHY_GDSC] = { 0x77004 }, + [USB30_PRIM_GDSC] = { 0xf004 }, + [USB30_SEC_GDSC] = { 0x10004 }, + [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { 0x7d030 }, + [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = { 0x7d03c }, + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { 0x7d034 }, + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { 0x7d038 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0x7d040 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 }, +}; + static struct msm_clk_data sdm845_clk_data = { .resets = sdm845_gcc_resets, .num_resets = ARRAY_SIZE(sdm845_gcc_resets), .clks = sdm845_clks, .num_clks = ARRAY_SIZE(sdm845_clks), + .power_domains = sdm845_gdscs, + .num_power_domains = ARRAY_SIZE(sdm845_gdscs), .enable = sdm845_clk_enable, .set_rate = sdm845_clk_set_rate, }; From patchwork Wed Apr 3 12:07:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 785418 Delivered-To: patch@linaro.org Received: by 2002:adf:f001:0:b0:33e:7753:30bd with SMTP id j1csp280693wro; Wed, 3 Apr 2024 05:09:07 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVpqAjV2pWcbYbgdvk/hlSlRFDMbh/xYsr0JCaYimGeOyL/2uSyhGJDO/7cDeftKDHbqLwz9Mn6rVyDLcxcnEQp X-Google-Smtp-Source: AGHT+IEqvmU2FvyFz5B4WpSiCO2JalJnYHEb1h0bWL6qT7UyyZseyzC9K5YeEqtmedqlH61sA6Nd X-Received: by 2002:a17:906:39d1:b0:a46:e0ab:40ff with SMTP id i17-20020a17090639d100b00a46e0ab40ffmr11775244eje.35.1712146147689; Wed, 03 Apr 2024 05:09:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712146147; cv=none; d=google.com; s=arc-20160816; b=pSxIkBUh2qUSuttJbUBTptBnJf0lacRGQTLk31M3N1s0LuIBFZ7sujsbne22eCENb1 Gi8hFf+BvB3iKzazdjaqQtI/x+/jY0FRbkgKWDEMSohPOaAgmZ5ZO0ubOaA1kuQ8ZdkR Zp3COpzYF9JwN+8ncY9gdemTssFPOGF4ubMDw/n0d9eoIBq3C68CHqZxBebyTqe+mxBr a4IUputIVFh5fyDT4L5FEUeeM5liWG+UNn/Pfi2BSup5DwPbGdnBpQfYz/ZKzOupA5d2 1agUpylOswE+8NJ1BOVr8UL2um2TQIlkLi56yCxZecTZDmS8j3LYu6lPCeUtDydlTUVn HZdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=GewhX1AhomHs5Aohn6YwaTX+GkXafQtxsWjEwPDqGAk=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=N7pj/+KuI3GYvlcuUFmyKwNK19k/XmgFbiDwcQ1Z4dlbJx/nIf3zUj1IvLrNVm7im9 BWfr/i5aMSq8nJmDS/jPWdwVDLfua8UbLDT6msYhQboeu2zsy4TXAlGfl3CqlyVNi6EQ Gm/EhtgZ57AnllkG30Unaibsybk3URtSz8W2hripscXFbqckJSYiaW7t5WR16677gB2M Rg5MkfySKDLne2yFYtBrTTGntrcmFmymSgRC+ZJ01rRUF1RwBHqLNGuJEfG7AG1krn+W O2DQxnh+GRRdD6s8LCNrLGpI+ZAHwSfAihqXZjPtxb2FtGkOh4zHop2SfiIEU+c6sJk+ OITg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QL4PZfnb; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Most devices only initialise the USB clocks for us if we boot via "fastboot boot", add the missing clock configuration to get both USB ports working regardless of the bootloader state. Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-sdm845.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index b7154360894a..e9c61eb480de 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -20,8 +20,12 @@ #include "clock-qcom.h" #define SE9_UART_APPS_CMD_RCGR 0x18148 +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf018 +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf030 +#define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf05c + static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), @@ -56,8 +60,10 @@ static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) } } static const struct gate_clk sdm845_clks[] = { + GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x82020, 0x00000001), + GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x05030, 0x00000001), GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, 0x00000400), GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, 0x00000800), GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, 0x00001000), GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x5200c, 0x00002000), @@ -120,8 +126,27 @@ static int sdm845_clk_enable(struct clk *clk) struct msm_clk_priv *priv = dev_get_priv(clk->dev); debug("%s: clk %s\n", __func__, sdm845_clks[clk->id].name); + switch (clk->id) { + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB_PHY_CFG_AHB2PHY_CLK); + /* These numbers are just pulled from the frequency tables in the Linux driver */ + clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, + (4.5 * 2) - 1, 0, 0, 1 << 8, 8); + clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, + 1, 0, 0, 0, 8); + clk_rcg_set_rate_mnd(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, + 1, 0, 0, 0, 8); + break; + case GCC_USB30_SEC_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK); + + qcom_gate_clk_en(priv, GCC_USB3_SEC_CLKREF_CLK); + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK); + break; + } + qcom_gate_clk_en(priv, clk->id); return 0; } From patchwork Wed Apr 3 12:07:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 785420 Delivered-To: patch@linaro.org Received: by 2002:adf:f001:0:b0:33e:7753:30bd with SMTP id j1csp280885wro; Wed, 3 Apr 2024 05:09:29 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWkdQpopFir9n//dexDeSqeBD53dQvhcpNnjcVKqk4ZHtvBa9irQI+rEbhu3Wo7cI36xRBNSgCbnzll8uvwkjVf X-Google-Smtp-Source: AGHT+IH0NfOpumCQlqSsSQ8MMwUTJH+sdMeqcdWmVR3DPo3s4idZJMnF+RuzMfX8IysfKfj2Xrfm X-Received: by 2002:a17:906:f58a:b0:a4e:3c1a:d6c with SMTP id cm10-20020a170906f58a00b00a4e3c1a0d6cmr14168192ejd.9.1712146168991; Wed, 03 Apr 2024 05:09:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712146168; cv=none; d=google.com; s=arc-20160816; b=kz+xZOQYL8zwz9TParHJ7L/cMp5JgEiJ/OZQBq5Fqkz0kXB33f/F0r21HC8p2ug3tU H1L2EzvVo61gDpJ0EHXKxigYOPJV4teRH6TxzSdSDXR+p0XrvYjdwACypS+J+b59QO0z 4sE5t/7OejMV3P3kG8YcwkVyUrnvr6qjBpOKdcW1rBAquf/raMbxbwAdk6Uvr2YPruHu PQzgOSOwOb2KxFD8RDpUuCHleNl5Q2KLv7AXpboBHkkxqDaEdNANDAAIUMGcKWcLdACM 2joBmMDFqjD0w6F6KzRdnspS3mR8EAxUUry62LXJJhh+PN5RReZNXD/Kzjm2ZDcDjWXI BceQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=R7r7yaX5GC6A7b+YWiB29a1fIsl80G8kHqu1xhDh7Zc=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=wAiD+cwzwhMtwuwiMTcHBQoYYGK7aPnRZwy3YvWMp/J84cghigy7GSAlCCwI1t1KYt iZWBBIu2i7Un7I0Xbp6qIrozhYbtW1RstGmQ0hIddBJ9fyBG5ehcroOpVxOMQ03UMxak n1UZOq/NUWlh9GyaJP9J4Cgx9ItelYUnCgLfPnoaiVaq7BVqsBv8/uy3QrSAuss/08rg sQzWbXKmqdkaVdoUxqLncrn3Mt6wLrRQZPiMOGnXlEFSYfX72uu4z9lwHnOlmr5MCYDW rIZFj0mzpJ5VqkwPKRv7v40AVw6YIKocJX4yTx6ObEeKY1RkdV+HZCxJJF8WSz8/k9x+ T+WA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P13VzyKF; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The .direction_input and .direction_output ops are deprecated, and don't seem to behave properly for us. Implement our own .set_flags op to handle this correctly. Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- drivers/gpio/msm_gpio.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index 5e57b0cbde75..f5d9ab54e817 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -34,21 +34,21 @@ struct msm_gpio_bank { #define GPIO_IN_OUT_REG(dev, x) \ (GPIO_CONFIG_REG(dev, x) + 0x4) -static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) +static void msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev); /* Always NOP for special pins, assume they're in the correct state */ if (qcom_is_special_pin(priv->pin_data, gpio)) - return 0; + return; /* Disable OE bit */ clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio), GPIO_OE_MASK, GPIO_OE_DISABLE); - return 0; + return; } static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value) { @@ -83,8 +83,25 @@ static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio, return 0; } +static int msm_gpio_set_flags(struct udevice *dev, unsigned int gpio, ulong flags) +{ + if (flags & GPIOD_IS_OUT_ACTIVE) { + return msm_gpio_direction_output(dev, gpio, 1); + } else if (flags & GPIOD_IS_OUT) { + return msm_gpio_direction_output(dev, gpio, 0); + } else if (flags & GPIOD_IS_IN) { + msm_gpio_direction_input(dev, gpio); + if (flags & GPIOD_PULL_UP) + return msm_gpio_set_value(dev, gpio, 1); + else if (flags & GPIOD_PULL_DOWN) + return msm_gpio_set_value(dev, gpio, 0); + } + + return 0; +} + static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev); @@ -109,12 +126,10 @@ static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio) return GPIOF_INPUT; } static const struct dm_gpio_ops gpio_msm_ops = { - .direction_input = msm_gpio_direction_input, - .direction_output = msm_gpio_direction_output, + .set_flags = msm_gpio_set_flags, .get_value = msm_gpio_get_value, - .set_value = msm_gpio_set_value, .get_function = msm_gpio_get_function, }; static int msm_gpio_probe(struct udevice *dev) From patchwork Wed Apr 3 12:07:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 785424 Delivered-To: patch@linaro.org Received: by 2002:adf:f001:0:b0:33e:7753:30bd with SMTP id j1csp281264wro; Wed, 3 Apr 2024 05:10:13 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU1q97jaYXFE6rtyBtiZJcj5YJnIrDBrJZfSUwXg2JtoNqprpdWdnA3zDoUPS+Q6x2c9atKV/pUEsm8qlaaaCZk X-Google-Smtp-Source: AGHT+IGPF5wYIQpzpAQYyA9ayznlj4I/UvCkkFs85cIUHX8xCGD5IyWvqjIl0zQ71MKq0EISiwu9 X-Received: by 2002:a17:907:7889:b0:a4e:8f4f:2f09 with SMTP id ku9-20020a170907788900b00a4e8f4f2f09mr2964129ejc.15.1712146212780; Wed, 03 Apr 2024 05:10:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712146212; cv=none; d=google.com; s=arc-20160816; b=H7y2XcWlHh+G0W0r60dJTFv77UlFjqVIsn1WjqJjHl6luWxFTyUCfVnlB1cLgIEvGm ssHgcSvsFoq7v6rNmvnbcXn873bTxs5ueIqFeAzrbyeuSGSY/J+ZmmXSo/HLZ3Qu1nAM IEeRHnN1Ht6SO5P4u56+IAIiEORsnmameSZQVUauvYIwSCdZGZVzn3OKM24xKcCH0Uj6 sSfrX6pqCrbug17t+Q54h3p3inwINd/LzFjBMU2OZ8vc8Ti5ZHqGXMSkvmSXNMhuImsJ uxNgSmPnxm/ySW3C0cAgKjvLaVn6TobSdxEnhTI6aJBVWtskNqbGvWpOr17gnb7la0gd 6ARw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=cgGFkOv1r6ZqedijumR44euV2V/PWTObj0uui6365Yw=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=z12RKBLXaFNfewf16+HvVfhCLDxxfXJwmVC0R+ViaHDxNoSRdfJJmDznKVz0/sHdmV YJo+Qco3w2bifJawulJK5YHB9RHKa0kaJyff0BV24lBRKMonuYfGlOF0Nl91C9IqPamk +x3Uzo/uYdJ9j6PFRvQ5YQaM+t9uOlUBzw1g6xKGPiCwTaS80AsF4vbVulWERCYOUTxH 7dhcDAT0nWzGL+um/sZMRwwdLU0iPLo7SRuAoQ5bfuU45glgJ5FMPGhhHMTrhJArrnMA h86/2Y/l3iByjU6eK+HQ1aIVW7i5R/6bHCXCN6Ymx1c4PvChMLEfTipsFXY4vCl+O9R5 bFSw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=shKD9eEh; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean When using OF_LIVE, the debug UART driver won't be probed if it's a subnode of the geni-se-qup controller. Add a NOP driver for the controller to correctly discover its child nodes. Reviewed-by: Neil Armstrong Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- drivers/serial/serial_msm_geni.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index 4aa0bc8c72bc..5260474fb9a4 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -605,8 +605,21 @@ U_BOOT_DRIVER(serial_msm_geni) = { .ops = &msm_serial_ops, .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, }; +static const struct udevice_id geniqup_ids[] = { + { .compatible = "qcom,geni-se-qup" }, + { } +}; + +U_BOOT_DRIVER(geni_se_qup) = { + .name = "geni-se-qup", + .id = UCLASS_NOP, + .of_match = geniqup_ids, + .bind = dm_scan_fdt_dev, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; + #ifdef CONFIG_DEBUG_UART_MSM_GENI static struct msm_serial_data init_serial_data = { .base = CONFIG_VAL(DEBUG_UART_BASE) From patchwork Wed Apr 3 12:07:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 785419 Delivered-To: patch@linaro.org Received: by 2002:adf:f001:0:b0:33e:7753:30bd with SMTP id j1csp280799wro; Wed, 3 Apr 2024 05:09:19 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUFHI1SuX8fcEVSTdKzqzX4mvlYqtf8YHwJiXb/q9twIPllnugIvTfwLlWe3nMkR6ilbvIpSMcS5pKC4tsQ/J0p X-Google-Smtp-Source: AGHT+IGidW24DGIDUZbdde/C1AzjFzVXOVItx6rXYEH8Yc5wi6mzEz3rvCaTb0PqTRPHAWZWIhLi X-Received: by 2002:a17:906:1d0d:b0:a4e:9a13:5090 with SMTP id n13-20020a1709061d0d00b00a4e9a135090mr2123989ejh.9.1712146159384; Wed, 03 Apr 2024 05:09:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712146159; cv=none; d=google.com; s=arc-20160816; b=VFHOiDtljsfgEaEWjZuBMz7NBDNAdHVyG3aCHFza3t3Xs6SyH6sM4Tv95lhmp/HMAi SULpmdMrNsRhGW9cud9QdqCSaFa8XpbJy1P7s3zwfa28MlxGdEA0ALw7pon0b/3kB5yL SxpZW8U9uj2TxW0T38i81M4MsupUi+JHK+Ukv/XYv/nmnbiLx8oixOAjyp+MF0GcnY7R MDtA7E16hWZ4o73NnHypm5LjZzfQ+tWIbHkeWl15eCZ+JHrRKM4M5/D4D+/1vCS9m0VA 1PNx/m2iri1xyxJIqewKwyAdLb2qL3jN36FjdbEswIGSgyBH5oaFIxpSucUxvW1N21Wt Q/Jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=w2IoZleQFmWAeQEyW4JHzoO3O7JYnf70UC0Z9/INMRQ=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=Tg4FfX2Y7cu/47Gq8owbPN/IW+Uy+xoqBm2J6gA/OYGx6zy/K/qUEV5NAVg7mMp+Dj yOLYKGiXV5gavFtCLt4EKd35Xra/cHUi4g06lMIS6boO/WmipxLM7XgeAzzQqW/Gm3lR 62ZpbQLm50E2ndBK6uY73WKo56+y20esrt0iZLW65x5ElfatKKe9I/nexwLeSA1D6h9Q QNMl6OcIkjMMlsbHxNGjc+tATgCs7nRuhFyQgxA+9GBAp6X6WfoQwm3Su9fu2b4PnhEk m3MflHIQXd75XcLBN0f3BTpSXhyw+cyq+DfllBcJScymi2q7IOXbqOAM3KTwmiPaoOcD fq8w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ismhyZR+; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean We don't support USB super-speed in U-Boot yet, we lack the SS PHY drivers, however from my testing even with a PHY driver there seem to be other issues when talking to super-speed peripherals. In pursuit of maintaining upstream DT compatibility, and simplifying porting for new devices, let's implement the DT fixups necessary to configure USB in high-speed only mode at runtime. The pattern is identical for all Qualcomm boards that use the Synaptics DWC3 controller: * Add an additional property on the Qualcomm wrapper node * Remove the super-speed phy phandle and phy-name entries. Acked-by: Sumit Garg Reviewed-by: Neil Armstrong Tested-by: Neil Armstrong Signed-off-by: Caleb Connolly --- arch/arm/mach-snapdragon/Makefile | 1 + arch/arm/mach-snapdragon/board.c | 3 + arch/arm/mach-snapdragon/of_fixup.c | 123 +++++++++++++++++++++++++++++++++++ arch/arm/mach-snapdragon/qcom-priv.h | 20 ++++++ 4 files changed, 147 insertions(+) diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 857171e593da..7a4495c8108f 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -2,4 +2,5 @@ # # (C) Copyright 2015 Mateusz Kulikowski obj-y += board.o +obj-$(CONFIG_OF_LIVE) += of_fixup.o diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 6f762fc948bf..65e4c61e866a 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -27,8 +27,10 @@ #include #include #include +#include "qcom-priv.h" + DECLARE_GLOBAL_DATA_PTR; static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } }; @@ -159,8 +161,9 @@ void __weak qcom_board_init(void) int board_init(void) { show_psci_version(); + qcom_of_fixup_nodes(); qcom_board_init(); return 0; } diff --git a/arch/arm/mach-snapdragon/of_fixup.c b/arch/arm/mach-snapdragon/of_fixup.c new file mode 100644 index 000000000000..4fdfed2dff16 --- /dev/null +++ b/arch/arm/mach-snapdragon/of_fixup.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * OF_LIVE devicetree fixup. + * + * This file implements runtime fixups for Qualcomm DT to improve + * compatibility with U-Boot. This includes adjusting the USB nodes + * to only use USB high-speed, as well as remapping volume buttons + * to behave as up/down for navigating U-Boot. + * + * We use OF_LIVE for this rather than early FDT fixup for a couple + * of reasons: it has a much nicer API, is most likely more efficient, + * and our changes are only applied to U-Boot. This allows us to use a + * DT designed for Linux, run U-Boot with a modified version, and then + * boot Linux with the original FDT. + * + * Copyright (c) 2024 Linaro Ltd. + * Author: Caleb Connolly + */ + +#include +#include +#include +#include +#include +#include + +/* U-Boot only supports USB high-speed mode on Qualcomm platforms with DWC3 + * USB controllers. Rather than requiring source level DT changes, we fix up + * DT here. This improves compatibility with upstream DT and simplifies the + * porting process for new devices. + */ +static int fixup_qcom_dwc3(struct device_node *glue_np) +{ + struct device_node *dwc3; + int ret, len, hsphy_idx = 1; + const __be32 *phandles; + const char *second_phy_name; + + debug("Fixing up %s\n", glue_np->name); + + /* Tell the glue driver to configure the wrapper for high-speed only operation */ + ret = of_write_prop(glue_np, "qcom,select-utmi-as-pipe-clk", 0, NULL); + if (ret) { + log_err("Failed to add property 'qcom,select-utmi-as-pipe-clk': %d\n", ret); + return ret; + } + + /* Find the DWC3 node itself */ + dwc3 = of_find_compatible_node(glue_np, NULL, "snps,dwc3"); + if (!dwc3) { + log_err("Failed to find dwc3 node\n"); + return -ENOENT; + } + + phandles = of_get_property(dwc3, "phys", &len); + len /= sizeof(*phandles); + if (len == 1) { + log_debug("Only one phy, not a superspeed controller\n"); + return 0; + } + + /* Figure out if the superspeed phy is present and if so then which phy is it? */ + ret = of_property_read_string_index(dwc3, "phy-names", 1, &second_phy_name); + if (ret == -ENODATA) { + log_debug("Only one phy, not a super-speed controller\n"); + return 0; + } else if (ret) { + log_err("Failed to read second phy name: %d\n", ret); + return ret; + } + + if (!strncmp("usb3-phy", second_phy_name, strlen("usb3-phy"))) { + log_debug("Second phy isn't superspeed (is '%s') assuming first phy is SS\n", + second_phy_name); + hsphy_idx = 0; + } + + /* Overwrite the "phys" property to only contain the high-speed phy */ + ret = of_write_prop(dwc3, "phys", sizeof(*phandles), phandles + hsphy_idx); + if (ret) { + log_err("Failed to overwrite 'phys' property: %d\n", ret); + return ret; + } + + /* Overwrite "phy-names" to only contain a single entry */ + ret = of_write_prop(dwc3, "phy-names", strlen("usb2-phy"), "usb2-phy"); + if (ret) { + log_err("Failed to overwrite 'phy-names' property: %d\n", ret); + return ret; + } + + ret = of_write_prop(dwc3, "maximum-speed", strlen("high-speed"), "high-speed"); + if (ret) { + log_err("Failed to set 'maximum-speed' property: %d\n", ret); + return ret; + } + + return 0; +} + +static void fixup_usb_nodes(void) +{ + struct device_node *glue_np = NULL; + int ret; + + while ((glue_np = of_find_compatible_node(glue_np, NULL, "qcom,dwc3"))) { + ret = fixup_qcom_dwc3(glue_np); + if (ret) + log_warning("Failed to fixup node %s: %d\n", glue_np->name, ret); + } +} + +#define time_call(func, ...) \ + do { \ + u64 start = timer_get_us(); \ + func(__VA_ARGS__); \ + debug(#func " took %lluus\n", timer_get_us() - start); \ + } while (0) + +void qcom_of_fixup_nodes(void) +{ + time_call(fixup_usb_nodes); +} diff --git a/arch/arm/mach-snapdragon/qcom-priv.h b/arch/arm/mach-snapdragon/qcom-priv.h new file mode 100644 index 000000000000..0a7ed5eff8b8 --- /dev/null +++ b/arch/arm/mach-snapdragon/qcom-priv.h @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 + +#ifndef __QCOM_PRIV_H__ +#define __QCOM_PRIV_H__ + +#if CONFIG_IS_ENABLED(OF_LIVE) +/** + * qcom_of_fixup_nodes() - Fixup Qualcomm DT nodes + * + * Adjusts nodes in the live tree to improve compatibility with U-Boot. + */ +void qcom_of_fixup_nodes(void); +#else +static inline void qcom_of_fixup_nodes(void) +{ + log_debug("Unable to dynamically fixup USB nodes, please enable CONFIG_OF_LIVE\n"); +} +#endif /* OF_LIVE */ + +#endif /* __QCOM_PRIV_H__ */ From patchwork Wed Apr 3 12:07:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 785421 Delivered-To: patch@linaro.org Received: by 2002:adf:f001:0:b0:33e:7753:30bd with SMTP id j1csp280977wro; Wed, 3 Apr 2024 05:09:38 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVdg72otkls7pdH6naEDN+p2c8Dw4HMf11cqhjB81LInFU0vmo/Poigc0j63sdcn2FmwcHHXOsbJYoMe5RTUDQV X-Google-Smtp-Source: AGHT+IHzcL/T1XkDMsRnvFGswLA7xCDm8vXc5PmMGsQzNqyz3PjKABf1uWX+h5J6BEx77fOhE0sw X-Received: by 2002:a50:d4d3:0:b0:56b:8d0e:1a08 with SMTP id e19-20020a50d4d3000000b0056b8d0e1a08mr1726598edj.26.1712146178447; Wed, 03 Apr 2024 05:09:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712146178; cv=none; d=google.com; s=arc-20160816; b=r0RIl0pgO66S/oyJsRVtWYfDxtvSnhJno83cQ2lMucGCegF3PIHOipY7conKSj285N ne/7T76T2VSwcFBApOaZaVSUhCn6lrGmJz3fPto42reVuRb+Uz9snelWNl+FNDusQuxo Ntpw7V7ncQvxLgCC22+/lJz3Jgzoa5lrlX76dJPxCJf6OnhQBCTtE5Y9rE1ROufwY4Kl TSgdvM792hbEQUcsOGFmd6OL4kLx31bwipX0AEuSePO7DX4yHBuhSLdVl7hFEjhjVHUT wmvtvAKxE+MtOnpkN55W7aobRFNAV6SxClzTnFMWRppdGiRHTZBuJpoiRINmhw/2JbFY xklw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=atk6K8T5n8lDURrFo1/qujfmQUqqKVW2EVC2laZ1DQA=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=M+E2RHGNfjl+twU1fPXkSuiNUiTZxMahmWwYgYZsTLeTPRUgd9cTemCiOY68/YqfBx E92RVnheAzwJ8qoSR1VxWR4SLUcXentxHCRbM+kDsVbtXiMg7ndl6JuabW3sS9fObhzb nTY7mE/OpjE6mJvveddQTfyrTK4l92MUDYLU4unf4axBUDIhiug+uzmVlg5hlvHTqz53 HdfANlYUqGD9KHKmkG/+44QL18uLMOre2Ug8np2+sZO+Y4ubujwchNCIHXORGubP8Xqs MqG+Oxj8BClZLTNiap9tzB3HCUQO1hKfqH2mxOE65l/ilCNfpjlKng7vUrKvJ9cUDAV1 FMuw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bNd8wJuC; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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a=openpgp-sha256; l=2816; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=+xkPcC5ur3MqWn3Swwn7ynawtVqmdU6FvDe+TLJNJp0=; b=owEBbQKS/ZANAwAIAQWDMSsZX2S2AcsmYgBmDUaR+lLCJ75/J9UzxAWvDD/XxTQTUvryQFyWq C9vmSgOneyJAjMEAAEIAB0WIQS2UaFGPGq+0GkMVc0FgzErGV9ktgUCZg1GkQAKCRAFgzErGV9k thm5D/wJO61B+q1mAWrgarXFIvpD1kR95szbkgIE3PhHqrog6o4W2+o6K/dgcwC7hyT8cnJ4LPj 5uh6j3ksd29UJEPLaAWewfJbRZ0HE7ozTy0RrkG7xnF5su8vIYXqO1YpiyesaECVSysT4+BPUZl IDtV3LtonAKsVU1S1WleE69waK0fZ4NRHhqdqk5cfw6/Iore1u4gLinXuA0o3nNtc2iYJ3uh9dK ibEYeEUP3wtCqWIcBQgW6N5tsxvv7KGIeFiAru9+jCNI8RW3gGsZQ1iXo516pPc/e6DWncLUBFb zUvum/7rd6t4m/mxTde3OrV++JlS9rtbe/keDNGKog3h6fZF6svyi+0BLhKvx+K6lAg2lhLJo49 gUP39LMfOqGDxOZhKSVOnLlclZ6txw2F+Bx3R/BlMxOIUXOHUEOuxQVkH/hOGGgJwXaAdFJPiKC zvzMYsrpM5KSS68fxT6ddQz+gaMrcu0wI6K94mPcF4XEfmVYWgrp5b5INPbnmxLlFTsxKGgHPnl yT5a/wHerFzLtnK2PrITFrI5O/b/Ec17j9mxRrElHdIPCuVHMt73ztdYEOqPSv1AX6IsWkj2r19 jZAufl1PK5kwaCE3w4eHBLvJsQ8HWGVB4bJrZtmzJm3lNm6GtR7bx9VZFihaGDPqu34Fg0lmMbA z8eFhnxuE2Ku2sQ== X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean We don't support the RPM(h)PD power domains in U-Boot, and we don't need to - the necessary resources are on, and we aren't going to enter any low power modes. We could try using a no-op device, but this requires adding a compatible for every platform, and just pollutes the driver model. So instead let's just remove every "power-domains" property that references the RPM(h)pd power controller. This takes <1ms as we're using OF_LIVE. Of note, this only applies to drivers which are loading post-relocation. Drivers loaded pre-reloc that reference the rpm(h)pd still need DM_FLAG_DEFAULT_PD_CTRL_OFF in their flags. Acked-by: Sumit Garg Reviewed-by: Neil Armstrong Tested-by: Neil Armstrong Signed-off-by: Caleb Connolly --- arch/arm/mach-snapdragon/of_fixup.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/mach-snapdragon/of_fixup.c b/arch/arm/mach-snapdragon/of_fixup.c index 4fdfed2dff16..3f7ac227bd09 100644 --- a/arch/arm/mach-snapdragon/of_fixup.c +++ b/arch/arm/mach-snapdragon/of_fixup.c @@ -21,8 +21,9 @@ #include #include #include #include +#include #include /* U-Boot only supports USB high-speed mode on Qualcomm platforms with DWC3 * USB controllers. Rather than requiring source level DT changes, we fix up @@ -109,8 +110,38 @@ static void fixup_usb_nodes(void) log_warning("Failed to fixup node %s: %d\n", glue_np->name, ret); } } +/* Remove all references to the rpmhpd device */ +static void fixup_power_domains(void) +{ + struct device_node *pd = NULL, *np = NULL; + struct property *prop; + const __be32 *val; + + /* All Qualcomm platforms name the rpm(h)pd "power-controller" */ + for_each_of_allnodes(pd) { + if (pd->name && !strcmp("power-controller", pd->name)) + break; + } + + /* Sanity check that this is indeed a power domain controller */ + if (!of_find_property(pd, "#power-domain-cells", NULL)) { + log_err("Found power-controller but it doesn't have #power-domain-cells\n"); + return; + } + + /* Remove all references to the power domain controller */ + for_each_of_allnodes(np) { + if (!(prop = of_find_property(np, "power-domains", NULL))) + continue; + + val = prop->value; + if (val[0] == cpu_to_fdt32(pd->phandle)) + of_remove_property(np, prop); + } +} + #define time_call(func, ...) \ do { \ u64 start = timer_get_us(); \ func(__VA_ARGS__); \ @@ -119,5 +150,6 @@ static void fixup_usb_nodes(void) void qcom_of_fixup_nodes(void) { time_call(fixup_usb_nodes); + time_call(fixup_power_domains); } From patchwork Wed Apr 3 12:07:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 785422 Delivered-To: patch@linaro.org Received: by 2002:adf:f001:0:b0:33e:7753:30bd with SMTP id j1csp281085wro; Wed, 3 Apr 2024 05:09:49 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWKSRADa0rIaAVN/GVv6/BY7IW/5ujMSBYDCd0rfjK+E8thE754tvb/EToer4das6/J54klVheMmAkRgreitwEH X-Google-Smtp-Source: AGHT+IHtbDQ++TVc0cqJemx/RC85KEoATwiNCGzteE7P6Xm/sbs4Dg/zZZagX46ghq+6eXEF03kl X-Received: by 2002:a17:906:6811:b0:a4e:1597:eb2f with SMTP id k17-20020a170906681100b00a4e1597eb2fmr11258525ejr.11.1712146189696; Wed, 03 Apr 2024 05:09:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712146189; cv=none; d=google.com; s=arc-20160816; b=GT9kFFowmuyveJs6tdEnUI+dzB42vw9wyq+LOxFMH4EU6x0mZ+0plhXr5X3NwwqMMu yQSvUH5dsUP5hR4rDfmT8pZ7gEwRA0set4rHemftrK4UNK8yvp56O3qsS6itGLDjrB6j z3ejY2xy0qIRopCAAaOgEsrKus0+Am/lht1C5rdqwT+YCcoQ53Nrepaqnmd1BGlUA5J9 mJS1qtyRaUxS7r1jjWj3jBorM045er2b2We71ZZ/QAM54uRrvZfTrsnk3NYa01NytKI6 n7T6vWwQjSh31eRIQmfJBslOeTY9NCI9L2+uNATc1KAM/X1dgUL2+6e4jrJQ7R0f6a3t pIzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=CEa1uvzHHZiFQ7KW80s5FU7jkCJCbFju98xTsCLC/qw=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=1Lg+GGBwI7XsGuEQ3j1tOb7JdX8e3RLx1ef2jBWJ8JJKSgDLhkr5fDmRjUPPV7xIQ3 X6x8esJXfiLx15/+74Q+LjKQitBSxTZomADr/oxXbQTmsh3WfmP0wcZtkUligwqFuyLq OLeNOcXjmHmMqDlWH2sQjBmGgoluyO+uc1B0rG4X7bXqpx/6AqIxg/oWb9n4RRXnfn6B jGkJ8HefNfOKxSQo11k8lcHM19uYi8FAg5ZFYQGtb2xPgKu6QaJ2xnetcMLqRpM2J00b 1vQFDeApNknTw3i9aIAXLZlgIxsKlymk9XL9dh8R027eMeR9WD61ENtYYq+allE1faUu yfvA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RzJvP38o; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Make sure we power on any boot-on or always-on regulators. These are used for peripherals like USB on some platforms. Reviewed-by: Sumit Garg Reviewed-by: Neil Armstrong Signed-off-by: Caleb Connolly --- arch/arm/mach-snapdragon/board.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 65e4c61e866a..3d5994c87886 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -15,8 +15,9 @@ #include #include #include #include +#include #include #include #include #include @@ -160,8 +161,9 @@ void __weak qcom_board_init(void) } int board_init(void) { + regulators_enable_boot_on(false); show_psci_version(); qcom_of_fixup_nodes(); qcom_board_init(); return 0; From patchwork Wed Apr 3 12:07:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 785423 Delivered-To: patch@linaro.org Received: by 2002:adf:f001:0:b0:33e:7753:30bd with SMTP id j1csp281166wro; Wed, 3 Apr 2024 05:10:00 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWwjICQVxpxYIplAWbokeP5wvIwPLxqGHZ+4kRbaC3aM8rmsMe7BUHxxM3QwJpN+YzPsOyo1tWXWZcrw/yuILEb X-Google-Smtp-Source: AGHT+IFPxIzfAdHdHndN3q6sKXZiEFbv7R4UIDhDn44skj0vyCWEynj6aFgK55fSzdDFhj/60XeE X-Received: by 2002:a05:6512:3295:b0:513:bf23:ce3 with SMTP id p21-20020a056512329500b00513bf230ce3mr1846676lfe.62.1712146200293; Wed, 03 Apr 2024 05:10:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712146200; cv=none; d=google.com; s=arc-20160816; b=NB4MiYgOLt6Yf/dOlA9KUeDYXaXTHEG99pFcSYKmPrrHhpn88QiHPfI2eM4z/oLiJN poB5dhuwNCctfTAJIfNAk9M6BmVvdX9P0ifdacdomIYEWovZ4i8VLl6Xlfbaa24BOwIQ 1I41SfHT4cN/8qmRs/d5UcpzEq5e7rJfiAvfgMg5Abo/GzLOXIXaouGQY3tB2HUorAUB nbd7GDxsEZsU1OJeUtbaiF321yDHIceSyLUE3nN75INurNXrrp7kTWi2muY+QkJMhtL6 KHhaJp/sM9GXAaa3JRDZV7m8E5du/fLPVj/08H1nQ56CbKbZtSoWh6UH4xTSIeJSLEQY E2mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=rT2hJHvXJ3OID9Ciyja3ANXjBepnBUwLb+A7aW2D5jw=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=E3S82Ts99eyGxU5Te0+dBeVOKqhuWzKPE5nvc3ZflvFc2Io5zBKsaPcUUeknbXJeIY lxaaHTxwRH+RjdkJmK3Ev0toYSVavz0nG896+bwvVu4jf3OBDNP9JLUL/JUK6/rb4tCS 69AVrxpaJqsxZEdTseJj56xGOVy5f5Tk64RpfloChs9EXadKwUx9J4acGc6V3WSLdl60 0TZpq8P/UAe1MljYdZVITcg0WLhFrvaftnLc9J7v009Fo8bjChGbwpquy4639jK16iSZ ncv/Gvjoe5riIs5kc0OXyEMG4Bj0jtIWKPJjpePTXdKcXwaPaPsXZDt1gnLlX0i4Rj6O yOQA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="i/hI2lk6"; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The USB VBUS supply for the type-A port is enabled via a GPIO regulator. This is incorrectly modelled in Linux where only the PCIe dependency is expressed. The correct way to handle this will be through a usb-connector node, but for now we'll just mark the regulator as always-on so that it will be enabled automatically during boot. Reviewed-by: Sumit Garg Reviewed-by: Neil Armstrong Signed-off-by: Caleb Connolly --- arch/arm/dts/sdm845-db845c-u-boot.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/dts/sdm845-db845c-u-boot.dtsi b/arch/arm/dts/sdm845-db845c-u-boot.dtsi new file mode 100644 index 000000000000..906f9faa5451 --- /dev/null +++ b/arch/arm/dts/sdm845-db845c-u-boot.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Needed for Linux to boot from USB, otherwise if PCIe driver is not in initramfs + * the VBUS supply will never get turned on. + * https://lore.kernel.org/linux-arm-msm/20240320122515.3243711-1-caleb.connolly@linaro.org/ + */ +&pcie0_3p3v_dual { + regulator-always-on; +}; From patchwork Wed Apr 3 12:07:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 785425 Delivered-To: patch@linaro.org Received: by 2002:adf:f001:0:b0:33e:7753:30bd with SMTP id j1csp281371wro; Wed, 3 Apr 2024 05:10:23 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV2lo/ddTcZFVOvQcTJb+lD+tBpQrw3ySQqeI0waZmPgfyYeDWBQN+cv0JS0jF1v5qxc6kMGAccOw7obv17dI0U X-Google-Smtp-Source: AGHT+IGLKorVuWsIkOXhZBLX72or8c8FOlSr1V7Y4CxWWyZVjVfdAm8xmqay2f1FzgVd65GMwqsP X-Received: by 2002:a50:c199:0:b0:56d:b7d6:d64b with SMTP id m25-20020a50c199000000b0056db7d6d64bmr9850007edf.29.1712146223137; Wed, 03 Apr 2024 05:10:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712146223; cv=none; d=google.com; s=arc-20160816; b=v8+0/2ZyRAGGtpiQhpPnoS/E5RZQhtVdiVurUuGcxWkIcg+Xw3N8KF4QF5DJfz2z56 EgrCDpfo9HEXkeVQWkHmeLiXSqqp6GgvE5a4jqOZiZrKf95PWsLiGVKPLXoH5sMNeQyf tEpJP9bTXTzTYMBuRRvXNa1nv8hE95XYcqeMAOF3/fTb8hPO3dKzr5hDGHm9ZVhyV6d0 BY/3qk0IzvrRS0X9peVWysyk5+9cpUzvpVwBpb8PgDBadpE1rA2lOvyHlMCG3fys4Xse SQdyyADZS244aFGUx18FkBzpsuYXfaX/vVlAWfvDQpBn7+2KcmwZzNBWgITgILBIZqMS ICQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=dkr+CmAQ64eUqOg4M49/tTSWR5zwY0MG3Z7wMHd84mg=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=RbrhG8C7E33Fj2cKPJxKtN3h5HrBrr7bfobD6/rwy2Fl0QDpVBbig2fwf55eYEgNoC 2Tm9HwnoGK9STZ8t/2GMhnBS2lZWjTvrOtYNgq/2DkFeN+BvXSmDLqUi75al0WhPIylq /YpOTR/iBuySrdvhOB834i5BpNJwmT7SABaGWwEaNdPFcXGH6bJeeVPonp0aiVwO+uv5 pXOQqbQEX+rcRgM9U+0aCm5VbmuxXdNng2uHE/K1+8JC+BFrFUlz8Chs5fFZY1N31Do0 B/KL8Pb2WOVLyC7busqoOPUqyVqYblnTU2q+8hfSU7oLI4WOgo16odvjioet/Xyqk7wa 8jPQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="f7tMCc/5"; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Qualcomm FDTs are on the larger size, and with the addition of DT modifications during board_init() it makes sense to enable OF_LIVE globally. The cost of building the tree should be offset by the increased efficiency at which we can walk it. Some rough measurements with CONFIG_BOOTSTAGE suggests that this might add 0.1-0.2ms to the boot-to-console time. However the reset-to-reset timer difference is in the range of 0.5ms so this could just be noise. Suffice to say, no significant slow down. Reviewed-by: Neil Armstrong Acked-by: Sumit Garg Signed-off-by: Caleb Connolly --- configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index cbc612b44bd9..8c4402e8f780 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -25,8 +25,9 @@ CONFIG_CMD_UFS=y CONFIG_CMD_USB=y CONFIG_CMD_CAT=y CONFIG_CMD_BMP=y CONFIG_CMD_LOG=y +CONFIG_OF_LIVE=y CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y CONFIG_CLK_QCOM_QCS404=y CONFIG_CLK_QCOM_SDM845=y From patchwork Wed Apr 3 12:07:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 785426 Delivered-To: patch@linaro.org Received: by 2002:adf:f001:0:b0:33e:7753:30bd with SMTP id j1csp281451wro; Wed, 3 Apr 2024 05:10:33 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUxCOg/KPK7RSqyyYxTDTx7POlQgpPIbY/qYowSoo5mihnrfehDpNzqq45nfWVponqW+SSeYwHBvYfJbusMLJOh X-Google-Smtp-Source: AGHT+IELipGqnrl7937JlIEjMuiHgaYXmWdouxVixlIeXJq8P0VUonDMxttdN4S4Rr+dYTRvO24H X-Received: by 2002:a50:aa94:0:b0:56b:6ec6:af2f with SMTP id q20-20020a50aa94000000b0056b6ec6af2fmr1682284edc.6.1712146232995; Wed, 03 Apr 2024 05:10:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712146232; cv=none; d=google.com; s=arc-20160816; b=v5B6VbaFcBJyP8f8zcx/tLEuiSZdkx7nV+j9Ys72t/dAGrUqO73TI9iJKu0cwoiNxD 7pmd628vO+cqKWiCyPMYqBvFSqZcWmzsFuL+WSNz5AVp7lJxXWg6WVR69muw3zwYY5du XJSyNQ6Tp/ig/PRCcFP+5ADGzwVL/5Url2kiuQC+LdekM1KJlKO4UsnA9EcHkkEwK1As SNumZMaR4/vCtBMwjIKVYNxqh2o2adpM0K9v8w2lNrFD536pp6A9PPBrn4FIjPP0mpmv iSqMWoYqO/Jtaj/Fkklphpl4Ui4qWRbqHG3FijWcv5+lElQkLfNUaWYsy3D2UODR2CvJ 7/yw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=lXyr6tJR6QFXRSTjw1XngBqNszpjZjRzQWF6T1YQB14=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=caGvxc/uvox7ZrskBR4ZJLwBTw7OGCwQf0IZuFjqNJLk8WXj+fxW2mHip8U9Accnnn MBWa7/Z1/mXJ2i6BA7pmzQ8zei3HAqFCJ/yV9lkpTXhsVOHyeI2smLgU63YtbN5y1Ge8 ymPAy9Or9HCQPdB1RnO4LiNdv730O1ytw4nbV9m8LZKqwVdTjtw+w6E7Ky28flsadGIn zRQd6b0/H5LFv35oeUQ7F4h36hVyinnEY552740efhgSXm2TIdlPwPuMJWPiqHAyO7fv Sp3dlRAHO10t7z4fTmwvtAEVvPSikEYflieWNtvQyfwmIQFWdOa6HVI8WOqAyBfI31h4 92nA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bRrIR0Yp; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Enable support for the DWC3 USB controller and required dependencies for Qualcomm boards, specifically the DB845c: * IOMMU / SMMU * USB high-speed PHYs * Mass storage and ACM gadgets Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- configs/qcom_defconfig | 52 ++++++++++++++++++++++++++++---------------------- 1 file changed, 29 insertions(+), 23 deletions(-) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 8c4402e8f780..1abb57345ff1 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -17,10 +17,16 @@ CONFIG_LOG_MAX_LEVEL=9 CONFIG_LOG_DEFAULT_LEVEL=4 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 +# CONFIG_CMD_BIND is not set CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_UFS=y CONFIG_CMD_USB=y CONFIG_CMD_CAT=y @@ -32,20 +38,39 @@ CONFIG_CLK=y CONFIG_CLK_QCOM_QCS404=y CONFIG_CLK_QCOM_SDM845=y CONFIG_MSM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_QUP=y +CONFIG_I2C_MUX=y CONFIG_DM_KEYBOARD=y CONFIG_BUTTON_KEYBOARD=y +CONFIG_IOMMU=y +CONFIG_QCOM_HYP_SMMU=y +CONFIG_MISC=y +CONFIG_NVMEM=y +CONFIG_I2C_EEPROM=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_MSM=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_QCOM=y +CONFIG_RGMII=y CONFIG_PHY=y +CONFIG_PHY_QCOM_QUSB2=y +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y CONFIG_PINCTRL=y CONFIG_PINCTRL_QCOM_QCS404=y CONFIG_PINCTRL_QCOM_SDM845=y CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_SCSI=y CONFIG_MSM_SERIAL=y CONFIG_MSM_GENI_SERIAL=y CONFIG_SPMI_MSM=y @@ -54,8 +79,12 @@ CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_UFS=y CONFIG_VIDEO=y # CONFIG_VIDEO_FONT_8X16 is not set CONFIG_VIDEO_FONT_16X32=y @@ -64,27 +93,4 @@ CONFIG_NO_FB_CLEAR=y CONFIG_VIDEO_SIMPLE=y CONFIG_HEXDUMP=y # CONFIG_GENERATE_SMBIOS_TABLE is not set CONFIG_LMB_MAX_REGIONS=64 -CONFIG_CMD_DHCP=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_PING=y -CONFIG_DM_ETH=y -CONFIG_DM_ETH_PHY=y -CONFIG_DM_MDIO=y -CONFIG_DWC_ETH_QOS=y -CONFIG_DWC_ETH_QOS_QCOM=y -CONFIG_RGMII=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_MISC=y -CONFIG_NVMEM=y -CONFIG_DM_I2C=y -CONFIG_I2C_SUPPORT=y -CONFIG_I2C_MUX=y -CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C=y -CONFIG_SYS_I2C_QUP=y -CONFIG_SYS_I2C_EEPROM_BUS=2 -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 From patchwork Wed Apr 3 12:07:51 2024 Content-Type: text/plain; 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The patch introducing support for dynamic sector sizes changed the types used in some divisions, resulting in the compiler attempting to use libgcc helpers (__aeabi_ldivmod). Replace these divisions with calls to lldiv() to handle this correctly. Fixes: 74e56e0c5065 ("usb: gadget: UMS: support multiple sector sizes") Signed-off-by: Caleb Connolly --- Cc: Mattijs Korpershoek --- drivers/usb/gadget/f_mass_storage.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index d880928044f4..ef90c7ec7fb5 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -239,8 +239,9 @@ /* #define VERBOSE_DEBUG */ /* #define DUMP_MSGS */ #include +#include #include #include #include #include @@ -768,10 +769,10 @@ static int do_read(struct fsg_common *common) } /* Perform the read */ rc = ums[common->lun].read_sector(&ums[common->lun], - file_offset / curlun->blksize, - amount / curlun->blksize, + lldiv(file_offset, curlun->blksize), + lldiv(amount, curlun->blksize), (char __user *)bh->buf); if (!rc) return -EIO; @@ -942,10 +943,10 @@ static int do_write(struct fsg_common *common) amount = bh->outreq->actual; /* Perform the write */ rc = ums[common->lun].write_sector(&ums[common->lun], - file_offset / curlun->blksize, - amount / curlun->blksize, + lldiv(file_offset, curlun->blksize), + lldiv(amount, curlun->blksize), (char __user *)bh->buf); if (!rc) return -EIO; nwritten = rc * curlun->blksize; @@ -1058,10 +1059,10 @@ static int do_verify(struct fsg_common *common) } /* Perform the read */ rc = ums[common->lun].read_sector(&ums[common->lun], - file_offset / curlun->blksize, - amount / curlun->blksize, + lldiv(file_offset, curlun->blksize), + lldiv(amount, curlun->blksize), (char __user *)bh->buf); if (!rc) return -EIO; nread = rc * curlun->blksize;