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Mon, 01 Apr 2024 13:33:43 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id j11-20020ac2550b000000b00515a6e4bdbdsm1478342lfk.250.2024.04.01.13.33.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Apr 2024 13:33:43 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 01 Apr 2024 23:33:40 +0300 Subject: [PATCH v3 1/9] dt-bindings: clk: qcom,dispcc-sm8x50: describe additional DP clocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240401-typec-fix-sm8250-v3-1-604dce3ad103@linaro.org> References: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org> In-Reply-To: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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Signed-off-by: Dmitry Baryshkov --- .../bindings/clock/qcom,dispcc-sm8x50.yaml | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 59cc88a52f6b..5831579b572e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -27,6 +27,7 @@ properties: - qcom,sm8350-dispcc clocks: + minItems: 7 items: - description: Board XO source - description: Byte clock from DSI PHY0 @@ -35,8 +36,15 @@ properties: - description: Pixel clock from DSI PHY1 - description: Link clock from DP PHY - description: VCO DIV clock from DP PHY + - description: Link clock from eDP PHY + - description: VCO DIV clock from eDP PHY + - description: Link clock from DP1 PHY + - description: VCO DIV clock from DP1 PHY + - description: Link clock from DP2 PHY + - description: VCO DIV clock from DP2 PHY clock-names: + minItems: 7 items: - const: bi_tcxo - const: dsi0_phy_pll_out_byteclk @@ -45,6 +53,12 @@ properties: - const: dsi1_phy_pll_out_dsiclk - const: dp_phy_pll_link_clk - const: dp_phy_pll_vco_div_clk + - const: edp_phy_pll_link_clk + - const: edp_phy_pll_vco_div_clk + - const: dptx1_phy_pll_link_clk + - const: dptx1_phy_pll_vco_div_clk + - const: dptx2_phy_pll_link_clk + - const: dptx2_phy_pll_vco_div_clk '#clock-cells': const: 1 @@ -68,6 +82,20 @@ properties: A phandle to an OPP node describing required MMCX performance point. maxItems: 1 +allOf: + - if: + not: + properties: + compatible: + contains: + const: qcom,sc8180x-dispcc + then: + properties: + clocks: + maxItems: 7 + clock-names: + maxItems: 7 + required: - compatible - reg From patchwork Mon Apr 1 20:33:42 2024 Content-Type: text/plain; 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Mon, 01 Apr 2024 13:33:44 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id j11-20020ac2550b000000b00515a6e4bdbdsm1478342lfk.250.2024.04.01.13.33.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Apr 2024 13:33:44 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 01 Apr 2024 23:33:42 +0300 Subject: [PATCH v3 3/9] arm64: dts: qcom: sm8250: describe HS signals properly Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240401-typec-fix-sm8250-v3-3-604dce3ad103@linaro.org> References: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org> In-Reply-To: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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There is no 'role switch' signal between Type-C connector and the DWC3 USB controller. Instead there is a HighSpeed signal lane between DWC3 controller and the USB-C connector. Rename endpoints in accordance to that (this follows the example lead by other plaforms, including QRB2210 RB1, QRB4210 RB2 and all PMIC GLINK platforms). Reviewed-by: Bryan O'Donoghue Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index cd0db4f31d4a..44239d1e57e9 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1356,8 +1356,8 @@ &usb_1_dwc3 { usb-role-switch; }; -&usb_1_role_switch_out { - remote-endpoint = <&pm8150b_role_switch_in>; +&usb_1_dwc3_hs_out { + remote-endpoint = <&pm8150b_hs_in>; }; &usb_1_hsphy { @@ -1465,8 +1465,8 @@ ports { port@0 { reg = <0>; - pm8150b_role_switch_in: endpoint { - remote-endpoint = <&usb_1_role_switch_out>; + pm8150b_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs_out>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 2042020eb0dd..6cc0bcb40f1f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -659,8 +659,8 @@ ports { port@0 { reg = <0>; - pm8150b_role_switch_in: endpoint { - remote-endpoint = <&usb_1_role_switch_out>; + pm8150b_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs_out>; }; }; }; @@ -723,8 +723,8 @@ &usb_1_hsphy { status = "okay"; }; -&usb_1_role_switch_out { - remote-endpoint = <&pm8150b_role_switch_in>; +&usb_1_dwc3_hs_out { + remote-endpoint = <&pm8150b_hs_in>; }; &ufs_mem_hc { diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 7f2333c9d17d..440bbb89bf8a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4196,7 +4196,7 @@ usb_1_dwc3: usb@a600000 { phy-names = "usb2-phy", "usb3-phy"; port { - usb_1_role_switch_out: endpoint {}; + usb_1_dwc3_hs_out: endpoint {}; }; }; }; From patchwork Mon Apr 1 20:33:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 784929 Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F96255E53 for ; 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Rename HS graph nodes to contain 'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 20 ++++---- .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 20 ++++---- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 54 ++++++++++++++++++++-- 3 files changed, 70 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 41215567b3ae..a2627ab4db9a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -56,7 +56,7 @@ port@0 { reg = <0>; pmic_glink_con0_hs: endpoint { - remote-endpoint = <&usb_0_role_switch>; + remote-endpoint = <&usb_0_dwc3_hs>; }; }; @@ -91,7 +91,7 @@ port@0 { reg = <0>; pmic_glink_con1_hs: endpoint { - remote-endpoint = <&usb_1_role_switch>; + remote-endpoint = <&usb_1_dwc3_hs>; }; }; @@ -675,6 +675,10 @@ &usb_0_dwc3 { dr_mode = "host"; }; +&usb_0_dwc3_hs { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_0_hsphy { vdda-pll-supply = <&vreg_l9d>; vdda18-supply = <&vreg_l1c>; @@ -700,10 +704,6 @@ &usb_0_qmpphy_out { remote-endpoint = <&pmic_glink_con0_ss>; }; -&usb_0_role_switch { - remote-endpoint = <&pmic_glink_con0_hs>; -}; - &usb_1 { status = "okay"; }; @@ -712,6 +712,10 @@ &usb_1_dwc3 { dr_mode = "host"; }; +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_con1_hs>; +}; + &usb_1_hsphy { vdda-pll-supply = <&vreg_l4b>; vdda18-supply = <&vreg_l1c>; @@ -737,10 +741,6 @@ &usb_1_qmpphy_out { remote-endpoint = <&pmic_glink_con1_ss>; }; -&usb_1_role_switch { - remote-endpoint = <&pmic_glink_con1_hs>; -}; - &xo_board_clk { clock-frequency = <38400000>; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 15ae94c1602d..53252bb93d9e 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -115,7 +115,7 @@ port@0 { reg = <0>; pmic_glink_con0_hs: endpoint { - remote-endpoint = <&usb_0_role_switch>; + remote-endpoint = <&usb_0_dwc3_hs>; }; }; @@ -150,7 +150,7 @@ port@0 { reg = <0>; pmic_glink_con1_hs: endpoint { - remote-endpoint = <&usb_1_role_switch>; + remote-endpoint = <&usb_1_dwc3_hs>; }; }; @@ -1102,6 +1102,10 @@ &usb_0_dwc3 { dr_mode = "host"; }; +&usb_0_dwc3_hs { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_0_hsphy { vdda-pll-supply = <&vreg_l9d>; vdda18-supply = <&vreg_l1c>; @@ -1127,10 +1131,6 @@ &usb_0_qmpphy_out { remote-endpoint = <&pmic_glink_con0_ss>; }; -&usb_0_role_switch { - remote-endpoint = <&pmic_glink_con0_hs>; -}; - &usb_1 { status = "okay"; }; @@ -1139,6 +1139,10 @@ &usb_1_dwc3 { dr_mode = "host"; }; +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_con1_hs>; +}; + &usb_1_hsphy { vdda-pll-supply = <&vreg_l4b>; vdda18-supply = <&vreg_l1c>; @@ -1164,10 +1168,6 @@ &usb_1_qmpphy_out { remote-endpoint = <&pmic_glink_con1_ss>; }; -&usb_1_role_switch { - remote-endpoint = <&pmic_glink_con1_hs>; -}; - &vamacro { pinctrl-0 = <&dmic01_default>, <&dmic23_default>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 9f6d98fbc28e..41caa8713cfd 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3164,6 +3164,14 @@ port@0 { usb_0_qmpphy_out: endpoint {}; }; + port@1 { + reg = <1>; + + usb_0_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_0_dwc3_ss>; + }; + }; + port@2 { reg = <2>; @@ -3217,6 +3225,14 @@ port@0 { usb_1_qmpphy_out: endpoint {}; }; + port@1 { + reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + port@2 { reg = <2>; @@ -3420,8 +3436,23 @@ usb_0_dwc3: usb@a600000 { phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; - port { - usb_0_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_0_dwc3_ss: endpoint { + remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; 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Mon, 01 Apr 2024 13:33:48 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id j11-20020ac2550b000000b00515a6e4bdbdsm1478342lfk.250.2024.04.01.13.33.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Apr 2024 13:33:48 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 01 Apr 2024 23:33:47 +0300 Subject: [PATCH v3 8/9] arm64: dts: qcom: x1e80100: describe USB signals properly Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240401-typec-fix-sm8250-v3-8-604dce3ad103@linaro.org> References: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org> In-Reply-To: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4103; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=TBIiNNBgZICGeD+NJeW5hxRyvvEMnqmHX98cdDr1ewo=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmCxolctFm0CNkwO5e3t2N98mW4RdPVs1cBwY4z 1yMa9if3LiJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZgsaJQAKCRCLPIo+Aiko 1RXwCAClh4NsehEIBHq7283mSUZkJVVAluMWGxSUsRScphIzCBljRO/jxut72DBuLsSvLnyF0tL epzRJvOw9jWThWPTilT7vVV7G0fRVD3ZXrDTTDXP/s6K03fR+QKKl7t/dzASP5BIwEX1Ex/MGPB bO0PQcEIq5XV/T8JM+ydNP4aC8kC6V/XkT7eiobuwTSB2YOpFc5kqbUfrEPZ+MJjXjakoQIXZxK UyB+DjPLIcLnAFUPqbNxJygbN4tOsqKXW3akMRJvwT9nsM+vKCuMb57y8suM4A/m3dsvALxKYve ez27JMSuC5QmLkn0hb4GBmswtd99j/C2ZTD82iTr499ty+fG X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Follow example of other platforms. Rename HS graph nodes to contain 'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 149 +++++++++++++++++++++++++++++++-- 1 file changed, 141 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index f5a3b39ae70e..3213eccc3a3a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2543,6 +2543,33 @@ usb_1_ss0_qmpphy: phy@fd5000 { #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss0_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss0_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_ss0_qmpphy_dp_in: endpoint { + }; + }; + }; }; usb_1_ss1_hsphy: phy@fd9000 { @@ -2583,6 +2610,33 @@ usb_1_ss1_qmpphy: phy@fda000 { #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_ss1_qmpphy_dp_in: endpoint { + }; + }; + }; }; usb_1_ss2_hsphy: phy@fde000 { @@ -2623,6 +2677,33 @@ usb_1_ss2_qmpphy: phy@fdf000 { #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss2_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss2_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_ss2_qmpphy_dp_in: endpoint { + }; + }; + }; }; cnoc_main: interconnect@1500000 { @@ -3445,8 +3526,23 @@ usb_1_ss2_dwc3: usb@a000000 { dma-coherent; - port { - usb_1_ss2_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss2_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss2_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>; + }; }; }; }; @@ -3514,8 +3610,15 @@ usb_2_dwc3: usb@a200000 { phy-names = "usb2-phy"; maximum-speed = "high-speed"; - port { - usb_2_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_2_dwc3_hs: endpoint { + }; }; }; }; @@ -3590,8 +3693,23 @@ usb_1_ss0_dwc3: usb@a600000 { dma-coherent; - port { - usb_1_ss0_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss0_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>; + }; }; }; }; @@ -3673,8 +3791,23 @@ usb_1_ss1_dwc3: usb@a800000 { dma-coherent; - port { - usb_1_ss1_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>; + }; }; }; };