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[98.147.7.212]) by smtp.gmail.com with ESMTPSA id f8-20020a170902684800b001e09b636cafsm4000955pln.287.2024.03.29.15.31.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 15:31:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 01/18] target/hppa: Fix BE,L set of sr0 Date: Fri, 29 Mar 2024 12:30:54 -1000 Message-Id: <20240329223111.1735826-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org> References: <20240329223111.1735826-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The return address comes from IA*Q_Next, and IASQ_Next is always equal to IASQ_Back, not IASQ_Front. Tested-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 19594f917e..1766a63001 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3817,7 +3817,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) load_spr(ctx, new_spc, a->sp); if (a->l) { copy_iaoq_entry(ctx, cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var); - tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_f); + tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_b); } if (a->n && use_nullify_skip(ctx)) { copy_iaoq_entry(ctx, cpu_iaoq_f, -1, tmp); From patchwork Fri Mar 29 22:30:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 784089 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp3428992wrt; Fri, 29 Mar 2024 15:32:27 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXrx2Cwmb2XsJ1wgeVGrGrEvH7CN/+Nxpa8EBgZvayw7lLfDgp2V3Q9oZCMcLUUAVgqaxlu94zsN2TfsOBzemwu X-Google-Smtp-Source: AGHT+IFQE+BQ81nV0vrQ6Yo43aV8si+tU2/wd9iNZgWWIZCrtZV05251CECMP8Daots7s1hX7qX+ X-Received: by 2002:a0c:d7cb:0:b0:696:93f3:7c9b with SMTP id g11-20020a0cd7cb000000b0069693f37c9bmr3069805qvj.40.1711751547377; Fri, 29 Mar 2024 15:32:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711751547; cv=none; d=google.com; s=arc-20160816; b=O2Ia7Gpyv/WEJ7hpSVbAekZc9qNTY60RuWU2qOuOYz7qC4aPSgpzwrVmPkyA/S1Ph3 lNYB/n9UXWs7OOxY2dYeZnHhxH2YO1IbD5d47RLR9vqRkqJq7JYUZEcQoSfhFEvNtwUs c/ocnEuJl4dmbMyaZTtlyEp5sSgVFA5v6oTW4zMnQr/bCTlVl/jIm+XGTgZzPV2kHubS ecwJwp/Yui0IkMn2pMyECUQMOXpZkMeI8XlV4YH+UUHpCVBOu6QvlSKWnf2QL7g1YHaS jESt05xNjxrIjTGDtfEYHCN1rKpLI+h56qd64TvT1JJ5zJTT1j8srC3jShvFtXcYXhTT iGAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zUaBJKSO6H1bbGryp1PQTqH1TE2lEnHyVoVrY4Z6LJ4=; fh=3//KcqJEsa04kIBt5Nb/DJuP+2GuH1NwDRxnSl44zdw=; b=iA66gpM5x3qHM+SSHVuXX41/qEVOsQRxOZrMYqisiOJ4+7Y59gigi/rY8E+zjNfMK4 j3WK4vZvG1NNuDMh6fVsorZ7UOZ3Oo/a12/xrjAPPiCMsHlo6myfXg2+vpaHnzfEeTq7 hjmyAwN2YblsKiZ8YmAIG+/HMOniFDKAApBVx27PHZM80pYTkF2MQ3RJRZz/Zke1nPSB Eh/87XKBg6Kkz7L3UmetljHIz7Jb63XrqF52CaOpwv1nPUj8H9jQxhBJ8o1M3OfIKJPc qIGCgyCAwgMwtI1Ld5av8xYpvm4DCR1pnrAQnZgjHIWpx3tDHyoPKcODHe2s+3GO43pt Fg0g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YMbDbEwa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 1766a63001..f875d76a23 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3880,7 +3880,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) } /* No change for non-gateway pages or for priv decrease. */ if (type >= 4 && type - 4 < ctx->privilege) { - dest = deposit32(dest, 0, 2, type - 4); + dest = deposit64(dest, 0, 2, type - 4); } } else { dest &= -4; /* priv = 0 */ From patchwork Fri Mar 29 22:30:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 784098 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp3429146wrt; Fri, 29 Mar 2024 15:32:59 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWI74bnjSAqx8pjiCPv8L2MFrv4t8EQLjTElqQEXaFJOfUJsWzDZRhEEwHALpczuBD3P5xvXjQJDuj7RuY3YePh X-Google-Smtp-Source: AGHT+IHmkCe5p/39Nyzj+5MCHOc01jiWTjXt0XWJRa18gu05uydV7E+3JtbHl6RYmPnBcgwEDyrs X-Received: by 2002:a81:8186:0:b0:611:26e0:f24b with SMTP id r128-20020a818186000000b0061126e0f24bmr4283104ywf.9.1711751579118; Fri, 29 Mar 2024 15:32:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711751579; cv=none; d=google.com; s=arc-20160816; b=aq2FKWI2CpsD+u+k/jEGPMtM72bZqX6yzmv/w1G/ZlpffbaIeNPOtrgApm8QR0INfo xL05AVKeKPJhQ1HG2yylJky/W5XibT9yTo/3I/MRbT2mAYAZpsoq5/koJr2Pkhmr1xRc a5QCFlykzUnJGGLGFqvbhYHCWT9g/CFvLpRFA3z2EtS8wHDJtbmNZFLGoZEF0p7wiDFw 2CZp0jNDCpFNGcOcy7K0QVMi6a4SyVzz7SFIuwCS1+ShCYWXu2Zk89DrZ5bHoQnUpUh4 nOiQTa7iIAFafcgaC4klZ3fMPvyjL8IW5vYzA/SyQ4bnYGeZpcHuQAjlqjY7nMen8iDF SyEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=S0QfsALuaN0+wWbot0bFHlDdwooZi0EKVcDM5oK6qSA=; fh=VrHP4sfoKA8I1LkS7u+zyL5sfQ9auI1Z6YYiaQiPlIc=; b=zAAChv3uiSNVVNFsQ53UABpuwqDJSbGACOT5WmIbBmSfxIHilDCsk54C+TEpBsxbCH QynqCozUe/I/K8p5nimru2Bhfrk1DaICNgbCC1t/NJcZYbUG01pjkYlowelI/YavmAHz YW+h6/EP9NnSkosDV4v12670YmWuu4yAwetWHnrS9WIEBkAiLO3y2QmiMLnRg+mLmy9i jEhe7KGztpsuPc3sdHI1jE934t9Q3ofQdALxIzAX7cgzFXwEwPgq1RqL3uwF2+M8HaS6 w3/fgAluLrsrFFRAkY4UwL3XeCreCN9gUEt3iQrpQkq+JD06Mc5woY+797CRO6tsasUb CKOg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E2BZFz8X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[98.147.7.212]) by smtp.gmail.com with ESMTPSA id f8-20020a170902684800b001e09b636cafsm4000955pln.287.2024.03.29.15.31.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 15:31:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Sven Schnelle Subject: [PULL 03/18] target/hppa: Handle unit conditions for wide mode Date: Fri, 29 Mar 2024 12:30:56 -1000 Message-Id: <20240329223111.1735826-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org> References: <20240329223111.1735826-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Sven Schnelle Wide mode provides two more conditions, add them. Fixes: 59963d8fdf42 ("target/hppa: Pass d to do_unit_cond") Signed-off-by: Sven Schnelle Reviewed-by: Richard Henderson Message-Id: <20240321184228.611897-1-svens@stackframe.org> Signed-off-by: Richard Henderson --- target/hppa/translate.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index f875d76a23..2cb91956da 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -967,11 +967,22 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_i64 res, switch (cf >> 1) { case 0: /* never / TR */ - case 1: /* undefined */ - case 5: /* undefined */ cond = cond_make_f(); break; + case 1: /* SBW / NBW */ + if (d) { + tmp = tcg_temp_new_i64(); + tcg_gen_subi_i64(tmp, res, d_repl * 0x00000001u); + tcg_gen_andc_i64(tmp, tmp, res); + tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80000000u); + cond = cond_make_0(TCG_COND_NE, tmp); + } else { + /* undefined */ + cond = cond_make_f(); + } + break; + case 2: /* SBZ / NBZ */ /* See hasless(v,1) from * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord @@ -996,6 +1007,16 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_i64 res, cond = cond_make_0(TCG_COND_NE, cb); break; + case 5: /* SWC / NWC */ + if (d) { + tcg_gen_andi_i64(cb, cb, d_repl * 0x80000000u); + cond = cond_make_0(TCG_COND_NE, cb); + } else { + /* undefined */ + cond = cond_make_f(); + } + break; + case 6: /* SBC / NBC */ tcg_gen_andi_i64(cb, cb, d_repl * 0x80808080u); cond = cond_make_0(TCG_COND_NE, cb); From patchwork Fri Mar 29 22:30:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 784093 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp3429001wrt; Fri, 29 Mar 2024 15:32:28 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWvy+qeiAsPKtamyNtJF0eGkwh1yXsaqqL6egqyd15c9GKcG4hK31B2Ts1Ttlk0sdQr86VkZGmjz9H1FrZaA6cm X-Google-Smtp-Source: AGHT+IGAqCPdc6KM77QTaQiWyO1mpgzHdZJgV7hCzKBoCSE/be2zX6eQ1vcG4oJm+fG7G4gSdUOO X-Received: by 2002:a05:620a:5e0d:b0:78b:bbb2:42a4 with SMTP id xz13-20020a05620a5e0d00b0078bbbb242a4mr4033161qkn.10.1711751548447; Fri, 29 Mar 2024 15:32:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711751548; cv=none; d=google.com; s=arc-20160816; b=T/ov9mncIMEMaPc5ozoLqbzw3PGrG07GaJtUYOMRfiTKAqkLd04LXUPXlmmfe9iQfv VxHUSMOXK9oHzJIwJYSnlve4Fw5UwejzZE3i5xlVgkGjXZSwPiy/Z2YkhQGnNt4LVWQ+ xqVOUkNgvJH4HCSvUyxapY350clPs97vLH1xF1I8QOau2X9QVLVUz0rns4ymkIfcUDNM 9uIuPGFT1BuVEL/RYNxGwdu1PD2qyaEE8nXm/JeBeba7XAviw3wG+yA+0vLFTp2vcsZ/ Ew87UwTnpLLI65t0AiJavZ5ui/HBuzT0k8bFFMvair10dH4TEq+pueH4KqOs5lGuIx90 YYYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=iCXMa8NXK4SslxAJzO8oJ4YsLhlZ/FlXinB3WAZag7c=; fh=VrHP4sfoKA8I1LkS7u+zyL5sfQ9auI1Z6YYiaQiPlIc=; b=SEniYW34RVtis5DcEp/AEf+IeM92aXr2hYTQGf04HbUobjAznSi+IN82G/4c9IOLqH 8y/yD722aSCQcnH76kGs60sTkA8B/T1NqtYE8nAaI6HqGmk+B0VY9tc9+rQxMr3GpAKA Bzw2OA9YsMyWT6OwxNKGPfaon0KvqdLiYKFV3kD/KKipoQ4H9hxONoJVWsrBSC+I7UNe 8Xzx2ZyVMB7JxlnattHnCP79FRhn/WNtYlHTeR1AnaIsSOLnSpQQy1xrAnrzEnXKwJMt 1KlvjYIm+u2dqMoqFD04cee/R33pKHjYry5UaFkGAlkN50Q1zxIzZWXHh3udxWZd1eq2 HyQQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tLImgu+5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[98.147.7.212]) by smtp.gmail.com with ESMTPSA id f8-20020a170902684800b001e09b636cafsm4000955pln.287.2024.03.29.15.31.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 15:31:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Sven Schnelle Subject: [PULL 04/18] target/hppa: Fix ADD/SUB trap on overflow for narrow mode Date: Fri, 29 Mar 2024 12:30:57 -1000 Message-Id: <20240329223111.1735826-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org> References: <20240329223111.1735826-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Sven Schnelle Fixes: c53e401ed9ff ("target/hppa: Remove TARGET_REGISTER_BITS") Signed-off-by: Sven Schnelle Reviewed-by: Richard Henderson Message-Id: <20240321184228.611897-2-svens@stackframe.org> Signed-off-by: Richard Henderson --- target/hppa/translate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 2cb91956da..ceb739c54a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1126,6 +1126,9 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1, if (is_tsv || cond_need_sv(c)) { sv = do_add_sv(ctx, dest, in1, in2); if (is_tsv) { + if (!d) { + tcg_gen_ext32s_i64(sv, sv); + } /* ??? Need to include overflow from shift. */ gen_helper_tsv(tcg_env, sv); } @@ -1217,6 +1220,9 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, if (is_tsv || cond_need_sv(c)) { sv = do_sub_sv(ctx, dest, in1, in2); if (is_tsv) { + if (!d) { + tcg_gen_ext32s_i64(sv, sv); + } gen_helper_tsv(tcg_env, sv); } } From patchwork Fri Mar 29 22:30:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 784097 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp3429117wrt; Fri, 29 Mar 2024 15:32:54 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX+xthUIuWrAGYy/oacjnQqh/PijJM8urol+IVQCPANfxAG7sbcRu+DAtP3ikKm2n4f31ft3nF08BiEzvAK5wXM X-Google-Smtp-Source: AGHT+IEJfaQ2+T0sf2yImN+m8YCpVJV4ytUyksxh1Xg6HaJ9WtZc4Ty1qgRzHUXiMlo3n4vIr9lm X-Received: by 2002:a05:6122:36a7:b0:4d4:1cb7:f57a with SMTP id ec39-20020a05612236a700b004d41cb7f57amr3584138vkb.9.1711751573907; Fri, 29 Mar 2024 15:32:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711751573; cv=none; d=google.com; s=arc-20160816; b=GdIS1bg5tkLmuPCe42BbcxKoXFRc7Z765F6Y+kU/Qh5OvqoFs7AkQ+eAfE8tm+qVsh /7GNilpIDuXGSNPCPIqy+6OEuzEnr8EkHp2v9+LeSntDu5bzBhrZFZsWgBKbUgrbcLfN 9iiDRV5L2VIfmlfiZPsOAh4Z3nKM2ALF9IN5tQKZ2e5k/5J2//jKkI/nQMT7uab6rjmy ghSR2maqcwE8OFq4dEXIqcHVvdmq08dj7qk5KSEnQqyPD6LLnxZ/PsZPE2ATx87HpoOd iQQyQ2huLjE/w90IhzBRh1EiplllT5zR7vohWzAErySNB2+78DN8qYnD4MlkVOECM3Rv nx+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4HCtEnOimuoA4trumoTnA/CP5fOcqoSfBq8bXqNwYa0=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=hM8opYLp+huJvU2NvlxF4137ZC6nI/zqat4Twl3uGwwJ+3RG4HeDTH/K5O7VaJA40G pSaDIegJ3PZGxm+8srXGEUxeX1FCuq7qtUAFFjVvPuZM6loGOwyWK2WZwIopABtFf+g4 xNz5hwnjz3IJ+FFs46KQVXUncycYn57Yc8EclL1/BpeOedI6HyLxeyDqGu4X8k/6Ttz2 Evvbc54a/PWoIT3niEswTMf6C/PlI5ixiLJ2usaKgh9sbQh/XY/cvQqAM/yfZYEqK+2/ O6KzrOhzLzkN9Pi/uRzCAlXnl2B1jyzGib1j0S/kaBgi3EF99CsxBNft+4GU0z/6iNa8 iSxg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nRFtev9E; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[98.147.7.212]) by smtp.gmail.com with ESMTPSA id f8-20020a170902684800b001e09b636cafsm4000955pln.287.2024.03.29.15.31.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 15:31:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 06/18] target/hppa: Tidy read of interval timer Date: Fri, 29 Mar 2024 12:30:59 -1000 Message-Id: <20240329223111.1735826-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org> References: <20240329223111.1735826-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The call to gen_helper_read_interval_timer is identical on both sides of the IF. Reviewed-by: Helge Deller Tested-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8c1a564c5d..5b8c1b06c3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2082,11 +2082,9 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a) nullify_over(ctx); tmp = dest_gpr(ctx, rt); if (translator_io_start(&ctx->base)) { - gen_helper_read_interval_timer(tmp); ctx->base.is_jmp = DISAS_IAQ_N_STALE; - } else { - gen_helper_read_interval_timer(tmp); } + gen_helper_read_interval_timer(tmp); save_gpr(ctx, rt, tmp); return nullify_end(ctx); case 26: From patchwork Fri Mar 29 22:31:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 784099 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp3429316wrt; Fri, 29 Mar 2024 15:33:34 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWZCFbkbef9nJehgH8z4077TWndsMohmuUle6s7VCbljJ/1JLiwFVxi/1UMYw/HrIwGrieY42fBxkPHtoYiNBBI X-Google-Smtp-Source: AGHT+IEKNllwPUpR7ZRlxb9JAfYZAQqaEc+LVHGvoByoCFctW5Rd/YDt95qh7hjz+FzRo3XUtqjp X-Received: by 2002:a0c:fac2:0:b0:691:82ed:396f with SMTP id p2-20020a0cfac2000000b0069182ed396fmr3228215qvo.42.1711751614396; Fri, 29 Mar 2024 15:33:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711751614; cv=none; d=google.com; s=arc-20160816; b=QYKRxCMsBUXeNweIkRQkPqcMo7o+fsoWCoD+jmSWyVpehgBAXqB/bWCjTlCmOsTCyj HpUthUfx7h9vo8lxE/09n0xORiiF8s4BOK54X6V3TL7F7xuzq4C5jOA/2GwDwfg9zssA goFc6WvZJyL7QZBDwH+vvMpJUdxK7E2HrQG0MNujkS0rhY7Lnft2C1KfzS6uNPAWc/E3 WauoANDijZPCB0SvKaaoK3VUmy7VFAt56C3Hofgk9/cSglO4xInlHlmN88RjgTckohHa /WzI2rJOhoXIzSqNAjfPOkTJPwp9uQ7VZ5heimtMiB18j8I1p4kjRNadRlIUI/6pFnTR JGhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+aKcsx9JEOh52ndAdHyeqzgetKk3eTEnbQJ4vqbujCg=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=nEZ8klb59iR2blGnDvo/Qv1m13Z2slEu+gvrrmvlcil2Fc/PG/TFo3zFen+9fvwYkb 55eRgHISy+c3SGALaLEpkU96Pa8ZJadFHpg+rLFIOwDl+vI3l3aeu0d5TLz5pSVBZWpH Nn/QYxoU6TZJ8+TZgrpflNjVdKLPuzFGFnBYWjDSAE/6gqRubIRPQvdKQ+HuaM92lTyC ZTI91YWleOkf0E8oaD8IBymUsAlPg6/T7jswbRZ4OGmjHbCDBG9chg/8vOtPZGQeetZR K5881oozm+YyiwtdfYmNwUYbkl84wal72dK0WB2vP8ZTgsfyH50Gx26unVpkdrXpGybp nv9w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wMA0iGpu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[98.147.7.212]) by smtp.gmail.com with ESMTPSA id f8-20020a170902684800b001e09b636cafsm4000955pln.287.2024.03.29.15.31.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 15:31:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 07/18] target/hppa: Fix EIRR, EIEM versus icount Date: Fri, 29 Mar 2024 12:31:00 -1000 Message-Id: <20240329223111.1735826-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org> References: <20240329223111.1735826-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Call translator_io_start before write to EIRR. Move evaluation of EIRR vs EIEM to hppa_cpu_exec_interrupt. Exit TB after write to EIEM, but otherwise use a straight store. Reviewed-by: Helge Deller Tested-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/helper.h | 1 - target/hppa/int_helper.c | 14 ++++---------- target/hppa/translate.c | 10 +++++++--- 3 files changed, 11 insertions(+), 14 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 1bdbcd8f98..8fd7ba65d8 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -91,7 +91,6 @@ DEF_HELPER_1(rfi, void, env) DEF_HELPER_1(rfi_r, void, env) DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tl) -DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tl, env, tl) DEF_HELPER_FLAGS_3(itlba_pa11, TCG_CALL_NO_RWG, void, env, tl, tl) DEF_HELPER_FLAGS_3(itlbp_pa11, TCG_CALL_NO_RWG, void, env, tl, tl) diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index efe638b36e..90437a92cd 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -28,7 +28,7 @@ static void eval_interrupt(HPPACPU *cpu) { CPUState *cs = CPU(cpu); - if (cpu->env.cr[CR_EIRR] & cpu->env.cr[CR_EIEM]) { + if (cpu->env.cr[CR_EIRR]) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); @@ -89,14 +89,6 @@ void HELPER(write_eirr)(CPUHPPAState *env, target_ulong val) bql_unlock(); } -void HELPER(write_eiem)(CPUHPPAState *env, target_ulong val) -{ - env->cr[CR_EIEM] = val; - bql_lock(); - eval_interrupt(env_archcpu(env)); - bql_unlock(); -} - void hppa_cpu_do_interrupt(CPUState *cs) { HPPACPU *cpu = HPPA_CPU(cs); @@ -280,7 +272,9 @@ bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } /* If interrupts are requested and enabled, raise them. */ - if ((env->psw & PSW_I) && (interrupt_request & CPU_INTERRUPT_HARD)) { + if ((interrupt_request & CPU_INTERRUPT_HARD) + && (env->psw & PSW_I) + && (env->cr[CR_EIRR] & env->cr[CR_EIEM])) { cs->exception_index = EXCP_EXT_INTERRUPT; hppa_cpu_do_interrupt(cs); return true; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 5b8c1b06c3..46b2d6508d 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2166,10 +2166,10 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a) gen_helper_write_interval_timer(tcg_env, reg); break; case CR_EIRR: + /* Helper modifies interrupt lines and is therefore IO. */ + translator_io_start(&ctx->base); gen_helper_write_eirr(tcg_env, reg); - break; - case CR_EIEM: - gen_helper_write_eiem(tcg_env, reg); + /* Exit to re-evaluate interrupts in the main loop. */ ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; break; @@ -2195,6 +2195,10 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a) #endif break; + case CR_EIEM: + /* Exit to re-evaluate interrupts in the main loop. */ + ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; + /* FALLTHRU */ default: tcg_gen_st_i64(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl])); break; From patchwork Fri Mar 29 22:31:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 784106 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp3429458wrt; Fri, 29 Mar 2024 15:34:02 -0700 (PDT) X-Forwarded-Encrypted: i=2; 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[98.147.7.212]) by smtp.gmail.com with ESMTPSA id f8-20020a170902684800b001e09b636cafsm4000955pln.287.2024.03.29.15.31.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 15:31:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Sven Schnelle , Helge Deller Subject: [PULL 08/18] target/hppa: Use gva_offset_mask() everywhere Date: Fri, 29 Mar 2024 12:31:01 -1000 Message-Id: <20240329223111.1735826-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org> References: <20240329223111.1735826-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Sven Schnelle Move it to cpu.h, so it can also be used in hppa_form_gva_psw(). Signed-off-by: Sven Schnelle Reviewed-by: Helge Deller Reviewed-by: Richard Henderson Message-Id: <20240324080945.991100-2-svens@stackframe.org> Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 10 ++++++++-- target/hppa/translate.c | 12 +++--------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index a92dc352cb..a072d0bb63 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -285,14 +285,20 @@ void hppa_translate_init(void); #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU +static inline uint64_t gva_offset_mask(target_ulong psw) +{ + return (psw & PSW_W + ? MAKE_64BIT_MASK(0, 62) + : MAKE_64BIT_MASK(0, 32)); +} + static inline target_ulong hppa_form_gva_psw(target_ulong psw, uint64_t spc, target_ulong off) { #ifdef CONFIG_USER_ONLY return off; #else - off &= psw & PSW_W ? MAKE_64BIT_MASK(0, 62) : MAKE_64BIT_MASK(0, 32); - return spc | off; + return spc | (off & gva_offset_mask(psw)); #endif } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 46b2d6508d..e041310207 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -586,17 +586,10 @@ static bool nullify_end(DisasContext *ctx) return true; } -static uint64_t gva_offset_mask(DisasContext *ctx) -{ - return (ctx->tb_flags & PSW_W - ? MAKE_64BIT_MASK(0, 62) - : MAKE_64BIT_MASK(0, 32)); -} - static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, uint64_t ival, TCGv_i64 vval) { - uint64_t mask = gva_offset_mask(ctx); + uint64_t mask = gva_offset_mask(ctx->tb_flags); if (ival != -1) { tcg_gen_movi_i64(dest, ival & mask); @@ -1430,7 +1423,8 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *pgva, TCGv_i64 *pofs, *pofs = ofs; *pgva = addr = tcg_temp_new_i64(); - tcg_gen_andi_i64(addr, modify <= 0 ? ofs : base, gva_offset_mask(ctx)); + tcg_gen_andi_i64(addr, modify <= 0 ? ofs : base, + gva_offset_mask(ctx->tb_flags)); #ifndef CONFIG_USER_ONLY if (!is_phys) { tcg_gen_or_i64(addr, addr, space_select(ctx, sp, base)); From patchwork Fri Mar 29 22:31:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 784096 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp3429107wrt; Fri, 29 Mar 2024 15:32:51 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXo6QHfUTUDiI6jbwgS5cc8awdKeASc/hOh7OOT56Eg/k6SeC0pZKuXADcgyTtu347lStbn/7PJ+zLm1S+TVYYw X-Google-Smtp-Source: AGHT+IFmYNfny3Svl9mNQizGitzoVmtBau9Lk8XrSf+hoL25szy0tA7zppls4omNJUpuYROxzxac X-Received: by 2002:a05:620a:57ca:b0:788:7213:6b93 with SMTP id wl10-20020a05620a57ca00b0078872136b93mr3561372qkn.75.1711751571207; Fri, 29 Mar 2024 15:32:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711751571; cv=none; d=google.com; s=arc-20160816; b=VXnMpBvHn6mllZSKih92Of5d3nsuBC6E5eQaoumElCbA1fj2xiqBLZ6ciWP35in4bo V42A1oYGnJw8GuqSYCUA/BN4YcHtWccsn+duUCcefg1jjO2GYi/tY3OT0BzYEMknAHoa 9+6YTuOS8kjE3iBC8I5rQcYWBx3DnlSV0cW+PDbkw4Ry4Swp21YEa8j711fWfAcJMpYC CY1/0SD9CoYXvwvjF4tcQF38dSwty4RMt1zvDoTM72vQv9V7o/5WYzgudx5BjOlglzqO 6xymQnYzJR6NcdL5JVxXaSNjK3S+/CILotpf/K6hAOvQESIjFgOQNUYs+D7dZyrdnq31 SVeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dPcM7F+bIMm+kpOtGS43p2VNPDZH3BZ56mw6e1fyEkk=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=RLUIKs7/muPga8MpfHrogx+zrMZ/e8lVY/h/W6lrDjpPt1QpaEkMQrEprHRYW0FpOV gYqcwFSgqZNK1CmOXUbDwWeulUW4sKVg80kPEcuDoligPGxeQ7voU/B7Kj2b34b+KKjb JNbiMRM6bH+rFS5jLsgMy4CgDnsBOGFeMKZlesf5JG2xPn0qyKIVplIRkPnAUPUABK2T yCNmXVfj3pRcxPgPSsjMKiVpkdJh4/3JZNQbCGk3L1ypMpU/mem8IpqFENHtF3TOh2fo dQHbcQkKN6iDYvUq6Ga4oe4bHl0gU2JEnFT5UiBq5qAbxWNLOoX2z6+XtUzoGCJW1Fsh 2cFQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=txzeo8Il; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[98.147.7.212]) by smtp.gmail.com with ESMTPSA id f8-20020a170902684800b001e09b636cafsm4000955pln.287.2024.03.29.15.31.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 15:31:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 09/18] target/hppa: Fix DCOR reconstruction of carry bits Date: Fri, 29 Mar 2024 12:31:02 -1000 Message-Id: <20240329223111.1735826-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org> References: <20240329223111.1735826-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The carry bits for each nibble N are located in bit (N+1)*4, so the shift by 3 was off by one. Furthermore, the carry bit for the most significant carry bit is indeed located in bit 64, which is located in a different storage word. Use a double-word shift-right to reassemble into a single word and place them all at bit 0 of their respective nibbles. Tested-by: Helge Deller Reviewed-by: Helge Deller Fixes: b2167459ae4 ("target-hppa: Implement basic arithmetic") Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e041310207..a3f425d861 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2791,7 +2791,7 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i) nullify_over(ctx); tmp = tcg_temp_new_i64(); - tcg_gen_shri_i64(tmp, cpu_psw_cb, 3); + tcg_gen_extract2_i64(tmp, cpu_psw_cb, cpu_psw_cb_msb, 4); if (!is_i) { tcg_gen_not_i64(tmp, tmp); } From patchwork Fri Mar 29 22:31:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 784105 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp3429454wrt; Fri, 29 Mar 2024 15:34:02 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVXu/T4ZQy1y4WXZrlUob08BG12R3oTCpkDPEXQqE1nOerHGMndMNHp2Mn8AwAmrMFKJjCWDPoIB3ZNm4HkzJ8K X-Google-Smtp-Source: AGHT+IHXYxlAu5gVQofxU9m1x6zve/QkMz9htLbdUiKKGvArcQ7+6eus7+pGNeeVfrXMJlXkd3ko X-Received: by 2002:ac8:5941:0:b0:431:6e46:ab4c with SMTP id 1-20020ac85941000000b004316e46ab4cmr4158331qtz.54.1711751642031; Fri, 29 Mar 2024 15:34:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711751642; cv=none; d=google.com; s=arc-20160816; b=NChWwkrjRmH9n2peqrJQO6NjOsSY7ZVS2KEvxFotG4Zty32DAw9jhm4DmYab/w7Se5 Ev+hMvjIX1XOKRoMY5HQHK+j94fgKYxPEgkKK0vLjDIKvzs8CqSEHAZzBwJ2fngiN4YX Yyc3AQztsQ7WiBENBA+UErX0NYPC5NQb4iCxtAAFesovAM1QqdQ0Ddqf3N5p0OeM9AJI PcC5JWD77iaRb9sMyPyNDGZMA8S+rwZgOxFNCY6tK/O8K5quaKNW1xAH9Pu66bH0b1oz M6OcX9RhZ2XvaHfwL+b7xmeE5xAqnDo9NtF7Y8X+lEdTUk5QXH+aVQdwgGubGCPxScnW MK2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vnjhMc8AFUnASgt/GDELAcE24oYis+MaL1Mj1wovAY4=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=TTZgVN4ujCGIw2GAeg/ukVC/BfNeN84/sGYwiUtctQVo+Y82Z4DSlpx2wBcL3aS0Px qs+NNHaNfb5R7JF64o+HYpg0mnKoMkgDqe9IEi/zSLg0eepyrouEhpY4AzCb0TiAj3YC P2x7UyJIWMoMhIpnt4pEoMsLBdTVI2f2DNYtQfFEpfuXm/bu2mTBV93r7S4kvlS9LyJA 5W3lpDryF/haKhyM9Ur6PrjvdUk98S3T4blR5GPV0BCjU5kcntaXNVQAOc6JUdiuqHB5 PBZ7lI+xVxY7EAf6ancvnxQ4HG+mYnBlEndoh89qjXykbLzorAYWZeuWq+sDrW8Wogl8 erAg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RG1tjgff; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[98.147.7.212]) by smtp.gmail.com with ESMTPSA id f8-20020a170902684800b001e09b636cafsm4000955pln.287.2024.03.29.15.31.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 15:31:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 10/18] target/hppa: Optimize UADDCM with no condition Date: Fri, 29 Mar 2024 12:31:03 -1000 Message-Id: <20240329223111.1735826-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org> References: <20240329223111.1735826-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org With r1 as zero is by far the most common usage of UADDCM, as the easiest way to invert a register. The compiler does occasionally use the addition step as well, and we can simplify that to avoid a temp and write directly into the destination. Tested-by: Helge Deller Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index a3f425d861..3fc3e7754c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2763,9 +2763,29 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc) { TCGv_i64 tcg_r1, tcg_r2, tmp; - if (a->cf) { - nullify_over(ctx); + if (a->cf == 0) { + tcg_r2 = load_gpr(ctx, a->r2); + tmp = dest_gpr(ctx, a->t); + + if (a->r1 == 0) { + /* UADDCM r0,src,dst is the common idiom for dst = ~src. */ + tcg_gen_not_i64(tmp, tcg_r2); + } else { + /* + * Recall that r1 - r2 == r1 + ~r2 + 1. + * Thus r1 + ~r2 == r1 - r2 - 1, + * which does not require an extra temporary. + */ + tcg_r1 = load_gpr(ctx, a->r1); + tcg_gen_sub_i64(tmp, tcg_r1, tcg_r2); + tcg_gen_subi_i64(tmp, tmp, 1); + } + save_gpr(ctx, a->t, tmp); + cond_free(&ctx->null_cond); + return true; } + + nullify_over(ctx); tcg_r1 = load_gpr(ctx, a->r1); tcg_r2 = load_gpr(ctx, a->r2); tmp = tcg_temp_new_i64(); From patchwork Fri Mar 29 22:31:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 784103 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp3429379wrt; Fri, 29 Mar 2024 15:33:45 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWStPe5HyKhd6oMcDjHeWSRtQA8IGZfRvhK9PvN20ivbykA14jiSEV1fdm+6DFE1Vdo8oeGZQORRZzrKBfxVClV X-Google-Smtp-Source: AGHT+IG4KhiWQ+7ey7k7f//OCdn8F/XpFT39fZaTyo6RcRjFmHSuWPfRty4kjx/BvCxqLWp4XF62 X-Received: by 2002:a25:1e42:0:b0:dcc:99b6:830b with SMTP id e63-20020a251e42000000b00dcc99b6830bmr3586642ybe.19.1711751625252; Fri, 29 Mar 2024 15:33:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711751625; cv=none; d=google.com; s=arc-20160816; b=m9l60ux3+l+DYaQMc1i/Gqr9o0ou1k2rb8pNXfA8YlmQ4QYLpJopWCuWnimaQd1is4 rGRv9tp50MQm4I6TrPS3ENW5fYggHITEwQ3fd+/ljk4BhTh+qHzSnvpFsVnBD6LY9LMr Wy5n0kr7JDSBjXFe/vJQ7jXAEoUi4RhxWZ2DLdOeI7r9sQQBZYWxntcvDnw5qM7ItNQW AQg163pBVOglanWJf2V5QhzfDkg+NXSDkgR/kjEg6IsumGK6Rl+pMIzinivymxCs6Fk6 Zp1z5KggXT2NE1tJSI+mUShZHK8JQQLndgsfXWIgXBc31N7yGg15/KN7jriRq1i7Pv8i fdUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=aRxvFx4jyf1OvdOEJQeIUF5yPpRtSfNlC9jIwIYW+p0=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=PRKgmc1jENCWfTc091/4isQOctGG4MqCRjm+dzBrV2Z2bRhyuPZkYNj+aNavw3XMCt m4XHNLLk3gtHfRe7bTnCI0IMQSTO8xnFq07fzll1PXblqkTIlGT/eB3ZZjtjSQUIkhMa 9NjNrvvXkkRd7M+eu5sUqbe8cxepDS55QAfHEqlx8M5sR8V+oWBfMWKiWM3ElBgGfkBR rmZsVg3HLBYAuRZcNf4EevyTAotZVp/ZBkWZxPJ9pyZhYvRc6R+ENrCMNfF56gW8VN17 MSW6bz7799G9e53sn7GhDLxMNFJo3ysMfjuM8YyXtNZdRrlcGAz7C2FpZw6ZU8W65AaG EYIQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=u8FrQ0L8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[98.147.7.212]) by smtp.gmail.com with ESMTPSA id f8-20020a170902684800b001e09b636cafsm4000955pln.287.2024.03.29.15.31.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 15:31:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 11/18] target/hppa: Fix unit carry conditions Date: Fri, 29 Mar 2024 12:31:04 -1000 Message-Id: <20240329223111.1735826-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org> References: <20240329223111.1735826-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Split do_unit_cond to do_unit_zero_cond to only handle conditions versus zero. These are the only ones that are legal for UXOR. Simplify trans_uxor accordingly. Rename do_unit to do_unit_addsub, since xor has been split. Properly compute carry-out bits for add and subtract, mirroring the code in do_add and do_sub. Tested-by: Helge Deller Reviewed-by: Helge Deller Fixes: b2167459ae4 ("target-hppa: Implement basic arithmetic") Signed-off-by: Richard Henderson --- target/hppa/translate.c | 218 +++++++++++++++++++++------------------- 1 file changed, 113 insertions(+), 105 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3fc3e7754c..99c5c4cbca 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -936,98 +936,44 @@ static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, bool d, return do_log_cond(ctx, c * 2 + f, d, res); } -/* Similar, but for unit conditions. */ - -static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_i64 res, - TCGv_i64 in1, TCGv_i64 in2) +/* Similar, but for unit zero conditions. */ +static DisasCond do_unit_zero_cond(unsigned cf, bool d, TCGv_i64 res) { - DisasCond cond; - TCGv_i64 tmp, cb = NULL; + TCGv_i64 tmp; uint64_t d_repl = d ? 0x0000000100000001ull : 1; - - if (cf & 8) { - /* Since we want to test lots of carry-out bits all at once, do not - * do our normal thing and compute carry-in of bit B+1 since that - * leaves us with carry bits spread across two words. - */ - cb = tcg_temp_new_i64(); - tmp = tcg_temp_new_i64(); - tcg_gen_or_i64(cb, in1, in2); - tcg_gen_and_i64(tmp, in1, in2); - tcg_gen_andc_i64(cb, cb, res); - tcg_gen_or_i64(cb, cb, tmp); - } + uint64_t ones = 0, sgns = 0; switch (cf >> 1) { - case 0: /* never / TR */ - cond = cond_make_f(); - break; - case 1: /* SBW / NBW */ if (d) { - tmp = tcg_temp_new_i64(); - tcg_gen_subi_i64(tmp, res, d_repl * 0x00000001u); - tcg_gen_andc_i64(tmp, tmp, res); - tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80000000u); - cond = cond_make_0(TCG_COND_NE, tmp); - } else { - /* undefined */ - cond = cond_make_f(); + ones = d_repl; + sgns = d_repl << 31; } break; - case 2: /* SBZ / NBZ */ - /* See hasless(v,1) from - * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord - */ - tmp = tcg_temp_new_i64(); - tcg_gen_subi_i64(tmp, res, d_repl * 0x01010101u); - tcg_gen_andc_i64(tmp, tmp, res); - tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80808080u); - cond = cond_make_0(TCG_COND_NE, tmp); + ones = d_repl * 0x01010101u; + sgns = ones << 7; break; - case 3: /* SHZ / NHZ */ - tmp = tcg_temp_new_i64(); - tcg_gen_subi_i64(tmp, res, d_repl * 0x00010001u); - tcg_gen_andc_i64(tmp, tmp, res); - tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80008000u); - cond = cond_make_0(TCG_COND_NE, tmp); + ones = d_repl * 0x00010001u; + sgns = ones << 15; break; - - case 4: /* SDC / NDC */ - tcg_gen_andi_i64(cb, cb, d_repl * 0x88888888u); - cond = cond_make_0(TCG_COND_NE, cb); - break; - - case 5: /* SWC / NWC */ - if (d) { - tcg_gen_andi_i64(cb, cb, d_repl * 0x80000000u); - cond = cond_make_0(TCG_COND_NE, cb); - } else { - /* undefined */ - cond = cond_make_f(); - } - break; - - case 6: /* SBC / NBC */ - tcg_gen_andi_i64(cb, cb, d_repl * 0x80808080u); - cond = cond_make_0(TCG_COND_NE, cb); - break; - - case 7: /* SHC / NHC */ - tcg_gen_andi_i64(cb, cb, d_repl * 0x80008000u); - cond = cond_make_0(TCG_COND_NE, cb); - break; - - default: - g_assert_not_reached(); } - if (cf & 1) { - cond.c = tcg_invert_cond(cond.c); + if (ones == 0) { + /* Undefined, or 0/1 (never/always). */ + return cf & 1 ? cond_make_t() : cond_make_f(); } - return cond; + /* + * See hasless(v,1) from + * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord + */ + tmp = tcg_temp_new_i64(); + tcg_gen_subi_i64(tmp, res, ones); + tcg_gen_andc_i64(tmp, tmp, res); + tcg_gen_andi_i64(tmp, tmp, sgns); + + return cond_make_0_tmp(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, tmp); } static TCGv_i64 get_carry(DisasContext *ctx, bool d, @@ -1330,34 +1276,86 @@ static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a, return nullify_end(ctx); } -static void do_unit(DisasContext *ctx, unsigned rt, TCGv_i64 in1, - TCGv_i64 in2, unsigned cf, bool d, bool is_tc, - void (*fn)(TCGv_i64, TCGv_i64, TCGv_i64)) +static void do_unit_addsub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, + TCGv_i64 in2, unsigned cf, bool d, + bool is_tc, bool is_add) { - TCGv_i64 dest; + TCGv_i64 dest = tcg_temp_new_i64(); + uint64_t test_cb = 0; DisasCond cond; - if (cf == 0) { - dest = dest_gpr(ctx, rt); - fn(dest, in1, in2); - save_gpr(ctx, rt, dest); - cond_free(&ctx->null_cond); - } else { - dest = tcg_temp_new_i64(); - fn(dest, in1, in2); - - cond = do_unit_cond(cf, d, dest, in1, in2); - - if (is_tc) { - TCGv_i64 tmp = tcg_temp_new_i64(); - tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); - gen_helper_tcond(tcg_env, tmp); + /* Select which carry-out bits to test. */ + switch (cf >> 1) { + case 4: /* NDC / SDC -- 4-bit carries */ + test_cb = dup_const(MO_8, 0x88); + break; + case 5: /* NWC / SWC -- 32-bit carries */ + if (d) { + test_cb = dup_const(MO_32, INT32_MIN); + } else { + cf &= 1; /* undefined -- map to never/always */ } - save_gpr(ctx, rt, dest); - - cond_free(&ctx->null_cond); - ctx->null_cond = cond; + break; + case 6: /* NBC / SBC -- 8-bit carries */ + test_cb = dup_const(MO_8, INT8_MIN); + break; + case 7: /* NHC / SHC -- 16-bit carries */ + test_cb = dup_const(MO_16, INT16_MIN); + break; } + if (!d) { + test_cb = (uint32_t)test_cb; + } + + if (!test_cb) { + /* No need to compute carries if we don't need to test them. */ + if (is_add) { + tcg_gen_add_i64(dest, in1, in2); + } else { + tcg_gen_sub_i64(dest, in1, in2); + } + cond = do_unit_zero_cond(cf, d, dest); + } else { + TCGv_i64 cb = tcg_temp_new_i64(); + + if (d) { + TCGv_i64 cb_msb = tcg_temp_new_i64(); + if (is_add) { + tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, in2, ctx->zero); + tcg_gen_xor_i64(cb, in1, in2); + } else { + /* See do_sub, !is_b. */ + TCGv_i64 one = tcg_constant_i64(1); + tcg_gen_sub2_i64(dest, cb_msb, in1, one, in2, ctx->zero); + tcg_gen_eqv_i64(cb, in1, in2); + } + tcg_gen_xor_i64(cb, cb, dest); + tcg_gen_extract2_i64(cb, cb, cb_msb, 1); + } else { + if (is_add) { + tcg_gen_add_i64(dest, in1, in2); + tcg_gen_xor_i64(cb, in1, in2); + } else { + tcg_gen_sub_i64(dest, in1, in2); + tcg_gen_eqv_i64(cb, in1, in2); + } + tcg_gen_xor_i64(cb, cb, dest); + tcg_gen_shri_i64(cb, cb, 1); + } + + tcg_gen_andi_i64(cb, cb, test_cb); + cond = cond_make_0_tmp(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, cb); + } + + if (is_tc) { + TCGv_i64 tmp = tcg_temp_new_i64(); + tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); + gen_helper_tcond(tcg_env, tmp); + } + save_gpr(ctx, rt, dest); + + cond_free(&ctx->null_cond); + ctx->null_cond = cond; } #ifndef CONFIG_USER_ONLY @@ -2748,14 +2746,24 @@ static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf_d *a) static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a) { - TCGv_i64 tcg_r1, tcg_r2; + TCGv_i64 tcg_r1, tcg_r2, dest; if (a->cf) { nullify_over(ctx); } + tcg_r1 = load_gpr(ctx, a->r1); tcg_r2 = load_gpr(ctx, a->r2); - do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, false, tcg_gen_xor_i64); + dest = dest_gpr(ctx, a->t); + + tcg_gen_xor_i64(dest, tcg_r1, tcg_r2); + save_gpr(ctx, a->t, dest); + + cond_free(&ctx->null_cond); + if (a->cf) { + ctx->null_cond = do_unit_zero_cond(a->cf, a->d, dest); + } + return nullify_end(ctx); } @@ -2790,7 +2798,7 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc) tcg_r2 = load_gpr(ctx, a->r2); tmp = tcg_temp_new_i64(); tcg_gen_not_i64(tmp, tcg_r2); - do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_i64); + do_unit_addsub(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, true); return nullify_end(ctx); } @@ -2817,8 +2825,8 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i) } tcg_gen_andi_i64(tmp, tmp, (uint64_t)0x1111111111111111ull); tcg_gen_muli_i64(tmp, tmp, 6); - do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, a->d, false, - is_i ? tcg_gen_add_i64 : tcg_gen_sub_i64); + do_unit_addsub(ctx, a->t, load_gpr(ctx, a->r), tmp, + a->cf, a->d, false, is_i); return nullify_end(ctx); } From patchwork Fri Mar 29 22:31:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 784094 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp3429042wrt; Fri, 29 Mar 2024 15:32:37 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVb+dc3mUejCpW7Pqlt1Pl2AK6M8dgaNNvPaiqydXSzZI7P+m8c77g+tHC+XfGaPuF4rf4Fwox9M2o4Mm1ahENQ X-Google-Smtp-Source: AGHT+IHgSDICJIV+whsGHJVclbt09EzsY5YZZndKIZku8jdH18tlPzGi0c9PTjijy4eUOCPet7Nb X-Received: by 2002:ac8:5c8d:0:b0:431:172d:645d with SMTP id r13-20020ac85c8d000000b00431172d645dmr11497957qta.26.1711751557152; Fri, 29 Mar 2024 15:32:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711751557; cv=none; d=google.com; s=arc-20160816; b=jvOIO7v0ddI0ylW1GoSrkg7nBzo7MVnbW4XsNVQw5gztnSdsYR3V+ZYwn/GYL0JeBj WrIcBQjyrvTZVzXWDRThOVFfP4rVBB6eDiuko4sB9U1cR3u+eEydTyo6KFYsL75x8/Vp 9aX6FyU58JXwtz26zMdLcgyeqUt4SnDhnq8wAq2vsQcFb0DEJNz0W8UqtX4f7NzS5SXF fv60aNFP10349BgvPFRLMUUGoHRy0qdgkFDNFdQ7PXSAQzS5HLEWumVgLBieT+U+1iJK XtdH8fHolToCPt0d4klVSSrpChh1PpHC7pP2x+HeMNuAgE6aRFVShki54/5Ssz+JkxN8 I7Dw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KMxM9BbQqKkbLwVKQwHtbDKmzoAaG7uKsKCnvfYND6Q=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=wtV5GWmMu1aQAq5prwKPFfEv0YAlMh85Ep2q05AAz/7OWn4AKutJUJ2jBBmNvpZVVi hdOnfEKjJJpELFDvzK2uxiR3USD9Cj+qVU3IPwgeCSTzfQGwilU4LlFbgMzWK38B7Kum 0Wg5vQAOtbjWxt58B170CFcWdz+iEjvR9A/sognAuvotrM83pdrQsv3j7Lpxo1vRLnwV P/EyykbRVDWkXACvw8BFR9i/jjziAIedtC/G+aVIKa6LHm7rootV0lw2nqx9V7hvz/9N S/a94QQEFRU1MHVDdTIP0HjsCzH6D2NLZyyJpo1aTwKrQN4o74kmfnSCjGoH/J6Wms6a njyA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="J/oSCaGf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[98.147.7.212]) by smtp.gmail.com with ESMTPSA id f8-20020a170902684800b001e09b636cafsm4000955pln.287.2024.03.29.15.31.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 15:31:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 12/18] target/hppa: Squash d for pa1.x during decode Date: Fri, 29 Mar 2024 12:31:05 -1000 Message-Id: <20240329223111.1735826-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org> References: <20240329223111.1735826-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The cond_need_ext predicate was created while we still had a 32-bit compilation mode. It now makes more sense to treat D as an absolute indicator of a 64-bit operation. Tested-by: Helge Deller Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 20 +++++++++++++------- target/hppa/translate.c | 38 ++++++++++++++++++++------------------ 2 files changed, 33 insertions(+), 25 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index f58455dfdb..6a74cf23cd 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -57,6 +57,9 @@ %neg_to_m 0:1 !function=neg_to_m %a_to_m 2:1 !function=neg_to_m %cmpbid_c 13:2 !function=cmpbid_c +%d_5 5:1 !function=pa20_d +%d_11 11:1 !function=pa20_d +%d_13 13:1 !function=pa20_d #### # Argument set definitions @@ -84,15 +87,16 @@ # Format definitions #### -@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d +@rr_cf_d ...... r:5 ..... cf:4 ...... . t:5 &rr_cf_d d=%d_5 @rrr ...... r2:5 r1:5 .... ....... t:5 &rrr @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf -@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d +@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... . t:5 &rrr_cf_d d=%d_5 @rrr_sh ...... r2:5 r1:5 ........ sh:2 . t:5 &rrr_sh -@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh -@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=0 +@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_d_sh d=%d_5 +@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... . t:5 &rrr_cf_d_sh d=%d_5 sh=0 @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 -@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11 +@rri_cf_d ...... r:5 t:5 cf:4 . ........... \ + &rri_cf_d d=%d_11 i=%lowsign_11 @rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ &rrb_c_f disp=%assemble_12 @@ -368,8 +372,10 @@ fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd # Conditional Branches #### -bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12 -bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12 +bb_sar 110000 00000 r:5 c:1 1 . ........... n:1 . \ + disp=%assemble_12 d=%d_13 +bb_imm 110001 p:5 r:5 c:1 1 . ........... n:1 . \ + disp=%assemble_12 d=%d_13 movb 110010 ..... ..... ... ........... . . @rrb_cf f=0 movbi 110011 ..... ..... ... ........... . . @rib_cf f=0 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 99c5c4cbca..a70d644c0b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -200,6 +200,14 @@ static int cmpbid_c(DisasContext *ctx, int val) return val ? val : 4; /* 0 == "*<<" */ } +/* + * In many places pa1.x did not decode the bit that later became + * the pa2.0 D bit. Suppress D unless the cpu is pa2.0. + */ +static int pa20_d(DisasContext *ctx, int val) +{ + return ctx->is_pa20 & val; +} /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" @@ -693,12 +701,6 @@ static bool cond_need_cb(int c) return c == 4 || c == 5; } -/* Need extensions from TCGv_i32 to TCGv_i64. */ -static bool cond_need_ext(DisasContext *ctx, bool d) -{ - return !(ctx->is_pa20 && d); -} - /* * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of * the Parisc 1.1 Architecture Reference Manual for details. @@ -715,7 +717,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, cond = cond_make_f(); break; case 1: /* = / <> (Z / !Z) */ - if (cond_need_ext(ctx, d)) { + if (!d) { tmp = tcg_temp_new_i64(); tcg_gen_ext32u_i64(tmp, res); res = tmp; @@ -725,7 +727,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, case 2: /* < / >= (N ^ V / !(N ^ V) */ tmp = tcg_temp_new_i64(); tcg_gen_xor_i64(tmp, res, sv); - if (cond_need_ext(ctx, d)) { + if (!d) { tcg_gen_ext32s_i64(tmp, tmp); } cond = cond_make_0_tmp(TCG_COND_LT, tmp); @@ -742,7 +744,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, */ tmp = tcg_temp_new_i64(); tcg_gen_eqv_i64(tmp, res, sv); - if (cond_need_ext(ctx, d)) { + if (!d) { tcg_gen_sextract_i64(tmp, tmp, 31, 1); tcg_gen_and_i64(tmp, tmp, res); tcg_gen_ext32u_i64(tmp, tmp); @@ -760,13 +762,13 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, tmp = tcg_temp_new_i64(); tcg_gen_neg_i64(tmp, cb_msb); tcg_gen_and_i64(tmp, tmp, res); - if (cond_need_ext(ctx, d)) { + if (!d) { tcg_gen_ext32u_i64(tmp, tmp); } cond = cond_make_0_tmp(TCG_COND_EQ, tmp); break; case 6: /* SV / NSV (V / !V) */ - if (cond_need_ext(ctx, d)) { + if (!d) { tmp = tcg_temp_new_i64(); tcg_gen_ext32s_i64(tmp, sv); sv = tmp; @@ -827,7 +829,7 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d, if (cf & 1) { tc = tcg_invert_cond(tc); } - if (cond_need_ext(ctx, d)) { + if (!d) { TCGv_i64 t1 = tcg_temp_new_i64(); TCGv_i64 t2 = tcg_temp_new_i64(); @@ -904,7 +906,7 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d, g_assert_not_reached(); } - if (cond_need_ext(ctx, d)) { + if (!d) { TCGv_i64 tmp = tcg_temp_new_i64(); if (ext_uns) { @@ -979,7 +981,7 @@ static DisasCond do_unit_zero_cond(unsigned cf, bool d, TCGv_i64 res) static TCGv_i64 get_carry(DisasContext *ctx, bool d, TCGv_i64 cb, TCGv_i64 cb_msb) { - if (cond_need_ext(ctx, d)) { + if (!d) { TCGv_i64 t = tcg_temp_new_i64(); tcg_gen_extract_i64(t, cb, 32, 1); return t; @@ -3448,12 +3450,12 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) tmp = tcg_temp_new_i64(); tcg_r = load_gpr(ctx, a->r); - if (cond_need_ext(ctx, a->d)) { + if (a->d) { + tcg_gen_shl_i64(tmp, tcg_r, cpu_sar); + } else { /* Force shift into [32,63] */ tcg_gen_ori_i64(tmp, cpu_sar, 32); tcg_gen_shl_i64(tmp, tcg_r, tmp); - } else { - tcg_gen_shl_i64(tmp, tcg_r, cpu_sar); } cond = cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); @@ -3470,7 +3472,7 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) tmp = tcg_temp_new_i64(); tcg_r = load_gpr(ctx, a->r); - p = a->p | (cond_need_ext(ctx, a->d) ? 32 : 0); + p = a->p | (a->d ? 0 : 32); tcg_gen_shli_i64(tmp, tcg_r, p); cond = cond_make_0(a->c ? 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[98.147.7.212]) by smtp.gmail.com with ESMTPSA id f8-20020a170902684800b001e09b636cafsm4000955pln.287.2024.03.29.15.31.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 15:31:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 13/18] target/hppa: Replace c with uv in do_cond Date: Fri, 29 Mar 2024 12:31:06 -1000 Message-Id: <20240329223111.1735826-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org> References: <20240329223111.1735826-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Prepare for proper indication of shladd unsigned overflow. The UV indicator will be zero/not-zero instead of a single bit. Tested-by: Helge Deller Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index a70d644c0b..9d31ef5764 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -707,7 +707,7 @@ static bool cond_need_cb(int c) */ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, - TCGv_i64 res, TCGv_i64 cb_msb, TCGv_i64 sv) + TCGv_i64 res, TCGv_i64 uv, TCGv_i64 sv) { DisasCond cond; TCGv_i64 tmp; @@ -754,14 +754,12 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, } cond = cond_make_0_tmp(TCG_COND_EQ, tmp); break; - case 4: /* NUV / UV (!C / C) */ - /* Only bit 0 of cb_msb is ever set. */ - cond = cond_make_0(TCG_COND_EQ, cb_msb); + case 4: /* NUV / UV (!UV / UV) */ + cond = cond_make_0(TCG_COND_EQ, uv); break; - case 5: /* ZNV / VNZ (!C | Z / C & !Z) */ + case 5: /* ZNV / VNZ (!UV | Z / UV & !Z) */ tmp = tcg_temp_new_i64(); - tcg_gen_neg_i64(tmp, cb_msb); - tcg_gen_and_i64(tmp, tmp, res); + tcg_gen_movcond_i64(TCG_COND_EQ, tmp, uv, ctx->zero, ctx->zero, res); if (!d) { tcg_gen_ext32u_i64(tmp, tmp); } From patchwork Fri Mar 29 22:31:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 784090 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp3428994wrt; Fri, 29 Mar 2024 15:32:27 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWPyZXraCrruLyQagjJIPNj5XVUNWTSkHsTBI/o3iMLAK+wCy7Jig9sRztgAOHmFKRnKH0BB3i3dp0NYf8xO27z X-Google-Smtp-Source: AGHT+IEO1yheF/QzOJ2mY9z/AMrh/b8IONdNPma4xPNuQJfdzzTFQM4XAsKIvShS3HBDEW793VSZ X-Received: by 2002:a05:622a:198c:b0:431:3b89:56ef with SMTP id u12-20020a05622a198c00b004313b8956efmr4422843qtc.26.1711751547610; Fri, 29 Mar 2024 15:32:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711751547; cv=none; d=google.com; s=arc-20160816; b=Muev0lXPRKpEdU+dl5C6zzRrlUTb1fdE55XxM1zboTiUyNIk4sS53sLyTyX5pjz4Px AR3dDaAdRHmoWYJUYjvA5BgmpPzuyu6ss3EkuRKtvVgZ4rHvPPwtCSv4ZZmwzLtk0u68 iVyuDTjLJK9JWq0JcevmYepZmd1G/kj55Q2nuIgMRXwTRjBj27qPfwlcp3hEcnX2RJoc Lzpn2hb3LVVzJJXi4f1KFINwO0xbDcFin8cBpmBZRGHuvEzBKb0juK6X2IS6+xpgoEuM DRZnBmzlyWNXUWbruz6jjRz9PZtPL20JQnCJNPyzIQUUV2o0cTL4ibNpo+6KIRSt6+Sb gceQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=K8E6cou+7Nj72A3SF6Jpjpj6zfeFiz5qaUOwtzCNxnY=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=NOxG87QuuL4UQ9+CpuQUvZN8e1Q9tVjnNlOwoeojJrWcSfLXvLsw/B0iDo2Lg78spz C4vpFyTbPWg/qyd935rjFJ85uumeu9BNG+7ij4YSQoW/r6pN4lhKtCBH/8/cdD6mB7sC kQD8SuljJvpIZ+RlGAe4HPEbac3wGX1Q78/i6HrhqJglohmvBapnjVCAFui7ZXf+Li2F E1Ulqq3bPalYOaH9KRpYqTd8xCx0FJwnBHMKXOIPlatgOK2vNXsiXCB120uzYsYWhiB2 NaX4OAaav3wfFKafmvwE1IokOpWzbq891VG0Fzj1eylAwYn0nV7VfdItLLz9tZtmVCmt FyjQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sbLoLvQ4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[98.147.7.212]) by smtp.gmail.com with ESMTPSA id f8-20020a170902684800b001e09b636cafsm4000955pln.287.2024.03.29.15.31.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 15:31:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 14/18] target/hppa: Fix overflow computation for shladd Date: Fri, 29 Mar 2024 12:31:07 -1000 Message-Id: <20240329223111.1735826-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org> References: <20240329223111.1735826-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Overflow indicator should include the effect of the shift step. We had previously left ??? comments about the issue. Tested-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 84 +++++++++++++++++++++++++++++++---------- 1 file changed, 65 insertions(+), 19 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 9d31ef5764..6da9503f33 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -994,7 +994,8 @@ static TCGv_i64 get_psw_carry(DisasContext *ctx, bool d) /* Compute signed overflow for addition. */ static TCGv_i64 do_add_sv(DisasContext *ctx, TCGv_i64 res, - TCGv_i64 in1, TCGv_i64 in2) + TCGv_i64 in1, TCGv_i64 in2, + TCGv_i64 orig_in1, int shift, bool d) { TCGv_i64 sv = tcg_temp_new_i64(); TCGv_i64 tmp = tcg_temp_new_i64(); @@ -1003,9 +1004,49 @@ static TCGv_i64 do_add_sv(DisasContext *ctx, TCGv_i64 res, tcg_gen_xor_i64(tmp, in1, in2); tcg_gen_andc_i64(sv, sv, tmp); + switch (shift) { + case 0: + break; + case 1: + /* Shift left by one and compare the sign. */ + tcg_gen_add_i64(tmp, orig_in1, orig_in1); + tcg_gen_xor_i64(tmp, tmp, orig_in1); + /* Incorporate into the overflow. */ + tcg_gen_or_i64(sv, sv, tmp); + break; + default: + { + int sign_bit = d ? 63 : 31; + + /* Compare the sign against all lower bits. */ + tcg_gen_sextract_i64(tmp, orig_in1, sign_bit, 1); + tcg_gen_xor_i64(tmp, tmp, orig_in1); + /* + * If one of the bits shifting into or through the sign + * differs, then we have overflow. + */ + tcg_gen_extract_i64(tmp, tmp, sign_bit - shift, shift); + tcg_gen_movcond_i64(TCG_COND_NE, sv, tmp, ctx->zero, + tcg_constant_i64(-1), sv); + } + } return sv; } +/* Compute unsigned overflow for addition. */ +static TCGv_i64 do_add_uv(DisasContext *ctx, TCGv_i64 cb, TCGv_i64 cb_msb, + TCGv_i64 in1, int shift, bool d) +{ + if (shift == 0) { + return get_carry(ctx, d, cb, cb_msb); + } else { + TCGv_i64 tmp = tcg_temp_new_i64(); + tcg_gen_extract_i64(tmp, in1, (d ? 63 : 31) - shift, shift); + tcg_gen_or_i64(tmp, tmp, get_carry(ctx, d, cb, cb_msb)); + return tmp; + } +} + /* Compute signed overflow for subtraction. */ static TCGv_i64 do_sub_sv(DisasContext *ctx, TCGv_i64 res, TCGv_i64 in1, TCGv_i64 in2) @@ -1020,19 +1061,19 @@ static TCGv_i64 do_sub_sv(DisasContext *ctx, TCGv_i64 res, return sv; } -static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1, +static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1, TCGv_i64 in2, unsigned shift, bool is_l, bool is_tsv, bool is_tc, bool is_c, unsigned cf, bool d) { - TCGv_i64 dest, cb, cb_msb, cb_cond, sv, tmp; + TCGv_i64 dest, cb, cb_msb, in1, uv, sv, tmp; unsigned c = cf >> 1; DisasCond cond; dest = tcg_temp_new_i64(); cb = NULL; cb_msb = NULL; - cb_cond = NULL; + in1 = orig_in1; if (shift) { tmp = tcg_temp_new_i64(); tcg_gen_shli_i64(tmp, in1, shift); @@ -1050,9 +1091,6 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1, } tcg_gen_xor_i64(cb, in1, in2); tcg_gen_xor_i64(cb, cb, dest); - if (cond_need_cb(c)) { - cb_cond = get_carry(ctx, d, cb, cb_msb); - } } else { tcg_gen_add_i64(dest, in1, in2); if (is_c) { @@ -1063,18 +1101,23 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1, /* Compute signed overflow if required. */ sv = NULL; if (is_tsv || cond_need_sv(c)) { - sv = do_add_sv(ctx, dest, in1, in2); + sv = do_add_sv(ctx, dest, in1, in2, orig_in1, shift, d); if (is_tsv) { if (!d) { tcg_gen_ext32s_i64(sv, sv); } - /* ??? Need to include overflow from shift. */ gen_helper_tsv(tcg_env, sv); } } + /* Compute unsigned overflow if required. */ + uv = NULL; + if (cond_need_cb(c)) { + uv = do_add_uv(ctx, cb, cb_msb, orig_in1, shift, d); + } + /* Emit any conditional trap before any writeback. */ - cond = do_cond(ctx, cf, d, dest, cb_cond, sv); + cond = do_cond(ctx, cf, d, dest, uv, sv); if (is_tc) { tmp = tcg_temp_new_i64(); tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); @@ -2843,7 +2886,6 @@ static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf_d *a) static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) { TCGv_i64 dest, add1, add2, addc, in1, in2; - TCGv_i64 cout; nullify_over(ctx); @@ -2880,19 +2922,23 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) tcg_gen_xor_i64(cpu_psw_cb, add1, add2); tcg_gen_xor_i64(cpu_psw_cb, cpu_psw_cb, dest); - /* Write back PSW[V] for the division step. */ - cout = get_psw_carry(ctx, false); - tcg_gen_neg_i64(cpu_psw_v, cout); + /* + * Write back PSW[V] for the division step. + * Shift cb{8} from where it lives in bit 32 to bit 31, + * so that it overlaps r2{32} in bit 31. + */ + tcg_gen_shri_i64(cpu_psw_v, cpu_psw_cb, 1); tcg_gen_xor_i64(cpu_psw_v, cpu_psw_v, in2); /* Install the new nullification. */ if (a->cf) { - TCGv_i64 sv = NULL; + TCGv_i64 sv = NULL, uv = NULL; if (cond_need_sv(a->cf >> 1)) { - /* ??? The lshift is supposed to contribute to overflow. */ - sv = do_add_sv(ctx, dest, add1, add2); + sv = do_add_sv(ctx, dest, add1, add2, in1, 1, false); + } else if (cond_need_cb(a->cf >> 1)) { + uv = do_add_uv(ctx, cpu_psw_cb, NULL, in1, 1, false); } - ctx->null_cond = do_cond(ctx, a->cf, false, dest, cout, sv); + ctx->null_cond = do_cond(ctx, a->cf, false, dest, uv, sv); } return nullify_end(ctx); @@ -3419,7 +3465,7 @@ static bool do_addb(DisasContext *ctx, unsigned r, TCGv_i64 in1, tcg_gen_add_i64(dest, in1, in2); } if (cond_need_sv(c)) { - sv = do_add_sv(ctx, dest, in1, in2); + sv = do_add_sv(ctx, dest, in1, in2, in1, 0, d); } cond = do_cond(ctx, c * 2 + f, d, dest, cb_cond, sv); From patchwork Fri Mar 29 22:31:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 784104 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp3429441wrt; Fri, 29 Mar 2024 15:34:00 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVDmvb2EMZZ9sYRZwf1LzkqSIRnIdagQr+08N4Oshef0RG96EmRbn/c6wsW5GmE+XYJhvVjewLoKgxzbQzvbqDR X-Google-Smtp-Source: AGHT+IGtNwnQkiTFTYgcUzzQfEPh99tiHbmSevT9z8GtebBM5EZIQTmRZZc3vDMlSCo0E9z0cFd6 X-Received: by 2002:a05:622a:491:b0:431:7c36:7f86 with SMTP id p17-20020a05622a049100b004317c367f86mr3748884qtx.59.1711751639984; Fri, 29 Mar 2024 15:33:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711751639; cv=none; d=google.com; s=arc-20160816; b=jKzW1ALTyFTwFfAEaQosRS6aATjBpS1ElD7eTIEEthCaO3cwbOWVFN2lGAiZR0cR5M 4XTbFdfK4Y1q6GAfo44ptw7WvlXt6V+BUR58Q+yrmhWkeKdlCjP1c1ii4vXJPAUrnw++ /9ZuXE9D0Wq9M0QoVmxdSeaw/8ImUyV9aUDNi+chshI19lzHpgukR/xj1PH6UYpvp7Ay njBXNiz65zkLVOv2c6fF1bOjDRSdXGTXIuJyghgQy+w8tUhGylrNmodnWaoUQvF/4CW3 lkJAUFK2oAw7sFW2BgLSBnREA9RHlvPG9BmY1tzaj4BTmNPN0Pl1m3OVjgVOkKjYZAiQ Qpxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zvYdGosSJzx/q33wx/CPl4VQF18FxpEZiKeNYnXcRT0=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=zhttxcHyYOWeqJkqDS960leyEd9XCT6WQlBBnPxKg6S5ufGia+kkgFhrrgjbGOkzOD jjwMAZVmgfhgmTq4TAa0QRJRwcfOIo27YeCNH0eBsh4uga2ikp1sYKvbgZZgIvJAljmg 7Ov8b+WbPhx5LbWVnYlz18jd5LwhZ8/4gnNv3lD7aWZ1rAV/5a6ajs9/FEJq+BOmGtap cijusnkYEmXCy8HulrPk09w9noa9gtesku3HX1JtUEFdSv097Pw/wSP645rsztv25ksu lqz4MnQ7mnNYy/HZIXRSnKSyF20xtqgS6YO6QFv3Q5DW2iY7wzO1ijZ+i20OQgVhV1Qc QVsQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uW0yAgHd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[98.147.7.212]) by smtp.gmail.com with ESMTPSA id f8-20020a170902684800b001e09b636cafsm4000955pln.287.2024.03.29.15.31.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 15:31:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 15/18] target/hppa: Generate getshadowregs inline Date: Fri, 29 Mar 2024 12:31:08 -1000 Message-Id: <20240329223111.1735826-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org> References: <20240329223111.1735826-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This operation is trivial and does not require a helper. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/helper.h | 1 - target/hppa/sys_helper.c | 4 ++-- target/hppa/translate.c | 17 +++++++++++++---- 3 files changed, 15 insertions(+), 7 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 8fd7ba65d8..5900fd70bc 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -86,7 +86,6 @@ DEF_HELPER_FLAGS_0(read_interval_timer, TCG_CALL_NO_RWG, tl) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(halt, noreturn, env) DEF_HELPER_1(reset, noreturn, env) -DEF_HELPER_1(getshadowregs, void, env) DEF_HELPER_1(rfi, void, env) DEF_HELPER_1(rfi_r, void, env) DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tl) diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c index 4a31748342..208e51c086 100644 --- a/target/hppa/sys_helper.c +++ b/target/hppa/sys_helper.c @@ -95,7 +95,7 @@ void HELPER(rfi)(CPUHPPAState *env) cpu_hppa_put_psw(env, env->cr[CR_IPSW]); } -void HELPER(getshadowregs)(CPUHPPAState *env) +static void getshadowregs(CPUHPPAState *env) { env->gr[1] = env->shadow[0]; env->gr[8] = env->shadow[1]; @@ -108,7 +108,7 @@ void HELPER(getshadowregs)(CPUHPPAState *env) void HELPER(rfi_r)(CPUHPPAState *env) { - helper_getshadowregs(env); + getshadowregs(env); helper_rfi(env); } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6da9503f33..29e4a64e40 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2385,14 +2385,23 @@ static bool trans_reset(DisasContext *ctx, arg_reset *a) #endif } -static bool trans_getshadowregs(DisasContext *ctx, arg_getshadowregs *a) +static bool do_getshadowregs(DisasContext *ctx) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); -#ifndef CONFIG_USER_ONLY nullify_over(ctx); - gen_helper_getshadowregs(tcg_env); + tcg_gen_ld_i64(cpu_gr[1], tcg_env, offsetof(CPUHPPAState, shadow[0])); + tcg_gen_ld_i64(cpu_gr[8], tcg_env, offsetof(CPUHPPAState, shadow[1])); + tcg_gen_ld_i64(cpu_gr[9], tcg_env, offsetof(CPUHPPAState, shadow[2])); + tcg_gen_ld_i64(cpu_gr[16], tcg_env, offsetof(CPUHPPAState, shadow[3])); + tcg_gen_ld_i64(cpu_gr[17], tcg_env, offsetof(CPUHPPAState, shadow[4])); + tcg_gen_ld_i64(cpu_gr[24], tcg_env, offsetof(CPUHPPAState, shadow[5])); + tcg_gen_ld_i64(cpu_gr[25], tcg_env, offsetof(CPUHPPAState, shadow[6])); return nullify_end(ctx); -#endif +} + +static bool trans_getshadowregs(DisasContext *ctx, arg_getshadowregs *a) +{ + return do_getshadowregs(ctx); } static bool trans_nop_addrx(DisasContext *ctx, arg_ldst *a) From patchwork Fri Mar 29 22:31:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 784101 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp3429360wrt; Fri, 29 Mar 2024 15:33:41 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXp5jUY607o3USyZPFhrSSLdL1T8K/rtiDbTO5j2Gvl7elRnIMc0StYO3HhTU6y21kYsd2WDKPaoayO7jAsEXEK X-Google-Smtp-Source: AGHT+IFc1d05qbFabtEUfWulF1zaPSelOxmAAlJn1WGIGoOsUM4J1KiwGicdzUBM+rsgSuzbHLwq X-Received: by 2002:a0d:e7c6:0:b0:611:30a2:1758 with SMTP id q189-20020a0de7c6000000b0061130a21758mr3670726ywe.37.1711751621444; Fri, 29 Mar 2024 15:33:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711751621; cv=none; d=google.com; s=arc-20160816; b=JXgmRTIHBM117HBikqkhPUXM5OSOZfFQD/2MSkhz8gfh8sFTviqCa3D6rsMVChvJCq aurzB9FwHqwxyUe+j7iDRYIrfjKh8DABRRT6UsElygAfxnWPBoLBMdL4hg3ok+X8tVDl C4s7Mi1Ph4P+6XC0ejqaoHTXyPvOde6/JZ7ROGXo7GGb+5Ndxl6HWYqrMg3y+tPjwh5j 7J6Ml1peiy3xjaOzBqbSE9p5zEyoaTJYcxXuxckQtaAI9v/ONepgf4tZIJWMlNAOeG8Z BSZVXR1TMDUGYVHK2J14YsC4eodLsaLnV9bZpK1C/6vTIVq1NdQKilpUGNkK4te1IXJ0 Ujow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3k8lclmQQ4F8nUAdVeP5eeR9f55SSu6v457WolvggHw=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=TeJK/1YiVPeAMsla/BZWc/YYbyaIyVSnP1yAc4ii0ODYW+F51wLlScibuNG1VBhBdv w5+g0wscwiFUTeHmb4lUehHZM6XrsffMDfVA7StUoAGcVJ+t9l78eIWCM+vGLVWHdnDt wBAP9EvfUhoVRP/btRSoTbIBfzO4kF5Q8eX97XPQ1QvAyiINKxa/ReZlgzisG3LxMj4O mE8NTy1trTkwZKBKGZuhZrUbPtZg8H6ly4+JgweRjBNAA1dZ1+37AQIoDFp3ajJL2IQ9 C47hVbpoXzDofVYGxULGuQDbfXRIGTPNi/DyQOyEbjFmmktCaqh7DOMiSY9ofxNdQgZR zaCA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MrPgI1jP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[98.147.7.212]) by smtp.gmail.com with ESMTPSA id f8-20020a170902684800b001e09b636cafsm4000955pln.287.2024.03.29.15.31.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 15:31:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 16/18] target/hppa: Move diag argument handling to decodetree Date: Fri, 29 Mar 2024 12:31:09 -1000 Message-Id: <20240329223111.1735826-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org> References: <20240329223111.1735826-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Split trans_diag into per-operation functions. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 8 +++++++- target/hppa/translate.c | 34 +++++++++++++++++++++------------- 2 files changed, 28 insertions(+), 14 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 6a74cf23cd..9f6ffd8e2c 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -634,4 +634,10 @@ fdiv_d 001110 ..... ..... 011 ..... ... ..... @f0e_d_3 xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64 # diag -diag 000101 i:26 +{ + [ + diag_btlb 000101 00 0000 0000 0000 0001 0000 0000 + diag_cout 000101 00 0000 0000 0000 0001 0000 0001 + ] + diag_unimp 000101 i:26 +} diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 29e4a64e40..42dd3f2c8d 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4572,23 +4572,31 @@ static bool trans_fmpyfadd_d(DisasContext *ctx, arg_fmpyfadd_d *a) return nullify_end(ctx); } -static bool trans_diag(DisasContext *ctx, arg_diag *a) +/* Emulate PDC BTLB, called by SeaBIOS-hppa */ +static bool trans_diag_btlb(DisasContext *ctx, arg_diag_btlb *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY - if (a->i == 0x100) { - /* emulate PDC BTLB, called by SeaBIOS-hppa */ - nullify_over(ctx); - gen_helper_diag_btlb(tcg_env); - return nullify_end(ctx); - } - if (a->i == 0x101) { - /* print char in %r26 to first serial console, used by SeaBIOS-hppa */ - nullify_over(ctx); - gen_helper_diag_console_output(tcg_env); - return nullify_end(ctx); - } + nullify_over(ctx); + gen_helper_diag_btlb(tcg_env); + return nullify_end(ctx); #endif +} + +/* Print char in %r26 to first serial console, used by SeaBIOS-hppa */ +static bool trans_diag_cout(DisasContext *ctx, arg_diag_cout *a) +{ + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); +#ifndef CONFIG_USER_ONLY + nullify_over(ctx); + gen_helper_diag_console_output(tcg_env); + return nullify_end(ctx); +#endif +} + +static bool trans_diag_unimp(DisasContext *ctx, arg_diag_unimp *a) +{ + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); qemu_log_mask(LOG_UNIMP, "DIAG opcode 0x%04x ignored\n", a->i); return true; } From patchwork Fri Mar 29 22:31:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 784102 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp3429377wrt; Fri, 29 Mar 2024 15:33:45 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXHhGJ1c9a5Ljwx/d3amtyGqZMxotFkzXLVG51oimakVDfAKzRMZOVsgP5+ZiQBNgtCcvsgB9zaPj0rXHLEkglR X-Google-Smtp-Source: AGHT+IH+2+wJ+ABS52HqxPoxXG43YdWVTnPWK3KhFAuu3uWzBc6MholzVeDVWXscM9GeLqhqhxIW X-Received: by 2002:a05:622a:1ba3:b0:431:3420:f60d with SMTP id bp35-20020a05622a1ba300b004313420f60dmr3690345qtb.42.1711751625076; Fri, 29 Mar 2024 15:33:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711751625; cv=none; d=google.com; s=arc-20160816; b=tOASb6tEyiyKe1AQtK1SC1za/mC5lAArZZj0C2n/Wf4pgmF9fcJrMo0uEMepRExcaH gwoDISLhZGfG7M7LgJ5URbhcEv3SO+n00QgD78ovwejI043Ix+MP+xe+5/jk+U/1LEes CA+HorIN4qQKAeQsfkbr3E/+qcLfj5hWaF0UIdD5LkbNaBMf3/qhZduM8rlbAzvJgrQp aE+Y/cI5h80r8gkJKbiUGXUkGEZscvtguYNjgvQLoM5Kfo5aY5QIHGJj0CRMqfYKbs9l yCJbuRP7khRpVqgL8bt02RH90G206NmL27tuMQoKkRqYDf8SCI3Fv3N2gZZ9OPeKwZQK pK6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=uX24NXcgU6IiX12Wm/xfyInlmTJOdDVKWFpfbbYjENA=; fh=L/zcBenwEF5glhwyLP21Krd2deVqVkTL6GpZ6TwRGPk=; b=GZAngCIoXzKQqkTv8eosi0KenGCNpDoeML0seALmYFWkF4Vflw6+4LuQKsBTxM7X5w PI4KgN7+vVFY8NNJfuICSv++NvnieCKLYVvn0DXnJzadzSiKUKBkc0ayBhoBfVMl95Ha 4a86yjAH/v8xtKelUObLpgN4AM3mAnU3IO/ort04Set+RPVappRifJglqQTFJafXedJv Vj0OvlUkyayVCheF0I+bdPaMXoHFx35feFANr92rSHiE7WYzoj2Pvvp6ZCNwLO2Yzsaj sKz5IcaeT1p0q79zGxntbpuFvJq7DuC/DHWgCbzH41rhQMHFtLAFpXrpcCx/TTrh9dXE eHtg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OQvZuSeZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[98.147.7.212]) by smtp.gmail.com with ESMTPSA id f8-20020a170902684800b001e09b636cafsm4000955pln.287.2024.03.29.15.31.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 15:31:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , Helge Deller Subject: [PULL 17/18] target/hppa: Add diag instructions to set/restore shadow registers Date: Fri, 29 Mar 2024 12:31:10 -1000 Message-Id: <20240329223111.1735826-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org> References: <20240329223111.1735826-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Helge Deller The 32-bit PA-7300LC (PCX-L2) CPU and the 64-bit PA8700 (PCX-W2) CPU use different diag instructions to save or restore the CPU registers to/from the shadow registers. Implement those per-CPU architecture diag instructions to fix those parts of the HP ODE testcases (L2DIAG and WDIAG, section 1) which test the shadow registers. Signed-off-by: Helge Deller [rth: Use decodetree to distinguish cases] Signed-off-by: Richard Henderson Reviewed-by: Helge Deller Tested-by: Helge Deller --- target/hppa/insns.decode | 10 ++++++++++ target/hppa/translate.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 9f6ffd8e2c..71074a64c1 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -65,6 +65,8 @@ # Argument set definitions #### +&empty + # All insns that need to form a virtual address should use this set. &ldst t b x disp sp m scale size @@ -638,6 +640,14 @@ xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64 [ diag_btlb 000101 00 0000 0000 0000 0001 0000 0000 diag_cout 000101 00 0000 0000 0000 0001 0000 0001 + + # For 32-bit PA-7300LC (PCX-L2) + diag_getshadowregs_pa1 000101 00 0000 0000 0001 1010 0000 0000 + diag_putshadowregs_pa1 000101 00 0000 0000 0001 1010 0100 0000 + + # For 64-bit PA8700 (PCX-W2) + diag_getshadowregs_pa2 000101 00 0111 1000 0001 1000 0100 0000 + diag_putshadowregs_pa2 000101 00 0111 0000 0001 1000 0100 0000 ] diag_unimp 000101 i:26 } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 42dd3f2c8d..143818c2d9 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2399,6 +2399,20 @@ static bool do_getshadowregs(DisasContext *ctx) return nullify_end(ctx); } +static bool do_putshadowregs(DisasContext *ctx) +{ + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + tcg_gen_st_i64(cpu_gr[1], tcg_env, offsetof(CPUHPPAState, shadow[0])); + tcg_gen_st_i64(cpu_gr[8], tcg_env, offsetof(CPUHPPAState, shadow[1])); + tcg_gen_st_i64(cpu_gr[9], tcg_env, offsetof(CPUHPPAState, shadow[2])); + tcg_gen_st_i64(cpu_gr[16], tcg_env, offsetof(CPUHPPAState, shadow[3])); + tcg_gen_st_i64(cpu_gr[17], tcg_env, offsetof(CPUHPPAState, shadow[4])); + tcg_gen_st_i64(cpu_gr[24], tcg_env, offsetof(CPUHPPAState, shadow[5])); + tcg_gen_st_i64(cpu_gr[25], tcg_env, offsetof(CPUHPPAState, shadow[6])); + return nullify_end(ctx); +} + static bool trans_getshadowregs(DisasContext *ctx, arg_getshadowregs *a) { return do_getshadowregs(ctx); @@ -4594,6 +4608,26 @@ static bool trans_diag_cout(DisasContext *ctx, arg_diag_cout *a) #endif } +static bool trans_diag_getshadowregs_pa1(DisasContext *ctx, arg_empty *a) +{ + return !ctx->is_pa20 && do_getshadowregs(ctx); +} + +static bool trans_diag_getshadowregs_pa2(DisasContext *ctx, arg_empty *a) +{ + return ctx->is_pa20 && do_getshadowregs(ctx); +} + +static bool trans_diag_putshadowregs_pa1(DisasContext *ctx, arg_empty *a) +{ + return !ctx->is_pa20 && do_putshadowregs(ctx); +} + +static bool trans_diag_putshadowregs_pa2(DisasContext *ctx, arg_empty *a) +{ + return ctx->is_pa20 && do_putshadowregs(ctx); +} + static bool trans_diag_unimp(DisasContext *ctx, arg_diag_unimp *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); From patchwork Fri Mar 29 22:31:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 784100 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp3429326wrt; Fri, 29 Mar 2024 15:33:37 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX78XDlDn3diUyLjU7hWPHgFNttuBSwmaEYCgGBINiu6FLAx7/vtUsPJP4sLxMzB1v7XqW2fQYKR/CpN0lh4Ow7 X-Google-Smtp-Source: AGHT+IFD7izBzYmnT3183tKDWRQnVU0tsQJOCt9VCvC2w4cXXlVajorDqrdgaCCbRHc8ob5DurgK X-Received: by 2002:a05:6214:1101:b0:696:7b17:4428 with SMTP id e1-20020a056214110100b006967b174428mr5372491qvs.29.1711751617102; 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[98.147.7.212]) by smtp.gmail.com with ESMTPSA id f8-20020a170902684800b001e09b636cafsm4000955pln.287.2024.03.29.15.31.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 15:31:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Sven Schnelle , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 18/18] target/hppa: Clear psw_n for BE on use_nullify_skip path Date: Fri, 29 Mar 2024 12:31:11 -1000 Message-Id: <20240329223111.1735826-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org> References: <20240329223111.1735826-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Along this path we have already skipped the insn to be nullified, so the subsequent insn should be executed. Cc: qemu-stable@nongnu.org Reported-by: Sven Schnelle Tested-by: Sven Schnelle Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 143818c2d9..8a1a8bc3aa 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3948,6 +3948,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp); tcg_gen_mov_i64(cpu_iasq_f, new_spc); tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f); + nullify_set(ctx, 0); } else { copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); if (ctx->iaoq_b == -1) {