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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id y13-20020a5d4acd000000b00341e5f487casm2292237wrs.46.2024.03.28.10.59.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 10:59:40 -0700 (PDT) From: Caleb Connolly Date: Thu, 28 Mar 2024 17:59:07 +0000 Subject: [PATCH v5 01/16] mailmap: update Bhupesh's email address MIME-Version: 1.0 Message-Id: <20240328-b4-qcom-livetree-v5-1-4e98228b3d03@linaro.org> References: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> In-Reply-To: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> To: Tom Rini , Caleb Connolly , Neil Armstrong , Sumit Garg , Lukasz Majewski , Sean Anderson Cc: u-boot@lists.denx.de, Bhupesh Sharma X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1165; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=XSvtB4NoCXg6pY1Nq/qGGGjasqOo57hNo8/eyKot594=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjTWDZwVuV3iRkfyjmqdt4lZb3mw5PdFmQB+N+59v63Zd kXXLzrVUcLCIMjBICumyCJ+Ypll09rL9hrbF1yAmcPKBDKEgYtTACZyWZbhe5RP8ew1yWLz1CS/ 3Ej7cKPu5aKDoUXLk136LVg0dibNZ/jDefM8/9/19x+xzrf8Ifm76tQb26O3Q2wUeG5dmPTv3n8 eBgA= X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Update Bhupesh's email to his new one. Reviewed-by: Neil Armstrong Signed-off-by: Caleb Connolly --- Cc: Bhupesh Sharma --- .mailmap | 1 + 1 file changed, 1 insertion(+) diff --git a/.mailmap b/.mailmap index d1f08f3eca8a..f6e0847b2168 100644 --- a/.mailmap +++ b/.mailmap @@ -29,8 +29,9 @@ Ashok Reddy Soma Atish Patra Bharat Kumar Gogada Bharat Kumar Gogada Bhargava Sreekantappa Gayathri +Bhupesh Sharma Bin Meng Boris Brezillon Boris Brezillon Christian Kohn From patchwork Thu Mar 28 17:59:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 783620 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp2859816wrt; Thu, 28 Mar 2024 11:00:17 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVj7l2UTJ0fGP459RyHTVHDaGEsAkimbsJqMY5ksem83qvc1fknfYqKXlvqSV3R3eqW4oJTogszVt5k/gVaj2Ep X-Google-Smtp-Source: AGHT+IFts5esWhGvTVurEU9z/w+MkHmDrr2NxCfJ3QA3CEoOPfDe8+RAPZnOn5KT9/QZ6TuMFnVY X-Received: by 2002:a5d:5343:0:b0:343:3034:7450 with SMTP id t3-20020a5d5343000000b0034330347450mr1889375wrv.69.1711648817663; Thu, 28 Mar 2024 11:00:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711648817; cv=none; d=google.com; s=arc-20160816; b=GwFY84SGxJlmDRzq/+dadJhkHqMeEuzgrAq5JWNL/GXHkNa8JND0TYFv983fGgGGCx 24T0F+iQAhV0PKi12dCVBH07riunzwD/V/fmsvAlF33WLurPgvHEKrB/5t6Wk/zTT9ZW igH+99npy/K/pQkH1b3QZvm2ubGcVbYGJgk5lYqP1zjLqMMaVvYPFwpbIHtwdUc7wFjx W2TNznB9ryU7Tz7Jl1dF2WW6zco98rukbqmPRdR4B9AxbggZngNuXKxOZUcwIK1qjKx6 5Y0Gr8QckkNxAlfTHo4mrPKRj06J2vNCJ3HW6u0H2mVV0KyYif2LcRKTwQijzTG8Tvkz pKww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=qGCzmrgWjVnXvlc1whxMVXz7swp/454mksJv05SdVXA=; fh=IUJzsJXR8tzOhtgP/Qm7FzQrRAC2ZStJPTaXNXY0swo=; b=U06w7JjcbVXCDeCr8AJiQ37IsdoTZiP4qsDgg0YJjrWTQHSdDC8TMZoRHsiOe8v12w zize+85btfj6+IQIS18TxhbokSBChatcFpC8OU5sxLjhOCiSVW5N2juC4aJaK0akUyao e9mSgO8AvKORGY7enMMzQVGnqpI/uHtsGvEApaTtxkZAu1GvtXFRYA5FOaWbwfYx15+L Gtsce/Zk9TfW8irpYiZK/zlWBl9Xj8A0tDtyce9xBVuaqOBZGtiAob5avC5OLfnqe0DL mjaE+EmOjNHe7XrDed+Uat2N2fA1P3yql8o7B3tgZqQLyXW4R4sTH4e7xzRuLw2scH5M EYpA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JZynXO6H; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id y13-20020a5d4acd000000b00341e5f487casm2292237wrs.46.2024.03.28.10.59.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 10:59:41 -0700 (PDT) From: Caleb Connolly Date: Thu, 28 Mar 2024 17:59:08 +0000 Subject: [PATCH v5 02/16] phy: qcom: add Qualcomm QUSB2 USB PHY driver MIME-Version: 1.0 Message-Id: <20240328-b4-qcom-livetree-v5-2-4e98228b3d03@linaro.org> References: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> In-Reply-To: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> To: Tom Rini , Caleb Connolly , Neil Armstrong , Sumit Garg , Lukasz Majewski , Sean Anderson Cc: u-boot@lists.denx.de, Bhupesh Sharma , Bhupesh Sharma X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=14054; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=6QjRXDEkft3TbS/fnHGbZFP6XtjSFfL2oVzjVoOE44A=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjTWDZxn9rqytdXk7ZD9cWir6JvGY0cuyWuWOgdni0o7M lTdTC3qKGVhEORgkBVTZBE/scyyae1le43tCy7AzGFlAhnCwMUpABPZMZXhf0ljo+MvSd1U9Vzb /28yinv1ShY9MbiyeOOF7XeT8jboZDP8j48s5bgxP37lK4FbKfu+bpwqOEM4qN6f9Zyq/66bLSt TuwE= X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Bhupesh Sharma The Snapdragon 845 and several other Qualcomm SoCs feature this USB high-speed phy. Add a driver for it based on the Linux driver, with support for the SDM845, and the QCM2290 and SM6115 SoCs which will gain support in U-Boot in future patches. Signed-off-by: Bhupesh Sharma [code cleanup, switch to clk_bulk] Signed-off-by: Caleb Connolly Acked-by: Sumit Garg --- drivers/phy/qcom/Kconfig | 7 + drivers/phy/qcom/Makefile | 1 + drivers/phy/qcom/phy-qcom-qusb2.c | 429 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 437 insertions(+) diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index f4ca174805a4..361dfb6e1126 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -11,8 +11,15 @@ config PHY_QCOM_IPQ4019_USB depends on PHY && ARCH_IPQ40XX help Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. +config PHY_QCOM_QUSB2 + tristate "Qualcomm USB QUSB2 PHY driver" + depends on PHY && ARCH_SNAPDRAGON + help + Enable this to support the Super-Speed USB transceiver on various + Qualcomm chipsets. + config PHY_QCOM_USB_HS_28NM tristate "Qualcomm 28nm High-Speed PHY" depends on PHY && ARCH_SNAPDRAGON help diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile index 2113f178c0c7..f6af985666a4 100644 --- a/drivers/phy/qcom/Makefile +++ b/drivers/phy/qcom/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o +obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c b/drivers/phy/qcom/phy-qcom-qusb2.c new file mode 100644 index 000000000000..c91ba18c4ab1 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qusb2.c @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Bhupesh Sharma + * + * Based on Linux driver + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define QUSB2PHY_PLL 0x0 +#define QUSB2PHY_PLL_TEST 0x04 +#define CLK_REF_SEL BIT(7) + +#define QUSB2PHY_PLL_TUNE 0x08 +#define QUSB2PHY_PLL_USER_CTL1 0x0c +#define QUSB2PHY_PLL_USER_CTL2 0x10 +#define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c +#define QUSB2PHY_PLL_PWR_CTRL 0x18 + +/* QUSB2PHY_PLL_STATUS register bits */ +#define PLL_LOCKED BIT(5) + +/* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */ +#define CORE_READY_STATUS BIT(0) + +/* QUSB2PHY_PORT_POWERDOWN register bits */ +#define CLAMP_N_EN BIT(5) +#define FREEZIO_N BIT(1) +#define POWER_DOWN BIT(0) + +/* QUSB2PHY_PWR_CTRL1 register bits */ +#define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5) +#define PWR_CTRL1_CLAMP_N_EN BIT(1) + +#define QUSB2PHY_REFCLK_ENABLE BIT(0) + +#define PHY_CLK_SCHEME_SEL BIT(0) + +/* QUSB2PHY_INTR_CTRL register bits */ +#define DMSE_INTR_HIGH_SEL BIT(4) +#define DPSE_INTR_HIGH_SEL BIT(3) +#define CHG_DET_INTR_EN BIT(2) +#define DMSE_INTR_EN BIT(1) +#define DPSE_INTR_EN BIT(0) + +/* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */ +#define CORE_PLL_EN_FROM_RESET BIT(4) +#define CORE_RESET BIT(5) +#define CORE_RESET_MUX BIT(6) + +/* QUSB2PHY_IMP_CTRL1 register bits */ +#define IMP_RES_OFFSET_MASK GENMASK(5, 0) +#define IMP_RES_OFFSET_SHIFT 0x0 + +/* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */ +#define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0) +#define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0 + +/* QUSB2PHY_CHG_CONTROL_2 register bits */ +#define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4) +#define CHG_CTRL2_OFFSET_SHIFT 0x4 + +/* QUSB2PHY_PORT_TUNE1 register bits */ +#define HSTX_TRIM_MASK GENMASK(7, 4) +#define HSTX_TRIM_SHIFT 0x4 +#define PREEMPH_WIDTH_HALF_BIT BIT(2) +#define PREEMPHASIS_EN_MASK GENMASK(1, 0) +#define PREEMPHASIS_EN_SHIFT 0x0 + +/* QUSB2PHY_PORT_TUNE2 register bits */ +#define HSDISC_TRIM_MASK GENMASK(1, 0) +#define HSDISC_TRIM_SHIFT 0x0 + +#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04 +#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c +#define QUSB2PHY_PLL_CMODE 0x2c +#define QUSB2PHY_PLL_LOCK_DELAY 0x184 +#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4 +#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194 +#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198 +#define QUSB2PHY_PWR_CTRL2 0x214 +#define QUSB2PHY_IMP_CTRL1 0x220 +#define QUSB2PHY_IMP_CTRL2 0x224 +#define QUSB2PHY_CHG_CTRL2 0x23c + +struct qusb2_phy_init_tbl { + unsigned int offset; + unsigned int val; + /* + * register part of layout ? + * if yes, then offset gives index in the reg-layout + */ + int in_layout; +}; + +struct qusb2_phy_cfg { + const struct qusb2_phy_init_tbl *tbl; + /* number of entries in the table */ + unsigned int tbl_num; + /* offset to PHY_CLK_SCHEME register in TCSR map */ + unsigned int clk_scheme_offset; + + /* array of registers with different offsets */ + const unsigned int *regs; + unsigned int mask_core_ready; + unsigned int disable_ctrl; + unsigned int autoresume_en; + + /* true if PHY has PLL_TEST register to select clk_scheme */ + bool has_pll_test; + + /* true if TUNE1 register must be updated by fused value, else TUNE2 */ + bool update_tune1_with_efuse; + + /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */ + bool has_pll_override; +}; + +/* set of registers with offsets different per-PHY */ +enum qusb2phy_reg_layout { + QUSB2PHY_PLL_CORE_INPUT_OVERRIDE, + QUSB2PHY_PLL_STATUS, + QUSB2PHY_PORT_TUNE1, + QUSB2PHY_PORT_TUNE2, + QUSB2PHY_PORT_TUNE3, + QUSB2PHY_PORT_TUNE4, + QUSB2PHY_PORT_TUNE5, + QUSB2PHY_PORT_TEST1, + QUSB2PHY_PORT_TEST2, + QUSB2PHY_PORT_POWERDOWN, + QUSB2PHY_INTR_CTRL, +}; + +#define QUSB2_PHY_INIT_CFG(o, v) \ + { \ + .offset = o, .val = v, \ + } + +#define QUSB2_PHY_INIT_CFG_L(o, v) \ + { \ + .offset = o, .val = v, .in_layout = 1, \ + } + +static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = { + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x81), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x17), + + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), + + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), + + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), +}; + +static const unsigned int sm6115_regs_layout[] = { + [QUSB2PHY_PLL_STATUS] = 0x38, [QUSB2PHY_PORT_TUNE1] = 0x80, + [QUSB2PHY_PORT_TUNE2] = 0x84, [QUSB2PHY_PORT_TUNE3] = 0x88, + [QUSB2PHY_PORT_TUNE4] = 0x8c, [QUSB2PHY_PORT_TUNE5] = 0x90, + [QUSB2PHY_PORT_TEST1] = 0xb8, [QUSB2PHY_PORT_TEST2] = 0x9c, + [QUSB2PHY_PORT_POWERDOWN] = 0xb4, [QUSB2PHY_INTR_CTRL] = 0xbc, +}; + +static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = { + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21), + QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0), + QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58), + + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03), + + QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0), +}; + +static const unsigned int qusb2_v2_regs_layout[] = { + [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8, + [QUSB2PHY_PLL_STATUS] = 0x1a0, + [QUSB2PHY_PORT_TUNE1] = 0x240, + [QUSB2PHY_PORT_TUNE2] = 0x244, + [QUSB2PHY_PORT_TUNE3] = 0x248, + [QUSB2PHY_PORT_TUNE4] = 0x24c, + [QUSB2PHY_PORT_TUNE5] = 0x250, + [QUSB2PHY_PORT_TEST1] = 0x254, + [QUSB2PHY_PORT_TEST2] = 0x258, + [QUSB2PHY_PORT_POWERDOWN] = 0x210, + [QUSB2PHY_INTR_CTRL] = 0x230, +}; + +static const struct qusb2_phy_cfg sm6115_phy_cfg = { + .tbl = sm6115_init_tbl, + .tbl_num = ARRAY_SIZE(sm6115_init_tbl), + .regs = sm6115_regs_layout, + + .has_pll_test = true, + .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), + .mask_core_ready = PLL_LOCKED, + .autoresume_en = BIT(3), +}; + +static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = { + .tbl = qusb2_v2_init_tbl, + .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl), + .regs = qusb2_v2_regs_layout, + + .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN | + POWER_DOWN), + .mask_core_ready = CORE_READY_STATUS, + .has_pll_override = true, + .autoresume_en = BIT(0), + .update_tune1_with_efuse = true, +}; + +/** + * struct qusb2_phy - structure holding qusb2 phy attributes + * + * @phy: generic phy + * @base: iomapped memory space for qubs2 phy + * + * @cfg_ahb_clk: AHB2PHY interface clock + * @phy_rst: phy reset control + * + * @cfg: phy config data + * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme + */ +struct qusb2_phy { + struct phy *phy; + void __iomem *base; + + struct clk cfg_ahb_clk; + struct reset_ctl phy_rst; + + const struct qusb2_phy_cfg *cfg; + bool has_se_clk_scheme; +}; + +static inline void qusb2_phy_configure(void __iomem *base, + const unsigned int *regs, + const struct qusb2_phy_init_tbl tbl[], + int num) +{ + int i; + + for (i = 0; i < num; i++) { + if (tbl[i].in_layout) + writel(tbl[i].val, base + regs[tbl[i].offset]); + else + writel(tbl[i].val, base + tbl[i].offset); + } +} + +static int qusb2phy_do_reset(struct qusb2_phy *qphy) +{ + int ret; + + ret = reset_assert(&qphy->phy_rst); + if (ret) + return ret; + + udelay(500); + + ret = reset_deassert(&qphy->phy_rst); + if (ret) + return ret; + + return 0; +} + +static int qusb2phy_power_on(struct phy *phy) +{ + struct qusb2_phy *qphy = dev_get_priv(phy->dev); + const struct qusb2_phy_cfg *cfg = qphy->cfg; + int ret; + u32 val; + + ret = qusb2phy_do_reset(qphy); + if (ret) + return ret; + + /* Disable the PHY */ + setbits_le32(qphy->base + cfg->regs[QUSB2PHY_PORT_POWERDOWN], + qphy->cfg->disable_ctrl); + + if (cfg->has_pll_test) { + /* save reset value to override reference clock scheme later */ + val = readl(qphy->base + QUSB2PHY_PLL_TEST); + } + + qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, cfg->tbl_num); + + /* Enable the PHY */ + clrbits_le32(qphy->base + cfg->regs[QUSB2PHY_PORT_POWERDOWN], + POWER_DOWN); + + /* Required to get phy pll lock successfully */ + udelay(150); + + if (cfg->has_pll_test) { + val |= CLK_REF_SEL; + + writel(val, qphy->base + QUSB2PHY_PLL_TEST); + + /* ensure above write is through */ + readl(qphy->base + QUSB2PHY_PLL_TEST); + } + + /* Required to get phy pll lock successfully */ + udelay(100); + + val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); + if (!(val & cfg->mask_core_ready)) { + pr_err("QUSB2PHY pll lock failed: status reg = %x\n", val); + ret = -EBUSY; + return ret; + } + + return 0; +} + +static int qusb2phy_power_off(struct phy *phy) +{ + struct qusb2_phy *qphy = dev_get_priv(phy->dev); + + /* Disable the PHY */ + setbits_le32(qphy->base + qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], + qphy->cfg->disable_ctrl); + + reset_assert(&qphy->phy_rst); + + clk_disable(&qphy->cfg_ahb_clk); + + return 0; +} + +static int qusb2phy_clk_init(struct udevice *dev, struct qusb2_phy *qphy) +{ + int ret; + + /* We ignore the ref clock as we currently lack a driver for rpmcc/rpmhcc where + * it usually comes from - we assume it's always on. + */ + ret = clk_get_by_name(dev, "cfg_ahb", &qphy->cfg_ahb_clk); + if (ret == -ENOSYS || ret == -ENOENT) + return 0; + if (ret) + return ret; + + ret = clk_enable(&qphy->cfg_ahb_clk); + if (ret) + return ret; + + return 0; +} + +static int qusb2phy_probe(struct udevice *dev) +{ + struct qusb2_phy *qphy = dev_get_priv(dev); + int ret; + + qphy->base = (void __iomem *)dev_read_addr(dev); + if (IS_ERR(qphy->base)) + return PTR_ERR(qphy->base); + + ret = qusb2phy_clk_init(dev, qphy); + if (ret) { + printf("%s: Couldn't get clocks: %d\n", __func__, ret); + return ret; + } + + ret = reset_get_by_index(dev, 0, &qphy->phy_rst); + if (ret) { + printf("%s: Couldn't get resets: %d\n", __func__, ret); + return ret; + } + + qphy->cfg = (const struct qusb2_phy_cfg *)dev_get_driver_data(dev); + if (!qphy->cfg) { + printf("%s: Couldn't get driver data\n", __func__); + return -EINVAL; + } + + debug("%s success qusb phy cfg %p\n", __func__, qphy->cfg); + return 0; +} + +static struct phy_ops qusb2phy_ops = { + .power_on = qusb2phy_power_on, + .power_off = qusb2phy_power_off, +}; + +static const struct udevice_id qusb2phy_ids[] = { + { .compatible = "qcom,qusb2-phy" }, + { .compatible = "qcom,qcm2290-qusb2-phy", + .data = (ulong)&sm6115_phy_cfg }, + { .compatible = "qcom,sm6115-qusb2-phy", + .data = (ulong)&sm6115_phy_cfg }, + { .compatible = "qcom,qusb2-v2-phy", .data = (ulong)&qusb2_v2_phy_cfg }, + {} +}; + +U_BOOT_DRIVER(qcom_qusb2_phy) = { + .name = "qcom-qusb2-phy", + .id = UCLASS_PHY, + .of_match = qusb2phy_ids, + .ops = &qusb2phy_ops, + .probe = qusb2phy_probe, + .priv_auto = sizeof(struct qusb2_phy), +}; From patchwork Thu Mar 28 17:59:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 783621 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp2859932wrt; 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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id y13-20020a5d4acd000000b00341e5f487casm2292237wrs.46.2024.03.28.10.59.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 10:59:42 -0700 (PDT) From: Caleb Connolly Date: Thu, 28 Mar 2024 17:59:09 +0000 Subject: [PATCH v5 03/16] phy: qcom: Add SNPS femto v2 USB HS phy MIME-Version: 1.0 Message-Id: <20240328-b4-qcom-livetree-v5-3-4e98228b3d03@linaro.org> References: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> In-Reply-To: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> To: Tom Rini , Caleb Connolly , Neil Armstrong , Sumit Garg , Lukasz Majewski , Sean Anderson Cc: u-boot@lists.denx.de, Bhupesh Sharma , Bhupesh Sharma X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=7987; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=O8MgnNvz8xNo/VZuwsqphFm+cOIRbPwCtp7k6WZHsHY=; b=kA0DAAgReTBFn7kwMhcByyZiAGYFsAmjPbDRkhIY1njrWDe4f6yOSYoeuX6Vmf1Z1PwTE3ej0 Yh1BAARCAAdFiEEF8imOYKt0z8ot6DQeTBFn7kwMhcFAmYFsAkACgkQeTBFn7kwMhdNAAD+NVmY MhPzE/Rk81IzC+NPp5XXecSTdQigJ2Sa0WmamhMA/RbGU96p8JYsWOGf5D59vHrjw+knSk0SR9C sdcpcSMO2 X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Bhupesh Sharma Some Qualcomm SoCs newer than SDM845 feature a so-called "7nm phy" driver, notable the SM8250 SoC which will gain U-Boot support in upcoming patches. Introduce a driver based on the Linux driver. Signed-off-by: Bhupesh Sharma [code cleanup, align symbol names with Linux, switch to clk/reset_bulk APIs] Signed-off-by: Caleb Connolly Acked-by: Sumit Garg --- drivers/phy/qcom/Kconfig | 8 ++ drivers/phy/qcom/Makefile | 1 + drivers/phy/qcom/phy-qcom-snps-femto-v2.c | 207 ++++++++++++++++++++++++++++++ 3 files changed, 216 insertions(+) diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index 361dfb6e1126..b9fe608c2798 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -18,8 +18,16 @@ config PHY_QCOM_QUSB2 help Enable this to support the Super-Speed USB transceiver on various Qualcomm chipsets. +config PHY_QCOM_USB_SNPS_FEMTO_V2 + tristate "Qualcomm SNPS FEMTO USB HS PHY v2" + depends on PHY && ARCH_SNAPDRAGON + help + Enable this to support the Qualcomm Synopsys DesignWare Core 7nm + High-Speed PHY driver. This driver supports the Hi-Speed PHY which + is usually paired with Synopsys DWC3 USB IPs on MSM SOCs. + config PHY_QCOM_USB_HS_28NM tristate "Qualcomm 28nm High-Speed PHY" depends on PHY && ARCH_SNAPDRAGON help diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile index f6af985666a4..5f4db4a53788 100644 --- a/drivers/phy/qcom/Makefile +++ b/drivers/phy/qcom/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o +obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2) += phy-qcom-snps-femto-v2.o obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qcom/phy-qcom-snps-femto-v2.c b/drivers/phy/qcom/phy-qcom-snps-femto-v2.c new file mode 100644 index 000000000000..58eb01972402 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-snps-femto-v2.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (C) 2023 Bhupesh Sharma + * + * Based on Linux driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c) +#define SLEEPM BIT(0) +#define OPMODE_MASK GENMASK(4, 3) +#define OPMODE_NORMAL (0x00) +#define OPMODE_NONDRIVING BIT(3) +#define TERMSEL BIT(5) + +#define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50) +#define POR BIT(1) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) +#define SIDDQ BIT(2) +#define RETENABLEN BIT(3) +#define FSEL_MASK GENMASK(6, 4) +#define FSEL_DEFAULT (0x3 << 4) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58) +#define VBUSVLDEXTSEL0 BIT(4) +#define PLLBTUNE BIT(5) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c) +#define VREGBYPASS BIT(0) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60) +#define VBUSVLDEXT0 BIT(0) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64) +#define USB2_AUTO_RESUME BIT(0) +#define USB2_SUSPEND_N BIT(2) +#define USB2_SUSPEND_N_SEL BIT(3) + +#define USB2_PHY_USB_PHY_CFG0 (0x94) +#define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0) +#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1) + +#define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0) +#define REFCLK_SEL_MASK GENMASK(1, 0) +#define REFCLK_SEL_DEFAULT (0x2 << 0) + +struct qcom_snps_hsphy { + void __iomem *base; + struct clk_bulk clks; + struct reset_ctl_bulk resets; +}; + +static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset, + u32 mask, u32 val) +{ + u32 reg; + + reg = readl_relaxed(base + offset); + + reg &= ~mask; + reg |= val & mask; + writel_relaxed(reg, base + offset); + + /* Ensure above write is completed */ + readl_relaxed(base + offset); +} + +static int qcom_snps_hsphy_usb_init(struct phy *phy) +{ + struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_CFG0, + UTMI_PHY_CMN_CTRL_OVERRIDE_EN, + UTMI_PHY_CMN_CTRL_OVERRIDE_EN); + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_UTMI_CTRL5, POR, + POR); + qcom_snps_hsphy_write_mask(priv->base, + USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, FSEL_MASK, 0); + qcom_snps_hsphy_write_mask(priv->base, + USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, + PLLBTUNE, PLLBTUNE); + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_REFCLK_CTRL, + REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK); + qcom_snps_hsphy_write_mask(priv->base, + USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, + VBUSVLDEXTSEL0, VBUSVLDEXTSEL0); + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1, + VBUSVLDEXT0, VBUSVLDEXT0); + + qcom_snps_hsphy_write_mask(priv->base, + USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, + VREGBYPASS, VREGBYPASS); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_UTMI_CTRL0, + SLEEPM, SLEEPM); + + qcom_snps_hsphy_write_mask( + priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ, 0); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_UTMI_CTRL5, POR, + 0); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL, 0); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_CFG0, + UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0); + + return 0; +} + +static int qcom_snps_hsphy_power_on(struct phy *phy) +{ + struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev); + int ret; + + clk_enable_bulk(&priv->clks); + + ret = reset_deassert_bulk(&priv->resets); + if (ret) + return ret; + + ret = qcom_snps_hsphy_usb_init(phy); + if (ret) + return ret; + + return 0; +} + +static int qcom_snps_hsphy_power_off(struct phy *phy) +{ + struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev); + + reset_assert_bulk(&priv->resets); + clk_disable_bulk(&priv->clks); + + return 0; +} + +static int qcom_snps_hsphy_phy_probe(struct udevice *dev) +{ + struct qcom_snps_hsphy *priv = dev_get_priv(dev); + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + ret = clk_get_bulk(dev, &priv->clks); + if (ret < 0 && ret != -ENOENT) { + printf("%s: Failed to get clocks %d\n", __func__, ret); + return ret; + } + + ret = reset_get_bulk(dev, &priv->resets); + if (ret < 0) { + printf("failed to get resets, ret = %d\n", ret); + return ret; + } + + clk_enable_bulk(&priv->clks); + reset_deassert_bulk(&priv->resets); + + return 0; +} + +static struct phy_ops qcom_snps_hsphy_phy_ops = { + .power_on = qcom_snps_hsphy_power_on, + .power_off = qcom_snps_hsphy_power_off, +}; + +static const struct udevice_id qcom_snps_hsphy_phy_ids[] = { + { .compatible = "qcom,sm8150-usb-hs-phy" }, + { .compatible = "qcom,usb-snps-hs-5nm-phy" }, + { .compatible = "qcom,usb-snps-hs-7nm-phy" }, + { .compatible = "qcom,usb-snps-femto-v2-phy" }, + {} +}; + +U_BOOT_DRIVER(qcom_usb_qcom_snps_hsphy) = { + .name = "qcom-snps-hsphy", + .id = UCLASS_PHY, + .of_match = qcom_snps_hsphy_phy_ids, + .ops = &qcom_snps_hsphy_phy_ops, + .probe = qcom_snps_hsphy_phy_probe, + .priv_auto = sizeof(struct qcom_snps_hsphy), +}; From patchwork Thu Mar 28 17:59:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 783622 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp2860043wrt; Thu, 28 Mar 2024 11:00:40 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX5qdeLJ/JGLsGZ58BQWLh35y5cZGj5DwCy423HH/Wy3KlHBS5k9poNReS9zaN7nEI4kMjul+bJ3O2fLN2alNqF X-Google-Smtp-Source: AGHT+IETwzlcb6Rw3C5YcKfns+jLJFCwpmDDTO2rVkCiMk01PYYajTduGn6AYdVp9Gy/ZTU2pyl0 X-Received: by 2002:a5d:53c9:0:b0:33e:4238:8615 with SMTP id a9-20020a5d53c9000000b0033e42388615mr2636003wrw.40.1711648840236; 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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id y13-20020a5d4acd000000b00341e5f487casm2292237wrs.46.2024.03.28.10.59.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 10:59:44 -0700 (PDT) From: Caleb Connolly Date: Thu, 28 Mar 2024 17:59:10 +0000 Subject: [PATCH v5 04/16] mach-snapdragon: disable power-domains for pre-reloc drivers MIME-Version: 1.0 Message-Id: <20240328-b4-qcom-livetree-v5-4-4e98228b3d03@linaro.org> References: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> In-Reply-To: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> To: Tom Rini , Caleb Connolly , Neil Armstrong , Sumit Garg , Lukasz Majewski , Sean Anderson Cc: u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2212; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=lNaop02wGgSTfoA1P61dU8gqi6TppeaoShUOEotMpkk=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjTWDZz9UbUzGK9YZ0+Z+E0ygsnn0sZbX4/yHWE74C8S/ eTcqgS5jlIWBkEOBlkxRRbxE8ssm9ZettfYvuACzBxWJpAhDFycAjCRpBaGf/ZvKqMZhJM+ijtF TIvWW6egpFO7wm+rFKP/lf8C6ZX/7jAyLLzM/dRJKvDmiV26ZYmz9WMWvJQKigmeq7Omzeiey0u T3QA= X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-qcom.c | 2 ++ drivers/clk/qcom/clock-sdm845.c | 2 +- drivers/serial/serial_msm_geni.c | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 7a5938a06a34..6303dcbf8461 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -226,8 +226,9 @@ U_BOOT_DRIVER(qcom_clk) = { .id = UCLASS_CLK, .ops = &msm_clk_ops, .priv_auto = sizeof(struct msm_clk_priv), .probe = msm_clk_probe, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, }; int qcom_cc_bind(struct udevice *parent) { @@ -410,5 +411,6 @@ U_BOOT_DRIVER(qcom_power) = { .name = "qcom_power", .id = UCLASS_POWER_DOMAIN, .ops = &qcom_power_ops, .probe = qcom_power_probe, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index 36ffee79d966..babd83119e2c 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -182,6 +182,6 @@ U_BOOT_DRIVER(gcc_sdm845) = { .name = "gcc_sdm845", .id = UCLASS_NOP, .of_match = gcc_sdm845_of_match, .bind = qcom_cc_bind, - .flags = DM_FLAG_PRE_RELOC, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, }; diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index e5c3dcffc1c6..4aa0bc8c72bc 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -602,9 +602,9 @@ U_BOOT_DRIVER(serial_msm_geni) = { .of_to_plat = msm_serial_ofdata_to_platdata, .priv_auto = sizeof(struct msm_serial_data), .probe = msm_serial_probe, .ops = &msm_serial_ops, - .flags = DM_FLAG_PRE_RELOC, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, }; #ifdef CONFIG_DEBUG_UART_MSM_GENI From patchwork Thu Mar 28 17:59:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 783623 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp2860166wrt; Thu, 28 Mar 2024 11:00:52 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXE01NXitBVpjwhPmJUSFUoZGoDWW2JaOpH/qJBptIanOZQwWNfS7K9mx6lEanVjhYFhvuqLghVvlZyTVBXtq+i X-Google-Smtp-Source: AGHT+IGErNuzcXJzK6TcdQ8k2BZhsnUiGgXvKq8au+SV27NNB0cgwlT9vORR6tm5DEMtSCPUkFr+ X-Received: by 2002:a5d:624b:0:b0:33e:d1fa:6627 with SMTP id m11-20020a5d624b000000b0033ed1fa6627mr2531578wrv.50.1711648852229; Thu, 28 Mar 2024 11:00:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711648852; cv=none; d=google.com; s=arc-20160816; b=PUOxlq1+xf9Z9oHFMKF3o7thApiWERgy1rc101qP4Pkm5RiF6fyAIGzVQF0OpZV3/X IGnkGvNSafw0LbU2Wwzwtj8bHXSj2gwv+IpQCEh87yLl3L2TuKbCA7QCqWjKT95g3jq9 d760J9dkmkyJ4VQmn8sd6Zvp6j9L8bmZlCWMjTKVrbtBmvqY1n3f6tEsNTk51b3TSiyV 9hkCRaRmIWJjr7k3CRuXjf+mkgtFArVjI/c4h14XHYGClzmks/5OA86fG8lUY60pE4av OOQd1OGPu9exTFJdnI2rmqk4pK2eF09Qvs0X/egyw0E0gJp0WLBZyThahaTrWI5fA3iZ 9MUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=juaadawQi5dtqVZYnJ+QwO1/OAexPncDaRDXhesSnrw=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=g6C5KvTcf1yjhh5n6EjRib6vInM7g41eXEMaCj7BZ9yCfXY9vmmz1dnbI/0JcOKO9I U6A1acGKXb5BaFp6qNsGu5fKYto0GeekzOh00VqKDVw1Uu6TzbqCjO84XG9XJJMFURsa s7tHTgqIxvzXqjh9W0w5Gp6qgJuX55yl8769PRp179LkQIiK1qARPNdusX8QRpZDIQDN n8Ze+QACGTVlDiWX3X3z/n3kC8uLLEMqStHNHoMeUrr7Ziz2SWR2xQBipGS/x6B4TnB4 ep27MTtZGNOm6uTeeUZencta1VL4+P75vWGN95ofhpwFlhL+CyTLLKX42bIQZLVdqoNA nQtw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NYjUAWIo; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id y13-20020a5d4acd000000b00341e5f487casm2292237wrs.46.2024.03.28.10.59.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 10:59:45 -0700 (PDT) From: Caleb Connolly Date: Thu, 28 Mar 2024 17:59:11 +0000 Subject: [PATCH v5 05/16] clk/qcom: use offsets for RCG registers MIME-Version: 1.0 Message-Id: <20240328-b4-qcom-livetree-v5-5-4e98228b3d03@linaro.org> References: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> In-Reply-To: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> To: Tom Rini , Caleb Connolly , Neil Armstrong , Sumit Garg , Lukasz Majewski , Sean Anderson Cc: u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=21534; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=eOFtlhU96dqlEnXPalbLBCT2nnod4qFsAzqcv/bfsS4=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjTWDZyJPySvtOzJnvjz3KVfpj8KP2+c2D3xNVMDT/DUi 18Cfu7Q6ShlYRDkYJAVU2QRP7HMsmntZXuN7QsuwMxhZQIZwsDFKQAT+eLLyLClV2mf6wvOHcuP LJGM65nxbJ/99KliuX/Y92+Ovra/5+13hv/pRm9Ordk7mVXleRGDotP8xKuCjGdVXp4VEF0dFl4 Xcl0VAA== X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-apq8016.c | 39 +------------ drivers/clk/qcom/clock-apq8096.c | 28 +-------- drivers/clk/qcom/clock-qcom.c | 22 +++---- drivers/clk/qcom/clock-qcom.h | 16 +++-- drivers/clk/qcom/clock-qcs404.c | 122 +++++---------------------------------- drivers/clk/qcom/clock-sdm845.c | 16 +---- 6 files changed, 39 insertions(+), 204 deletions(-) diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index e6647f7c41dd..5a5868169c89 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -22,13 +22,9 @@ #define APCS_GPLL_ENA_VOTE (0x45000) #define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) #define SDCC_BCR(n) ((n * 0x1000) + 0x41000) -#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004) -#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008) -#define SDCC_M(n) ((n * 0x1000) + 0x4100C) -#define SDCC_N(n) ((n * 0x1000) + 0x41010) -#define SDCC_D(n) ((n * 0x1000) + 0x41014) +#define SDCC_CMD_RCGR(n) (((n + 1) * 0x1000) + 0x41004) #define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018) #define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C) /* BLSP1 AHB clock (root clock for BLSP) */ @@ -37,33 +33,12 @@ /* Uart clock control registers */ #define BLSP1_UART2_BCR (0x3028) #define BLSP1_UART2_APPS_CBCR (0x302C) #define BLSP1_UART2_APPS_CMD_RCGR (0x3034) -#define BLSP1_UART2_APPS_CFG_RCGR (0x3038) -#define BLSP1_UART2_APPS_M (0x303C) -#define BLSP1_UART2_APPS_N (0x3040) -#define BLSP1_UART2_APPS_D (0x3044) /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(17) -static const struct bcr_regs sdc_regs[] = { - { - .cfg_rcgr = SDCC_CFG_RCGR(1), - .cmd_rcgr = SDCC_CMD_RCGR(1), - .M = SDCC_M(1), - .N = SDCC_N(1), - .D = SDCC_D(1), - }, - { - .cfg_rcgr = SDCC_CFG_RCGR(2), - .cmd_rcgr = SDCC_CMD_RCGR(2), - .M = SDCC_M(2), - .N = SDCC_N(2), - .D = SDCC_D(2), - } -}; - static struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, .ena_vote = APCS_GPLL_ENA_VOTE, @@ -85,32 +60,24 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) div = 4; clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot)); /* 800Mhz/div, gpll0 */ - clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0, + clk_rcg_set_rate_mnd(priv->base, SDCC_CMD_RCGR(slot), div, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot)); return rate; } -static const struct bcr_regs uart2_regs = { - .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR, - .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR, - .M = BLSP1_UART2_APPS_M, - .N = BLSP1_UART2_APPS_N, - .D = BLSP1_UART2_APPS_D, -}; - /* UART: 115200 */ int apq8016_clk_init_uart(phys_addr_t base) { /* Enable AHB clock */ clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk); /* 7372800 uart block clock @ GPLL0 */ - clk_rcg_set_rate_mnd(base, &uart2_regs, 1, 144, 15625, + clk_rcg_set_rate_mnd(base, BLSP1_UART2_APPS_CMD_RCGR, 1, 144, 15625, CFG_CLK_SRC_GPLL0, 16); /* Vote for gpll0 clock */ clk_enable_gpll0(base, &gpll0_vote_clk); diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index a4731613c5e0..479f9771a464 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -25,33 +25,17 @@ #define SDCC2_BCR (0x14000) /* block reset */ #define SDCC2_APPS_CBCR (0x14004) /* branch control */ #define SDCC2_AHB_CBCR (0x14008) #define SDCC2_CMD_RCGR (0x14010) -#define SDCC2_CFG_RCGR (0x14014) -#define SDCC2_M (0x14018) -#define SDCC2_N (0x1401C) -#define SDCC2_D (0x14020) #define BLSP2_AHB_CBCR (0x25004) #define BLSP2_UART2_APPS_CBCR (0x29004) #define BLSP2_UART2_APPS_CMD_RCGR (0x2900C) -#define BLSP2_UART2_APPS_CFG_RCGR (0x29010) -#define BLSP2_UART2_APPS_M (0x29014) -#define BLSP2_UART2_APPS_N (0x29018) -#define BLSP2_UART2_APPS_D (0x2901C) /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(30) #define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0) -static const struct bcr_regs sdc_regs = { - .cfg_rcgr = SDCC2_CFG_RCGR, - .cmd_rcgr = SDCC2_CMD_RCGR, - .M = SDCC2_M, - .N = SDCC2_N, - .D = SDCC2_D, -}; - static const struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, .ena_vote = APCS_GPLL_ENA_VOTE, @@ -68,31 +52,23 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) { int div = 5; clk_enable_cbc(priv->base + SDCC2_AHB_CBCR); - clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0, + clk_rcg_set_rate_mnd(priv->base, SDCC2_CMD_RCGR, div, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC2_APPS_CBCR); return rate; } -static const struct bcr_regs uart2_regs = { - .cfg_rcgr = BLSP2_UART2_APPS_CFG_RCGR, - .cmd_rcgr = BLSP2_UART2_APPS_CMD_RCGR, - .M = BLSP2_UART2_APPS_M, - .N = BLSP2_UART2_APPS_N, - .D = BLSP2_UART2_APPS_D, -}; - static int clk_init_uart(struct msm_clk_priv *priv) { /* Enable AHB clock */ clk_enable_vote_clk(priv->base, &gcc_blsp2_ahb_clk); /* 7372800 uart block clock @ GPLL0 */ - clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625, + clk_rcg_set_rate_mnd(priv->base, BLSP2_UART2_APPS_CMD_RCGR, 1, 192, 15625, CFG_CLK_SRC_GPLL0, 16); /* Vote for gpll0 clock */ clk_enable_gpll0(priv->base, &gpll0_vote_clk); diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 6303dcbf8461..05e5ab7d094b 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -103,9 +103,9 @@ void clk_bcr_update(phys_addr_t apps_cmd_rcgr) /* * root set rate for clocks with half integer and MND divider * div should be pre-calculated ((div * 2) - 1) */ -void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, +void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr, int div, int m, int n, int source, u8 mnd_width) { u32 cfg; /* M value for MND divider. */ @@ -119,14 +119,14 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, debug("m %#x n %#x d %#x div %#x mask %#x\n", m_val, n_val, d_val, div, mask); /* Program MND values */ - writel(m_val & mask, base + regs->M); - writel(n_val & mask, base + regs->N); - writel(d_val & mask, base + regs->D); + writel(m_val & mask, base + cmd_rcgr + RCG_M_REG); + writel(n_val & mask, base + cmd_rcgr + RCG_N_REG); + writel(d_val & mask, base + cmd_rcgr + RCG_D_REG); /* setup src select and divider */ - cfg = readl(base + regs->cfg_rcgr); + cfg = readl(base + cmd_rcgr + RCG_CFG_REG); cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK | CFG_SRC_DIV_MASK); cfg |= source & CFG_SRC_SEL_MASK; /* Select clock source */ @@ -135,22 +135,22 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, if (n && n != m) cfg |= CFG_MODE_DUAL_EDGE; - writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ + writel(cfg, base + cmd_rcgr + RCG_CFG_REG); /* Write new clock configuration */ /* Inform h/w to start using the new config. */ - clk_bcr_update(base + regs->cmd_rcgr); + clk_bcr_update(base + cmd_rcgr); } /* root set rate for clocks with half integer and mnd_width=0 */ -void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, +void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, int source) { u32 cfg; /* setup src select and divider */ - cfg = readl(base + regs->cfg_rcgr); + cfg = readl(base + cmd_rcgr + RCG_CFG_REG); cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK); cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */ /* @@ -159,12 +159,12 @@ void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, */ if (div) cfg |= (2 * div - 1) & CFG_SRC_DIV_MASK; - writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ + writel(cfg, base + cmd_rcgr + RCG_CFG_REG); /* Write new clock configuration */ /* Inform h/w to start using the new config. */ - clk_bcr_update(base + regs->cmd_rcgr); + clk_bcr_update(base + cmd_rcgr); } const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) { diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index 12a1eaec2b2e..a7f833a4b6dd 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -11,8 +11,13 @@ #define CFG_CLK_SRC_GPLL0 (1 << 8) #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8) #define CFG_CLK_SRC_MASK (7 << 8) +#define RCG_CFG_REG 0x4 +#define RCG_M_REG 0x8 +#define RCG_N_REG 0xc +#define RCG_D_REG 0x10 + struct pll_vote_clk { uintptr_t status; int status_bit; uintptr_t ena_vote; @@ -23,15 +28,8 @@ struct vote_clk { uintptr_t cbcr_reg; uintptr_t ena_vote; int vote_bit; }; -struct bcr_regs { - uintptr_t cfg_rcgr; - uintptr_t cmd_rcgr; - uintptr_t M; - uintptr_t N; - uintptr_t D; -}; struct freq_tbl { uint freq; uint src; @@ -87,11 +85,11 @@ void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0); void clk_bcr_update(phys_addr_t apps_cmd_rgcr); void clk_enable_cbc(phys_addr_t cbcr); void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate); -void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, +void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr, int div, int m, int n, int source, u8 mnd_width); -void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, +void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, int source); static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id) { diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index 958312b88842..8a897a52bc00 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -27,37 +27,24 @@ /* Uart clock control registers */ #define BLSP1_UART2_BCR (0x3028) #define BLSP1_UART2_APPS_CBCR (0x302C) #define BLSP1_UART2_APPS_CMD_RCGR (0x3034) -#define BLSP1_UART2_APPS_CFG_RCGR (0x3038) -#define BLSP1_UART2_APPS_M (0x303C) -#define BLSP1_UART2_APPS_N (0x3040) -#define BLSP1_UART2_APPS_D (0x3044) /* I2C controller clock control registerss */ #define BLSP1_QUP0_I2C_APPS_CBCR (0x6028) #define BLSP1_QUP0_I2C_APPS_CMD_RCGR (0x602C) -#define BLSP1_QUP0_I2C_APPS_CFG_RCGR (0x6030) #define BLSP1_QUP1_I2C_APPS_CBCR (0x2008) #define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x200C) -#define BLSP1_QUP1_I2C_APPS_CFG_RCGR (0x2010) #define BLSP1_QUP2_I2C_APPS_CBCR (0x3010) #define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x3000) -#define BLSP1_QUP2_I2C_APPS_CFG_RCGR (0x3004) #define BLSP1_QUP3_I2C_APPS_CBCR (0x4020) #define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x4000) -#define BLSP1_QUP3_I2C_APPS_CFG_RCGR (0x4004) #define BLSP1_QUP4_I2C_APPS_CBCR (0x5020) #define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x5000) -#define BLSP1_QUP4_I2C_APPS_CFG_RCGR (0x5004) /* SD controller clock control registers */ #define SDCC_BCR(n) (((n) * 0x1000) + 0x41000) -#define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x41004) -#define SDCC_CFG_RCGR(n) (((n) * 0x1000) + 0x41008) -#define SDCC_M(n) (((n) * 0x1000) + 0x4100C) -#define SDCC_N(n) (((n) * 0x1000) + 0x41010) -#define SDCC_D(n) (((n) * 0x1000) + 0x41014) +#define SDCC_CMD_RCGR(n) (((n + 1) * 0x1000) + 0x41004) #define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018) #define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C) /* USB-3.0 controller clock control registers */ @@ -69,12 +56,8 @@ #define USB30_MOCK_UTMI_CBCR (0x39014) #define USB30_MOCK_UTMI_CMD_RCGR (0x3901C) #define USB30_MOCK_UTMI_CFG_RCGR (0x39020) #define USB30_MASTER_CMD_RCGR (0x39028) -#define USB30_MASTER_CFG_RCGR (0x3902C) -#define USB30_MASTER_M (0x39030) -#define USB30_MASTER_N (0x39034) -#define USB30_MASTER_D (0x39038) #define USB2A_PHY_SLEEP_CBCR (0x4102C) #define USB_HS_PHY_CFG_AHB_CBCR (0x41030) /* ETH controller clock control registers */ @@ -82,14 +65,9 @@ #define ETH_RGMII_CBCR (0x4e008) #define ETH_SLAVE_AHB_CBCR (0x4e00c) #define ETH_AXI_CBCR (0x4e010) #define EMAC_PTP_CMD_RCGR (0x4e014) -#define EMAC_PTP_CFG_RCGR (0x4e018) #define EMAC_CMD_RCGR (0x4e01c) -#define EMAC_CFG_RCGR (0x4e020) -#define EMAC_M (0x4e024) -#define EMAC_N (0x4e028) -#define EMAC_D (0x4e02c) /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(31) @@ -102,24 +80,8 @@ static struct vote_clk gcc_blsp1_ahb_clk = { .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE, .vote_bit = BIT(10) | BIT(5) | BIT(4), }; -static const struct bcr_regs uart2_regs = { - .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR, - .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR, - .M = BLSP1_UART2_APPS_M, - .N = BLSP1_UART2_APPS_N, - .D = BLSP1_UART2_APPS_D, -}; - -static const struct bcr_regs sdc_regs = { - .cfg_rcgr = SDCC_CFG_RCGR(1), - .cmd_rcgr = SDCC_CMD_RCGR(1), - .M = SDCC_M(1), - .N = SDCC_N(1), - .D = SDCC_D(1), -}; - static struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, .ena_vote = APCS_GPLL_ENA_VOTE, @@ -132,92 +94,38 @@ static struct pll_vote_clk gpll1_vote_clk = { .ena_vote = APCS_GPLL_ENA_VOTE, .vote_bit = BIT(1), }; -static const struct bcr_regs usb30_master_regs = { - .cfg_rcgr = USB30_MASTER_CFG_RCGR, - .cmd_rcgr = USB30_MASTER_CMD_RCGR, - .M = USB30_MASTER_M, - .N = USB30_MASTER_N, - .D = USB30_MASTER_D, -}; - -static const struct bcr_regs emac_regs = { - .cfg_rcgr = EMAC_CFG_RCGR, - .cmd_rcgr = EMAC_CMD_RCGR, - .M = EMAC_M, - .N = EMAC_N, - .D = EMAC_D, -}; - -static const struct bcr_regs emac_ptp_regs = { - .cfg_rcgr = EMAC_PTP_CFG_RCGR, - .cmd_rcgr = EMAC_PTP_CMD_RCGR, - .M = EMAC_M, - .N = EMAC_N, - .D = EMAC_D, -}; - -static const struct bcr_regs blsp1_qup0_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP0_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP0_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - -static const struct bcr_regs blsp1_qup1_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP1_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP1_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - -static const struct bcr_regs blsp1_qup2_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP2_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP2_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - -static const struct bcr_regs blsp1_qup3_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP3_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP3_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - -static const struct bcr_regs blsp1_qup4_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP4_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP4_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); switch (clk->id) { case GCC_BLSP1_UART2_APPS_CLK: /* UART: 1843200Hz for a fixed 115200 baudrate (19200000 * (12/125)) */ - clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125, + clk_rcg_set_rate_mnd(priv->base, BLSP1_UART2_APPS_CMD_RCGR, 0, 12, 125, CFG_CLK_SRC_CXO, 16); clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); return 1843200; case GCC_SDCC1_APPS_CLK: /* SDCC1: 200MHz */ - clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 7, 0, 0, + clk_rcg_set_rate_mnd(priv->base, SDCC_CMD_RCGR(0), 7, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1)); return rate; case GCC_ETH_RGMII_CLK: if (rate == 250000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 0, 0, CFG_CLK_SRC_GPLL1, 8); else if (rate == 125000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 7, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 7, 0, 0, CFG_CLK_SRC_GPLL1, 8); else if (rate == 50000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 19, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 19, 0, 0, CFG_CLK_SRC_GPLL1, 8); else if (rate == 5000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 1, 50, CFG_CLK_SRC_GPLL1, 8); return rate; } @@ -236,9 +144,9 @@ static int qcs404_clk_enable(struct clk *clk) switch (clk->id) { case GCC_USB30_MASTER_CLK: clk_enable_cbc(priv->base + USB30_MASTER_CBCR); - clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 7, 0, 0, + clk_rcg_set_rate_mnd(priv->base, USB30_MASTER_CMD_RCGR, 7, 0, 0, CFG_CLK_SRC_GPLL0, 8); break; case GCC_SYS_NOC_USB3_CLK: clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR); @@ -258,16 +166,16 @@ static int qcs404_clk_enable(struct clk *clk) case GCC_ETH_PTP_CLK: /* SPEED_1000: freq -> 250MHz */ clk_enable_cbc(priv->base + ETH_PTP_CBCR); clk_enable_gpll0(priv->base, &gpll1_vote_clk); - clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 3, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_PTP_CMD_RCGR, 3, 0, 0, CFG_CLK_SRC_GPLL1, 8); break; case GCC_ETH_RGMII_CLK: /* SPEED_1000: freq -> 250MHz */ clk_enable_cbc(priv->base + ETH_RGMII_CBCR); clk_enable_gpll0(priv->base, &gpll1_vote_clk); - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 0, 0, CFG_CLK_SRC_GPLL1, 8); break; case GCC_ETH_SLAVE_AHB_CLK: clk_enable_cbc(priv->base + ETH_SLAVE_AHB_CBCR); @@ -279,29 +187,29 @@ static int qcs404_clk_enable(struct clk *clk) clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk); break; case GCC_BLSP1_QUP0_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP0_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup0_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP0_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_BLSP1_QUP1_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP1_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup1_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP1_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_BLSP1_QUP2_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP2_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup2_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP2_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_BLSP1_QUP3_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP3_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup3_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP3_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_BLSP1_QUP4_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP4_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP4_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_SDCC1_AHB_CLK: clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1)); diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index babd83119e2c..ccb0cf245d33 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -18,15 +18,9 @@ #include #include "clock-qcom.h" -#define SE9_AHB_CBCR 0x25004 -#define SE9_UART_APPS_CBCR 0x29004 #define SE9_UART_APPS_CMD_RCGR 0x18148 -#define SE9_UART_APPS_CFG_RCGR 0x1814C -#define SE9_UART_APPS_M 0x18150 -#define SE9_UART_APPS_N 0x18154 -#define SE9_UART_APPS_D 0x18158 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), @@ -45,25 +39,17 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75), { } }; -static const struct bcr_regs uart2_regs = { - .cfg_rcgr = SE9_UART_APPS_CFG_RCGR, - .cmd_rcgr = SE9_UART_APPS_CMD_RCGR, - .M = SE9_UART_APPS_M, - .N = SE9_UART_APPS_N, - .D = SE9_UART_APPS_D, -}; - static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); const struct freq_tbl *freq; switch (clk->id) { case GCC_QUPV3_WRAP1_S1_CLK: /* UART9 */ freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); - clk_rcg_set_rate_mnd(priv->base, &uart2_regs, + clk_rcg_set_rate_mnd(priv->base, SE9_UART_APPS_CMD_RCGR, freq->pre_div, freq->m, freq->n, freq->src, 16); return freq->freq; default: return 0; From patchwork Thu Mar 28 17:59:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 783625 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp2860442wrt; Thu, 28 Mar 2024 11:01:17 -0700 (PDT) X-Forwarded-Encrypted: i=2; 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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id y13-20020a5d4acd000000b00341e5f487casm2292237wrs.46.2024.03.28.10.59.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 10:59:46 -0700 (PDT) From: Caleb Connolly Date: Thu, 28 Mar 2024 17:59:12 +0000 Subject: [PATCH v5 06/16] clk/qcom: sdm845: add gdscs MIME-Version: 1.0 Message-Id: <20240328-b4-qcom-livetree-v5-6-4e98228b3d03@linaro.org> References: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> In-Reply-To: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> To: Tom Rini , Caleb Connolly , Neil Armstrong , Sumit Garg , Lukasz Majewski , Sean Anderson Cc: u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1714; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=J2wyNARYq0khhF05IOZjfXaKY3NwgELyfaNZ+Dn9LDc=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjTWDZypKrqLKmf87QpfNCPp2mVmn2/tyd1Jn9ztfC9HX 7229W1RRykLgyAHg6yYIov4iWWWTWsv22tsX3ABZg4rE8gQBi5OAZhI9G9Ghs7wg9ELe/d9rI89 KF7weP33cqWG5aH/8t1UohMvf33+KJvhn8LklBMNnVUmJmtZRJ3cLRxYk53q9FcInfHbnOxhNl+ oHQA= X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Define the GDSC power domains for SDM845. Reviewed-by: Neil Armstrong Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-sdm845.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index ccb0cf245d33..b7154360894a 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -145,13 +145,31 @@ static const struct qcom_reset_map sdm845_gcc_resets[] = { [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, }; +static const struct qcom_power_map sdm845_gdscs[] = { + [PCIE_0_GDSC] = { 0x6b004 }, + [PCIE_1_GDSC] = { 0x8d004 }, + [UFS_CARD_GDSC] = { 0x75004 }, + [UFS_PHY_GDSC] = { 0x77004 }, + [USB30_PRIM_GDSC] = { 0xf004 }, + [USB30_SEC_GDSC] = { 0x10004 }, + [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { 0x7d030 }, + [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = { 0x7d03c }, + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { 0x7d034 }, + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { 0x7d038 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0x7d040 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 }, +}; + static struct msm_clk_data sdm845_clk_data = { .resets = sdm845_gcc_resets, .num_resets = ARRAY_SIZE(sdm845_gcc_resets), .clks = sdm845_clks, .num_clks = ARRAY_SIZE(sdm845_clks), + .power_domains = sdm845_gdscs, + .num_power_domains = ARRAY_SIZE(sdm845_gdscs), .enable = sdm845_clk_enable, .set_rate = sdm845_clk_set_rate, }; From patchwork Thu Mar 28 17:59:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 783624 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp2860331wrt; Thu, 28 Mar 2024 11:01:05 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWFUbM7bPe9CPx1Y/FIoZAGY/DKNSkqccwIXvvDSnJmWWNnKxhbFzWAI69/7AAB49J5XE+Wy7xXfmcHdhikViFr X-Google-Smtp-Source: AGHT+IEGPom+xZzR3yYdoG9g7B290HMpDlxQteoii6jS+ZMV8yR305rAqE4YV0+7QkoCVsx38jqY X-Received: by 2002:a5d:6086:0:b0:341:c673:f1e8 with SMTP id w6-20020a5d6086000000b00341c673f1e8mr3582341wrt.9.1711648865173; Thu, 28 Mar 2024 11:01:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711648865; cv=none; d=google.com; s=arc-20160816; b=AFNGudE3ocKegXc88hoArnZsyIaAHMb5Bt4w1LTCfNpFmtr2tJey3hPDiVR2sFY5Dz XIgyxrNgJTiwBfyv1qcP0anOF1p/43f+cKnS5i4g9aFOvL1nhjaHTT44d/trABWK/5aR XuRXHP/pSyGlkeEZOo3APzrNHFT02m/95EKzp7lmT5CqRXj/BgYq5rjttHg75SDTcYWp qsQlcRF7e1VYiEf6dBiTeavURfm7Bic0ZSmOcqiGA2MCLEcXDY+fjUXThbI9xlN4DaD0 WSqiysLUlVoIhkz4NUpiTclwQ4zTZCoSGsDQn5I1uTQMmH/jT93xYMOwzpsuPVLxDBk7 /okQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=GewhX1AhomHs5Aohn6YwaTX+GkXafQtxsWjEwPDqGAk=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=Vp0yXMCZgWJKnxYdqw40z3wcLXWOvlssxBSisA1TtE127GCY+WbPMFYF0m50424N0g 7hDgaQk1pLmHUsErDvW4mO6Q9bNTSJgQRw58H+lvEvZYoehkREaCGM9ZWs+IO1po+iwp ke0qbE8Bse4GqYOU96sWYdqigtT4/WrX05B+ptPrwDXTyG+5nRlFR4lYoaMUZSPT9t+k mzOlBDWpMUnHElBnwYJSAmfCJ9Ot7owTPYc4Wjll/djC+V6Yx1gAUbLusVunzn+q763l tgYptMVJ9fWsoZcyw/cQFDekZ4DlRACnsR9/VhdIoWIVmZRMZjDVKXuR3KWPanf/N4Yh oMnw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=btPev3XJ; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id y13-20020a5d4acd000000b00341e5f487casm2292237wrs.46.2024.03.28.10.59.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 10:59:48 -0700 (PDT) From: Caleb Connolly Date: Thu, 28 Mar 2024 17:59:13 +0000 Subject: [PATCH v5 07/16] clk/qcom: sdm845: add USB clocks MIME-Version: 1.0 Message-Id: <20240328-b4-qcom-livetree-v5-7-4e98228b3d03@linaro.org> References: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> In-Reply-To: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> To: Tom Rini , Caleb Connolly , Neil Armstrong , Sumit Garg , Lukasz Majewski , Sean Anderson Cc: u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2569; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=LQeBYALcRlahXsl7p+tCEbXEjlrRYAIfZnvrRJ8uguA=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjTWDZybL17bMu3Q56w5iy/N39H363ar4/8dRX/qctjun jvYtTx6bUcxC4MgB4OsmCKL+Illlk1rL9trbF9wAWYOKxPIEAYuTgGYiCEnI0NzN8tRd907d9Ye 5+qLkZRgChLNvbn7VQYv8xW7OTdUDt5geB/w1XtHdGO1tar37223Hzp3Tn+94tPuvHsx5f/EJ7+ dAwA= X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Most devices only initialise the USB clocks for us if we boot via "fastboot boot", add the missing clock configuration to get both USB ports working regardless of the bootloader state. Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-sdm845.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index b7154360894a..e9c61eb480de 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -20,8 +20,12 @@ #include "clock-qcom.h" #define SE9_UART_APPS_CMD_RCGR 0x18148 +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf018 +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf030 +#define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf05c + static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), @@ -56,8 +60,10 @@ static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) } } static const struct gate_clk sdm845_clks[] = { + GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x82020, 0x00000001), + GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x05030, 0x00000001), GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, 0x00000400), GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, 0x00000800), GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, 0x00001000), GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x5200c, 0x00002000), @@ -120,8 +126,27 @@ static int sdm845_clk_enable(struct clk *clk) struct msm_clk_priv *priv = dev_get_priv(clk->dev); debug("%s: clk %s\n", __func__, sdm845_clks[clk->id].name); + switch (clk->id) { + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB_PHY_CFG_AHB2PHY_CLK); + /* These numbers are just pulled from the frequency tables in the Linux driver */ + clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, + (4.5 * 2) - 1, 0, 0, 1 << 8, 8); + clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, + 1, 0, 0, 0, 8); + clk_rcg_set_rate_mnd(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, + 1, 0, 0, 0, 8); + break; + case GCC_USB30_SEC_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK); + + qcom_gate_clk_en(priv, GCC_USB3_SEC_CLKREF_CLK); + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK); + break; + } + qcom_gate_clk_en(priv, clk->id); return 0; } From patchwork Thu Mar 28 17:59:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 783627 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp2860696wrt; Thu, 28 Mar 2024 11:01:39 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWxyapdstg3vAPuDvGCOGJCwC8c25GJWCwma9sK8NavFhSwu1NvNLzZgWE+q1VgCFHtvspqHBR+IpS9qjACRa62 X-Google-Smtp-Source: AGHT+IFd+y5vi+MTS9c9XchLM7Y5JZHe9IfmwqMlj9IyIOcbY/5mZYQi7IE2kLGKn7f6wYD0DkhF X-Received: by 2002:a2e:b0e2:0:b0:2d6:bb18:81b5 with SMTP id h2-20020a2eb0e2000000b002d6bb1881b5mr2633814ljl.2.1711648899395; Thu, 28 Mar 2024 11:01:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711648899; cv=none; d=google.com; s=arc-20160816; b=vDmfP0VTyW9cLxWkKFSVltmM0WqDE3+ufRMWodTVNwul4C3/8ZO818vRYohh9+UtS2 a1LRM/gLoD6otrlOgg05DCPl1aAHaoN7zq3TDuEoPYFX9A2wQZClZNBzxAKE6EKhYvXK rRQ+956p3wZuyghL8iBz/NO7XEelcVGoXjXrQuJrqwxq7aGYy1SwvATt75nOtHrgvZkW gmbseGsg5GFVJRP7OwRWRprqe0+Mn9imHVBEJRVotKbhFnX967WnyXNtSBPM36lNEumD ca6DCjOsxfnltR3Dpfs6CeA8BHpaXQyz0DDMW2u4auB88UnNdS/mSTvERR+1pfsA73g6 5kOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=R7r7yaX5GC6A7b+YWiB29a1fIsl80G8kHqu1xhDh7Zc=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=RYxA7G49GrwWokxiQ5lxZpNa7czXPJKlhsaHZTMyEDHMmucC5oJ7hd3V1OlyJLBSLv NpMAOX5DINEU/a6YaHfDF4weFi79TDfzrCD3vsgU+/sdPYQRlKMLjUO+TtX++44Bc3a3 C2BhvQBqRn2FA57N1Hp8v/rVBWyIsy6CoAj8hiYRqQISk52kYGOOiMLEy3myOadU90uN Y6aFGJLnWT1uBT9zxBktRfdfvvswySMxJ2jBrDUbQfO1x7kdGiDKE/rP2PsvUZjzL62E d6KtvKoWmTjIPfibQVtv7aRCMbfH19j85lUB/YuWouB/pgXf1mhYtV4UsDLu5C7bCebH pV8g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=USr++w93; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id y13-20020a5d4acd000000b00341e5f487casm2292237wrs.46.2024.03.28.10.59.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 10:59:49 -0700 (PDT) From: Caleb Connolly Date: Thu, 28 Mar 2024 17:59:14 +0000 Subject: [PATCH v5 08/16] gpio: msm_gpio: add .set_flags op MIME-Version: 1.0 Message-Id: <20240328-b4-qcom-livetree-v5-8-4e98228b3d03@linaro.org> References: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> In-Reply-To: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> To: Tom Rini , Caleb Connolly , Neil Armstrong , Sumit Garg , Lukasz Majewski , Sean Anderson Cc: u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2578; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=O61GGp35CPRo6Gs3ecjo0wdiQX5EtInYxOC3wND9vEE=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjTWDZxbTOueWl1rE2PcHNss5LnBjF07RPhpaX6Yf/PC6 uSmhNUdpSwMghwMsmKKLOInllk2rb1sr7F9wQWYOaxMIEMYuDgFYCJ3pjH899lkevvTim2J7Hbz mIVe/NrR9P7h7+VNlffym/vCMpU++jMybJpYv/dr9vzsF8ue+M79eMk+mje8RnpJyku9junTA3M /1wAA X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The .direction_input and .direction_output ops are deprecated, and don't seem to behave properly for us. Implement our own .set_flags op to handle this correctly. Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- drivers/gpio/msm_gpio.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index 5e57b0cbde75..f5d9ab54e817 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -34,21 +34,21 @@ struct msm_gpio_bank { #define GPIO_IN_OUT_REG(dev, x) \ (GPIO_CONFIG_REG(dev, x) + 0x4) -static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) +static void msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev); /* Always NOP for special pins, assume they're in the correct state */ if (qcom_is_special_pin(priv->pin_data, gpio)) - return 0; + return; /* Disable OE bit */ clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio), GPIO_OE_MASK, GPIO_OE_DISABLE); - return 0; + return; } static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value) { @@ -83,8 +83,25 @@ static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio, return 0; } +static int msm_gpio_set_flags(struct udevice *dev, unsigned int gpio, ulong flags) +{ + if (flags & GPIOD_IS_OUT_ACTIVE) { + return msm_gpio_direction_output(dev, gpio, 1); + } else if (flags & GPIOD_IS_OUT) { + return msm_gpio_direction_output(dev, gpio, 0); + } else if (flags & GPIOD_IS_IN) { + msm_gpio_direction_input(dev, gpio); + if (flags & GPIOD_PULL_UP) + return msm_gpio_set_value(dev, gpio, 1); + else if (flags & GPIOD_PULL_DOWN) + return msm_gpio_set_value(dev, gpio, 0); + } + + return 0; +} + static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev); @@ -109,12 +126,10 @@ static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio) return GPIOF_INPUT; } static const struct dm_gpio_ops gpio_msm_ops = { - .direction_input = msm_gpio_direction_input, - .direction_output = msm_gpio_direction_output, + .set_flags = msm_gpio_set_flags, .get_value = msm_gpio_get_value, - .set_value = msm_gpio_set_value, .get_function = msm_gpio_get_function, }; static int msm_gpio_probe(struct udevice *dev) From patchwork Thu Mar 28 17:59:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 783626 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp2860576wrt; Thu, 28 Mar 2024 11:01:28 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVGpW8+VwioI0jzUufC3Bx4RzbxlTa/dk6/RevPNII90EBtTEY4e2HTsMGPtRMDWNO0bQOoJG5Aw+UWmGRElHwp X-Google-Smtp-Source: AGHT+IFXRszXFngDjDJdHY/qfz68Ol+Lw50n+5J0/BC7HPXrxoKZgwOI5i+QtVeTLhgyX+1gNFOu X-Received: by 2002:adf:e8c5:0:b0:341:b393:3c70 with SMTP id k5-20020adfe8c5000000b00341b3933c70mr2814948wrn.61.1711648888393; Thu, 28 Mar 2024 11:01:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711648888; cv=none; d=google.com; s=arc-20160816; b=tXwzYKdjraNOW4fdopNwIUumpZco5nu9xv8kTeA5r8r3f4trOb774AJ9YqrFJkvIuU nM+Xq/qfF3au3HTSgdxZ+bnxq/6DVJnWYjDiUsr52COGmXHXPc3Uitf2KCw6NJhPu2fL tGg0o1gsLZDZVyz9IyIF3rNk9i96OKjs4S01sCoTEMYlYguqk5L5LIjH8qpBwL9dU3uG Y/CRk6uh9GbELHuq0WttJRa+++Mkvc+TB9s54WlOf1L+6dQrYnRbJKjHqGSvGPVCO3gv dOWZkM/XSGGyO0ZY5erQ8WdBc5IP5hTqfkEoMvD5hBXQ43f3vlpjfzv8C0SKoHaioHb8 7mlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=cgGFkOv1r6ZqedijumR44euV2V/PWTObj0uui6365Yw=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=U6EZ6RftXF0LO/7ZbEjFYCxZqgt3onldaq3AclISraxSZyduX3HrPQAdsiYU41eBKL 2pE8LQQfq2TgeE+LWc76I7tv6XZhEYykZKOIEu5rRM95/1xABDre9DduF2r6DNBmzjGQ SwJjV1AD05Lg/66Ckd9qq+VoPYHkldAXzvvL33gQkX26+sGsdxgDvrsfduPSchu8fcJs 4UvXChCCMEdOgtQrin4nlzAfXy5FHN0AHxw80hdMg+7Tu6q6iQVr8PmIJ9dOMNk1GLUc KrCzyp4B+8xtUz8TtpH7qj8NjL7DDcsW3zXYfLGAnpCJMOdqovmj1LDmgDhgInuQwZmI HgqA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iXd8FfLt; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id y13-20020a5d4acd000000b00341e5f487casm2292237wrs.46.2024.03.28.10.59.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 10:59:50 -0700 (PDT) From: Caleb Connolly Date: Thu, 28 Mar 2024 17:59:15 +0000 Subject: [PATCH v5 09/16] serial: msm-geni: support livetree MIME-Version: 1.0 Message-Id: <20240328-b4-qcom-livetree-v5-9-4e98228b3d03@linaro.org> References: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> In-Reply-To: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> To: Tom Rini , Caleb Connolly , Neil Armstrong , Sumit Garg , Lukasz Majewski , Sean Anderson Cc: u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1262; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=e9QvEtgQXqVS65y/B+mDQKCzyUPIH18kPws1KWRjbZI=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjTWDVxnTYJmLVRbmZX1cMdpVbOwH7M/TmxJ0OefuI+nz VtKQHx3RykLgyAHg6yYIov4iWWWTWsv22tsX3ABZg4rE8gQBi5OAZiI8CqGv1L6Rudvmvl8Ynz/ r2tlg+hizrYXV7/0Srsdvr+5VMH28iZGhmZBjibJF8JbvH/5rZ3Mt1vgaUefVtjO74eLhCMT1od 9Og8A X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean When using OF_LIVE, the debug UART driver won't be probed if it's a subnode of the geni-se-qup controller. Add a NOP driver for the controller to correctly discover its child nodes. Reviewed-by: Neil Armstrong Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- drivers/serial/serial_msm_geni.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index 4aa0bc8c72bc..5260474fb9a4 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -605,8 +605,21 @@ U_BOOT_DRIVER(serial_msm_geni) = { .ops = &msm_serial_ops, .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, }; +static const struct udevice_id geniqup_ids[] = { + { .compatible = "qcom,geni-se-qup" }, + { } +}; + +U_BOOT_DRIVER(geni_se_qup) = { + .name = "geni-se-qup", + .id = UCLASS_NOP, + .of_match = geniqup_ids, + .bind = dm_scan_fdt_dev, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; + #ifdef CONFIG_DEBUG_UART_MSM_GENI static struct msm_serial_data init_serial_data = { .base = CONFIG_VAL(DEBUG_UART_BASE) From patchwork Thu Mar 28 17:59:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 783628 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp2860794wrt; Thu, 28 Mar 2024 11:01:50 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXUIiOtsh/XJrSvwS+PEe1ySeZRc1EC7YppcBYa6Sw6xajukJB/9/ZloDxqhk1KuBYiuwS2wabNwdjhaEQUuGxH X-Google-Smtp-Source: AGHT+IHUdOaRsRQmAKvvKc5Sh6+VeeA0TaqxGBvxDRksoDPGvysLxaHQW6Q8463if7t7uhh02TvL X-Received: by 2002:a5d:4950:0:b0:33d:f719:83c3 with SMTP id r16-20020a5d4950000000b0033df71983c3mr2075107wrs.34.1711648910187; Thu, 28 Mar 2024 11:01:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711648910; cv=none; d=google.com; s=arc-20160816; b=liZWlmYkujMQ8H5dVGptXVq5AxWxyKH9zaVHCAYswaw97pRT3n6siafXpViEfPXEqY 0VL8Vkh2yPpSNEblo3vIm7EF+gH5esY0In/rHHsfhddR5JwLsuZ6pYk83DVoUAVJjxlV U32BP8UfY8qQdVK4NJU4XRHIRZIRi4BOVyAYUW/h7KfG+qvLAE3w884cm6uUBh+TS+AB AuNkTuW7L/nixIW1LvfEdSQu8+qz//uYerLh6F6eCYRL2LgmraHy4U7Q8Ucy3CW1od5l pOsa4o1g7IbViRwxaMqhJ/2tSWd7/AfycpPksohOgF4iM6+ntLW4w3Is1DhoXexk2/OG uLlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=8kYov/liTQ82x2KMJHf3ZjJBU6Bbzvx3nDiFsfzeCZs=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=UsTezzEgBneCJpBeP4YN1/Iwb+WgFiW8LfInseutUdifF6mRRNapz4Pp1pziGPm6sX 0+5i4CGnJgMPjsoQCb2AZj6Amqfy8fYIJwNUplHED+VPMrpzMqlFkHyaFX3B/0HqlHHj HE0t8HCSuhpDobwFYyn8M8qpsRDKMgeK6Cuh++xg0R7IcU7pZBCkRp0eeYtwJCG2oEOg Kp2vTtJe1PDfcXZfj/G9dPtqwUHS/2n0kwJTv7HlSGf4jEK24nSD6orq9zqlJ0loyfC+ Mz6aF6a7JE89YZEEO2cUZI+LbOPOesuTZ3MTQJdMV7rbq5PCOH2JsW6w7v+StFxjAyWP y8fA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cSq4qb26; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id y13-20020a5d4acd000000b00341e5f487casm2292237wrs.46.2024.03.28.10.59.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 10:59:51 -0700 (PDT) From: Caleb Connolly Date: Thu, 28 Mar 2024 17:59:16 +0000 Subject: [PATCH v5 10/16] mach-snapdragon: fixup USB nodes MIME-Version: 1.0 Message-Id: <20240328-b4-qcom-livetree-v5-10-4e98228b3d03@linaro.org> References: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> In-Reply-To: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> To: Tom Rini , Caleb Connolly , Neil Armstrong , Sumit Garg , Lukasz Majewski , Sean Anderson Cc: u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=6817; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=gK9Jwt3hMxnTPj7O/O0mZ0f7yso4mriyeJANT7O7crM=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjTWDVxX8oITV6T9nOaweO2LCyIm66UK4vRKt199sylx+ kHxqy8nd5SyMAhyMMiKKbKIn1hm2bT2sr3G9gUXYOawMoEMYeDiFICJNCQz/PeU5epQXSJRsTap 8xLP5ZgDs79L6bvaGk6IZ9i07hHbCVFGhraio48q08Oe5kZy2FStNw/7vIJr+fqPsf/UDD0tlp/ gbgYA X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean We don't support USB super-speed in U-Boot yet, we lack the SS PHY drivers, however from my testing even with a PHY driver there seem to be other issues when talking to super-speed peripherals. In pursuit of maintaining upstream DT compatibility, and simplifying porting for new devices, let's implement the DT fixups necessary to configure USB in high-speed only mode at runtime. The pattern is identical for all Qualcomm boards that use the Synaptics DWC3 controller: * Add an additional property on the Qualcomm wrapper node * Remove the super-speed phy phandle and phy-name entries. Signed-off-by: Caleb Connolly Acked-by: Sumit Garg Reviewed-by: Neil Armstrong Tested-by: Neil Armstrong --- arch/arm/mach-snapdragon/Makefile | 1 + arch/arm/mach-snapdragon/board.c | 3 + arch/arm/mach-snapdragon/of_fixup.c | 123 +++++++++++++++++++++++++++++++++++ arch/arm/mach-snapdragon/qcom-priv.h | 20 ++++++ 4 files changed, 147 insertions(+) diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 857171e593da..7a4495c8108f 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -2,4 +2,5 @@ # # (C) Copyright 2015 Mateusz Kulikowski obj-y += board.o +obj-$(CONFIG_OF_LIVE) += of_fixup.o diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 6f762fc948bf..65e4c61e866a 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -27,8 +27,10 @@ #include #include #include +#include "qcom-priv.h" + DECLARE_GLOBAL_DATA_PTR; static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } }; @@ -159,8 +161,9 @@ void __weak qcom_board_init(void) int board_init(void) { show_psci_version(); + qcom_of_fixup_nodes(); qcom_board_init(); return 0; } diff --git a/arch/arm/mach-snapdragon/of_fixup.c b/arch/arm/mach-snapdragon/of_fixup.c new file mode 100644 index 000000000000..4fdfed2dff16 --- /dev/null +++ b/arch/arm/mach-snapdragon/of_fixup.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * OF_LIVE devicetree fixup. + * + * This file implements runtime fixups for Qualcomm DT to improve + * compatibility with U-Boot. This includes adjusting the USB nodes + * to only use USB high-speed, as well as remapping volume buttons + * to behave as up/down for navigating U-Boot. + * + * We use OF_LIVE for this rather than early FDT fixup for a couple + * of reasons: it has a much nicer API, is most likely more efficient, + * and our changes are only applied to U-Boot. This allows us to use a + * DT designed for Linux, run U-Boot with a modified version, and then + * boot Linux with the original FDT. + * + * Copyright (c) 2024 Linaro Ltd. + * Author: Caleb Connolly + */ + +#include +#include +#include +#include +#include +#include + +/* U-Boot only supports USB high-speed mode on Qualcomm platforms with DWC3 + * USB controllers. Rather than requiring source level DT changes, we fix up + * DT here. This improves compatibility with upstream DT and simplifies the + * porting process for new devices. + */ +static int fixup_qcom_dwc3(struct device_node *glue_np) +{ + struct device_node *dwc3; + int ret, len, hsphy_idx = 1; + const __be32 *phandles; + const char *second_phy_name; + + debug("Fixing up %s\n", glue_np->name); + + /* Tell the glue driver to configure the wrapper for high-speed only operation */ + ret = of_write_prop(glue_np, "qcom,select-utmi-as-pipe-clk", 0, NULL); + if (ret) { + log_err("Failed to add property 'qcom,select-utmi-as-pipe-clk': %d\n", ret); + return ret; + } + + /* Find the DWC3 node itself */ + dwc3 = of_find_compatible_node(glue_np, NULL, "snps,dwc3"); + if (!dwc3) { + log_err("Failed to find dwc3 node\n"); + return -ENOENT; + } + + phandles = of_get_property(dwc3, "phys", &len); + len /= sizeof(*phandles); + if (len == 1) { + log_debug("Only one phy, not a superspeed controller\n"); + return 0; + } + + /* Figure out if the superspeed phy is present and if so then which phy is it? */ + ret = of_property_read_string_index(dwc3, "phy-names", 1, &second_phy_name); + if (ret == -ENODATA) { + log_debug("Only one phy, not a super-speed controller\n"); + return 0; + } else if (ret) { + log_err("Failed to read second phy name: %d\n", ret); + return ret; + } + + if (!strncmp("usb3-phy", second_phy_name, strlen("usb3-phy"))) { + log_debug("Second phy isn't superspeed (is '%s') assuming first phy is SS\n", + second_phy_name); + hsphy_idx = 0; + } + + /* Overwrite the "phys" property to only contain the high-speed phy */ + ret = of_write_prop(dwc3, "phys", sizeof(*phandles), phandles + hsphy_idx); + if (ret) { + log_err("Failed to overwrite 'phys' property: %d\n", ret); + return ret; + } + + /* Overwrite "phy-names" to only contain a single entry */ + ret = of_write_prop(dwc3, "phy-names", strlen("usb2-phy"), "usb2-phy"); + if (ret) { + log_err("Failed to overwrite 'phy-names' property: %d\n", ret); + return ret; + } + + ret = of_write_prop(dwc3, "maximum-speed", strlen("high-speed"), "high-speed"); + if (ret) { + log_err("Failed to set 'maximum-speed' property: %d\n", ret); + return ret; + } + + return 0; +} + +static void fixup_usb_nodes(void) +{ + struct device_node *glue_np = NULL; + int ret; + + while ((glue_np = of_find_compatible_node(glue_np, NULL, "qcom,dwc3"))) { + ret = fixup_qcom_dwc3(glue_np); + if (ret) + log_warning("Failed to fixup node %s: %d\n", glue_np->name, ret); + } +} + +#define time_call(func, ...) \ + do { \ + u64 start = timer_get_us(); \ + func(__VA_ARGS__); \ + debug(#func " took %lluus\n", timer_get_us() - start); \ + } while (0) + +void qcom_of_fixup_nodes(void) +{ + time_call(fixup_usb_nodes); +} diff --git a/arch/arm/mach-snapdragon/qcom-priv.h b/arch/arm/mach-snapdragon/qcom-priv.h new file mode 100644 index 000000000000..0a7ed5eff8b8 --- /dev/null +++ b/arch/arm/mach-snapdragon/qcom-priv.h @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 + +#ifndef __QCOM_PRIV_H__ +#define __QCOM_PRIV_H__ + +#if CONFIG_IS_ENABLED(OF_LIVE) +/** + * qcom_of_fixup_nodes() - Fixup Qualcomm DT nodes + * + * Adjusts nodes in the live tree to improve compatibility with U-Boot. + */ +void qcom_of_fixup_nodes(void); +#else +static inline void qcom_of_fixup_nodes(void) +{ + log_debug("Unable to dynamically fixup USB nodes, please enable CONFIG_OF_LIVE\n"); +} +#endif /* OF_LIVE */ + +#endif /* __QCOM_PRIV_H__ */ From patchwork Thu Mar 28 17:59:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 783629 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp2860919wrt; Thu, 28 Mar 2024 11:02:01 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXWu4HB1poDQbyTvJaYbF/FtKl/pIUSLyWfgjFzx0BpTRy3v4r5w6yyU/fRWzeaduEfsu56srXr1Xel5MIvfkbg X-Google-Smtp-Source: AGHT+IFO+GBPKOP4PTA7Vz00wanSYEBBE/VyEFMQ2sNAgeRdG8QvtVhB1hZCBxmpHiHKBczmNkKo X-Received: by 2002:a05:600c:470e:b0:414:8065:2d12 with SMTP id v14-20020a05600c470e00b0041480652d12mr155465wmo.14.1711648921091; Thu, 28 Mar 2024 11:02:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711648921; cv=none; d=google.com; s=arc-20160816; b=kL4F03XzqxRV4ldUEGJ2/SDvjOGu8LMSM1rZAFMp6QpbXnNG+N+cM/HGgSYy/kzTsd Kndc5v094Hw+4LN7OnujcDcOl9uXbniphLLWLSbLnoOnKcpsMxpjz2JXTe9Uc0gYcxwm 4FWXeJumru4BLSWXS0kt4c/xlbIp46kabSuCdxZcAbdco+LaNmA33QG9NKHDsmIxkUel Du1+VtvmDA24QWAI7beelMh+2gtgoXYa50/ubE/KiFSx7u2e+0MyHs5/avfFyb2OEMlE 6Ti4GlurjPnk+NTyO3yHX5HjSlEs6iWri00NGtmKklPVBfsBPMBEp0L9a1BBM7SFfnGD 5RAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=fSfO4nPxMkXp295NH+BMKdLi91fCv2a9KEPcm90GuVY=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=SN84mNdissW1seESTeoFFYD9vMfgjga5xwER1ULuo+sf1D5Jw5b7IQtIp5DDucUrKF toansXdWU9yOxjJ0np8ZAhLopDXAmaiR5mxXc4+Yp3VvYfv8tzKyb6iQf+acqOVf8hgx aRsI9rrQsBuGnZ8xF6RGQA3MpLV2Nr/u5bYxiCm63Qpx5K0UMuboGmbEDlUBCy9qQCJm Df7MCEvhvHLMSU6VWVb9FDx47LgaJm66fl/uPe7fRKONAiBzdKLymbHxkwJnwcF6EYGC fb56xyELVjFZF2LaHrZlz+b29MyXLl0hs0SLQzAYbH6bzizzQVCltan8Ib8LmzPg2DZS zVEA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=w0OVPzc0; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id y13-20020a5d4acd000000b00341e5f487casm2292237wrs.46.2024.03.28.10.59.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 10:59:52 -0700 (PDT) From: Caleb Connolly Date: Thu, 28 Mar 2024 17:59:17 +0000 Subject: [PATCH v5 11/16] mach-snapdragon: fixup power-domains MIME-Version: 1.0 Message-Id: <20240328-b4-qcom-livetree-v5-11-4e98228b3d03@linaro.org> References: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> In-Reply-To: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> To: Tom Rini , Caleb Connolly , Neil Armstrong , Sumit Garg , Lukasz Majewski , Sean Anderson Cc: u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2658; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=F5sYJt36I+PI1NFYlyJGjSiVgDKon6nM15HEp4AUWhc=; b=kA0DAAgReTBFn7kwMhcByyZiAGYFsAqh5luzf0gKXsKWp8G8qE2qCaeyeQfqyGbbV7GkYEGo8 Ih1BAARCAAdFiEEF8imOYKt0z8ot6DQeTBFn7kwMhcFAmYFsAoACgkQeTBFn7kwMhdwggEAsDXQ 4cH2mFGXMJOFFbPipRBYuQpVctPOJydEB8gAINcA/3kn8dXEe1OLyhfFL9qD7W8kjfPzJnx8/5e GPxCAl2Lh X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean We don't support the RPM(h)PD power domains in U-Boot, and we don't need to - the necessary resources are on, and we aren't going to enter any low power modes. We could try using a no-op device, but this requires adding a compatible for every platform, and just pollutes the driver model. So instead let's just remove every "power-domains" property that references the RPM(h)pd power controller. This takes <1ms as we're using OF_LIVE. Of note, this only applies to drivers which are loading post-relocation. Drivers loaded pre-reloc that reference the rpm(h)pd still need DM_FLAG_DEFAULT_PD_CTRL_OFF in their flags. Signed-off-by: Caleb Connolly Acked-by: Sumit Garg Reviewed-by: Neil Armstrong Tested-by: Neil Armstrong --- arch/arm/mach-snapdragon/of_fixup.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/mach-snapdragon/of_fixup.c b/arch/arm/mach-snapdragon/of_fixup.c index 4fdfed2dff16..3f7ac227bd09 100644 --- a/arch/arm/mach-snapdragon/of_fixup.c +++ b/arch/arm/mach-snapdragon/of_fixup.c @@ -21,8 +21,9 @@ #include #include #include #include +#include #include /* U-Boot only supports USB high-speed mode on Qualcomm platforms with DWC3 * USB controllers. Rather than requiring source level DT changes, we fix up @@ -109,8 +110,38 @@ static void fixup_usb_nodes(void) log_warning("Failed to fixup node %s: %d\n", glue_np->name, ret); } } +/* Remove all references to the rpmhpd device */ +static void fixup_power_domains(void) +{ + struct device_node *pd = NULL, *np = NULL; + struct property *prop; + const __be32 *val; + + /* All Qualcomm platforms name the rpm(h)pd "power-controller" */ + for_each_of_allnodes(pd) { + if (pd->name && !strcmp("power-controller", pd->name)) + break; + } + + /* Sanity check that this is indeed a power domain controller */ + if (!of_find_property(pd, "#power-domain-cells", NULL)) { + log_err("Found power-controller but it doesn't have #power-domain-cells\n"); + return; + } + + /* Remove all references to the power domain controller */ + for_each_of_allnodes(np) { + if (!(prop = of_find_property(np, "power-domains", NULL))) + continue; + + val = prop->value; + if (val[0] == cpu_to_fdt32(pd->phandle)) + of_remove_property(np, prop); + } +} + #define time_call(func, ...) \ do { \ u64 start = timer_get_us(); \ func(__VA_ARGS__); \ @@ -119,5 +150,6 @@ static void fixup_usb_nodes(void) void qcom_of_fixup_nodes(void) { time_call(fixup_usb_nodes); + time_call(fixup_power_domains); } From patchwork Thu Mar 28 17:59:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 783630 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp2861035wrt; Thu, 28 Mar 2024 11:02:12 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWkEHugOMC7aN9+Xk/bTueQL5D3ODXIhkWgn0pUQ3aWHWsXCrHyp6HqXlUoEwunXJyo+6ioGOHoAUA3uDKuylfY X-Google-Smtp-Source: AGHT+IGxFDclnDH4hl+wpHloSkSPkrdVBZXX2xBLe9tcprY4zIWj1xqnVj9U1B6vWsTWGKIN85LU X-Received: by 2002:a5d:6d0e:0:b0:33d:a185:17ec with SMTP id e14-20020a5d6d0e000000b0033da18517ecmr3947300wrq.4.1711648932511; Thu, 28 Mar 2024 11:02:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711648932; cv=none; d=google.com; s=arc-20160816; b=OgH6UCEFE63efX87y5WaUtZWe3JcU4cqbk7ttWx6NdTqLxw0QxP6Qn5fVY+B8BeIqm EC8ZINn1wrfaa7v7UL3jTCX4mI19yqYp2Yh1/pnzUFlq1HkL/dwReA4AyhuSZNFFlhLt E/PpGk1R/Ii93p1x6I3UzwdcMijZXV6tV9tNwLhfDTfiYxlctVOVlZmdOm7LIw2rzVUn 2iARPLVwnCS5smyFLq61R/KMajhyHW9fX3CiEaz7hQz14iuYV3t42i3lJhz8fdOtpSEP WjFxbhgAaTKd7dZ/Ox8q2eFMLoznRyo1/T6fmMKl5QNZtEn4XwvyZOg1/TEVDgFC6yyd Vz5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=NRQksOoQBBCu1S502LG/RKcB23CbUdRKpxTRdGODXGI=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=LtV5bjPfq9QfJeFX3+eHLajXynMred+OjAxNUOtfo43UgM0ACmkG6RD9RtSZJh55M0 GkI3bD5ilPfNqdjOHstFJdPmFU3KKij602HZJ5CrEPkm5UXhG7/CvTn0B42SwSUAiyaa U83p9VVNmEYdmgahEyR/1SB4+/ux9rivMwukXnC9CTnZxwH44wr0lw7pjidRYQtHux+j ReHGEXOOhAkKlwTpGDJt4LBRoBtX+55ZrBlcLk3kLIkOe4IxdLtATmrqVABcZPyyQTEI q5enP5fmarfi4oP9LIK08iAkzeyHOioQOZ+z7swRGZCngkBfiK4riVK+oliXcSOL1Ace lgMw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UXMThWSO; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id y13-20020a5d4acd000000b00341e5f487casm2292237wrs.46.2024.03.28.10.59.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 10:59:52 -0700 (PDT) From: Caleb Connolly Date: Thu, 28 Mar 2024 17:59:18 +0000 Subject: [PATCH v5 12/16] mach-snapdragon: call regulators_enable_boot_on() MIME-Version: 1.0 Message-Id: <20240328-b4-qcom-livetree-v5-12-4e98228b3d03@linaro.org> References: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> In-Reply-To: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> To: Tom Rini , Caleb Connolly , Neil Armstrong , Sumit Garg , Lukasz Majewski , Sean Anderson Cc: u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=946; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=iHXnsqcVLhfSIq88PzmJ9sTxqmVwLCybN5TBqignPCs=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjTWDVzbrq01kAhauFz2jZvo4fcSX24xWU5dPLuIQ3DK7 cO3M8PiOkpZGAQ5GGTFFFnETyyzbFp72V5j+4ILMHNYmUCGMHBxCsBE/O4xMuydLiEodstg6t4j ryNvi5h/cNw7TeBE7DeN9lndbLPVmg8x/C/e6fyg5/mVY4/TG+4+lm6MXC/Gs2p6zv0v//dP7gj 4fnk2AA== X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Make sure we power on any boot-on or always-on regulators. These are used for peripherals like USB on some platforms. Signed-off-by: Caleb Connolly Reviewed-by: Sumit Garg Reviewed-by: Neil Armstrong --- arch/arm/mach-snapdragon/board.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 65e4c61e866a..3d5994c87886 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -15,8 +15,9 @@ #include #include #include #include +#include #include #include #include #include @@ -160,8 +161,9 @@ void __weak qcom_board_init(void) } int board_init(void) { + regulators_enable_boot_on(false); show_psci_version(); qcom_of_fixup_nodes(); qcom_board_init(); return 0; From patchwork Thu Mar 28 17:59:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 783631 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp2861135wrt; Thu, 28 Mar 2024 11:02:23 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVmm2OmP6+ObUluLMDxECDkmMEE2wk2N/UvOR5QmzR5AdpQTGL8Hwnc24Uaen5oN/9zO0kpmqX2kg3qBF7HqxdA X-Google-Smtp-Source: AGHT+IEvzJuRDG03W+9xEP2+olhlfDuVZX9XbuijfvzXae5uRsHy73nbevynlUxaPtzaRHJwfTic X-Received: by 2002:a5d:6b87:0:b0:33e:7402:f4d3 with SMTP id n7-20020a5d6b87000000b0033e7402f4d3mr2881159wrx.33.1711648942713; Thu, 28 Mar 2024 11:02:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711648942; cv=none; d=google.com; s=arc-20160816; b=m6gfUv0BX0X9f/5ejAQgrY1NyPYUw/YJGEo7hP/57oJY39NRgj55n6R/8bPydP2uZZ MH6OdQdrWwpa3Q/BDGwrUh7RMrhKUuaA01FQcYWhg90GVi6uRkriCX1cIQzA4i7XLmWF nenH6fjRLsCq8U9pMhyV07EdSkwSg58zI0gBCTy+LVhv7NQ+m7gwj1q9ntAMLw5IRPBf 56XTsBNGvcGk8ygSb+gYpPjArrTKsMv61FEW8YGTmjY3jk5ztTWjC1EIQp8LO6CEmlvb O4JC+hZPoiMRBFU0DlNdIa9A2VP/nPIeFmWQt1lcALdbi+kRukIHI9UhZZY2SdCkrPSV NaHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=O6Q4iPHqNBQ1Q20gSfmWBGk3J7Uofd34Sexw0LNLNLk=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=dBQ5acEYfAEWrpXYmVb8RCjiLXCsRAPdZiJRsMtvvRAhZoXEdQ/AuvlxsNHwVcc1vm OLaKMN08wiw1esYXw2wxpVZwS91mkJT6RXAGxBWEF3jxHIo4TmCwXbzGHnsfU3Qy5egJ muQGspwiAEpwUY1tkq39WzdVwIAK6h/h4m8e8JyfjO33EfwoFEdumBP+pnkv88k87Ngd bfhLZ+Viwica2qtDE4gcF9C+BEXVB0q8xk+RlMljezvzMk6sGr/Mcu4SNbcVH4IMh1xU 5NOKTUMd7bVtNZpzdLxjpXid3xvjSX5yOa3k57YUCWHBcjnidSt/8vWLvXMmX+SUnRRk EGfw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gjBWhshw; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id y13-20020a5d4acd000000b00341e5f487casm2292237wrs.46.2024.03.28.10.59.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 10:59:53 -0700 (PDT) From: Caleb Connolly Date: Thu, 28 Mar 2024 17:59:19 +0000 Subject: [PATCH v5 13/16] dts: sdm845-db845c: add u-boot fixups MIME-Version: 1.0 Message-Id: <20240328-b4-qcom-livetree-v5-13-4e98228b3d03@linaro.org> References: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> In-Reply-To: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> To: Tom Rini , Caleb Connolly , Neil Armstrong , Sumit Garg , Lukasz Majewski , Sean Anderson Cc: u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1063; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=JWwpm6PYEfZfiLMJYt/BfVr0y0ivgV4Se6+WvKM3mNY=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjTWDVwfjk3+tyFodb9WW/p+j+lRH+aev9T6YOGbhX5nk tZ6Lu5g6ihlYRDkYJAVU2QRP7HMsmntZXuN7QsuwMxhZQIZwsDFKQAT2WHIyNDK2PndZR2zWWaV jHc196Pu2tNHJmvu/6oXMq1/Z57DRgeGv4JnfUNeJN8Q3V6Y0qF0L0+r42LENebzVU1ijQEbap9 EXQcA X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The USB VBUS supply for the type-A port is enabled via a GPIO regulator. This is incorrectly modelled in Linux where only the PCIe dependency is expressed. The correct way to handle this will be through a usb-connector node, but for now we'll just mark the regulator as always-on so that it will be enabled automatically during boot. Signed-off-by: Caleb Connolly Reviewed-by: Sumit Garg Reviewed-by: Neil Armstrong --- arch/arm/dts/sdm845-db845c-u-boot.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/dts/sdm845-db845c-u-boot.dtsi b/arch/arm/dts/sdm845-db845c-u-boot.dtsi new file mode 100644 index 000000000000..906f9faa5451 --- /dev/null +++ b/arch/arm/dts/sdm845-db845c-u-boot.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Needed for Linux to boot from USB, otherwise if PCIe driver is not in initramfs + * the VBUS supply will never get turned on. + * https://lore.kernel.org/linux-arm-msm/20240320122515.3243711-1-caleb.connolly@linaro.org/ + */ +&pcie0_3p3v_dual { + regulator-always-on; +}; From patchwork Thu Mar 28 17:59:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 783632 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp2861240wrt; Thu, 28 Mar 2024 11:02:33 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUyek8TGIm4oNdqf+FUPT+6Jrn+ecd+ib0h8bsCr57/Wp5VWDi6tu77BMT5soQdPE1XVn71NhglGcKfP2Qzdu1O X-Google-Smtp-Source: AGHT+IF27utVdq2RmwG/KNLQ+N3lpFApKp4WK9eR0J932YTmsVibtOji6mjBAB2Dn2Zds7m2xBhi X-Received: by 2002:a5d:5343:0:b0:343:3034:7450 with SMTP id t3-20020a5d5343000000b0034330347450mr1895130wrv.69.1711648952985; Thu, 28 Mar 2024 11:02:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711648952; cv=none; d=google.com; s=arc-20160816; b=d1sMkg3H33+7EsnkaAewn/47jSalInk+MEo54cJPiOGQxscd2z2VcdPDBA9OYesaxF Kk8v+bUEB79y+TaEGIAYKDtj1TGgBH5h4sa4YZ1scO2S6VbCLDLDUGBXpGfwW9Ed74G6 zXM/2EDNbATpVPF7ycZoJ1CTIbI9XHyelY/IHa3kuCocyc6kgQho8+jBGN79pNQoUYs0 LFNpP5T8f2gCyIW3DE4UAbpi8l34/PfD1lps9vtGb17A2283vqgMsqi9HCDZgzYZbMY0 lXOPFLIcz6fdLkAm7zxepTx1sq+whOUJMSWI6tmTzXP760+Mfr7wiMln8WmI8U73A4ny ZnLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=P6XcPr9pfYOEmSnzHa2qooJBhM9QEIsjkS+to/+R8LA=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=Uja+o9CGF3szKK9ur6xiGIttjdxn6YhmUYKTX0RMxkxX0Fx10MffabX7wKhOwbqiJW kHTc7cIc2w6xGxB5Rg2o8A2RtCOdR+upEY82plL4n2/8dlzT/cDUG9Xk/MmtCfryDrv8 A/iOYWMOv/7w8dUEPKrNkqwA2NBpaRg2uGi/DNoc3vTXkCxQlonzjX4gp61ezY5lKYGm IUw63tHz/aO+nUQuJhLRYUg/pEnG4/OOUglqjkyjGOD/XSYQ/bTSUoEVX6vRedQYTHs5 T4If7tmmHiztiVAnFjuVn19dEkm0uezyE0t30/9oiFL1jJCSEJAIn4bC4MBxr2C5nR8U 0T6Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PYyDMVWE; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id y13-20020a5d4acd000000b00341e5f487casm2292237wrs.46.2024.03.28.10.59.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 10:59:54 -0700 (PDT) From: Caleb Connolly Date: Thu, 28 Mar 2024 17:59:20 +0000 Subject: [PATCH v5 14/16] qcom_defconfig: enable livetree MIME-Version: 1.0 Message-Id: <20240328-b4-qcom-livetree-v5-14-4e98228b3d03@linaro.org> References: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> In-Reply-To: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> To: Tom Rini , Caleb Connolly , Neil Armstrong , Sumit Garg , Lukasz Majewski , Sean Anderson Cc: u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1104; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=nJRZofJGcS/sPbnQvIzqGqi1p7++HEANmQebMMxA9oM=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjTWDVzTLTIydadF8F1TNogwO+B97qrlhu2da42K7HaJH JPu3SbRUcrCIMjBICumyCJ+Ypll09rL9hrbF1yAmcPKBDKEgYtTACay24ORYf2GO6rn5qqcmSpR 9qGERUZWZ98iHYlj69g6TUMrBZbOf8jwzyS0qG+mzuFQt7tsIWbPtQQXzPrIflErXC/ktmSccMz vEAA= X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Qualcomm FDTs are on the larger size, and with the addition of DT modifications during board_init() it makes sense to enable OF_LIVE globally. The cost of building the tree should be offset by the increased efficiency at which we can walk it. Some rough measurements with CONFIG_BOOTSTAGE suggests that this might add 0.1-0.2ms to the boot-to-console time. However the reset-to-reset timer difference is in the range of 0.5ms so this could just be noise. Suffice to say, no significant slow down. Reviewed-by: Neil Armstrong Signed-off-by: Caleb Connolly Acked-by: Sumit Garg --- configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index cbc612b44bd9..8c4402e8f780 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -25,8 +25,9 @@ CONFIG_CMD_UFS=y CONFIG_CMD_USB=y CONFIG_CMD_CAT=y CONFIG_CMD_BMP=y CONFIG_CMD_LOG=y +CONFIG_OF_LIVE=y CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y CONFIG_CLK_QCOM_QCS404=y CONFIG_CLK_QCOM_SDM845=y From patchwork Thu Mar 28 17:59:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 783633 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp2861354wrt; Thu, 28 Mar 2024 11:02:44 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWp4pOz6MVWZAxTb46stJINrs3GBIVdW3f3PITIpG71rMz4jxSzwKWnu7fV61/cwQrehZY72Ies+xpK1a8bMnMy X-Google-Smtp-Source: AGHT+IG01mmj9lJygydvMbJGcnQcIshRKS4HvW+KpqaTenqcSErSAKNP2RM3ew+OfT6ilkcBw6f4 X-Received: by 2002:a05:6000:1806:b0:341:ca5c:93da with SMTP id m6-20020a056000180600b00341ca5c93damr2985292wrh.1.1711648964013; Thu, 28 Mar 2024 11:02:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711648963; cv=none; d=google.com; s=arc-20160816; b=KpLBrxNwWSVRsC3gzpu3bW0zlDUrowqvaWptyVa2RLpyA4XzWkdDSdN3eHOr3diHu7 Ul6Ez2ycjlwcFv8lQa1ZKz0c+JKrDRBrO7q0gOnP3uXLNgh+WHg4hrvIFl9X47BHSxAG whlEX13mfOpnGV1Ik9dCYAyb8ziG+OC3HDQLpqa4MJmZcd5ICVraEx6sGUZXEZH25g8c Y3LOTJITfQedk7cpeAP055SPIBh4qlchS4Rd1pbppq7oLESacpL/rILUj9u2nLvM58zo qtq1c+lOHMeeD3rp0/G+M4ifD2ZO8ERrsrqtyhNmqsj+tamyB3qllnhxfSQAR8pLB8l8 W/AA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=lO21LnQXMCtSkhTkeX8Wl6Wtl5Wfo0r1/e3rYdUQqpc=; fh=gSVpyLKtvZ+QePPYgVwr0OwBuSQ/slJGUurC/y9msiw=; b=c4bO4TWUQwxPG0eVPDAq3/lvH9BlZx7u5zK31wRFD8BgOz1cXDEkAZhlgbtFrEMVIt ldXiZWAmbZmstDe0EtkjwkI+oQqp/9+lgQFX4VAlB9dTUF8Fby+iJN922d1HqWypdXM7 9XDgcFcwRy/T7ezPUD4Cg/6kbb0wmnaUPM+UAgP+mI9/znvuJgGI+GQpJ2QOG+Vg3gFP md+o/dVsBguMX2jVBh5NJo0XSKj9YrJQKpwodqh2lyYgYo3Yo17flZrCeWPTCD4eXbtp D9hLSFgEjYAJ1E7M4CLf54itvtt5d9qlqlmmyLzwIHx8OeJ/OfS534gwPkrWS2gwxJOm d3bg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o4H1ZrlW; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Enable support for the DWC3 USB controller and required dependencies for Qualcomm boards, specifically the DB845c: * IOMMU / SMMU * USB high-speed PHYs * Mass storage and ACM gadgets Signed-off-by: Caleb Connolly Reviewed-by: Sumit Garg --- configs/qcom_defconfig | 52 ++++++++++++++++++++++++++++---------------------- 1 file changed, 29 insertions(+), 23 deletions(-) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 8c4402e8f780..1abb57345ff1 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -17,10 +17,16 @@ CONFIG_LOG_MAX_LEVEL=9 CONFIG_LOG_DEFAULT_LEVEL=4 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 +# CONFIG_CMD_BIND is not set CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_UFS=y CONFIG_CMD_USB=y CONFIG_CMD_CAT=y @@ -32,20 +38,39 @@ CONFIG_CLK=y CONFIG_CLK_QCOM_QCS404=y CONFIG_CLK_QCOM_SDM845=y CONFIG_MSM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_QUP=y +CONFIG_I2C_MUX=y CONFIG_DM_KEYBOARD=y CONFIG_BUTTON_KEYBOARD=y +CONFIG_IOMMU=y +CONFIG_QCOM_HYP_SMMU=y +CONFIG_MISC=y +CONFIG_NVMEM=y +CONFIG_I2C_EEPROM=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_MSM=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_QCOM=y +CONFIG_RGMII=y CONFIG_PHY=y +CONFIG_PHY_QCOM_QUSB2=y +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y CONFIG_PINCTRL=y CONFIG_PINCTRL_QCOM_QCS404=y CONFIG_PINCTRL_QCOM_SDM845=y CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_SCSI=y CONFIG_MSM_SERIAL=y CONFIG_MSM_GENI_SERIAL=y CONFIG_SPMI_MSM=y @@ -54,8 +79,12 @@ CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_UFS=y CONFIG_VIDEO=y # CONFIG_VIDEO_FONT_8X16 is not set CONFIG_VIDEO_FONT_16X32=y @@ -64,27 +93,4 @@ CONFIG_NO_FB_CLEAR=y CONFIG_VIDEO_SIMPLE=y CONFIG_HEXDUMP=y # CONFIG_GENERATE_SMBIOS_TABLE is not set CONFIG_LMB_MAX_REGIONS=64 -CONFIG_CMD_DHCP=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_PING=y -CONFIG_DM_ETH=y -CONFIG_DM_ETH_PHY=y -CONFIG_DM_MDIO=y -CONFIG_DWC_ETH_QOS=y -CONFIG_DWC_ETH_QOS_QCOM=y -CONFIG_RGMII=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_MISC=y -CONFIG_NVMEM=y -CONFIG_DM_I2C=y -CONFIG_I2C_SUPPORT=y -CONFIG_I2C_MUX=y -CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C=y -CONFIG_SYS_I2C_QUP=y -CONFIG_SYS_I2C_EEPROM_BUS=2 -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 From patchwork Thu Mar 28 17:59:22 2024 Content-Type: text/plain; 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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id y13-20020a5d4acd000000b00341e5f487casm2292237wrs.46.2024.03.28.10.59.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 10:59:57 -0700 (PDT) From: Caleb Connolly Date: Thu, 28 Mar 2024 17:59:22 +0000 Subject: [PATCH v5 16/16] usb: gadget: UMS: fix 64-bit division on ARM32 MIME-Version: 1.0 Message-Id: <20240328-b4-qcom-livetree-v5-16-4e98228b3d03@linaro.org> References: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> In-Reply-To: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> To: Tom Rini , Caleb Connolly , Neil Armstrong , Sumit Garg , Lukasz Majewski , Sean Anderson Cc: u-boot@lists.denx.de, Mattijs Korpershoek X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2332; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=GILrVlJTLB7vGoUqwXYfiSFWeP5Fqv5LLGhQ18mVlh4=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjTWDVwHLU3WZuzJkhAQvvLzAOPldO9bixbuywjcsfvp+ tOPN4QkdZSyMAhyMMiKKbKIn1hm2bT2sr3G9gUXYOawMoEMYeDiFICJ1Kgz/E/m8La2Z4haV5PP LM6scOvA0flRgQxOctVrqkNX6KotWMPIMFN1Xb3RwyarF2mlCYcmqXqudrzP2Xqmxdv+7ZN/5hX XXwMA X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The patch introducing support for dynamic sector sizes changed the types used in some divisions, resulting in the compiler attempting to use libgcc helpers (__aeabi_ldivmod). Replace these divisions with calls to lldiv() to handle this correctly. Fixes: 74e56e0c5065 ("usb: gadget: UMS: support multiple sector sizes") Signed-off-by: Caleb Connolly --- Cc: Mattijs Korpershoek --- drivers/usb/gadget/f_mass_storage.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index d880928044f4..ef90c7ec7fb5 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -239,8 +239,9 @@ /* #define VERBOSE_DEBUG */ /* #define DUMP_MSGS */ #include +#include #include #include #include #include @@ -768,10 +769,10 @@ static int do_read(struct fsg_common *common) } /* Perform the read */ rc = ums[common->lun].read_sector(&ums[common->lun], - file_offset / curlun->blksize, - amount / curlun->blksize, + lldiv(file_offset, curlun->blksize), + lldiv(amount, curlun->blksize), (char __user *)bh->buf); if (!rc) return -EIO; @@ -942,10 +943,10 @@ static int do_write(struct fsg_common *common) amount = bh->outreq->actual; /* Perform the write */ rc = ums[common->lun].write_sector(&ums[common->lun], - file_offset / curlun->blksize, - amount / curlun->blksize, + lldiv(file_offset, curlun->blksize), + lldiv(amount, curlun->blksize), (char __user *)bh->buf); if (!rc) return -EIO; nwritten = rc * curlun->blksize; @@ -1058,10 +1059,10 @@ static int do_verify(struct fsg_common *common) } /* Perform the read */ rc = ums[common->lun].read_sector(&ums[common->lun], - file_offset / curlun->blksize, - amount / curlun->blksize, + lldiv(file_offset, curlun->blksize), + lldiv(amount, curlun->blksize), (char __user *)bh->buf); if (!rc) return -EIO; nread = rc * curlun->blksize;