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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id c3-20020a633503000000b005dc36761ad1sm6958819pga.33.2024.03.25.23.44.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Mar 2024 23:44:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 1/3] target/hppa: Squash d for pa1.x during decode Date: Mon, 25 Mar 2024 20:44:03 -1000 Message-Id: <20240326064405.320551-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240326064405.320551-1-richard.henderson@linaro.org> References: <20240326064405.320551-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The cond_need_ext predicate was created while we still had a 32-bit compilation mode. It now makes more sense to treat D as an absolute indicator of a 64-bit operation. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller Tested-by: Helge Deller --- target/hppa/insns.decode | 20 +++++++++++++------- target/hppa/translate.c | 38 ++++++++++++++++++++------------------ 2 files changed, 33 insertions(+), 25 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index f58455dfdb..6a74cf23cd 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -57,6 +57,9 @@ %neg_to_m 0:1 !function=neg_to_m %a_to_m 2:1 !function=neg_to_m %cmpbid_c 13:2 !function=cmpbid_c +%d_5 5:1 !function=pa20_d +%d_11 11:1 !function=pa20_d +%d_13 13:1 !function=pa20_d #### # Argument set definitions @@ -84,15 +87,16 @@ # Format definitions #### -@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d +@rr_cf_d ...... r:5 ..... cf:4 ...... . t:5 &rr_cf_d d=%d_5 @rrr ...... r2:5 r1:5 .... ....... t:5 &rrr @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf -@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d +@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... . t:5 &rrr_cf_d d=%d_5 @rrr_sh ...... r2:5 r1:5 ........ sh:2 . t:5 &rrr_sh -@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh -@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=0 +@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_d_sh d=%d_5 +@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... . t:5 &rrr_cf_d_sh d=%d_5 sh=0 @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 -@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11 +@rri_cf_d ...... r:5 t:5 cf:4 . ........... \ + &rri_cf_d d=%d_11 i=%lowsign_11 @rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ &rrb_c_f disp=%assemble_12 @@ -368,8 +372,10 @@ fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd # Conditional Branches #### -bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12 -bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12 +bb_sar 110000 00000 r:5 c:1 1 . ........... n:1 . \ + disp=%assemble_12 d=%d_13 +bb_imm 110001 p:5 r:5 c:1 1 . ........... n:1 . \ + disp=%assemble_12 d=%d_13 movb 110010 ..... ..... ... ........... . . @rrb_cf f=0 movbi 110011 ..... ..... ... ........... . . @rib_cf f=0 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 99c5c4cbca..a70d644c0b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -200,6 +200,14 @@ static int cmpbid_c(DisasContext *ctx, int val) return val ? val : 4; /* 0 == "*<<" */ } +/* + * In many places pa1.x did not decode the bit that later became + * the pa2.0 D bit. Suppress D unless the cpu is pa2.0. + */ +static int pa20_d(DisasContext *ctx, int val) +{ + return ctx->is_pa20 & val; +} /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" @@ -693,12 +701,6 @@ static bool cond_need_cb(int c) return c == 4 || c == 5; } -/* Need extensions from TCGv_i32 to TCGv_i64. */ -static bool cond_need_ext(DisasContext *ctx, bool d) -{ - return !(ctx->is_pa20 && d); -} - /* * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of * the Parisc 1.1 Architecture Reference Manual for details. @@ -715,7 +717,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, cond = cond_make_f(); break; case 1: /* = / <> (Z / !Z) */ - if (cond_need_ext(ctx, d)) { + if (!d) { tmp = tcg_temp_new_i64(); tcg_gen_ext32u_i64(tmp, res); res = tmp; @@ -725,7 +727,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, case 2: /* < / >= (N ^ V / !(N ^ V) */ tmp = tcg_temp_new_i64(); tcg_gen_xor_i64(tmp, res, sv); - if (cond_need_ext(ctx, d)) { + if (!d) { tcg_gen_ext32s_i64(tmp, tmp); } cond = cond_make_0_tmp(TCG_COND_LT, tmp); @@ -742,7 +744,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, */ tmp = tcg_temp_new_i64(); tcg_gen_eqv_i64(tmp, res, sv); - if (cond_need_ext(ctx, d)) { + if (!d) { tcg_gen_sextract_i64(tmp, tmp, 31, 1); tcg_gen_and_i64(tmp, tmp, res); tcg_gen_ext32u_i64(tmp, tmp); @@ -760,13 +762,13 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, tmp = tcg_temp_new_i64(); tcg_gen_neg_i64(tmp, cb_msb); tcg_gen_and_i64(tmp, tmp, res); - if (cond_need_ext(ctx, d)) { + if (!d) { tcg_gen_ext32u_i64(tmp, tmp); } cond = cond_make_0_tmp(TCG_COND_EQ, tmp); break; case 6: /* SV / NSV (V / !V) */ - if (cond_need_ext(ctx, d)) { + if (!d) { tmp = tcg_temp_new_i64(); tcg_gen_ext32s_i64(tmp, sv); sv = tmp; @@ -827,7 +829,7 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d, if (cf & 1) { tc = tcg_invert_cond(tc); } - if (cond_need_ext(ctx, d)) { + if (!d) { TCGv_i64 t1 = tcg_temp_new_i64(); TCGv_i64 t2 = tcg_temp_new_i64(); @@ -904,7 +906,7 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d, g_assert_not_reached(); } - if (cond_need_ext(ctx, d)) { + if (!d) { TCGv_i64 tmp = tcg_temp_new_i64(); if (ext_uns) { @@ -979,7 +981,7 @@ static DisasCond do_unit_zero_cond(unsigned cf, bool d, TCGv_i64 res) static TCGv_i64 get_carry(DisasContext *ctx, bool d, TCGv_i64 cb, TCGv_i64 cb_msb) { - if (cond_need_ext(ctx, d)) { + if (!d) { TCGv_i64 t = tcg_temp_new_i64(); tcg_gen_extract_i64(t, cb, 32, 1); return t; @@ -3448,12 +3450,12 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) tmp = tcg_temp_new_i64(); tcg_r = load_gpr(ctx, a->r); - if (cond_need_ext(ctx, a->d)) { + if (a->d) { + tcg_gen_shl_i64(tmp, tcg_r, cpu_sar); + } else { /* Force shift into [32,63] */ tcg_gen_ori_i64(tmp, cpu_sar, 32); tcg_gen_shl_i64(tmp, tcg_r, tmp); - } else { - tcg_gen_shl_i64(tmp, tcg_r, cpu_sar); } cond = cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); @@ -3470,7 +3472,7 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) tmp = tcg_temp_new_i64(); tcg_r = load_gpr(ctx, a->r); - p = a->p | (cond_need_ext(ctx, a->d) ? 32 : 0); + p = a->p | (a->d ? 0 : 32); tcg_gen_shli_i64(tmp, tcg_r, p); cond = cond_make_0(a->c ? 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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id c3-20020a633503000000b005dc36761ad1sm6958819pga.33.2024.03.25.23.44.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Mar 2024 23:44:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 2/3] target/hppa: Replace c with uv in do_cond Date: Mon, 25 Mar 2024 20:44:04 -1000 Message-Id: <20240326064405.320551-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240326064405.320551-1-richard.henderson@linaro.org> References: <20240326064405.320551-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Prepare for proper indication of shladd unsigned overflow. The UV indicator will be zero/not-zero instead of a single bit. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller Tested-by: Helge Deller --- target/hppa/translate.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index a70d644c0b..9d31ef5764 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -707,7 +707,7 @@ static bool cond_need_cb(int c) */ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, - TCGv_i64 res, TCGv_i64 cb_msb, TCGv_i64 sv) + TCGv_i64 res, TCGv_i64 uv, TCGv_i64 sv) { DisasCond cond; TCGv_i64 tmp; @@ -754,14 +754,12 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, } cond = cond_make_0_tmp(TCG_COND_EQ, tmp); break; - case 4: /* NUV / UV (!C / C) */ - /* Only bit 0 of cb_msb is ever set. */ - cond = cond_make_0(TCG_COND_EQ, cb_msb); + case 4: /* NUV / UV (!UV / UV) */ + cond = cond_make_0(TCG_COND_EQ, uv); break; - case 5: /* ZNV / VNZ (!C | Z / C & !Z) */ + case 5: /* ZNV / VNZ (!UV | Z / UV & !Z) */ tmp = tcg_temp_new_i64(); - tcg_gen_neg_i64(tmp, cb_msb); - tcg_gen_and_i64(tmp, tmp, res); + tcg_gen_movcond_i64(TCG_COND_EQ, tmp, uv, ctx->zero, ctx->zero, res); if (!d) { tcg_gen_ext32u_i64(tmp, tmp); } From patchwork Tue Mar 26 06:44:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 782596 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp1535103wrt; Mon, 25 Mar 2024 23:45:08 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUtwEag1ztXILY0fdhW+N4OoFxkvoUVC2/4msJoeILN/MBWEppcwNbNPvmZ+wzQG5CLwNDmWcCWYOUp25ZJNhXL X-Google-Smtp-Source: AGHT+IEotXqjJlRxB+8Md32BpzvVFvczlnWR2Mm6oGDlO3w4ZoOQ4EKlqzK8jEI7451lXax/oQFu X-Received: by 2002:ae9:e30e:0:b0:78a:29f3:afc7 with SMTP id v14-20020ae9e30e000000b0078a29f3afc7mr9444222qkf.42.1711435508249; Mon, 25 Mar 2024 23:45:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711435508; cv=none; d=google.com; s=arc-20160816; b=csBepDDDijhbtjVFYvZ5w7WQMmuO6FpEIa2G98zd6dygOovr5JcZNR2pDmUdqEB65u MpowT84EkolG2xwG4iWRcplrDfu7W39eC5MuEwIieaoR3iM0IrpKmAFK3uZGssKP10vX bz2sW22o5ATW1dBpAtf9F3M8I4cFlkGtDx6SjZsKk/7XR2VJhwgbnJuMZOlFd6B48e+3 gqTKt5Vsnxg9a4v+1oMnGLKuieIQmLzmhlnMYTQ33TlpH/SIc7a6f2YtbpRouO8jPuEi /Y5SqF0+B5VLoKI0V9pH5aZjv291BbLfMhHfi44u2g8Ic5Wu0NerLLE32PC/Bs7jnvFC 5sow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=j9CLORt38yZiQ1fCLl5knbBMBJnlvZ9He6LtCWjt6QA=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=VtOhq4dl6eUrXl+jgN8RFNN7pQnE3KeeaZY2Y3Z1v3VZ+vsEtgBhNWf1P5hG7lsS3T RkVmvcc46aEUCMpn3BqIiOMh1aL/gD3S9Vx2vBga6aM1l5TqBGstqCq/M4Z0J4xIRL0t nZKJsnm/pdJLzakWtkAxMgJYsSgn7vZY1D9UONkWuP5JWkcfmmlZJ3JAb78h4zBHz4IR dnt8CPDhipSqio92znYAgTeKimtQQWRQXxRW1utnACnUm3wkAmr5MEX3enJim/CPE7N8 N7fUVcf8jxeqe8bP/010FmjwEBJg5g4nSX1iF0NcyVUifG0/8n9A9Gs/hP7ie2byU0nA mQSw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NzZiqrW9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(173-197-098-125.biz.spectrum.com. [173.197.98.125]) by smtp.gmail.com with ESMTPSA id c3-20020a633503000000b005dc36761ad1sm6958819pga.33.2024.03.25.23.44.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Mar 2024 23:44:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 3/3] target/hppa: Fix overflow computation for shladd Date: Mon, 25 Mar 2024 20:44:05 -1000 Message-Id: <20240326064405.320551-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240326064405.320551-1-richard.henderson@linaro.org> References: <20240326064405.320551-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Overflow indicator should include the effect of the shift step. We had previously left ??? comments about the issue. Signed-off-by: Richard Henderson Tested-by: Helge Deller --- target/hppa/translate.c | 85 ++++++++++++++++++++++++++++++++--------- 1 file changed, 66 insertions(+), 19 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 9d31ef5764..0976372d16 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -994,7 +994,8 @@ static TCGv_i64 get_psw_carry(DisasContext *ctx, bool d) /* Compute signed overflow for addition. */ static TCGv_i64 do_add_sv(DisasContext *ctx, TCGv_i64 res, - TCGv_i64 in1, TCGv_i64 in2) + TCGv_i64 in1, TCGv_i64 in2, + TCGv_i64 orig_in1, int shift, bool d) { TCGv_i64 sv = tcg_temp_new_i64(); TCGv_i64 tmp = tcg_temp_new_i64(); @@ -1003,9 +1004,50 @@ static TCGv_i64 do_add_sv(DisasContext *ctx, TCGv_i64 res, tcg_gen_xor_i64(tmp, in1, in2); tcg_gen_andc_i64(sv, sv, tmp); + switch (shift) { + case 0: + break; + case 1: + /* Shift left by one and compare the sign. */ + tcg_gen_add_i64(tmp, orig_in1, orig_in1); + tcg_gen_xor_i64(tmp, tmp, orig_in1); + /* Incorporate into the overflow. */ + tcg_gen_or_i64(sv, sv, tmp); + break; + default: + { + int sign_bit = d ? 63 : 31; + uint64_t mask = MAKE_64BIT_MASK(sign_bit - shift, shift); + + /* Compare the sign against all lower bits. */ + tcg_gen_sextract_i64(tmp, orig_in1, sign_bit, 1); + tcg_gen_xor_i64(tmp, tmp, orig_in1); + /* + * If one of the bits shifting into or through the sign + * differs, then we have overflow. + */ + tcg_gen_movcond_i64(TCG_COND_TSTNE, sv, + tmp, tcg_constant_i64(mask), + tcg_constant_i64(-1), sv); + } + } return sv; } +/* Compute unsigned overflow for addition. */ +static TCGv_i64 do_add_uv(DisasContext *ctx, TCGv_i64 cb, TCGv_i64 cb_msb, + TCGv_i64 in1, int shift, bool d) +{ + if (shift == 0) { + return get_carry(ctx, d, cb, cb_msb); + } else { + TCGv_i64 tmp = tcg_temp_new_i64(); + tcg_gen_extract_i64(tmp, in1, (d ? 63 : 31) - shift, shift); + tcg_gen_or_i64(tmp, tmp, get_carry(ctx, d, cb, cb_msb)); + return tmp; + } +} + /* Compute signed overflow for subtraction. */ static TCGv_i64 do_sub_sv(DisasContext *ctx, TCGv_i64 res, TCGv_i64 in1, TCGv_i64 in2) @@ -1020,19 +1062,19 @@ static TCGv_i64 do_sub_sv(DisasContext *ctx, TCGv_i64 res, return sv; } -static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1, +static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1, TCGv_i64 in2, unsigned shift, bool is_l, bool is_tsv, bool is_tc, bool is_c, unsigned cf, bool d) { - TCGv_i64 dest, cb, cb_msb, cb_cond, sv, tmp; + TCGv_i64 dest, cb, cb_msb, in1, uv, sv, tmp; unsigned c = cf >> 1; DisasCond cond; dest = tcg_temp_new_i64(); cb = NULL; cb_msb = NULL; - cb_cond = NULL; + in1 = orig_in1; if (shift) { tmp = tcg_temp_new_i64(); tcg_gen_shli_i64(tmp, in1, shift); @@ -1050,9 +1092,6 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1, } tcg_gen_xor_i64(cb, in1, in2); tcg_gen_xor_i64(cb, cb, dest); - if (cond_need_cb(c)) { - cb_cond = get_carry(ctx, d, cb, cb_msb); - } } else { tcg_gen_add_i64(dest, in1, in2); if (is_c) { @@ -1063,18 +1102,23 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1, /* Compute signed overflow if required. */ sv = NULL; if (is_tsv || cond_need_sv(c)) { - sv = do_add_sv(ctx, dest, in1, in2); + sv = do_add_sv(ctx, dest, in1, in2, orig_in1, shift, d); if (is_tsv) { if (!d) { tcg_gen_ext32s_i64(sv, sv); } - /* ??? Need to include overflow from shift. */ gen_helper_tsv(tcg_env, sv); } } + /* Compute unsigned overflow if required. */ + uv = NULL; + if (cond_need_cb(c)) { + uv = do_add_uv(ctx, cb, cb_msb, orig_in1, shift, d); + } + /* Emit any conditional trap before any writeback. */ - cond = do_cond(ctx, cf, d, dest, cb_cond, sv); + cond = do_cond(ctx, cf, d, dest, uv, sv); if (is_tc) { tmp = tcg_temp_new_i64(); tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); @@ -2843,7 +2887,6 @@ static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf_d *a) static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) { TCGv_i64 dest, add1, add2, addc, in1, in2; - TCGv_i64 cout; nullify_over(ctx); @@ -2880,19 +2923,23 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) tcg_gen_xor_i64(cpu_psw_cb, add1, add2); tcg_gen_xor_i64(cpu_psw_cb, cpu_psw_cb, dest); - /* Write back PSW[V] for the division step. */ - cout = get_psw_carry(ctx, false); - tcg_gen_neg_i64(cpu_psw_v, cout); + /* + * Write back PSW[V] for the division step. + * Shift cb{8} from where it lives in bit 32 to bit 31, + * so that it overlaps r2{32} in bit 31. + */ + tcg_gen_shri_i64(cpu_psw_v, cpu_psw_cb, 1); tcg_gen_xor_i64(cpu_psw_v, cpu_psw_v, in2); /* Install the new nullification. */ if (a->cf) { - TCGv_i64 sv = NULL; + TCGv_i64 sv = NULL, uv = NULL; if (cond_need_sv(a->cf >> 1)) { - /* ??? The lshift is supposed to contribute to overflow. */ - sv = do_add_sv(ctx, dest, add1, add2); + sv = do_add_sv(ctx, dest, add1, add2, in1, 1, false); + } else if (cond_need_cb(a->cf >> 1)) { + uv = do_add_uv(ctx, cpu_psw_cb, NULL, in1, 1, false); } - ctx->null_cond = do_cond(ctx, a->cf, false, dest, cout, sv); + ctx->null_cond = do_cond(ctx, a->cf, false, dest, uv, sv); } return nullify_end(ctx); @@ -3419,7 +3466,7 @@ static bool do_addb(DisasContext *ctx, unsigned r, TCGv_i64 in1, tcg_gen_add_i64(dest, in1, in2); } if (cond_need_sv(c)) { - sv = do_add_sv(ctx, dest, in1, in2); + sv = do_add_sv(ctx, dest, in1, in2, in1, 0, d); } cond = do_cond(ctx, c * 2 + f, d, dest, cb_cond, sv);