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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/core/clock.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/core/clock.c b/hw/core/clock.c index d82e44cd1a..c73f0c2f98 100644 --- a/hw/core/clock.c +++ b/hw/core/clock.c @@ -147,6 +147,10 @@ void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider) { assert(divider != 0); + if (clk->multiplier == multiplier && clk->divider == divider) { + return; + } + trace_clock_set_mul_div(CLOCK_PATH(clk), clk->multiplier, multiplier, clk->divider, divider); clk->multiplier = multiplier; From patchwork Mon Mar 25 13:32:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 782334 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp1176155wrt; Mon, 25 Mar 2024 06:34:15 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW3/RhEffViNkUtKndrpDnDFOzm/2L6Ns/OIJfOtAtkPRnGn4l/JUZHvmxFEMYhSUx99DXA3UQKBzwtap7Qvrv+ X-Google-Smtp-Source: AGHT+IFWpjH9IaOIKd6fRVjY2mEPXgqoyoxg/N4EGiY0yBaGC44XP8wkjEGvuNLOT8jgP3BX/HqM X-Received: by 2002:ae9:e905:0:b0:78a:3ece:c4a4 with SMTP id x5-20020ae9e905000000b0078a3ecec4a4mr7051338qkf.77.1711373654946; Mon, 25 Mar 2024 06:34:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711373654; cv=none; d=google.com; s=arc-20160816; b=VfCRqnyqPw4dYF37hsJxPBQDHqfQBUo4kI/5NA7Cm1CNCn/fzBENdv0sssNQojk/8j iOMTKlAcczvxvw+tVQ4v8OAdj9i6AUH+OLzggRb7QzqDboqyeE5Yo0ugiCTOmsNMT4iX Y4vwySb63muWwnToFrzIGHANPiMyv9norV3PdXy9AH3OKv0BZ26/hYX1qQLSvFa5Igoa kNsyFjxL3uFWr7oc5uYqKnY5cscRQ38of2F8pX6kXPANeKWTMlvSSyqy14Oxg4VR1i2A XVxbogzrQFYV0G0QqVZAF4g6fwEpXLYMACiQSpJppXhdSoGzXPJx77h/9JkJG8JYpqPy YXtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LcyveRM01RBdsZUoJvcc1ljUZ85bZnawQAlgxiQ5g44=; fh=t3X8QBlUt8lTNNYLmXnvt7uYZqjf0Fo0hWn60R6P6ms=; b=aFvMCKF5BMZYM2rbVMW/D+sFtnhSeR7zu3Xw4BG78f28cEx9H7ew0eJHVdJOVPIjJj RQJvuppsEK0aiM6eRHxLAC705jjRZl0wzHINgPZ26hAlFy3twt6LNrZwe842sK3tKuvz x/g6ESsY9AlNGZt8NBXv5w1nMVpMYMe80VqF1lkhdaRKhQIAN9GwnuD9oi1tCQwEr/9i iaW3P3hdHWJzP7RYIAzHl4kvqgVkYOEaP07n5XsSkaLP8+VJAI0tErLxQc7rg7xRa3y5 Kz1tDVNdpXXTx8FPEhajXk6vbfdvBfXnuxucb/z60wfEs+Paj1dg24WM5u4b1zGPtY6e e0Pg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="zkogC/o/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" Subject: [PATCH-for-9.0? v2 2/8] hw/clock: Pass optional &bool argument to clock_set() Date: Mon, 25 Mar 2024 14:32:52 +0100 Message-ID: <20240325133259.57235-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240325133259.57235-1-philmd@linaro.org> References: <20240325133259.57235-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently clock_set() returns whether the clock has been changed or not. In order to combine this information with other clock calls, pass an optional boolean and do not return anything. The single caller ignores the return value, have it use NULL. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/clock.h | 22 ++++++++++++++++------ hw/core/clock.c | 8 +++++--- hw/misc/bcm2835_cprman.c | 2 +- hw/misc/zynq_slcr.c | 4 ++-- 4 files changed, 24 insertions(+), 12 deletions(-) diff --git a/include/hw/clock.h b/include/hw/clock.h index bb12117f67..474bbc07fe 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -180,21 +180,28 @@ static inline bool clock_has_source(const Clock *clk) * clock_set: * @clk: the clock to initialize. * @value: the clock's value, 0 means unclocked + * @changed: set to true if the clock is changed, ignored if set to NULL. * * Set the local cached period value of @clk to @value. - * - * @return: true if the clock is changed. */ -bool clock_set(Clock *clk, uint64_t value); +void clock_set(Clock *clk, uint64_t period, bool *changed); static inline bool clock_set_hz(Clock *clk, unsigned hz) { - return clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz)); + bool changed = false; + + clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz), &changed); + + return changed; } static inline bool clock_set_ns(Clock *clk, unsigned ns) { - return clock_set(clk, CLOCK_PERIOD_FROM_NS(ns)); + bool changed = false; + + clock_set(clk, CLOCK_PERIOD_FROM_NS(ns), &changed); + + return changed; } /** @@ -220,7 +227,10 @@ void clock_propagate(Clock *clk); */ static inline void clock_update(Clock *clk, uint64_t value) { - if (clock_set(clk, value)) { + bool changed = false; + + clock_set(clk, value, &changed); + if (changed) { clock_propagate(clk); } } diff --git a/hw/core/clock.c b/hw/core/clock.c index c73f0c2f98..e0f257b141 100644 --- a/hw/core/clock.c +++ b/hw/core/clock.c @@ -52,16 +52,18 @@ void clock_clear_callback(Clock *clk) clock_set_callback(clk, NULL, NULL, 0); } -bool clock_set(Clock *clk, uint64_t period) +void clock_set(Clock *clk, uint64_t period, bool *changed) { if (clk->period == period) { - return false; + return; } trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_HZ(clk->period), CLOCK_PERIOD_TO_HZ(period)); clk->period = period; - return true; + if (changed) { + *changed = true; + } } static uint64_t clock_get_child_period(Clock *clk) diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index 91c8f7bd17..f16f7978ae 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -680,7 +680,7 @@ static void cprman_init(Object *obj) s->xosc = clock_new(obj, "xosc"); s->gnd = clock_new(obj, "gnd"); - clock_set(s->gnd, 0); + clock_set(s->gnd, 0, NULL); memory_region_init_io(&s->iomem, obj, &cprman_ops, s, "bcm2835-cprman", 0x2000); diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index d2ac2e77f2..e637798507 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -279,9 +279,9 @@ static void zynq_slcr_compute_clocks_internal(ZynqSLCRState *s, uint64_t ps_clk) /* compute uartX reference clocks */ clock_set(s->uart0_ref_clk, - ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0)); + ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0), NULL); clock_set(s->uart1_ref_clk, - ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1)); 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Since all callers ignore the return value, have them use NULL. Signed-off-by: Philippe Mathieu-Daudé --- docs/devel/clocks.rst | 2 +- include/hw/clock.h | 8 ++------ hw/arm/stellaris.c | 2 +- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst index c4d14bde04..3360e5616d 100644 --- a/docs/devel/clocks.rst +++ b/docs/devel/clocks.rst @@ -298,7 +298,7 @@ object during device instance init. For example: clk = qdev_init_clock_in(DEVICE(dev), "clk-in", clk_in_callback, dev, ClockUpdate); /* set initial value to 10ns / 100MHz */ - clock_set_ns(clk, 10); + clock_set_ns(clk, 10, NULL); To enforce that the clock is wired up by the board code, you can call ``clock_has_source()`` in your device's realize method: diff --git a/include/hw/clock.h b/include/hw/clock.h index 474bbc07fe..94ed5ba6e6 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -195,13 +195,9 @@ static inline bool clock_set_hz(Clock *clk, unsigned hz) return changed; } -static inline bool clock_set_ns(Clock *clk, unsigned ns) +static inline void clock_set_ns(Clock *clk, unsigned ns, bool *changed) { - bool changed = false; - - clock_set(clk, CLOCK_PERIOD_FROM_NS(ns), &changed); - - return changed; + clock_set(clk, CLOCK_PERIOD_FROM_NS(ns), changed); } /** diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index a2f998bf9e..d4381beeb7 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -279,7 +279,7 @@ static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) } else { period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1); } - clock_set_ns(s->sysclk, period_ns); + clock_set_ns(s->sysclk, period_ns, NULL); if (propagate_clock) { clock_propagate(s->sysclk); } From patchwork Mon Mar 25 13:32:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 782333 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp1176145wrt; Mon, 25 Mar 2024 06:34:14 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWFSnobMT8O1LzxrAmLGIROyBRSgGzUNbO6kYXgSYclG+kCgvl8NuTZK14PjksHz5KC2+Sy1nJpQUFSG6Obq1FS X-Google-Smtp-Source: AGHT+IHRgzVk9D0Qo5Ug4Szlo6zqncCBNkjis7UPgRCSXb08M7zRnY9kRjv+aaz6zvEl030kfP/+ X-Received: by 2002:a05:620a:38b:b0:78a:3590:d56c with SMTP id q11-20020a05620a038b00b0078a3590d56cmr6768685qkm.41.1711373653894; Mon, 25 Mar 2024 06:34:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711373653; cv=none; d=google.com; s=arc-20160816; b=ztTL+se3yR3fNQ5K8egfkf1zkbK41DBvmYdVMU+UilH/9hVl1tqjTqTDDUZ7TqBBGf mUGx4rmi2YXo7R+fqWbCpYbilVXBH2Xfkir6KpxHYBicTrDD0e+EBc2zN7TWUTGL8kgW 5LZ+QjcZeLW6xIOZ8dWiqex3muzjl5UXLPNmwcj5OnmVTT58TBNRy4DHIsYOpAq11LaJ zUmxrbGP31ub0r+AzbjxeAAHgeowQDdPjSBt6ExYcw/f7sXj8w6bVDenfsvUez+xJHZZ +wfkg02jUIBBT2cimmXNzSd9wuy4xQ1JS3vegwTQGnwGgs1ZPrinOQHLx7t6PakFgE48 jkrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+iChHJV7sNlvRqqjFzQcgZJQ2tuinOgYhEDNJOHyzoE=; fh=sX73gQooOJ/ScGgG3nRK5WElQNOeQmmc0dWD/aseozQ=; b=dG1yyM8BNBzmgk24DBlvZgkPDNlljTMdajV+pco7wGRLhOrp3CxIM1e1VpnSS2gypO 1QZhfzbolJNYFacAK2YXDHGluRCzVIBizxOjv5KtrnMCRAxJT5YmElBYHiEHjXwOziLI NDstHCVBTFRLSmoH9wAWAYeNDrC4bDPOS8nBaL7ZmUeGUxfMNKauPW9bbf9g5wnMud9j QDivj7izaJbO5N75zyvef7fQsptzrrGYYm/kO9jOcmXs3HJjCxfzLjanafwBcNdKX8Tb 3kXWn8rSpbVE0rfeFEgTAw+80l6B3VVFnS2PKpWDE1JCeCHVSk3+G0/Uomd1wfNucRA3 1S2A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yzSINfOc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , =?utf-8?q?Marc-Andr=C3=A9_L?= =?utf-8?q?ureau?= , Paolo Bonzini Subject: [PATCH-for-9.0? v2 4/8] hw/clock: Pass optional &bool argument to clock_set_hz() Date: Mon, 25 Mar 2024 14:32:54 +0100 Message-ID: <20240325133259.57235-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240325133259.57235-1-philmd@linaro.org> References: <20240325133259.57235-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass optional &bool argument to clock_set_ns(). Since all callers ignore the return value, have them use NULL. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/clock.h | 8 ++------ hw/arm/aspeed.c | 2 +- hw/arm/fby35.c | 2 +- hw/arm/mps2-tz.c | 4 ++-- hw/arm/mps2.c | 4 ++-- hw/arm/mps3r.c | 2 +- hw/arm/msf2-som.c | 2 +- hw/arm/musca.c | 4 ++-- hw/arm/netduino2.c | 2 +- hw/arm/netduinoplus2.c | 2 +- hw/arm/nrf51_soc.c | 2 +- hw/arm/olimex-stm32-h405.c | 2 +- hw/arm/stm32vldiscovery.c | 2 +- hw/arm/xilinx_zynq.c | 2 +- hw/char/cadence_uart.c | 4 ++-- 15 files changed, 20 insertions(+), 24 deletions(-) diff --git a/include/hw/clock.h b/include/hw/clock.h index 94ed5ba6e6..f0ac410fc8 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -186,13 +186,9 @@ static inline bool clock_has_source(const Clock *clk) */ void clock_set(Clock *clk, uint64_t period, bool *changed); -static inline bool clock_set_hz(Clock *clk, unsigned hz) +static inline void clock_set_hz(Clock *clk, unsigned hz, bool *changed) { - bool changed = false; - - clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz), &changed); - - return changed; + clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz), changed); } static inline void clock_set_ns(Clock *clk, unsigned ns, bool *changed) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 8854581ca8..7e4ed71e9f 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1521,7 +1521,7 @@ static void aspeed_minibmc_machine_init(MachineState *machine) Clock *sysclk; sysclk = clock_new(OBJECT(machine), "SYSCLK"); - clock_set_hz(sysclk, SYSCLK_FRQ); + clock_set_hz(sysclk, SYSCLK_FRQ, NULL); bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c index c9964bd283..dd4abdd768 100644 --- a/hw/arm/fby35.c +++ b/hw/arm/fby35.c @@ -119,7 +119,7 @@ static void fby35_bic_init(Fby35State *s) AspeedSoCState *soc; s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK"); - clock_set_hz(s->bic_sysclk, 200000000ULL); + clock_set_hz(s->bic_sysclk, 200000000ULL, NULL); object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1"); soc = ASPEED_SOC(&s->bic); diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index a2d18afd79..015db74ab8 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -818,9 +818,9 @@ static void mps2tz_common_init(MachineState *machine) /* These clocks don't need migration because they are fixed-frequency */ mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); - clock_set_hz(mms->sysclk, mmc->sysclk_frq); + clock_set_hz(mms->sysclk, mmc->sysclk_frq, NULL); mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); - clock_set_hz(mms->s32kclk, S32KCLK_FRQ); + clock_set_hz(mms->s32kclk, S32KCLK_FRQ, NULL); object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, mmc->armsse_type); diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 50919ee46d..7176305239 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -151,10 +151,10 @@ static void mps2_common_init(MachineState *machine) /* This clock doesn't need migration because it is fixed-frequency */ mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); - clock_set_hz(mms->sysclk, SYSCLK_FRQ); + clock_set_hz(mms->sysclk, SYSCLK_FRQ, NULL); mms->refclk = clock_new(OBJECT(machine), "REFCLK"); - clock_set_hz(mms->refclk, REFCLK_FRQ); + clock_set_hz(mms->refclk, REFCLK_FRQ, NULL); /* The FPGA images have an odd combination of different RAMs, * because in hardware they are different implementations and diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c index 4d55a6564c..84f1f9d3a2 100644 --- a/hw/arm/mps3r.c +++ b/hw/arm/mps3r.c @@ -360,7 +360,7 @@ static void mps3r_common_init(MachineState *machine) QList *oscclk; mms->clk = clock_new(OBJECT(machine), "CLK"); - clock_set_hz(mms->clk, CLK_FRQ); + clock_set_hz(mms->clk, CLK_FRQ, NULL); for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) { MemoryRegion *mr = mr_for_raminfo(mms, ri); diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index 5c415abe85..420c0ae332 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -71,7 +71,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine) */ /* This clock doesn't need migration because it is fixed-frequency */ m3clk = clock_new(OBJECT(machine), "m3clk"); - clock_set_hz(m3clk, 142 * 1000000); + clock_set_hz(m3clk, 142 * 1000000, NULL); qdev_connect_clock_in(dev, "m3clk", m3clk); qdev_prop_set_uint32(dev, "apb0div", 2); qdev_prop_set_uint32(dev, "apb1div", 2); diff --git a/hw/arm/musca.c b/hw/arm/musca.c index e2c9d49af5..6fdcb76dfa 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -366,9 +366,9 @@ static void musca_init(MachineState *machine) assert(mmc->num_mpcs <= MUSCA_MPC_MAX); mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); - clock_set_hz(mms->sysclk, SYSCLK_FRQ); + clock_set_hz(mms->sysclk, SYSCLK_FRQ, NULL); mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); - clock_set_hz(mms->s32kclk, S32KCLK_FRQ); + clock_set_hz(mms->s32kclk, S32KCLK_FRQ, NULL); object_initialize_child(OBJECT(machine), "sse-200", &mms->sse, TYPE_SSE200); diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 8b1a9a2437..49a3ee2c47 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -41,7 +41,7 @@ static void netduino2_init(MachineState *machine) /* This clock doesn't need migration because it is fixed-frequency */ sysclk = clock_new(OBJECT(machine), "SYSCLK"); - clock_set_hz(sysclk, SYSCLK_FRQ); + clock_set_hz(sysclk, SYSCLK_FRQ, NULL); dev = qdev_new(TYPE_STM32F205_SOC); object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index bccd100354..30d9c0410d 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -41,7 +41,7 @@ static void netduinoplus2_init(MachineState *machine) /* This clock doesn't need migration because it is fixed-frequency */ sysclk = clock_new(OBJECT(machine), "SYSCLK"); - clock_set_hz(sysclk, SYSCLK_FRQ); + clock_set_hz(sysclk, SYSCLK_FRQ, NULL); dev = qdev_new(TYPE_STM32F405_SOC); object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index ac53441630..9aebb98934 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -75,7 +75,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) return; } /* This clock doesn't need migration because it is fixed-frequency */ - clock_set_hz(s->sysclk, HCLK_FRQ); + clock_set_hz(s->sysclk, HCLK_FRQ, NULL); qdev_connect_clock_in(DEVICE(&s->cpu), "cpuclk", s->sysclk); /* * This SoC has no systick device, so don't connect refclk. diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c index 4ad7b043be..394875608a 100644 --- a/hw/arm/olimex-stm32-h405.c +++ b/hw/arm/olimex-stm32-h405.c @@ -44,7 +44,7 @@ static void olimex_stm32_h405_init(MachineState *machine) /* This clock doesn't need migration because it is fixed-frequency */ sysclk = clock_new(OBJECT(machine), "SYSCLK"); - clock_set_hz(sysclk, SYSCLK_FRQ); + clock_set_hz(sysclk, SYSCLK_FRQ, NULL); dev = qdev_new(TYPE_STM32F405_SOC); object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index cc41935160..4be626e878 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -44,7 +44,7 @@ static void stm32vldiscovery_init(MachineState *machine) /* This clock doesn't need migration because it is fixed-frequency */ sysclk = clock_new(OBJECT(machine), "SYSCLK"); - clock_set_hz(sysclk, SYSCLK_FRQ); + clock_set_hz(sysclk, SYSCLK_FRQ, NULL); dev = qdev_new(TYPE_STM32F100_SOC); object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index fc3abcbe88..1fd13caa58 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -228,7 +228,7 @@ static void zynq_init(MachineState *machine) object_property_add_child(OBJECT(zynq_machine), "ps_clk", OBJECT(zynq_machine->ps_clk)); object_unref(OBJECT(zynq_machine->ps_clk)); - clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY); + clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY, NULL); /* Create slcr, keep a pointer to connect clocks */ slcr = qdev_new("xilinx-zynq_slcr"); diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index db31d7cc85..4619209af4 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -566,7 +566,7 @@ static void cadence_uart_init(Object *obj) s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", cadence_uart_refclk_update, s, ClockUpdate); /* initialize the frequency in case the clock remains unconnected */ - clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK); + clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK, NULL); s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10; } @@ -576,7 +576,7 @@ static int cadence_uart_pre_load(void *opaque) CadenceUARTState *s = opaque; /* the frequency will be overridden if the refclk field is present */ - clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK); + clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK, NULL); return 0; } From patchwork Mon Mar 25 13:32:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 782337 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp1176626wrt; Mon, 25 Mar 2024 06:35:11 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWF7e6ZLDHGZBVDFN8aO6Si+ciXPoYsRi2xShSfgj8t38omLtp5VfGOaFs5rnXugxiupKLc6qogpjBeVeK2i7cR X-Google-Smtp-Source: AGHT+IGY6I/XVE2BAGHam9Mg670g3/nxV6mXG3gllXE2JOjpcK6syTWmEmPVMKuME5nwl9vbpzW0 X-Received: by 2002:ac8:5cc3:0:b0:431:49c1:cfc6 with SMTP id s3-20020ac85cc3000000b0043149c1cfc6mr7770929qta.20.1711373711051; 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Since all callers ignore the return value, have them use NULL. Signed-off-by: Philippe Mathieu-Daudé --- docs/devel/clocks.rst | 4 ++++ include/hw/clock.h | 3 ++- hw/arm/msf2-soc.c | 2 +- hw/arm/stm32f100_soc.c | 2 +- hw/arm/stm32f205_soc.c | 2 +- hw/arm/stm32f405_soc.c | 2 +- hw/core/clock.c | 7 ++++++- hw/misc/stm32l4x5_rcc.c | 2 +- 8 files changed, 17 insertions(+), 7 deletions(-) diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst index 3360e5616d..027a3c5dbc 100644 --- a/docs/devel/clocks.rst +++ b/docs/devel/clocks.rst @@ -279,6 +279,10 @@ You can change the multiplier and divider of a clock at runtime, so you can use this to model clock controller devices which have guest-programmable frequency multipliers or dividers. +Similary to ``clock_set()``, ``clock_set_mul_div()`` takes an optional +boolean pointer which is set to ``true`` if the clock state was modified, +that it, if the multiplier or the diviser or both were changed by the call. + Note that ``clock_set_mul_div()`` does not automatically call ``clock_propagate()``. If you make a runtime change to the multiplier or divider you must call clock_propagate() yourself. diff --git a/include/hw/clock.h b/include/hw/clock.h index f0ac410fc8..0e4c5b67a2 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -376,6 +376,7 @@ char *clock_display_freq(Clock *clk); * Note that this function does not call clock_propagate(); the * caller should do that if necessary. */ -void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider); +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider, + bool *changed); #endif /* QEMU_HW_CLOCK_H */ diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index a94a10adcc..7257bd5ded 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -111,7 +111,7 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) * implement the divisor as a fixed /32, which matches the reset value * of SYSTICK_CR. */ - clock_set_mul_div(s->refclk, 32, 1); + clock_set_mul_div(s->refclk, 32, 1, NULL); clock_set_source(s->refclk, s->m3clk); memory_region_init_rom(&s->nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_size, diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c index 808b783515..4879bd6188 100644 --- a/hw/arm/stm32f100_soc.c +++ b/hw/arm/stm32f100_soc.c @@ -93,7 +93,7 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp) */ /* The refclk always runs at frequency HCLK / 8 */ - clock_set_mul_div(s->refclk, 8, 1); + clock_set_mul_div(s->refclk, 8, 1, NULL); clock_set_source(s->refclk, s->sysclk); /* diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index a451e21f59..aeb0cb0a5a 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -110,7 +110,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) */ /* The refclk always runs at frequency HCLK / 8 */ - clock_set_mul_div(s->refclk, 8, 1); + clock_set_mul_div(s->refclk, 8, 1, NULL); clock_set_source(s->refclk, s->sysclk); memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash", diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c index 2ad5b79a06..07cf0e8287 100644 --- a/hw/arm/stm32f405_soc.c +++ b/hw/arm/stm32f405_soc.c @@ -115,7 +115,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) */ /* The refclk always runs at frequency HCLK / 8 */ - clock_set_mul_div(s->refclk, 8, 1); + clock_set_mul_div(s->refclk, 8, 1, NULL); clock_set_source(s->refclk, s->sysclk); memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F405.flash", diff --git a/hw/core/clock.c b/hw/core/clock.c index e0f257b141..6ef60a2423 100644 --- a/hw/core/clock.c +++ b/hw/core/clock.c @@ -145,7 +145,8 @@ char *clock_display_freq(Clock *clk) return freq_to_str(clock_get_hz(clk)); } -void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider) +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider, + bool *changed) { assert(divider != 0); @@ -157,6 +158,10 @@ void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider) clk->divider, divider); clk->multiplier = multiplier; clk->divider = divider; + + if (changed) { + *changed = true; + } } static void clock_initfn(Object *obj) diff --git a/hw/misc/stm32l4x5_rcc.c b/hw/misc/stm32l4x5_rcc.c index bc2d63528b..f01113308a 100644 --- a/hw/misc/stm32l4x5_rcc.c +++ b/hw/misc/stm32l4x5_rcc.c @@ -59,7 +59,7 @@ static void clock_mux_update(RccClockMuxState *mux, bool bypass_source) freq_multiplier = mux->divider; } - clock_set_mul_div(mux->out, freq_multiplier, mux->multiplier); + clock_set_mul_div(mux->out, freq_multiplier, mux->multiplier, NULL); clock_update(mux->out, clock_get(current_source)); src_freq = clock_get_hz(current_source); From patchwork Mon Mar 25 13:32:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 782336 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp1176456wrt; Mon, 25 Mar 2024 06:34:50 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXfofBBPuT/Ym430swW7hg9XjxeAAS2rszvsVhE6HLP7aJunXKkGnimXKO6XMHlbCYnSi1kqvc3VjC/MpLGf2n+ X-Google-Smtp-Source: AGHT+IHo4WARRxh2ZZ9ttT4HayCLljbXLBeHFYz8YfUa6AzRdPnhEqRl/tkdnwhu9e9fSCVGHUKa X-Received: by 2002:a05:620a:1a:b0:788:2ada:3a3d with SMTP id j26-20020a05620a001a00b007882ada3a3dmr7154384qki.24.1711373690366; Mon, 25 Mar 2024 06:34:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; 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Signed-off-by: Philippe Mathieu-Daudé --- hw/misc/stm32l4x5_rcc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/misc/stm32l4x5_rcc.c b/hw/misc/stm32l4x5_rcc.c index f01113308a..8852b434db 100644 --- a/hw/misc/stm32l4x5_rcc.c +++ b/hw/misc/stm32l4x5_rcc.c @@ -48,6 +48,8 @@ static void clock_mux_update(RccClockMuxState *mux, bool bypass_source) uint64_t src_freq; Clock *current_source = mux->srcs[mux->src]; uint32_t freq_multiplier = 0; + bool clk_changed = false; + /* * To avoid rounding errors, we use the clock period instead of the * frequency. @@ -60,7 +62,10 @@ static void clock_mux_update(RccClockMuxState *mux, bool bypass_source) } clock_set_mul_div(mux->out, freq_multiplier, mux->multiplier, NULL); - clock_update(mux->out, clock_get(current_source)); + clock_set(mux->out, clock_get(current_source), &clk_changed); + if (clk_changed) { + clock_propagate(mux->out); + } src_freq = clock_get_hz(current_source); /* TODO: can we simply detect if the config changed so that we reduce log spam ? */ From patchwork Mon Mar 25 13:32:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 782335 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp1176286wrt; Mon, 25 Mar 2024 06:34:30 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUECs+NJkYKGahlo7KDjq/Fg1LGWVs3RzfAQPuMMvfOfnn2U6R6hAtCbDFfoXjAwJAy6dyVRqtDl7Pguby9XMsm X-Google-Smtp-Source: AGHT+IFC1KMvSvpxRASgPumEUqpm2zwCxZMqEGFnb9DAuY4UZPO/V179M1Ya+8Mp5IcW9kElesha X-Received: by 2002:a9d:6318:0:b0:6e6:99d9:adc3 with SMTP id q24-20020a9d6318000000b006e699d9adc3mr9042427otk.24.1711373670672; Mon, 25 Mar 2024 06:34:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711373670; cv=none; d=google.com; s=arc-20160816; b=xo+WpNtElYMMCr2ZCh9hKogeUp9Q9pzAVxMKy9lD9uXxnPhj8IPToR6+HDzPecPLyk l2hbHPomllo9oq1LlaMoc+r0hGnYWL7x7Fv/XjzKNWVp7hFFs7Ke6SuhhctceMdVJJXE at75FV/fqzo4Ufv06pdobxzWWOSCqQFkgEaus0f8E+WcEVRO/AJ3l//jArbGBXdql6Wo 1ePre6unPNjetERgetUhkZYUaxfOxhKdamlJvQbeVdbnSYNBfngvL8X1QjoenKQEuvw4 N63ZbTUOO2gwt++ce2NqPo+50FBDLX/ISZTvwiOIGCLJzs3GutaiWHnax8YfMo94GoIq p5+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dmBZnvObELGs1VJCtsjfXQQHR8FYa+eCE52ifx9aDFo=; fh=Z6ebApcLFJbaZHsWuXWH2AHWI2xWYXqDDJv2NwjBOYY=; b=wR02ErgNil55vH8phok0D1o8hRNSu67v+B6DuC2Pv4smK7qmsT2vSLM7imJ05JHjpy eLpU31WJDEV0pJ7z4ZtYKbKHPgZk2/n9UWec9PIZjnFCQpF6OnBnraarXMKaharn4ioc yJ1HCkRI5RSrOgvD76Zf4VlsUFCJZlIo+fQhOGtSep+gp+6yqi1ujfjKk96WilL8nlBh Mum27CXw1HYV7hf9XAOWk6fCjx0xH4W9Vsa+sJQSSjUgnUXhP5rp7gH1Bmg+QQm/srdC pRruRW4OwWpV4MbHzwA8L5CNAM6QMZPt7qcBFOxZ1Orzjs94EgMWbDgllYC4ou6tndzo 5PbA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TkcmmaY3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This was overlooked during the implementation due to late changes. This commit propagates the change if the multiplier or divider changes. Fixes: ec7d83acbd ("hw/misc/stm32l4x5_rcc: Add an internal clock multiplexer object") Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Message-ID: <20240317103918.44375-2-arnaud.minier@telecom-paris.fr> [PMD: Pass argument to clock_set_mul_div()] Signed-off-by: Philippe Mathieu-Daudé --- hw/misc/stm32l4x5_rcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/misc/stm32l4x5_rcc.c b/hw/misc/stm32l4x5_rcc.c index 8852b434db..166c727e52 100644 --- a/hw/misc/stm32l4x5_rcc.c +++ b/hw/misc/stm32l4x5_rcc.c @@ -61,7 +61,7 @@ static void clock_mux_update(RccClockMuxState *mux, bool bypass_source) freq_multiplier = mux->divider; } - clock_set_mul_div(mux->out, freq_multiplier, mux->multiplier, NULL); + clock_set_mul_div(mux->out, freq_multiplier, mux->multiplier, &clk_changed); clock_set(mux->out, clock_get(current_source), &clk_changed); if (clk_changed) { clock_propagate(mux->out); From patchwork Mon Mar 25 13:32:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 782339 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp1176837wrt; Mon, 25 Mar 2024 06:35:38 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUkxJi7Zrw7fXlqb8yoF0gT8RppF0PVbz0IGqwgLIhIDoZUUsyR8nXx2fWdD4OJyXCv/SnBwm0Y/aCGW9PUmoma X-Google-Smtp-Source: AGHT+IE1wd7mIuJtA/qVFX4OxyklHKAQxqoNAFyNw0qsqWuBXHS8MxEzzg+AVEvf5cMilK8HVEEp X-Received: by 2002:a05:622a:1883:b0:431:2051:4798 with SMTP id v3-20020a05622a188300b0043120514798mr8858436qtc.14.1711373738246; Mon, 25 Mar 2024 06:35:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711373738; cv=none; d=google.com; s=arc-20160816; b=eLSRVBGqMMrn71o+u0CM2a63ceIc3NRDP6lRgsvpwmIlyRf6pZ9Hxs+IwSSiX5iynd A9PuxR4J/AunddUO4P54H7DrQWzNsfENKkVJoFUyIpU6kHmbqABYblr5bjm2/kobZipC zwoCD3GIrD4GcvQvrsips9HxM36FsVH2f0OhfR2eunB34WS75ljAH5j9fP37jVCazK+T tqHvoBkrIeqw9ILjrGfSI3zatcWulxRYKgM4u+z7fi/ARU/FmNSqzQ3yO5I11YSQqH8h X0y0byca9CcvTHPOq6yyWgVyu7iXdtUXnmcbaLHVjo2GdlFyVG77vmORXJnqBEpGnueK qIPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cC2Yz91nzGrohL4G/Awv0+dd4I3kt82iWAFcfxuwSZM=; fh=t3X8QBlUt8lTNNYLmXnvt7uYZqjf0Fo0hWn60R6P6ms=; b=EAywQ83/8/YyeIPCGg1HHkfmB4kbumpdN/u+DilcnstAe9c3kbdXwPmreobt7WRQBb ut9u4GdForsN7izvBNszoA4RDSF5Ba72CUizGqwN0jeCbT8+NOgj+fSk4fAMMRyvnLMZ /CiqBxeVW+TLiYC9lmUmwgxXTrAc7/i8B/nz793y19W1TYNpzeldRIt3b/yFq0LjsIDZ dNJtJtjlaHEahoCdkzn0BOEJF/PW81x61XnRxBNCmyNpRjs6SN2+2j5wL5XE22JVaWkS pHW7Uzooi+4cK0s6cnFHCGJwZlqGo0eRBrOze6avAgHFsat33NQidkou+OD/ycTPrTIy ClQQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=c4m9fmaT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" Subject: [PATCH-for-9.1 v2 8/8] hw/misc/zynq_slcr: Only propagate clock changes when necessary Date: Mon, 25 Mar 2024 14:32:58 +0100 Message-ID: <20240325133259.57235-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240325133259.57235-1-philmd@linaro.org> References: <20240325133259.57235-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=philmd@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass &bool to zynq_slcr_compute_clocks[_internal](), so we can pass it to the clock_set() calls which might update it. Then check it and only call zynq_slcr_propagate_clocks() and clock_propagate() when necessary. Signed-off-by: Philippe Mathieu-Daudé --- hw/misc/zynq_slcr.c | 39 ++++++++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 13 deletions(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index e637798507..ad9c575137 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -269,7 +269,8 @@ static uint64_t zynq_slcr_compute_clock(const uint64_t periods[], zynq_slcr_compute_clock((plls), (state)->regs[reg], \ reg ## _ ## enable_field ## _SHIFT) -static void zynq_slcr_compute_clocks_internal(ZynqSLCRState *s, uint64_t ps_clk) +static void zynq_slcr_compute_clocks_internal(ZynqSLCRState *s, uint64_t ps_clk, + bool *changed) { uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]); uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]); @@ -279,9 +280,9 @@ static void zynq_slcr_compute_clocks_internal(ZynqSLCRState *s, uint64_t ps_clk) /* compute uartX reference clocks */ clock_set(s->uart0_ref_clk, - ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0), NULL); + ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0), changed); clock_set(s->uart1_ref_clk, - ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1), NULL); + ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1), changed); } /** @@ -289,7 +290,7 @@ static void zynq_slcr_compute_clocks_internal(ZynqSLCRState *s, uint64_t ps_clk) * But do not propagate them further. Connected clocks * will not receive any updates (See zynq_slcr_compute_clocks()) */ -static void zynq_slcr_compute_clocks(ZynqSLCRState *s) +static void zynq_slcr_compute_clocks(ZynqSLCRState *s, bool *changed) { uint64_t ps_clk = clock_get(s->ps_clk); @@ -298,7 +299,7 @@ static void zynq_slcr_compute_clocks(ZynqSLCRState *s) ps_clk = 0; } - zynq_slcr_compute_clocks_internal(s, ps_clk); + zynq_slcr_compute_clocks_internal(s, ps_clk, changed); } /** @@ -315,9 +316,12 @@ static void zynq_slcr_propagate_clocks(ZynqSLCRState *s) static void zynq_slcr_ps_clk_callback(void *opaque, ClockEvent event) { ZynqSLCRState *s = (ZynqSLCRState *) opaque; + bool propagate = false; - zynq_slcr_compute_clocks(s); - zynq_slcr_propagate_clocks(s); + zynq_slcr_compute_clocks(s, &propagate); + if (propagate) { + zynq_slcr_propagate_clocks(s); + } } static void zynq_slcr_reset_init(Object *obj, ResetType type) @@ -419,19 +423,25 @@ static void zynq_slcr_reset_init(Object *obj, ResetType type) static void zynq_slcr_reset_hold(Object *obj) { ZynqSLCRState *s = ZYNQ_SLCR(obj); + bool propagate = false; /* will disable all output clocks */ - zynq_slcr_compute_clocks_internal(s, 0); - zynq_slcr_propagate_clocks(s); + zynq_slcr_compute_clocks_internal(s, 0, &propagate); + if (propagate) { + zynq_slcr_propagate_clocks(s); + } } static void zynq_slcr_reset_exit(Object *obj) { ZynqSLCRState *s = ZYNQ_SLCR(obj); + bool propagate = false; /* will compute output clocks according to ps_clk and registers */ - zynq_slcr_compute_clocks_internal(s, clock_get(s->ps_clk)); - zynq_slcr_propagate_clocks(s); + zynq_slcr_compute_clocks_internal(s, clock_get(s->ps_clk), &propagate); + if (propagate) { + zynq_slcr_propagate_clocks(s); + } } static bool zynq_slcr_check_offset(hwaddr offset, bool rnw) @@ -516,6 +526,7 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) { ZynqSLCRState *s = (ZynqSLCRState *)opaque; + bool propagate = false; offset /= 4; DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4, val); @@ -569,8 +580,10 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, case R_ARM_PLL_CTRL: case R_DDR_PLL_CTRL: case R_UART_CLK_CTRL: - zynq_slcr_compute_clocks(s); - zynq_slcr_propagate_clocks(s); + zynq_slcr_compute_clocks(s, &propagate); + if (propagate) { + zynq_slcr_propagate_clocks(s); + } break; } }