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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id q12-20020aa7982c000000b006e6b4c637b6sm3291880pfl.116.2024.03.24.20.04.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Mar 2024 20:04:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 1/3] targt/hppa: Fix DCOR reconstruction of carry bits Date: Sun, 24 Mar 2024 17:04:46 -1000 Message-Id: <20240325030448.52110-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240325030448.52110-1-richard.henderson@linaro.org> References: <20240325030448.52110-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The carry bits for each nibble N are located in bit (N+1)*4, so the shift by 3 was off by one. Furthermore, the carry bit for the most significant carry bit is indeed located in bit 64, which is located in a different storage word. Use a double-word shift-right to reassemble into a single word and place them all at bit 0 of their respective nibbles. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller Tested-by: Helge Deller --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e041310207..a3f425d861 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2791,7 +2791,7 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i) nullify_over(ctx); tmp = tcg_temp_new_i64(); - tcg_gen_shri_i64(tmp, cpu_psw_cb, 3); + tcg_gen_extract2_i64(tmp, cpu_psw_cb, cpu_psw_cb_msb, 4); if (!is_i) { tcg_gen_not_i64(tmp, tmp); } From patchwork Mon Mar 25 03:04:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 782311 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp970950wrt; Sun, 24 Mar 2024 20:06:08 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVp3hqHtjGjF1P2UvZEs/Fhj08vVXBKXcpQ8gmbgG4cLRVDtomGPZ10pN0FHOllRvaNCvdmO+J4YU8KCZNZpuYP X-Google-Smtp-Source: AGHT+IG3S3oBtPAz8BFxnTRnZYbF94RrpUfdlE5372Hk0l734DRy6L/uwozlwtppxUNtub8Xrlv/ X-Received: by 2002:a05:6214:3002:b0:696:8de9:dbf with SMTP id ke2-20020a056214300200b006968de90dbfmr2240358qvb.0.1711335968409; Sun, 24 Mar 2024 20:06:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711335968; cv=none; d=google.com; s=arc-20160816; b=k7eTfRsRMCT4e+lHi0cwGs8P74+Ei8JlG4ZFg+d3/ohGb1m/8BIw0qkLjXSVPoiZCO Z+Sap+CIIaZAFtytlDRoibCMrN+6b8IfCWIwOQNDJ4+eA817YLvmhpZNqAPX7ummbPtY EApIYdKUbdAWIBsD7vTadatTm+jd1Z764n0mYANMfqzeldJ0yhpVNMtir4zC7nmJLWMl bwdz5rEJhoWSNICU1QzFnjHW4KM/AHp3PlHKjzS+S43CVEA45dPg8ah3r23QH2qmzMAM pAzvKrByVy6/cLEtFVD3D28/kXGzjqLTZaGTRhU/GF11GrmN7XExVjWX6nlTsk3fJAP4 aD1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zRr5RGAyB8xudWpBYabctLeDWU/P34mdZOuJNR73ZqU=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=QeFwPnnGsMBJAg8PSPtPZwMeiAiY53zchLiTv/5I/onmsSrkXLysrW2OTH6cMQwXl6 a/AQEJwP+l02tOYijRca40b79ndM62ZVCCNivMQVADH4KcJHQyVynscUVDxqOcYhp5Yp dQz5swDjuCzOPDF8HjLIjbc2TB4KAbwoWmP5fpDLpvvbzOr7ZN+4eaw1J3ES2tbpgg/B RTk7XPOdLMz/+z34Orr5UAeZRUr/QvLefleADK6iqNPmbKf7OJQdO8XXP7uzkZZPnmQb udIEt3Q2+nJCGhqV2A2TtKrnfaLKHlUVV4d7O+2Qt1rucxaWZDnY8YhlL1TXu6y9C6Ys ohDw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N+98b+VO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id q12-20020aa7982c000000b006e6b4c637b6sm3291880pfl.116.2024.03.24.20.04.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Mar 2024 20:04:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 2/3] target/hppa: Optimize UADDCM with no condition Date: Sun, 24 Mar 2024 17:04:47 -1000 Message-Id: <20240325030448.52110-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240325030448.52110-1-richard.henderson@linaro.org> References: <20240325030448.52110-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org With r1 as zero is by far the only usage of UADDCM, as the easiest way to invert a register. The compiler does occasionally use the addition step as well, and we can simplify that to avoid a temp and write directly into the destination. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller Tested-by: Helge Deller --- target/hppa/translate.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index a3f425d861..3fc3e7754c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2763,9 +2763,29 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc) { TCGv_i64 tcg_r1, tcg_r2, tmp; - if (a->cf) { - nullify_over(ctx); + if (a->cf == 0) { + tcg_r2 = load_gpr(ctx, a->r2); + tmp = dest_gpr(ctx, a->t); + + if (a->r1 == 0) { + /* UADDCM r0,src,dst is the common idiom for dst = ~src. */ + tcg_gen_not_i64(tmp, tcg_r2); + } else { + /* + * Recall that r1 - r2 == r1 + ~r2 + 1. + * Thus r1 + ~r2 == r1 - r2 - 1, + * which does not require an extra temporary. + */ + tcg_r1 = load_gpr(ctx, a->r1); + tcg_gen_sub_i64(tmp, tcg_r1, tcg_r2); + tcg_gen_subi_i64(tmp, tmp, 1); + } + save_gpr(ctx, a->t, tmp); + cond_free(&ctx->null_cond); + return true; } + + nullify_over(ctx); tcg_r1 = load_gpr(ctx, a->r1); tcg_r2 = load_gpr(ctx, a->r2); tmp = tcg_temp_new_i64(); From patchwork Mon Mar 25 03:04:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 782310 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:b0:33e:7753:30bd with SMTP id p1csp970861wrt; Sun, 24 Mar 2024 20:05:49 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUzBiU3v3UkTY2Gdi0PuLo+cj0/fxgQBxeQWQ2a3t1qS8OZfYtxG2Is1wEaey6uMz5bEDZRs2G+e3likI9K+LZn X-Google-Smtp-Source: AGHT+IEc1zYfq45XpeetEtAHh9AoYvinmjRxBuOKtOwPuv05lzk3wMzHuzTSwMDmIpBGBDcAkhKW X-Received: by 2002:a25:9703:0:b0:dc7:45d3:ffd0 with SMTP id d3-20020a259703000000b00dc745d3ffd0mr4210104ybo.1.1711335948913; Sun, 24 Mar 2024 20:05:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1711335948; cv=none; d=google.com; s=arc-20160816; b=SV5o+nETUas5vqLqotnoK5I/k08N8rrmBuFYk4m8lClKyXGw/Sv1lFBFViKQHHZBQj 7ynJFHHC4OPmRqG5VdvRFtugr7/8rEdx64HGZPR9DMJpSrsgjLk85KV5vme1lKa9Caro ZeWxt+kSoqF1jUJ6AZbXS2FoxH5Q9/TU+xLV8Uxq4pzxjoWDWPYR+FgMHWt8vhLPX3JW Ff/15Ci+XPZNc7v5guHGdAGI0XGeCXFkEQ46OA9qYzWweQMojxYlrOys+Lws6gfI4zup ihT5DpHzoKVFDiay3FQGNF9nmS7AzfPonBAPwXlVNjnjhf5RBx13wsEiRAn1eZNDHApq xETg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3ygd2hohHyz1hjnK91t3c4RKZU1JwhP7r3ax20czZi4=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=uc8ujPyLlZ7UGz0TPdkrFJ+BCa8UWfHfQHjSIFqOoqPSnIkY8LMQ4A22H2WVUcY+Aj zBOJGqFPQo2iMqTaM/BLGwkMVmiFyWZwBOIgtuLTTV8czGo8xZtz58LjIpB+Z3ejc3gz mqgoqNH/1ZPVEUxRa8DOvnucju4LHI6pGHPVum+3zlU9HLUal1hHMdPmXPvlOrzR4MrP 2BkxIk2jNawLkMc3ZHVEmlEgVj81aotaL7dpTCdCzWvadOjtklFShLCWG4g6NJsvw9fk xbrHiobn5aXpV4dKhe6j0ux/ZDazdrI5WXRs32MTcvsBT9/O+S09HAIasmisSjCCIvz4 883g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Hol11W7r; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id q12-20020aa7982c000000b006e6b4c637b6sm3291880pfl.116.2024.03.24.20.04.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Mar 2024 20:04:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 3/3] target/hppa: Fix unit carry conditions Date: Sun, 24 Mar 2024 17:04:48 -1000 Message-Id: <20240325030448.52110-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240325030448.52110-1-richard.henderson@linaro.org> References: <20240325030448.52110-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Split do_unit_cond to do_unit_zero_cond to only handle conditions versus zero. These are the only ones that are legal for UXOR. Simplify trans_uxor accordingly. Rename do_unit to do_unit_addsub, since xor has been split. Properly compute carry-out bits for add and subtract, mirroring the code in do_add and do_sub. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 214 ++++++++++++++++++++-------------------- 1 file changed, 109 insertions(+), 105 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3fc3e7754c..2bf213c938 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -936,98 +936,44 @@ static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, bool d, return do_log_cond(ctx, c * 2 + f, d, res); } -/* Similar, but for unit conditions. */ - -static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_i64 res, - TCGv_i64 in1, TCGv_i64 in2) +/* Similar, but for unit zero conditions. */ +static DisasCond do_unit_zero_cond(unsigned cf, bool d, TCGv_i64 res) { - DisasCond cond; - TCGv_i64 tmp, cb = NULL; + TCGv_i64 tmp; uint64_t d_repl = d ? 0x0000000100000001ull : 1; - - if (cf & 8) { - /* Since we want to test lots of carry-out bits all at once, do not - * do our normal thing and compute carry-in of bit B+1 since that - * leaves us with carry bits spread across two words. - */ - cb = tcg_temp_new_i64(); - tmp = tcg_temp_new_i64(); - tcg_gen_or_i64(cb, in1, in2); - tcg_gen_and_i64(tmp, in1, in2); - tcg_gen_andc_i64(cb, cb, res); - tcg_gen_or_i64(cb, cb, tmp); - } + uint64_t ones = 0, sgns = 0; switch (cf >> 1) { - case 0: /* never / TR */ - cond = cond_make_f(); - break; - case 1: /* SBW / NBW */ if (d) { - tmp = tcg_temp_new_i64(); - tcg_gen_subi_i64(tmp, res, d_repl * 0x00000001u); - tcg_gen_andc_i64(tmp, tmp, res); - tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80000000u); - cond = cond_make_0(TCG_COND_NE, tmp); - } else { - /* undefined */ - cond = cond_make_f(); + ones = d_repl; + sgns = d_repl << 31; } break; - case 2: /* SBZ / NBZ */ - /* See hasless(v,1) from - * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord - */ - tmp = tcg_temp_new_i64(); - tcg_gen_subi_i64(tmp, res, d_repl * 0x01010101u); - tcg_gen_andc_i64(tmp, tmp, res); - tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80808080u); - cond = cond_make_0(TCG_COND_NE, tmp); + ones = d_repl * 0x01010101u; + sgns = ones << 7; break; - case 3: /* SHZ / NHZ */ - tmp = tcg_temp_new_i64(); - tcg_gen_subi_i64(tmp, res, d_repl * 0x00010001u); - tcg_gen_andc_i64(tmp, tmp, res); - tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80008000u); - cond = cond_make_0(TCG_COND_NE, tmp); + ones = d_repl * 0x00010001u; + sgns = ones << 15; break; - - case 4: /* SDC / NDC */ - tcg_gen_andi_i64(cb, cb, d_repl * 0x88888888u); - cond = cond_make_0(TCG_COND_NE, cb); - break; - - case 5: /* SWC / NWC */ - if (d) { - tcg_gen_andi_i64(cb, cb, d_repl * 0x80000000u); - cond = cond_make_0(TCG_COND_NE, cb); - } else { - /* undefined */ - cond = cond_make_f(); - } - break; - - case 6: /* SBC / NBC */ - tcg_gen_andi_i64(cb, cb, d_repl * 0x80808080u); - cond = cond_make_0(TCG_COND_NE, cb); - break; - - case 7: /* SHC / NHC */ - tcg_gen_andi_i64(cb, cb, d_repl * 0x80008000u); - cond = cond_make_0(TCG_COND_NE, cb); - break; - - default: - g_assert_not_reached(); } - if (cf & 1) { - cond.c = tcg_invert_cond(cond.c); + if (ones == 0) { + /* Undefined, or 0/1 (never/always). */ + return cf & 1 ? cond_make_t() : cond_make_f(); } - return cond; + /* + * See hasless(v,1) from + * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord + */ + tmp = tcg_temp_new_i64(); + tcg_gen_subi_i64(tmp, res, ones); + tcg_gen_andc_i64(tmp, tmp, res); + + return cond_make_tmp(cf & 1 ? TCG_COND_TSTEQ : TCG_COND_TSTNE, + tmp, tcg_constant_i64(sgns)); } static TCGv_i64 get_carry(DisasContext *ctx, bool d, @@ -1330,34 +1276,82 @@ static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a, return nullify_end(ctx); } -static void do_unit(DisasContext *ctx, unsigned rt, TCGv_i64 in1, - TCGv_i64 in2, unsigned cf, bool d, bool is_tc, - void (*fn)(TCGv_i64, TCGv_i64, TCGv_i64)) +static void do_unit_addsub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, + TCGv_i64 in2, unsigned cf, bool d, + bool is_tc, bool is_add) { - TCGv_i64 dest; + TCGv_i64 dest, cb = NULL; + uint64_t test_cb = 0; DisasCond cond; - if (cf == 0) { - dest = dest_gpr(ctx, rt); - fn(dest, in1, in2); - save_gpr(ctx, rt, dest); - cond_free(&ctx->null_cond); - } else { - dest = tcg_temp_new_i64(); - fn(dest, in1, in2); - - cond = do_unit_cond(cf, d, dest, in1, in2); - - if (is_tc) { - TCGv_i64 tmp = tcg_temp_new_i64(); - tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); - gen_helper_tcond(tcg_env, tmp); + /* Select which carry-out bits to test. */ + switch (cf >> 1) { + case 4: /* NDC / SDC -- 4-bit carries */ + test_cb = 0x8888888888888888ull; + break; + case 5: /* NWC / SWC -- 32-bit carries */ + if (d) { + test_cb = 0x8000000080000000ull; + } else { + cf &= 1; /* undefined -- map to never/always */ } - save_gpr(ctx, rt, dest); - - cond_free(&ctx->null_cond); - ctx->null_cond = cond; + break; + case 6: /* NBC / SBC -- 8-bit carries */ + test_cb = 0x8080808080808080ull; + break; + case 7: /* NHC / SHC -- 16-bit carries */ + test_cb = 0x8000800080008000ull; + break; } + + dest = tcg_temp_new_i64(); + if (test_cb) { + cb = tcg_temp_new_i64(); + if (d) { + TCGv_i64 cb_msb = tcg_temp_new_i64(); + if (is_add) { + tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, in2, ctx->zero); + tcg_gen_xor_i64(cb, in1, in2); + } else { + /* See do_sub, !is_b. */ + TCGv_i64 one = tcg_constant_i64(1); + tcg_gen_sub2_i64(dest, cb_msb, in1, one, in2, ctx->zero); + tcg_gen_eqv_i64(cb, in1, in2); + } + tcg_gen_xor_i64(cb, cb, dest); + /* For 64-bit tests, put all carry-out bits back in one word. */ + tcg_gen_extract2_i64(cb, cb, cb_msb, 1); + } else { + if (is_add) { + tcg_gen_add_i64(dest, in1, in2); + tcg_gen_xor_i64(cb, in1, in2); + } else { + tcg_gen_sub_i64(dest, in1, in2); + tcg_gen_eqv_i64(cb, in1, in2); + } + /* For 32-bit tests, test carry-in instead of carry-out. */ + test_cb = (uint64_t)(uint32_t)test_cb << 1; + } + cond = cond_make_tmp(cf & 1 ? TCG_COND_TSTEQ : TCG_COND_TSTNE, + cb, tcg_constant_i64(test_cb)); + } else { + if (is_add) { + tcg_gen_add_i64(dest, in1, in2); + } else { + tcg_gen_sub_i64(dest, in1, in2); + } + cond = do_unit_zero_cond(cf, d, dest); + } + + if (is_tc) { + TCGv_i64 tmp = tcg_temp_new_i64(); + tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); + gen_helper_tcond(tcg_env, tmp); + } + save_gpr(ctx, rt, dest); + + cond_free(&ctx->null_cond); + ctx->null_cond = cond; } #ifndef CONFIG_USER_ONLY @@ -2748,14 +2742,24 @@ static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf_d *a) static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a) { - TCGv_i64 tcg_r1, tcg_r2; + TCGv_i64 tcg_r1, tcg_r2, dest; if (a->cf) { nullify_over(ctx); } + tcg_r1 = load_gpr(ctx, a->r1); tcg_r2 = load_gpr(ctx, a->r2); - do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, false, tcg_gen_xor_i64); + dest = dest_gpr(ctx, a->t); + + tcg_gen_xor_i64(dest, tcg_r1, tcg_r2); + save_gpr(ctx, a->t, dest); + + cond_free(&ctx->null_cond); + if (a->cf) { + ctx->null_cond = do_unit_zero_cond(a->cf, a->d, dest); + } + return nullify_end(ctx); } @@ -2790,7 +2794,7 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc) tcg_r2 = load_gpr(ctx, a->r2); tmp = tcg_temp_new_i64(); tcg_gen_not_i64(tmp, tcg_r2); - do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_i64); + do_unit_addsub(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, true); return nullify_end(ctx); } @@ -2817,8 +2821,8 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i) } tcg_gen_andi_i64(tmp, tmp, (uint64_t)0x1111111111111111ull); tcg_gen_muli_i64(tmp, tmp, 6); - do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, a->d, false, - is_i ? tcg_gen_add_i64 : tcg_gen_sub_i64); + do_unit_addsub(ctx, a->t, load_gpr(ctx, a->r), tmp, + a->cf, a->d, false, is_i); return nullify_end(ctx); }