From patchwork Tue Jun 13 11:48:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 105154 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp362164qgd; Tue, 13 Jun 2017 04:50:15 -0700 (PDT) X-Received: by 10.84.217.25 with SMTP id o25mr29706163pli.201.1497354615483; Tue, 13 Jun 2017 04:50:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497354615; cv=none; d=google.com; s=arc-20160816; b=uMUmC5tHbzG/VF1SZf9u3oTxob29jlQXMY8VYP8umcHTVwq3KosaSKvi5vQLulorDh EAxHSAfcZFI3T3n31cGnmDDl8Ioh866dAF1QnVp4qg+zN3ZKeJ6WWB3Mh86HmYLrmbzL VdPHNVs3mGPmMINDlSgpx/BpqlTb7eqOYIGjT1w/tqpT52Tc2jpEZWNXWX6swPKqFS2J DMQXlEC5aX41vUlx4Iv4NqcA3hgcRLGDBuKzgFb2uu0P4AnKTtjI3KtfSsimeNO9aI2q kU/NdweaGXcNnsrUzr5SzBWTommWAb57RJ8yDw1J2TpnFjkYn2GWeIWmf9SJQWEzmSRF +8wA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=zhxaagEBCuodBYVFPnCMirfSuw9ulLbDOvf8PK94muo=; b=FaOZdQIGtuE0I2ZytV3MTiIN2FNehCEbtd0D9tnc/tcmKGmMdBHVCoeg0N/W1e4ljT L/U2ngin9ERlgytsZV88KuIEhKFwwL3wIXmC7v0g5LnlmDxsVFadpPm13iVljF1dntX7 QfBJimfvjkT6tcJyYffVo3IaSkLDojQ3JBrFTeDro67d7H5v0CU9/YZtzJK95m01yHYy jU4Cp0Osx3pUO5TE8cMw8X4lE+7RsWM9rQFUYmM0fgN2ROmb+FlbubkhdHgHYUA6qEId LxP5/f2PXnz6ij1HZzdj2E1B98G7LPRvt0LprVLN0mT4N0JsvGRiOkYjZpx5NN9HN7tb ZijA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z73si9570643plh.548.2017.06.13.04.50.15; Tue, 13 Jun 2017 04:50:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753024AbdFMLuO (ORCPT + 8 others); Tue, 13 Jun 2017 07:50:14 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:7411 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753128AbdFMLuN (ORCPT ); Tue, 13 Jun 2017 07:50:13 -0400 Received: from 172.30.72.55 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.55]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APH83185; Tue, 13 Jun 2017 19:49:59 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Tue, 13 Jun 2017 19:49:48 +0800 From: shameer To: , , , , , CC: , , , , , , , , , shameer Subject: [PATCH 1/2] acpi:iort: Add an IORT helper function to reserve HW ITS address regions for IOMMU drivers Date: Tue, 13 Jun 2017 12:48:28 +0100 Message-ID: <20170613114829.188036-2-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170613114829.188036-1-shameerali.kolothum.thodi@huawei.com> References: <20170613114829.188036-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.593FD169.025A, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: da1ae870c541f9226fedfc8c94adc1c7 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The helper function retrieves ITS address regions through IORT device <-> ITS mappings and reserves it so that these regions will not be translated by IOMMU and will be excluded from IOVA allocations. IOMMU drivers can use this to implement their .get_resv_regions callback. Signed-off-by: shameer --- drivers/acpi/arm64/iort.c | 92 ++++++++++++++++++++++++++++++++++++++-- drivers/irqchip/irq-gic-v3-its.c | 3 +- include/linux/acpi_iort.h | 7 ++- 3 files changed, 97 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index c5fecf9..0ee9965 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -34,6 +34,7 @@ struct iort_its_msi_chip { struct list_head list; struct fwnode_handle *fw_node; + phys_addr_t base_addr; u32 translation_id; }; @@ -131,14 +132,16 @@ typedef acpi_status (*iort_find_node_callback) static DEFINE_SPINLOCK(iort_msi_chip_lock); /** - * iort_register_domain_token() - register domain token and related ITS ID - * to the list from where we can get it back later on. + * iort_register_domain_token() - register domain token along with related + * ITS ID and base address to the list from where we can get it back later on. * @trans_id: ITS ID. + * @base: ITS base address. * @fw_node: Domain token. * * Returns: 0 on success, -ENOMEM if no memory when allocating list element */ -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node) +int iort_register_domain_token(int trans_id, phys_addr_t base, + struct fwnode_handle *fw_node) { struct iort_its_msi_chip *its_msi_chip; @@ -148,6 +151,7 @@ int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node) its_msi_chip->fw_node = fw_node; its_msi_chip->translation_id = trans_id; + its_msi_chip->base_addr = base; spin_lock(&iort_msi_chip_lock); list_add(&its_msi_chip->list, &iort_msi_chip_list); @@ -491,6 +495,24 @@ int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id) return -ENODEV; } +static int iort_find_its_base(u32 its_id, phys_addr_t *base) +{ + struct iort_its_msi_chip *its_msi_chip; + bool match = false; + + spin_lock(&iort_msi_chip_lock); + list_for_each_entry(its_msi_chip, &iort_msi_chip_list, list) { + if (its_msi_chip->translation_id == its_id) { + *base = its_msi_chip->base_addr; + match = true; + break; + } + } + spin_unlock(&iort_msi_chip_lock); + + return match ? 0 : -ENODEV; +} + /** * iort_dev_find_its_id() - Find the ITS identifier for a device * @dev: The device. @@ -649,6 +671,68 @@ int iort_add_device_replay(const struct iommu_ops *ops, struct device *dev) return err; } + +/** + * iort_iommu_its_get_resv_regions - Reserved region driver helper + * @dev: Device from iommu_get_resv_regions() + * @list: Reserved region list from iommu_get_resv_regions() + * + * Returns: 0 on at least one ITS address region reservation, + * appropriate error value otherwise. + * + * IOMMU drivers can use this to implement their .get_resv_regions callback + * for reserving the HW ITS address regions. + */ +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head) +{ + int i; + struct acpi_iort_node *node; + struct acpi_iort_its_group *its; + bool resv = false; + + node = iort_find_dev_node(dev); + if (!node) + return -ENODEV; + + if (dev_is_pci(dev)) { + u32 rid; + + pci_for_each_dma_alias(to_pci_dev(dev), __get_pci_rid, &rid); + node = iort_node_map_id(node, rid, NULL, IORT_MSI_TYPE); + + } else { + for (i = 0; i < node->mapping_count; i++) { + node = iort_node_map_platform_id(node, NULL, + IORT_MSI_TYPE, i); + if (node) + break; + } + } + + if (!node) + return -ENODEV; + + /* Move to ITS specific data */ + its = (struct acpi_iort_its_group *)node->node_data; + + for (i = 0; i < its->its_count; i++) { + phys_addr_t base; + + if (!iort_find_its_base(its->identifiers[i], &base)) { + int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + struct iommu_resv_region *region; + + region = iommu_alloc_resv_region(base, SZ_128K, prot, + IOMMU_RESV_MSI); + if (region) { + list_add_tail(®ion->list, head); + resv = true; + } + } + } + + return resv ? 0 : -ENODEV; +} #else static inline const struct iommu_ops *iort_fwspec_iommu_ops(struct iommu_fwspec *fwspec) @@ -656,6 +740,8 @@ const struct iommu_ops *iort_fwspec_iommu_ops(struct iommu_fwspec *fwspec) static inline int iort_add_device_replay(const struct iommu_ops *ops, struct device *dev) { return 0; } +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head) +{ return -ENODEV; } #endif static const struct iommu_ops *iort_iommu_xlate(struct device *dev, diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 45ea1933..c45a2ad 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1854,7 +1854,8 @@ static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, return -ENOMEM; } - err = iort_register_domain_token(its_entry->translation_id, dom_handle); + err = iort_register_domain_token(its_entry->translation_id, res.start, + dom_handle); if (err) { pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", &res.start, its_entry->translation_id); diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 3ff9ace..35cf45c 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -26,7 +26,8 @@ #define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL) #define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL) -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node); +int iort_register_domain_token(int trans_id, phys_addr_t base, + struct fwnode_handle *fw_node); void iort_deregister_domain_token(int trans_id); struct fwnode_handle *iort_find_domain_token(int trans_id); #ifdef CONFIG_ACPI_IORT @@ -39,6 +40,7 @@ /* IOMMU interface */ void iort_set_dma_mask(struct device *dev); const struct iommu_ops *iort_iommu_configure(struct device *dev); +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head); #else static inline void acpi_iort_init(void) { } static inline bool iort_node_match(u8 type) { return false; } @@ -53,6 +55,9 @@ static inline void iort_set_dma_mask(struct device *dev) { } static inline const struct iommu_ops *iort_iommu_configure(struct device *dev) { return NULL; } +static inline +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head) +{ return -ENODEV; } #endif #endif /* __ACPI_IORT_H__ */ From patchwork Tue Jun 13 11:48:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 105153 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp362133qgd; Tue, 13 Jun 2017 04:50:09 -0700 (PDT) X-Received: by 10.101.89.2 with SMTP id f2mr41837701pgu.237.1497354609139; Tue, 13 Jun 2017 04:50:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497354609; cv=none; d=google.com; s=arc-20160816; b=k43ES+KJlgEA+wLNWiKHkgfYMdfATZxeg7r09B5JPdg5zjDlg/a/0xA6Cbudz/h6qV dFU4ahF0J1ekpxPr68r5Jjq6+qMRmsL9M+epl5cOiqPsWuriGjJn3BZJd1+pUstUutii P3/TBMEFvGN0XsfeFz55waR2YTvQhm9i6i5hQWEl1P43bZqpxQezo19FEMgcb3mvp/Ou qmljrcubWAz9FBXHZRQFuHJrCfcx0tcsYLE5opCaY9xDAefQWlyvlhDOR0qi9UbW/8UK 778Wuejqr5quMvoYN4LnBhLBkKfSmahycfvX0+LjDmHgxhaPyRcrNRwa9jFD47QHjUvU WkrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=emdck5TW+6hJqhDlzzcoPhli+Pb2yGs/ef9Zp2SsHnI=; b=siBjpyce+hrkfjRfnY8uwTc2zfOoVmrrcdjt9VmUdD7gggvKq6A0CIyoBRPeHkNmg1 yEgrb963vboi5hfRj2JJuINZcqFOTvW3PYKjItZ88MSk/JNzJ2/4RCEUtEMu9FvsUe5c GsSouKiPTmym0p3xteM4rsfNxSTGteblDXn768l0ixFU5LuTCx0xMj43V+YQ+HT4SJUU Shldwm1z1rjfJ6mhRqz3WjmYAq3LU+8MiE2Qm16ktrkxDk77v8Z6Lb26JwusKL8YzgFa vMhpeWbLNzyfprUkraXg32bKfmBRQtNGnm4kUVTZV2BendkGirrWgnKX40Ov9gshIHPm vQbg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z73si9570643plh.548.2017.06.13.04.50.08; Tue, 13 Jun 2017 04:50:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752187AbdFMLuF (ORCPT + 8 others); Tue, 13 Jun 2017 07:50:05 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:8273 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753128AbdFMLuE (ORCPT ); Tue, 13 Jun 2017 07:50:04 -0400 Received: from 172.30.72.55 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AQF82972; Tue, 13 Jun 2017 19:50:01 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Tue, 13 Jun 2017 19:49:53 +0800 From: shameer To: , , , , , CC: , , , , , , , , , shameer Subject: [PATCH 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 Date: Tue, 13 Jun 2017 12:48:29 +0100 Message-ID: <20170613114829.188036-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170613114829.188036-1-shameerali.kolothum.thodi@huawei.com> References: <20170613114829.188036-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.593FD16A.007A, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 36b61414f7b40c6cfa71bbee3e687ddd Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a ACPI table based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. Signed-off-by: shameer --- drivers/iommu/arm-smmu-v3.c | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index abe4b88..2636c85 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -597,6 +597,7 @@ struct arm_smmu_device { u32 features; #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) +#define ARM_SMMU_OPT_RESV_HW_MSI (1 << 1) u32 options; struct arm_smmu_cmdq cmdq; @@ -1904,14 +1905,29 @@ static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { struct iommu_resv_region *region; + struct arm_smmu_device *smmu; + struct iommu_fwspec *fwspec = dev->iommu_fwspec; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI); - if (!region) - return; + smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); - list_add_tail(®ion->list, head); + if (smmu && (smmu->options & ARM_SMMU_OPT_RESV_HW_MSI) && + dev_is_pci(dev)) { + int ret; + + ret = iort_iommu_its_get_resv_regions(dev, head); + if (ret) { + dev_warn(dev, "HW MSI region reserve failed\n"); + return; + } + } else { + region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, + prot, IOMMU_RESV_SW_MSI); + if (!region) + return; + + list_add_tail(®ion->list, head); + } iommu_dma_get_resv_regions(dev, head); } @@ -2611,6 +2627,7 @@ static void parse_driver_acpi_options(struct acpi_iort_smmu_v3 *iort_smmu, switch (iort_smmu->model) { case ACPI_IORT_SMMU_HISILICON_HI161X: smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; + smmu->options |= ARM_SMMU_OPT_RESV_HW_MSI; break; default: break;