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Fri, 22 Mar 2024 04:58:18 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id d7-20020a2e8907000000b002d10daeb6dasm307430lji.126.2024.03.22.04.58.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 04:58:17 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 22 Mar 2024 13:58:16 +0200 Subject: [PATCH 1/2] arm64: dts: qcom: sm8250: describe HS signals properly Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240322-typec-fix-sm8250-v1-1-1ac22b333ea9@linaro.org> References: <20240322-typec-fix-sm8250-v1-0-1ac22b333ea9@linaro.org> In-Reply-To: <20240322-typec-fix-sm8250-v1-0-1ac22b333ea9@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2665; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=98BCJ0NbsVizpp9ZzVzT5Y699xuRAXE4zH1lvoYksiQ=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBl/XJYDQuh4AMoszLe6Ko2XoV3XCUdNdq3KUnBz eq8by4gPE6JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZf1yWAAKCRCLPIo+Aiko 1WypB/4gZqLlhCDi6OQO8X76Ew0qC8bPbwLRiZmRdV1gxJhodt+I5yQgsdi3R82CW5BhrV6TcjI 4Ww6E1lC0dpafpUbkh7SOngl2F5dE23ErkFgq9f615zBwK495/XZGRkH4F0tdzDgulquG2hVlQm 5N3kwdhqhm5vmK/svzdoXwzod8VIMELwvGfkLZXpXAWOAc43U0mpIeJV9WzywhnUQnRpWrFS5/h oeReZoUDLwk/dmzol2Vt5BmEGSeunVFR4U4RfXoWMp87mt54dvO/wd7OCx0Kg3AMd3jP2UqYvcQ Vg2aryVZBiZUB73wioZ4TP1mmnajGLT2VCC3boDA8dEUwd+8 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The OF graph should describe physical signals. There is no 'role switch' signal between Type-C connector and the DWC3 USB controller. Instead there is a HighSpeed signal lane between DWC3 controller and the USB-C connector. Rename endpoints in accordance to that (this follows the example lead by other plaforms, including QRB2210 RB1, QRB4210 RB2 and all PMIC GLINK platforms). Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index cd0db4f31d4a..44239d1e57e9 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1356,8 +1356,8 @@ &usb_1_dwc3 { usb-role-switch; }; -&usb_1_role_switch_out { - remote-endpoint = <&pm8150b_role_switch_in>; +&usb_1_dwc3_hs_out { + remote-endpoint = <&pm8150b_hs_in>; }; &usb_1_hsphy { @@ -1465,8 +1465,8 @@ ports { port@0 { reg = <0>; - pm8150b_role_switch_in: endpoint { - remote-endpoint = <&usb_1_role_switch_out>; + pm8150b_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs_out>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 6f54f50a70b0..99915a2b97e2 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -652,8 +652,8 @@ ports { port@0 { reg = <0>; - pm8150b_role_switch_in: endpoint { - remote-endpoint = <&usb_1_role_switch_out>; + pm8150b_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs_out>; }; }; }; @@ -716,8 +716,8 @@ &usb_1_hsphy { status = "okay"; }; -&usb_1_role_switch_out { - remote-endpoint = <&pm8150b_role_switch_in>; +&usb_1_dwc3_hs_out { + remote-endpoint = <&pm8150b_hs_in>; }; &ufs_mem_hc { diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 39bd8f0eba1e..d57039a4c3aa 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4196,7 +4196,7 @@ usb_1_dwc3: usb@a600000 { phy-names = "usb2-phy", "usb3-phy"; port { - usb_1_role_switch_out: endpoint {}; + usb_1_dwc3_hs_out: endpoint {}; }; }; }; From patchwork Fri Mar 22 11:58:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 781882 Received: from mail-lj1-f179.google.com (mail-lj1-f179.google.com [209.85.208.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D99873FE28 for ; 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Fri, 22 Mar 2024 04:58:21 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id d7-20020a2e8907000000b002d10daeb6dasm307430lji.126.2024.03.22.04.58.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 04:58:20 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 22 Mar 2024 13:58:17 +0200 Subject: [PATCH 2/2] arm64: dts: qcom: sm8250: add a link between DWC3 and QMP PHY Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240322-typec-fix-sm8250-v1-2-1ac22b333ea9@linaro.org> References: <20240322-typec-fix-sm8250-v1-0-1ac22b333ea9@linaro.org> In-Reply-To: <20240322-typec-fix-sm8250-v1-0-1ac22b333ea9@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1441; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=klWITmiUJAw96kWolfMC0LTldb0sS5vuE/5wLwzaZNg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBl/XJY9dDW/dpFrSrExyz91hnEVYf666AvKdGua PDyoheR51KJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZf1yWAAKCRCLPIo+Aiko 1X8RB/9n5scURPgViJl1VJYYtVMKsNP5WP4dVhy0Q28t+ySGo27BT8UKeubreNO9MBBJNd3jtpk ZklTwIL3zAxW8CIjhJt5z0wGQaGaxMyk/h3+Hs8ctDlO4E9XF9+HnvI7P6ymaa7ka/t2sHgUykx dvn+odliSvU4kN7rQ8dqB2cZ0jafTiQqVOKUSgYI3FqEviuO63Np0oNeZdXg5r63ymGazNhEhS9 UXNnQgLGgYtb56syElR+P5qHE5OuEnTR/CKIUAELJm6IuCp94jG57U+T7j6lzzL0lpHyBFARN1p +fQyYmzjnLdLAmf6RlwbMCTV6uzOQUOQtP86sMUbFDBYUH4b X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SuperSpeed signals originate from the DWC3 host controller and then are routed through the Combo QMP PHY, where they are multiplexed with the DisplayPort signals. Add corresponding OF graph link. Reported-by: Luca Weiss Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index d57039a4c3aa..e551e733ab94 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3917,6 +3917,10 @@ port@0 { port@1 { reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss_out>; + }; }; port@2 { @@ -4195,8 +4199,24 @@ usb_1_dwc3: usb@a600000 { phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; - port { - usb_1_dwc3_hs_out: endpoint {}; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; + }; + }; }; }; };