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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ5PEPF000001D6.mail.protection.outlook.com (10.167.242.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7409.10 via Frontend Transport; Tue, 19 Mar 2024 08:29:06 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 19 Mar 2024 03:29:03 -0500 From: Perry Yuan To: , , , , , CC: , , , , , , Subject: [PATCH v9 1/8] cpufreq: amd-pstate: Document *_limit_* fields in struct amd_cpudata Date: Tue, 19 Mar 2024 16:28:36 +0800 Message-ID: <4b00dae2cc2ed3146a747a7fc72438972c689dca.1710836407.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D6:EE_|IA0PR12MB9047:EE_ X-MS-Office365-Filtering-Correlation-Id: 6ee6e07b-c14a-410f-7bd4-08dc47eea4a7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2024 08:29:06.8589 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ee6e07b-c14a-410f-7bd4-08dc47eea4a7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB9047 From: "Gautham R. Shenoy" The four fields of struct cpudata namely min_limit_perf, max_limit_perf, min_limit_freq, max_limit_freq introduced in the commit febab20caeba("cpufreq/amd-pstate: Fix scaling_min_freq and scaling_max_freq update") are currently undocumented Add comments describing these fields Fixes: febab20caeba("cpufreq/amd-pstate: Fix scaling_min_freq and scaling_max_freq update") Signed-off-by: Gautham R. Shenoy Signed-off-by: Perry Yuan --- include/linux/amd-pstate.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index d21838835abd..212f377d615b 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -49,6 +49,10 @@ struct amd_aperf_mperf { * @lowest_perf: the absolute lowest performance level of the processor * @prefcore_ranking: the preferred core ranking, the higher value indicates a higher * priority. + * @min_limit_perf: Cached value of the perf corresponding to policy->min + * @max_limit_perf: Cached value of the perf corresponding to policy->max + * @min_limit_freq: Cached value of policy->min + * @max_limit_freq: Cached value of policy->max * @max_freq: the frequency that mapped to highest_perf * @min_freq: the frequency that mapped to lowest_perf * @nominal_freq: the frequency that mapped to nominal_perf From patchwork Tue Mar 19 08:28:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 781285 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2042.outbound.protection.outlook.com [40.107.223.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63D8D7C0A6; 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Tue, 19 Mar 2024 03:29:06 -0500 From: Perry Yuan To: , , , , , CC: , , , , , , Subject: [PATCH v9 2/8] cpufreq: amd-pstate: Document the units for freq variables in amd_cpudata Date: Tue, 19 Mar 2024 16:28:37 +0800 Message-ID: <0ee190df1d882d826faeeee28a000b06eacf6034.1710836407.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D2:EE_|MN6PR12MB8591:EE_ X-MS-Office365-Filtering-Correlation-Id: 22bd9725-3788-4591-9231-08dc47eea6ec X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5+9QYS6KXkhhJ7tP1lgxzmR+Ud9Fs2vk3HvAsOlgrXMTo6+CV9aR0NL48kZaRPewGN2+f8zdDaCQ0wDEWwEz4cwp6tc8kHz9WNSWyH2LqbrLusm1GhDUEkucZWh1G5tJiWuNoZ2nwePho4SpXaZP7p0TmFgSW9DwTcqkWRX9yb9+d74sZzjDyg0paS1xZBAZ/U+l6Onw8t+KoMHMfatieAKEdc0HH0xKo6m53hJOknmCEWe7TvRB8H3sclJEYfGjlSLdpX/9xDA0k9GNuRzwv7dI8zBzNfED84AxZlW/FD7DuuJRdu0VTUsygSoDQNj2nPxf9bA/kjmlUeSmpnhL9BoO8WFetdQsPNYL6TXRAbREQTR0c9aOgBwh5ZTPTf/fmiF5CA2lmufYRZcmgRCY2hIYB5y6T7ke4alHTGzYbHw46ll/5TFbzmpCj9iV1s+hAAjU21fT2ImNjvtx1XwntLRVk/+mrz/SKpl+2KZsnNEpUxuaO9FUFyki2iY8XHdhPJQ0dX1rquyaL8OeswG0tCtjxm4bCwzHfxSIb9U6iNICnK43ZKLqSzU4FaTPXRya++64+QvEfWG7mBkJulhtwdy0WvH1g4eE0zmqpetZPgY1Xs/epkrctMjMb16PlVS5tMa2zSU+hGRL208/1Y9eWYqAM7NoOaqlBrmZGUtjLNb8CCxruIBTXo9NsHVmBJ537gqC2qwxpH67uHNKSoQB/5ocX3Pb39CaCRRqiZWkb2qvseujPCSuK5lysMcb3K8P X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Shenoy" The min_limit_freq, max_limit_freq, min_freq, max_freq, nominal_freq and the lowest_nominal_freq members of struct cpudata store the frequency value in khz to be consistent with the cpufreq core. Update the comment to document this. Signed-off-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Reviewed-by: Li Meng < li.meng@amd.com> --- include/linux/amd-pstate.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 212f377d615b..ab7e82533718 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -51,15 +51,15 @@ struct amd_aperf_mperf { * priority. * @min_limit_perf: Cached value of the perf corresponding to policy->min * @max_limit_perf: Cached value of the perf corresponding to policy->max - * @min_limit_freq: Cached value of policy->min - * @max_limit_freq: Cached value of policy->max - * @max_freq: the frequency that mapped to highest_perf - * @min_freq: the frequency that mapped to lowest_perf - * @nominal_freq: the frequency that mapped to nominal_perf - * @lowest_nonlinear_freq: the frequency that mapped to lowest_nonlinear_perf + * @min_limit_freq: Cached value of policy->min (in khz) + * @max_limit_freq: Cached value of policy->max (in khz) + * @max_freq: the frequency (in khz) that mapped to highest_perf + * @min_freq: the frequency (in khz) that mapped to lowest_perf + * @nominal_freq: the frequency (in khz) that mapped to nominal_perf + * @lowest_nonlinear_freq: the frequency (in khz) that mapped to lowest_nonlinear_perf * @cur: Difference of Aperf/Mperf/tsc count between last and current sample * @prev: Last Aperf/Mperf/tsc count value read from register - * @freq: current cpu frequency value + * @freq: current cpu frequency value (in khz) * @boost_supported: check whether the Processor or SBIOS supports boost mode * @hw_prefcore: check whether HW supports preferred core featue. * Only when hw_prefcore and early prefcore param are true, From patchwork Tue Mar 19 08:28:39 2024 Content-Type: text/plain; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ5PEPF000001D0.mail.protection.outlook.com (10.167.242.52) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7409.10 via Frontend Transport; Tue, 19 Mar 2024 08:29:18 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 19 Mar 2024 03:29:13 -0500 From: Perry Yuan To: , , , , , CC: , , , , , , Subject: [PATCH v9 4/8] cpufreq: amd-pstate: Remove amd_get_{min,max,nominal,lowest_nonlinear}_freq() Date: Tue, 19 Mar 2024 16:28:39 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D0:EE_|SA0PR12MB4414:EE_ X-MS-Office365-Filtering-Correlation-Id: f7eafdc2-8662-4d45-33a9-08dc47eeab53 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2024 08:29:18.0819 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f7eafdc2-8662-4d45-33a9-08dc47eeab53 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4414 From: "Gautham R. Shenoy" amd_get_{min,max,nominal,lowest_nonlinear}_freq() functions merely return cpudata->{min,max,nominal,lowest_nonlinear}_freq values. There is no loss in readability in replacing their invocations by accesses to the corresponding members of cpudata. Do so and remove these helper functions. Signed-off-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Reviewed-by: Li Meng < li.meng@amd.com> --- drivers/cpufreq/amd-pstate.c | 40 +++++++++--------------------------- 1 file changed, 10 insertions(+), 30 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index ba1baa6733e6..132330b4942f 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -604,26 +604,6 @@ static void amd_pstate_adjust_perf(unsigned int cpu, cpufreq_cpu_put(policy); } -static int amd_get_min_freq(struct amd_cpudata *cpudata) -{ - return READ_ONCE(cpudata->min_freq); -} - -static int amd_get_max_freq(struct amd_cpudata *cpudata) -{ - return READ_ONCE(cpudata->max_freq); -} - -static int amd_get_nominal_freq(struct amd_cpudata *cpudata) -{ - return READ_ONCE(cpudata->nominal_freq); -} - -static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) -{ - return READ_ONCE(cpudata->lowest_nonlinear_freq); -} - static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) { struct amd_cpudata *cpudata = policy->driver_data; @@ -854,10 +834,10 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) if (ret) goto free_cpudata1; - min_freq = amd_get_min_freq(cpudata); - max_freq = amd_get_max_freq(cpudata); - nominal_freq = amd_get_nominal_freq(cpudata); - lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata); + min_freq = READ_ONCE(cpudata->min_freq); + max_freq = READ_ONCE(cpudata->max_freq); + nominal_freq = READ_ONCE(cpudata->nominal_freq); + lowest_nonlinear_freq = READ_ONCE(cpudata->lowest_nonlinear_freq); if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) { dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n", @@ -960,7 +940,7 @@ static ssize_t show_amd_pstate_max_freq(struct cpufreq_policy *policy, int max_freq; struct amd_cpudata *cpudata = policy->driver_data; - max_freq = amd_get_max_freq(cpudata); + max_freq = READ_ONCE(cpudata->max_freq); if (max_freq < 0) return max_freq; @@ -973,7 +953,7 @@ static ssize_t show_amd_pstate_lowest_nonlinear_freq(struct cpufreq_policy *poli int freq; struct amd_cpudata *cpudata = policy->driver_data; - freq = amd_get_lowest_nonlinear_freq(cpudata); + freq = READ_ONCE(cpudata->lowest_nonlinear_freq); if (freq < 0) return freq; @@ -1315,10 +1295,10 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) if (ret) goto free_cpudata1; - min_freq = amd_get_min_freq(cpudata); - max_freq = amd_get_max_freq(cpudata); - nominal_freq = amd_get_nominal_freq(cpudata); - lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata); + min_freq = READ_ONCE(cpudata->min_freq); + max_freq = READ_ONCE(cpudata->max_freq); + nominal_freq = READ_ONCE(cpudata->nominal_freq); + lowest_nonlinear_freq = READ_ONCE(cpudata->lowest_nonlinear_freq); if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) { dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n", min_freq, max_freq); From patchwork Tue Mar 19 08:28:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 781283 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2079.outbound.protection.outlook.com [40.107.244.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D2327E566; 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Tue, 19 Mar 2024 03:29:21 -0500 From: Perry Yuan To: , , , , , CC: , , , , , , Subject: [PATCH v9 6/8] cpufreq: amd-pstate: get transition delay and latency value from ACPI tables Date: Tue, 19 Mar 2024 16:28:41 +0800 Message-ID: <25f02e3e98ae4b66c11189bc7857de56ba1b129f.1710836407.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D5:EE_|IA0PR12MB8930:EE_ X-MS-Office365-Filtering-Correlation-Id: 49eec4e6-891a-4fde-eb2c-08dc47eeaf4b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 1ufozVleMGj7domEmuhisgoPcRtMzZF2jSCS8VKN2TSCinwPlOBVZ0UnM6c9tv7R50ZpqDWhoWTkr6WJvwjfoa3ciYZWcfxMuYTBNJLnLVyTPp7AU14ay6Z09sgihXRmRfe3frIva3BGZCm3rhiJfXdP6Aoasvjw2hrZsCCDrMmjm71UG/Basve12+5lZ4A5rrUQma786O519sEJguML63HiHwsCRV2FhSSXSgRQ+2QScpYCXNpU22t+CPRfz1iIdu+tMURc2BNJb23SyQrvLqzCtbAs8/3Y810jB324tixme1xVtxSeiEOXlCAqnQM2T+AuKQ7zn/AVIbd+brq0KOgn4f2AFgTMFZHwS4T/3+Rw9ljqdVezntOhP0LYqz8WCTiN1x07ihirdVRdBhE4c0DK3tJbKhn2C37aiXY56zTDAVGn64F1BilcHHhpec4K3OzU3mgkK98qxZmNZkhMny9e8pRnWp5CE7DhNjFpdIP7K0SO+QUwVnVdPHWDAKmPEhRxhQ6BOa6NnL6TPHonmQQ7ry5VebZp+ZHoyPtlivswPYrDJ5Q3ImcrlHflt2+nyvdTUieVj+b1K/I/21qICI7nyN/Az0kt+3StcowtAJjp1M2p680CGI5Fqt7A55oJr9Fpd2SBLYPsHBbEk4hIijyxIJLQQGg4QMpq9UBXUMbPBGdi/YkGGRbHW/n/cYXAXOTCzhKYJFauPSL9hFQqpAgXkJ+DMAT162/q/dN+49niem5E4/9VIyZT+hDmKjVd X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(1800799015)(376005)(36860700004)(82310400014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2024 08:29:24.7294 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49eec4e6-891a-4fde-eb2c-08dc47eeaf4b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8930 Make pstate driver initially retrieve the P-state transition delay and latency values from the BIOS ACPI tables which has more reasonable delay and latency values according to the platform design and requirements. Previously there values were hardcoded at specific value which may have conflicted with platform and it might not reflect the most accurate or optimized setting for the processor. [054h 0084 8] Preserve Mask : FFFFFFFF00000000 [05Ch 0092 8] Write Mask : 0000000000000001 [064h 0100 4] Command Latency : 00000FA0 [068h 0104 4] Maximum Access Rate : 0000EA60 [06Ch 0108 2] Minimum Turnaround Time : 0000 Reviewed-by: Gautham R. Shenoy Reviewed-by: Mario Limonciello Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 6708c436e1a2..ec049b62b366 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -756,6 +756,36 @@ static void amd_pstate_update_limits(unsigned int cpu) mutex_unlock(&amd_pstate_driver_lock); } +/** + * Get pstate transition delay time from ACPI tables that firmware set + * instead of using hardcode value directly. + */ +static u32 amd_pstate_get_transition_delay_us(unsigned int cpu) +{ + u32 transition_delay_ns; + + transition_delay_ns = cppc_get_transition_latency(cpu); + if (transition_delay_ns == CPUFREQ_ETERNAL) + return AMD_PSTATE_TRANSITION_DELAY; + + return transition_delay_ns / NSEC_PER_USEC; +} + +/** + * Get pstate transition latency value from ACPI tables that firmware + * set instead of using hardcode value directly. + */ +static u32 amd_pstate_get_transition_latency(unsigned int cpu) +{ + u32 transition_latency; + + transition_latency = cppc_get_transition_latency(cpu); + if (transition_latency == CPUFREQ_ETERNAL) + return AMD_PSTATE_TRANSITION_LATENCY; + + return transition_latency; +} + /** * amd_pstate_init_freq: Initialize the max_freq, min_freq, * nominal_freq and lowest_nonlinear_freq for @@ -848,8 +878,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) goto free_cpudata1; } - policy->cpuinfo.transition_latency = AMD_PSTATE_TRANSITION_LATENCY; - policy->transition_delay_us = AMD_PSTATE_TRANSITION_DELAY; + policy->cpuinfo.transition_latency = amd_pstate_get_transition_latency(policy->cpu); + policy->transition_delay_us = amd_pstate_get_transition_delay_us(policy->cpu); policy->min = min_freq; policy->max = max_freq; From patchwork Tue Mar 19 08:28:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 781282 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2074.outbound.protection.outlook.com [40.107.243.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 437347C0A7; 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Tue, 19 Mar 2024 03:29:27 -0500 From: Perry Yuan To: , , , , , CC: , , , , , , Subject: [PATCH v9 8/8] cpufreq: amd-pstate: Add quirk for the pstate CPPC capabilities missing Date: Tue, 19 Mar 2024 16:28:43 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D4:EE_|SJ2PR12MB7896:EE_ X-MS-Office365-Filtering-Correlation-Id: c9b7807d-9969-4cd3-10e9-08dc47eeb36f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: aqxf70//zge2nSEJRuf8J6ZgT15FaYUC9uNZopv/8cDxC1jl3nG8i0UqoWan3rLrTpTg35v2jhAwdc+E/u3x8bWxbBJiKXjBsBQoEkuxssLgk0G8Dzy7bRfFZT5myBi5Op74vVEjJLCdFU4WMbPpEj1MalQIUprTbOjyYqofqysHzKE67YQsi6JcwKKIs86m5/+anL+R/UkvyTyO7Ki/GMFUhal4H7kDIXT8NBxFOpvxCY7WjFYLbk7Pb8wm9x6ej69TTbs0l0Qb8q5ibujzoFW61LoAD+IuePsdjd8n7UNSs6O3BMr+BonKiJLKG1dSrwkCJ3DqYtQCJOkEdO6e/cK5QssnkeoT9XuBsS487uhQd6o0PYam2hKQOIfAxtmSkez4DvJMjbOW+aLosdgsC1cwGDYnYt2y7ruzpQXzOFATuRa5dE588+vbqpHKEOXcTghlta28uvw4b7GFFH5awAFN/fPxODZyQLLmNXqLNuz0OgoWgIRdR0ZmuWnuMa1rZXyXk+P2Zc05J3yjqrRRmR54TsYrPeYtEWvrmfO9LELUmmRWE59zaYKuxPKe6axQbbJ7Z1mfB0P8vHRbXtBg46Pv4FhrYvzOlUjaOt9tk697jz/UPOveym8/OOADvGNxEOsKK3bycy6uvumi21QmjAS8O01fZGgLn0gbzd3E3z+DdTeV75RhyIFDAvlYSpVGsLXJInGdrMM1BM7G2iJfq95QB3bDjwdSUlCrHyIiD5RFXzznQHDWlckVU7rUh7AK X-Forefront-Antispam-Report: CIP:165.204.84.17; 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If CPPC capabilities are not defined in the ACPI tables or wrongly defined by platform firmware, it needs to use quick to get those issues fixed with correct workaround values to make pstate driver can be loaded even though there are CPPC capabilities errors. The workaround will match the broken BIOS which lack of CPPC capabilities nominal_freq and lowest_freq definition in the ACPI table. $ cat /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_freq 0 $ cat /sys/devices/system/cpu/cpu0/acpi_cppc/nominal_freq 0 Reviewed-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 53 ++++++++++++++++++++++++++++++++++-- include/linux/amd-pstate.h | 6 ++++ 2 files changed, 57 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index ec049b62b366..59a2db225d98 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -67,6 +67,7 @@ static struct cpufreq_driver amd_pstate_epp_driver; static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; static bool amd_pstate_prefcore = true; +static struct quirk_entry *quirks; /* * AMD Energy Preference Performance (EPP) @@ -111,6 +112,41 @@ static unsigned int epp_values[] = { typedef int (*cppc_mode_transition_fn)(int); +static struct quirk_entry quirk_amd_7k62 = { + .nominal_freq = 2600, + .lowest_freq = 550, +}; + +static int __init dmi_matched_7k62_bios_bug(const struct dmi_system_id *dmi) +{ + /** + * match the broken bios for family 17h processor support CPPC V2 + * broken BIOS lack of nominal_freq and lowest_freq capabilities + * definition in ACPI tables + */ + if (boot_cpu_has(X86_FEATURE_ZEN2)) { + quirks = dmi->driver_data; + pr_info("Overriding nominal and lowest frequencies for %s\n", dmi->ident); + return 1; + } + + return 0; +} + +static const struct dmi_system_id amd_pstate_quirks_table[] __initconst = { + { + .callback = dmi_matched_7k62_bios_bug, + .ident = "AMD EPYC 7K62", + .matches = { + DMI_MATCH(DMI_BIOS_VERSION, "5.14"), + DMI_MATCH(DMI_BIOS_RELEASE, "12/12/2019"), + }, + .driver_data = &quirk_amd_7k62, + }, + {} +}; +MODULE_DEVICE_TABLE(dmi, amd_pstate_quirks_table); + static inline int get_mode_idx_from_str(const char *str, size_t size) { int i; @@ -812,8 +848,16 @@ static int amd_pstate_init_freq(struct amd_cpudata *cpudata) if (ret) return ret; - min_freq = cppc_perf.lowest_freq * 1000; - nominal_freq = cppc_perf.nominal_freq * 1000; + if (quirks && quirks->lowest_freq) + min_freq = quirks->lowest_freq * 1000; + else + min_freq = cppc_perf.lowest_freq * 1000; + + if (quirks && quirks->nominal_freq) + nominal_freq = quirks->nominal_freq * 1000; + else + nominal_freq = cppc_perf.nominal_freq * 1000; + nominal_perf = READ_ONCE(cpudata->nominal_perf); highest_perf = READ_ONCE(cpudata->highest_perf); @@ -1662,6 +1706,11 @@ static int __init amd_pstate_init(void) if (cpufreq_get_current_driver()) return -EEXIST; + quirks = NULL; + + /* check if this machine need CPPC quirks */ + dmi_check_system(amd_pstate_quirks_table); + switch (cppc_state) { case AMD_PSTATE_UNDEFINED: /* Disable on the following configs by default: diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index ab7e82533718..6b832153a126 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -128,4 +128,10 @@ static const char * const amd_pstate_mode_string[] = { [AMD_PSTATE_GUIDED] = "guided", NULL, }; + +struct quirk_entry { + u32 nominal_freq; + u32 lowest_freq; +}; + #endif /* _LINUX_AMD_PSTATE_H */