From patchwork Tue Oct 1 13:51:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 174862 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp8582337ill; Tue, 1 Oct 2019 06:53:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqwHvkO61xzWN4KlM3wSuXBlkNsy6I/J4spRuU0/CZ+2CA8g5K9OkUYdG8aUmymODVPD8kwP X-Received: by 2002:aa7:d698:: with SMTP id d24mr7924866edr.32.1569938036557; Tue, 01 Oct 2019 06:53:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569938036; cv=none; d=google.com; s=arc-20160816; b=LDq5F7XyU34YpmTkI//6cDJFZT/VKRICVCU5sNzDcww17s1YudPd9NoDpcezJBu1Nf aONy14hE290SSmrcRDh9lPDI3NXMFWblUKh26sbBTS6RQIMJFcvUxCxuF4In4Grb43La B2JTKNMDU1qnmfn933VmZ2bydZMBRaTgJyUYEI8ARHuz8hranzmXSdr5WmGxD8ogaS4e 9GcCAAgRG47EReSLlKPlKYbzYZOmSTUqk7UCKJxrzcH/31Xabhw5a8UxR43PoHqsuIM0 +o9XeEPo3uUs3pYIUyc9Ol1uYC6XOVeJZ53q6P5EAjoykP/pgIaaO3RMRMH/MFcLXeTy 95ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=gvBQeIEI/x9mXZQVwgqeZ7kaM6LzZwxLRjfLMfWieM8=; b=RHmqhNbLWVzKlQHgiKpkyOEe8PREYPnGUYa4rnCsoJGd/Vq5ES/ag0EXClGBazlh6Z I768WttyILvlj2O+0u4vgW8gBBhIMXgkt7REMzwTNpN9/7vcNwDAK7dlg03eZiMSXCTN eH/6s8KYbYoszN1AMY2fU/bdmyLhcs4q1cxQ4ev28bXTRkHbKSXH86h//LWex9JK659f WC2p0FQ8rma1nCsoU2llr2oB0y1hYZ9WTsj8GN5mKVm8usKAgbaP/GdTUstSdpjm9rDZ FoX6aI/yxRJJcYVHRgHn8amxdkmFiTn0aRsKped/VuaI9ussh/dw5VkT9CNTqq8KJdvk +TCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J83fHGTj; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h26si8292119ejx.177.2019.10.01.06.53.56; Tue, 01 Oct 2019 06:53:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J83fHGTj; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388567AbfJANxz (ORCPT + 5 others); Tue, 1 Oct 2019 09:53:55 -0400 Received: from mail-lj1-f195.google.com ([209.85.208.195]:40321 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726152AbfJANxz (ORCPT ); Tue, 1 Oct 2019 09:53:55 -0400 Received: by mail-lj1-f195.google.com with SMTP id 7so13449950ljw.7 for ; Tue, 01 Oct 2019 06:53:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=gvBQeIEI/x9mXZQVwgqeZ7kaM6LzZwxLRjfLMfWieM8=; b=J83fHGTjCSsnD1rpKCckbThsAiZLaz7BVzauZaMZH8+lchnX36lKowk7qjMYE7ZEv1 Qku5To+b/dbVZG5xuY7GWm4aftlo9M4Yz3Wriy0IvA4VQxyW84JY/IL0PFSrIvbL1fBB w2xbBUW/rqv4fJXsfMHiFtgiuQdeZKxkshbQResFrF2Ddb2gavWImZgr+fkPqOi1OMiE JeerwhtL60jma8sDEiEHeY/ZrxMeIklXF7AEySjNsf6CGZQbTACH5rTCctySiNTV50ka Y8dcxGFIAkzzJlO7fr40MrBVKAk2zRNSLQYiSQ+Fr5jwfc7OlMufup6gh3ZP0jUzglh2 EOoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=gvBQeIEI/x9mXZQVwgqeZ7kaM6LzZwxLRjfLMfWieM8=; b=aXMQtLi+ffIe8paVtv05zCkTF7+IeS9rQS958srdPePaNPt4CgvoJETuLKtpzib00M BbryQ7v5dYVpERm3dyd5ZZVKY9rTpHLijh4xtvvB7z6Za0TsaIZoMdu4Cyiz+e1r5i4G h3t9rK0zetoyhHRWr92YBk8uWMepB+IQF6pz65qcb8Y8ydthG08+aSPzxI/znujxBamF W5pZrR/r9VteOfBDK7xOxyERGNwsAFwvaD7MQwLGBwj3IFkR6CyNShM9Hh896INLQYxt KAH39ew2wLF3/GrxTFO78IVs6I5HXa1nRKkNUP6uou6/8VQ+tTEs4xBUeJdlpPTfmzpE P0kA== X-Gm-Message-State: APjAAAXDO3rxW7Icefjubpb3fb+pml6FHVazV8TpmRfA7ZVRZ8AUZihH BXfc2m4/TY5a7yT64Owkj6ZInOxWuVaQSA== X-Received: by 2002:a2e:730a:: with SMTP id o10mr15969464ljc.214.1569938033179; Tue, 01 Oct 2019 06:53:53 -0700 (PDT) Received: from localhost.localdomain (c-79c8225c.014-348-6c756e10.bbcust.telenor.se. [92.34.200.121]) by smtp.gmail.com with ESMTPSA id e19sm4024023lja.8.2019.10.01.06.53.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2019 06:53:52 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Bartosz Golaszewski , Linus Walleij , Benjamin Gaignard , Amelie Delaunay , Patrice Chotard , Thierry Reding Subject: [PATCH] pinctrl: st: Pass irqchip when adding gpiochip Date: Tue, 1 Oct 2019 15:51:47 +0200 Message-Id: <20191001135147.29416-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion: the ST pin controller errors out of adding a irqchip if the interrupt is invalid or missing or if the irqmux is not present: the irqchip should not be added if either of these errors happen, so rewrite the code to deal with that. Keep the exit path where the gpio_chip is added no matter what the status of the irq is. Cc: Benjamin Gaignard Cc: Amelie Delaunay Cc: Patrice Chotard Cc: Thierry Reding Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-st.c | 53 ++++++++++++++++++++++-------------- 1 file changed, 32 insertions(+), 21 deletions(-) -- 2.21.0 diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 00db8b9efb2c..4f39a7945d01 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1477,7 +1477,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, struct device *dev = info->dev; int bank_num = of_alias_get_id(np, "gpio"); struct resource res, irq_res; - int gpio_irq = 0, err; + int err; if (of_address_to_resource(np, 0, &res)) return -ENODEV; @@ -1500,12 +1500,6 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; range->npins = bank->gpio_chip.ngpio; range->gc = &bank->gpio_chip; - err = gpiochip_add_data(&bank->gpio_chip, bank); - if (err) { - dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num); - return err; - } - dev_info(dev, "%s bank added.\n", range->name); /** * GPIO bank can have one of the two possible types of @@ -1527,23 +1521,40 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, */ if (of_irq_to_resource(np, 0, &irq_res) > 0) { - gpio_irq = irq_res.start; - gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip, - gpio_irq, st_gpio_irq_handler); - } + struct gpio_irq_chip *girq; + int gpio_irq = irq_res.start; - if (info->irqmux_base || gpio_irq > 0) { - err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip, - 0, handle_simple_irq, - IRQ_TYPE_NONE); - if (err) { - gpiochip_remove(&bank->gpio_chip); - dev_info(dev, "could not add irqchip\n"); - return err; + /* This is not a valid IRQ */ + if (gpio_irq <= 0) { + dev_err(dev, "invalid IRQ for %pOF bank\n", np); + goto skip_irq; } - } else { - dev_info(dev, "No IRQ support for %pOF bank\n", np); + /* We need to have a mux as well */ + if (!info->irqmux_base) { + dev_err(dev, "no irqmux for %pOF bank\n", np); + goto skip_irq; + } + + girq = &bank->gpio_chip.irq; + girq->chip = &st_gpio_irqchip; + girq->parent_handler = st_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = gpio_irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_simple_irq; + } + +skip_irq: + err = gpiochip_add_data(&bank->gpio_chip, bank); + if (err) { + dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num); + return err; } + dev_info(dev, "%s bank added.\n", range->name); return 0; }