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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 01/15] tcg/optimize: Fold andc with immediate to and Date: Tue, 12 Mar 2024 04:38:25 -1000 Message-Id: <20240312143839.136408-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/optimize.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 752cc5c56b..2ec52df368 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1324,17 +1324,23 @@ static bool fold_andc(OptContext *ctx, TCGOp *op) z1 = arg_info(op->args[1])->z_mask; - /* - * Known-zeros does not imply known-ones. Therefore unless - * arg2 is constant, we can't infer anything from it. - */ if (arg_is_const(op->args[2])) { - uint64_t z2 = ~arg_info(op->args[2])->z_mask; - ctx->a_mask = z1 & ~z2; - z1 &= z2; - } - ctx->z_mask = z1; + uint64_t val = ~arg_info(op->args[2])->val; + /* Fold andc r,x,i to and r,x,~i. */ + op->opc = (ctx->type == TCG_TYPE_I32 + ? INDEX_op_and_i32 : INDEX_op_and_i64); + op->args[2] = arg_new_constant(ctx, val); + + /* + * Known-zeros does not imply known-ones. Therefore unless + * arg2 is constant, we can't infer anything from it. + */ + ctx->a_mask = z1 & ~val; + z1 &= val; + } + + ctx->z_mask = z1; ctx->s_mask = arg_info(op->args[1])->s_mask & arg_info(op->args[2])->s_mask; return fold_masks(ctx, op); From patchwork Tue Mar 12 14:38:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 779755 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2057469wrt; Tue, 12 Mar 2024 07:43:31 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUQwou0PfuqehvoNz9Tb5mnQqG9iVnEdK7ijLogGWHJB+vcGY0krzgawnPbvhKTlvmadKHkSMOPyvHVJ75jrE8P X-Google-Smtp-Source: AGHT+IFISzsmRvzgkr3JIN1wu2euxHlmKNhfTDS1ViGer/54qkJuHygCGyfnZPbCbOLDWY7gpQC4 X-Received: by 2002:a05:6870:b14a:b0:221:6840:d131 with SMTP id a10-20020a056870b14a00b002216840d131mr1951498oal.58.1710254611315; Tue, 12 Mar 2024 07:43:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1710254611; cv=none; d=google.com; s=arc-20160816; b=pDYCpCOB6PuHCe+Yo5DxtdJBXf/iI9hAht6FM4P7693eq5Jf97ihC1AP1nNGGzcZeI hVwBWbfl1rtV99LBuJN1UBtGlZfmse/av+TIRVYCdR2kf9+0k3AXaKYfnU3oA0/lf96k 6JRXQLz/B0rW4o5S/fdiyoSXyPScLYkqpysxOvfpGsRGHY4hy5YaXJ6FzeXPqpAIdsrN RnG/h96tarKeFfCocHV5OaeesGhJXuKpDgwfcEOfoDtvKqqQQ3aJyS7iReXB9DYNphPK +EloxWshcULMfse53Um0kUCUyG27yLfyUmoUAm8GqnkJGZxx9Ikv4QYN+hPrSRcK8wkc DtOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RnJQyEnXrtZcjBCHyJq+5yv9WO+0xDyYir75PeP3MhY=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=wIbeMRkUc7qUn9Z4hb8jmA90uMySZpNE5TjSVGz6AbLdyTfnNMfrajMLtA9WR6il/8 7fu3ekPryhE9siNMWIkGY7DrxudmBVPYPtE53p/U9dJKriX4wi3r93sKoF2zJxqIePBt LYjbq1heTjhaUnc7/C+kJMknIZJV3fx/MgZmO/c1ItOmTQAYivL1369lnzqBUp7uKbuz jwmPCEIxpaLHNqsiEr1LVzUaMyreUILIvjEmjz5eHLV7QfGMH8AfzEEBEz1n8dNSDK++ tmi6sheuk0IoCAPGzo/oOzA+KrPo+FklMq8uI6dIlNLawNA5ApmCr9qOV7cdmViam/32 zUqw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kATDgmQm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 02/15] tcg/optimize: Fold orc with immediate to or Date: Tue, 12 Mar 2024 04:38:26 -1000 Message-Id: <20240312143839.136408-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/optimize.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index 2ec52df368..5729433548 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2065,6 +2065,15 @@ static bool fold_orc(OptContext *ctx, TCGOp *op) return true; } + /* Fold orc r,x,i to or r,x,~i. */ + if (arg_is_const(op->args[2])) { + uint64_t val = ~arg_info(op->args[2])->val; + + op->opc = (ctx->type == TCG_TYPE_I32 + ? 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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 03/15] tcg/optimize: Fold eqv with immediate to xor Date: Tue, 12 Mar 2024 04:38:27 -1000 Message-Id: <20240312143839.136408-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/optimize.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index 5729433548..c6b0ab35c8 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1687,6 +1687,15 @@ static bool fold_eqv(OptContext *ctx, TCGOp *op) return true; } + /* Fold eqv r,x,i to xor r,x,~i. */ + if (arg_is_const(op->args[2])) { + uint64_t val = ~arg_info(op->args[2])->val; + + op->opc = (ctx->type == TCG_TYPE_I32 + ? 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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 04/15] tcg/i386: Do not accept immediate operand for andc Date: Tue, 12 Mar 2024 04:38:28 -1000 Message-Id: <20240312143839.136408-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The transformation of andc with immediate to and is now done generically and need not be handled by the backend. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-con-set.h | 3 +-- tcg/i386/tcg-target-con-str.h | 1 - tcg/i386/tcg-target.c.inc | 20 +++++--------------- 3 files changed, 6 insertions(+), 18 deletions(-) diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/i386/tcg-target-con-set.h index e24241cfa2..69d2d38570 100644 --- a/tcg/i386/tcg-target-con-set.h +++ b/tcg/i386/tcg-target-con-set.h @@ -40,11 +40,10 @@ C_O1_I2(r, 0, r) C_O1_I2(r, 0, re) C_O1_I2(r, 0, reZ) C_O1_I2(r, 0, ri) -C_O1_I2(r, 0, rI) C_O1_I2(r, L, L) +C_O1_I2(r, r, r) C_O1_I2(r, r, re) C_O1_I2(r, r, ri) -C_O1_I2(r, r, rI) C_O1_I2(x, x, x) C_N1_I2(r, r, r) C_N1_I2(r, r, rW) diff --git a/tcg/i386/tcg-target-con-str.h b/tcg/i386/tcg-target-con-str.h index cc22db227b..0c766eac7e 100644 --- a/tcg/i386/tcg-target-con-str.h +++ b/tcg/i386/tcg-target-con-str.h @@ -27,7 +27,6 @@ REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_st8_i32 data */ * CONST(letter, TCG_CT_CONST_* bit set) */ CONST('e', TCG_CT_CONST_S32) -CONST('I', TCG_CT_CONST_I32) CONST('T', TCG_CT_CONST_TST) CONST('W', TCG_CT_CONST_WSZ) CONST('Z', TCG_CT_CONST_U32) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index c6ba498623..ed70524864 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -130,9 +130,8 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) /* Constants we accept. */ #define TCG_CT_CONST_S32 0x100 #define TCG_CT_CONST_U32 0x200 -#define TCG_CT_CONST_I32 0x400 -#define TCG_CT_CONST_WSZ 0x800 -#define TCG_CT_CONST_TST 0x1000 +#define TCG_CT_CONST_WSZ 0x400 +#define TCG_CT_CONST_TST 0x800 /* Registers used with L constraint, which are the first argument registers on x86_64, and two random call clobbered registers on @@ -203,8 +202,7 @@ static bool tcg_target_const_match(int64_t val, int ct, return 1; } if (type == TCG_TYPE_I32) { - if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | - TCG_CT_CONST_I32 | TCG_CT_CONST_TST)) { + if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | TCG_CT_CONST_TST)) { return 1; } } else { @@ -214,9 +212,6 @@ static bool tcg_target_const_match(int64_t val, int ct, if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { return 1; } - if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) { - return 1; - } /* * This will be used in combination with TCG_CT_CONST_S32, * so "normal" TESTQ is already matched. Also accept: @@ -2666,12 +2661,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; OP_32_64(andc): - if (const_a2) { - tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1); - tgen_arithi(s, ARITH_AND + rexw, a0, ~a2, 0); - } else { - tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1); - } + tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1); break; OP_32_64(mul): @@ -3442,7 +3432,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_andc_i32: case INDEX_op_andc_i64: - return C_O1_I2(r, r, rI); + return C_O1_I2(r, r, r); case INDEX_op_shl_i32: case INDEX_op_shl_i64: From patchwork Tue Mar 12 14:38:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 779750 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2056640wrt; Tue, 12 Mar 2024 07:41:49 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUh8C1EWBi68U5Xb+sRoMTLWMtQP5Y2nLbPHkWdYADcQ7On0m1z9jHVGIJXSn3Mjgv0aDlwfhHnqyWtlOiYxM4M X-Google-Smtp-Source: AGHT+IGhwInHA6sOMDYPdmbdDhWs2uLdVSy4wfW7K3z9ImgK7Pfoq0fxcv66lQTBDldfAkzBImhA X-Received: by 2002:a05:6808:d53:b0:3c2:598e:8d8e with SMTP id w19-20020a0568080d5300b003c2598e8d8emr1450574oik.7.1710254509055; Tue, 12 Mar 2024 07:41:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1710254509; cv=none; d=google.com; s=arc-20160816; b=IrBaNkUtPHLisEYPGrdyx/UK9f1K4aUNgAWBrno7kYKV5G994hfBIhNoQU63La/Fx9 1AnTIbpB7mPt2zoKF4nKOpZ3KrN4h+2vXIpeVIFA8b1i63R4BnSEScHdD3sIh6y4QIXR 1FDi2HH31PhuP8tvvwyJUHGL19AmRsabumeIMAxq1U7Yc1Atc9tHv7M9q5MZy1ncvCJX 7LTe5LfvnYHEbMs/p1omZ4OEZB+GdUUTlE7XH2XclZ+TJs+KbZ6olrDKlf52yhKXwdtw jNr2NoVXFMixjeruGRP2VtAIoFI09P+mGtAYGwN/Rw6gSKMjUclj1bxyvo2EdL/JwU3h Ym6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aSfVCHCwzSzRVXOz7WshzegXhabuAUGT/As/uR9fcX8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=rzgFjJAcVpQXdS6H6G6Tf/nypICpEQhOqb/owtdvaryygilgpt65SXxzP7+JJqrFpC HRH3zugh9BKvB7kDtXBtGXHMpgq+3FEwOpH1iKUE1hoV7cMg0IZDq4wkgSrVhWXo1cCn QEJA7ETTHLTbzWBd+JPNJT+eC6R7BBTb0WU4bgs26fFAL2DJDSXXkIaAWGH7rT4Oxee1 gghU9HVBej6nhC5ZkVDuxkBDiQhZ2wHNzMljrrp5F6iyf2Bqdyi4viIfblpf+tCP6V3J 2PDuM6aOTW350iyu3SCzTwiV12tmrT7VJAjZ3vkn/2i3vB81AUGg6cvtkowyEcf3W6um Na6w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S9Fl3hzV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 05/15] tcg/aarch64: Do not accept immediate operand for andc, orc, eqv Date: Tue, 12 Mar 2024 04:38:29 -1000 Message-Id: <20240312143839.136408-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The transformations with inverted immediate are now done generically and need not be handled by the backend. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 50 +++++++++++------------------------- 1 file changed, 15 insertions(+), 35 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index dec8ecc1b6..68a381e4af 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2216,17 +2216,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; - case INDEX_op_andc_i32: - a2 = (int32_t)a2; - /* FALLTHRU */ - case INDEX_op_andc_i64: - if (c2) { - tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, ~a2); - } else { - tcg_out_insn(s, 3510, BIC, ext, a0, a1, a2); - } - break; - case INDEX_op_or_i32: a2 = (int32_t)a2; /* FALLTHRU */ @@ -2238,17 +2227,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; - case INDEX_op_orc_i32: - a2 = (int32_t)a2; - /* FALLTHRU */ - case INDEX_op_orc_i64: - if (c2) { - tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, ~a2); - } else { - tcg_out_insn(s, 3510, ORN, ext, a0, a1, a2); - } - break; - case INDEX_op_xor_i32: a2 = (int32_t)a2; /* FALLTHRU */ @@ -2260,15 +2238,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + tcg_out_insn(s, 3510, BIC, ext, a0, a1, a2); + break; + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + tcg_out_insn(s, 3510, ORN, ext, a0, a1, a2); + break; case INDEX_op_eqv_i32: - a2 = (int32_t)a2; - /* FALLTHRU */ case INDEX_op_eqv_i64: - if (c2) { - tcg_out_logicali(s, I3404_EORI, ext, a0, a1, ~a2); - } else { - tcg_out_insn(s, 3510, EON, ext, a0, a1, a2); - } + tcg_out_insn(s, 3510, EON, ext, a0, a1, a2); break; case INDEX_op_not_i64: @@ -2995,6 +2975,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_negsetcond_i64: return C_O1_I2(r, r, rC); + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + case INDEX_op_eqv_i32: + case INDEX_op_eqv_i64: case INDEX_op_mul_i32: case INDEX_op_mul_i64: case INDEX_op_div_i32: @@ -3015,12 +3001,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: - case INDEX_op_andc_i32: - case INDEX_op_andc_i64: - case INDEX_op_orc_i32: - case INDEX_op_orc_i64: - case INDEX_op_eqv_i32: - case INDEX_op_eqv_i64: return C_O1_I2(r, r, rL); case INDEX_op_shl_i32: From patchwork Tue Mar 12 14:38:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 779744 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2055889wrt; Tue, 12 Mar 2024 07:40:21 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXTOXrZ8jazYIHDCHRaaM5u3TOCZeosFwdjZD7GS7peAAtaWblAvCSDnY9au9Dn6tKtlrmCaeukeAKN6kg+e2nf X-Google-Smtp-Source: AGHT+IG1jfwecTWN9HeQOJCB2IpNM+s6MqdgeaBUPvkjp5eGeVZyedpMXzJbsOcqgVBJf3TGiFUW X-Received: by 2002:a05:620a:b03:b0:788:186f:1f30 with SMTP id t3-20020a05620a0b0300b00788186f1f30mr534218qkg.66.1710254420870; Tue, 12 Mar 2024 07:40:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1710254420; cv=none; d=google.com; s=arc-20160816; b=ah8n52qTVNhfA4uuR674SAIxONRxEdx+pdeiocCabA7zzN69yDcgp2vsMdPIjRYAag qIzrUiz2WrDA7ituJtAktyYwR6Fs2oYFzCAH0LzCyqYDx9WQPl7dtxSDebUS+5zzA3vj GAhrlKKG40KnT2lm2aK6j2v9aTeTVDBXwm7q0Wg2Vs0y2NiLjxfGqNV6tunI2lcuMcdo VzO5AMcWbGQi8BrHhxL40qBas3etEQSvHv+4lBLlmj+ZhLm/NJYImF7xnbZvNsgpf/o0 eK7U36xZvbihORTDhQh27KemDkFe3yWNTxJlSb+gWsbwCu7sElhEj0x94GRVm2JyhgiF fSQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+U6hRnnu1FyU4GsVaJb1EG0lBm+OsXguv63B7cAYsao=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=QZJNWfHkzXglkVXnHkFk8p4UUYPvKFVTd37Pzp8U4i1dkwbS2V3OjCuFOWm2lxwNGL GucItHQwlyK67lsgCEd4rIEqhHORv7jksdxsc/EVzZPlVcFLNNjjkujol3CNK8wUKTKO 0cHdj29mL5W77ThKRhIrdaXyhlLOBZj2V1lWXNh3hIX6KPnPMPdH4EWS8rm9/WnYoa/C wdxSfe0wBdGy2hZ5EBx9IA8G+sjDYTr7EdsXB+Mj9ZzpFElYdtvkzS2BcnABqXRcnc4J /Sdo0kuZ+etELf9vg0vR9Ok3bFAjZlGL2w9ItfoMdFic4Sz4xhUB01aHT8XLD+US8Qj4 0XiA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TwKx0AFK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 06/15] tcg/arm: Do not accept immediate operand for andc Date: Tue, 12 Mar 2024 04:38:30 -1000 Message-Id: <20240312143839.136408-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The transformation of andc with immediate to and is now done generically and need not be handled by the backend. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 6a04c73c76..a0c5887579 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1869,8 +1869,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, args[0], args[1], args[2], const_args[2]); break; case INDEX_op_andc_i32: - tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND, - args[0], args[1], args[2], const_args[2]); + tcg_out_dat_reg(s, COND_AL, ARITH_BIC, args[0], args[1], + args[2], SHIFT_IMM_LSL(0)); break; case INDEX_op_or_i32: c = ARITH_ORR; @@ -2152,11 +2152,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) return C_O1_I2(r, r, rIN); case INDEX_op_and_i32: - case INDEX_op_andc_i32: case INDEX_op_clz_i32: case INDEX_op_ctz_i32: return C_O1_I2(r, r, rIK); + case INDEX_op_andc_i32: case INDEX_op_mul_i32: case INDEX_op_div_i32: case INDEX_op_divu_i32: From patchwork Tue Mar 12 14:38:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 779748 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2056603wrt; Tue, 12 Mar 2024 07:41:45 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW7qPL5+cc7ZzBq7PXx7nghEPP1sg/c0XK2UgFJAA286RDYdhfhG35AUKNdKwREf2rPElE+hGgAZG4tcIASpKVh X-Google-Smtp-Source: AGHT+IFFfhME1y9tT5rW5CoOk8vUJvLpty1K61OCrnlLYAh1FZvTIjN9/Zu1AIr9tu74iwS5D9nx X-Received: by 2002:a0c:8bda:0:b0:690:ac0d:c528 with SMTP id a26-20020a0c8bda000000b00690ac0dc528mr4052686qvc.52.1710254505074; Tue, 12 Mar 2024 07:41:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1710254505; cv=none; d=google.com; s=arc-20160816; b=Q4o9keI5G+Oh45bUvxvEtIn/DUsNcAuHxTi55QMBn7QfzOJIlFnTrUGpQhBFWYpWDy H+gTTsip5VuGyyRe4xx+iazryzPoDj9AWqFouhWjwU4yQBQqgzOP9DUkx/mhYVxQfVSU DHS2SiNONWpc2KvNF++IGRBZs1a630dTSfQa+hkUmtUHcU6gN9f/O/FOR4z+sYcF2qVO yKkEKUqKY+Se/dD7NuRaDitQfrvVIGl0NbJFJJhn+kvzKk8Eq6zcfpm6IeBq07WxqafC T4BUDrEj4Lp4JYxxXtYu5jD6TGGAFc4bmeB/LjS8QSTuvYUHM+oH5Wp56HIYwyL6omVB YvDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6WDUOYZWLT555AjxYlW12yt2eENGmiwsLor7nsvhIVw=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=TN3O6toRe2+QdMGcaTxCXot2uK3Xaj9t+gPcSVmZE1fLS+HWG2oVO9U5RHoCt4P3OR ysTTjM2QemqBM+s5QGkbM6cOCNhure19+/H90hEYHUXVY3sj9PkH4W4yW5v/48TUqox7 nKekbRv1kRYYCvnlct+0fku9bMG9yB6yp92/xQhBoi2FG/tOqshn5sqFX+72DBIfK+FJ cJ5HbQsb/62NX8/rvE3BNZb6/9qdwdnHZFl36utEXa51S/+0xVVb7F/O50MP3fMeL7y5 21DLkpcUwfxLrmqTsbyYxUUf1uaIBBWk3pFs5wBQZPYiDCwo76VustutBNWyvi1FwFEg sREA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lRLcYKbk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 07/15] tcg/ppc: Do not accept immediate operand for andc, orc, eqv Date: Tue, 12 Mar 2024 04:38:31 -1000 Message-Id: <20240312143839.136408-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The transformations with inverted immediate are now done generically and need not be handled by the backend. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 32 +++++--------------------------- 1 file changed, 5 insertions(+), 27 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 7f3829beeb..336b8a28ba 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3070,36 +3070,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_andc_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_andi32(s, a0, a1, ~a2); - } else { - tcg_out32(s, ANDC | SAB(a1, a0, a2)); - } - break; case INDEX_op_andc_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_andi64(s, a0, a1, ~a2); - } else { - tcg_out32(s, ANDC | SAB(a1, a0, a2)); - } + tcg_out32(s, ANDC | SAB(args[1], args[0], args[2])); break; case INDEX_op_orc_i32: - if (const_args[2]) { - tcg_out_ori32(s, args[0], args[1], ~args[2]); - break; - } - /* FALLTHRU */ case INDEX_op_orc_i64: tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); break; case INDEX_op_eqv_i32: - if (const_args[2]) { - tcg_out_xori32(s, args[0], args[1], ~args[2]); - break; - } - /* FALLTHRU */ case INDEX_op_eqv_i64: tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); break; @@ -4120,16 +4098,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_and_i32: case INDEX_op_or_i32: case INDEX_op_xor_i32: - case INDEX_op_andc_i32: - case INDEX_op_orc_i32: - case INDEX_op_eqv_i32: case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: case INDEX_op_rotl_i32: case INDEX_op_rotr_i32: case INDEX_op_and_i64: - case INDEX_op_andc_i64: case INDEX_op_shl_i64: case INDEX_op_shr_i64: case INDEX_op_sar_i64: @@ -4145,10 +4119,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_divu_i32: case INDEX_op_rem_i32: case INDEX_op_remu_i32: + case INDEX_op_andc_i32: + case INDEX_op_orc_i32: + case INDEX_op_eqv_i32: case INDEX_op_nand_i32: case INDEX_op_nor_i32: case INDEX_op_muluh_i32: case INDEX_op_mulsh_i32: + case INDEX_op_andc_i64: case INDEX_op_orc_i64: case INDEX_op_eqv_i64: case INDEX_op_nand_i64: From patchwork Tue Mar 12 14:38:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 779758 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2058069wrt; Tue, 12 Mar 2024 07:44:47 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVKL+gU/UELyBcb3ITOhTStVumIa9eM6DWeQcgNkvzqXH8gaJSbVv5YA+LJHsHUH51ejioKe+g6/BRaXv0BNnkJ X-Google-Smtp-Source: AGHT+IGSYc2U5wDAzi7+WLcJKgcGHpHAcZHspH82A1k2pvzLk6dlAyrON/5qB6Hf7TmyxCQV6Kdv X-Received: by 2002:a05:6808:2f0c:b0:3c2:266e:4e38 with SMTP id gu12-20020a0568082f0c00b003c2266e4e38mr2533281oib.25.1710254687577; Tue, 12 Mar 2024 07:44:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1710254687; cv=none; d=google.com; s=arc-20160816; b=iNUip02dKZxEo1ZMFQRs2BXJD/0feYC27PUpIMXIczPdkuO8JP7oGoWpu7BDp1FuqC jIuR5MJwwSmb4xBOccS6uGpo25uDeY2RZlHrp25ibydL6777onKrH8EQSzTn1wqp70yG 4yJJAe3VZkveZH+nQVPFrGP+m9Hpld3GyDVNVfefDgNqMfELlhBDlmwGOek+vgdBSczA 89R3ZmSH8La0iUKTCl9bik7JWHxBt2BlALwblRUog08m618HSYh2TddavaPke2nHJMam 3I28cruTk3/WwPi2rIr/MdiCj8K5DOTjQ/ow+ID/6SIRm3zEgY26A96/qBQ/oSRN4+2a h4LA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jbNLo5y1YUnPREukd4mIwrgqxX0R9HS5MZo8QZlenPA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=W+XKDbmRsiEpPuVspzs54SP257xCuymn8ygWfj5OF1KJR1YxlF+HBrrmtQP7xaISCk l1na7CLHwQQjjD+WDqqIGcLBnOobpO1tmk/sN4GOC7VjG4tXbh+ZsbU6Sy6MCcBnaE1x WQ9aeb/lVT2uskqXbVZ93sVMjC5Z8eS9A00jM0zB6sewSrYh5/KSQ0iRMNjq8WHCigXn WOdr2AsypgTx1I1n2J5LfHspOSjOQJreh3odmxPxpxVIXxBh9nG5iI8eiBwCX1KIRQWW qt5LyCTk2Pa/iluL1RfOm/Kqtmq+DENguqNQeSHTqLzMcx4X7LFBV796msVubjfPFBhr 4ppA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EyMHQIRO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 08/15] tcg/loongarch64: Do not accept immediate operand for andc, orc Date: Tue, 12 Mar 2024 04:38:32 -1000 Message-Id: <20240312143839.136408-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The transformations with inverted immediate are now done generically and need not be handled by the backend. Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 2 +- tcg/loongarch64/tcg-target-con-str.h | 1 - tcg/loongarch64/tcg-target.c.inc | 31 ++++++---------------------- 3 files changed, 7 insertions(+), 27 deletions(-) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h index cae6c2aad6..272f33c1e4 100644 --- a/tcg/loongarch64/tcg-target-con-set.h +++ b/tcg/loongarch64/tcg-target-con-set.h @@ -22,7 +22,7 @@ C_O0_I3(r, r, r) C_O1_I1(r, r) C_O1_I1(w, r) C_O1_I1(w, w) -C_O1_I2(r, r, rC) +C_O1_I2(r, r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) C_O1_I2(r, r, rJ) diff --git a/tcg/loongarch64/tcg-target-con-str.h b/tcg/loongarch64/tcg-target-con-str.h index 2ba9c135ac..e7d2686db3 100644 --- a/tcg/loongarch64/tcg-target-con-str.h +++ b/tcg/loongarch64/tcg-target-con-str.h @@ -24,7 +24,6 @@ CONST('I', TCG_CT_CONST_S12) CONST('J', TCG_CT_CONST_S32) CONST('U', TCG_CT_CONST_U12) CONST('Z', TCG_CT_CONST_ZERO) -CONST('C', TCG_CT_CONST_C12) CONST('W', TCG_CT_CONST_WSZ) CONST('M', TCG_CT_CONST_VCMP) CONST('A', TCG_CT_CONST_VADD) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 69c5b8ac4f..e343d33dba 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -169,10 +169,9 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) #define TCG_CT_CONST_S12 0x200 #define TCG_CT_CONST_S32 0x400 #define TCG_CT_CONST_U12 0x800 -#define TCG_CT_CONST_C12 0x1000 -#define TCG_CT_CONST_WSZ 0x2000 -#define TCG_CT_CONST_VCMP 0x4000 -#define TCG_CT_CONST_VADD 0x8000 +#define TCG_CT_CONST_WSZ 0x1000 +#define TCG_CT_CONST_VCMP 0x2000 +#define TCG_CT_CONST_VADD 0x4000 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) #define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) @@ -201,9 +200,6 @@ static bool tcg_target_const_match(int64_t val, int ct, if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) { return true; } - if ((ct & TCG_CT_CONST_C12) && ~val >= 0 && ~val <= 0xfff) { - return true; - } if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { return true; } @@ -1236,22 +1232,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_andc_i32: case INDEX_op_andc_i64: - if (c2) { - /* guaranteed to fit due to constraint */ - tcg_out_opc_andi(s, a0, a1, ~a2); - } else { - tcg_out_opc_andn(s, a0, a1, a2); - } + tcg_out_opc_andn(s, a0, a1, a2); break; case INDEX_op_orc_i32: case INDEX_op_orc_i64: - if (c2) { - /* guaranteed to fit due to constraint */ - tcg_out_opc_ori(s, a0, a1, ~a2); - } else { - tcg_out_opc_orn(s, a0, a1, a2); - } + tcg_out_opc_orn(s, a0, a1, a2); break; case INDEX_op_and_i32: @@ -2120,12 +2106,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_andc_i64: case INDEX_op_orc_i32: case INDEX_op_orc_i64: - /* - * LoongArch insns for these ops don't have reg-imm forms, but we - * can express using andi/ori if ~constant satisfies - * TCG_CT_CONST_U12. - */ - return C_O1_I2(r, r, rC); + return C_O1_I2(r, r, r); case INDEX_op_shl_i32: case INDEX_op_shl_i64: From patchwork Tue Mar 12 14:38:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 779749 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2056634wrt; Tue, 12 Mar 2024 07:41:48 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU20xpHQN5tnE0CiB5cYgWGbUvMERoGrVn56BuxlrsUsPCUUUl/rIdIXQBsm+yA39SoMSlzObzWP+3tbhyD4otY X-Google-Smtp-Source: AGHT+IFcibZnqGYvCNrbntDv3Gu6XqwpYOe4pG/J58/yxX7GFs25xojVei27aP0yRMnsMakCtOyC X-Received: by 2002:a05:620a:9c8:b0:788:3f9d:5ef2 with SMTP id y8-20020a05620a09c800b007883f9d5ef2mr14302196qky.25.1710254508367; Tue, 12 Mar 2024 07:41:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1710254508; cv=none; d=google.com; s=arc-20160816; b=CmyhvC11Iqy8dkbjKwdSlnBqxUPd4Rguw4+4+nVvnJ+hlXajI6YA6vhRjDf6Xp8LRq q0qo/nyx0pqZN+3DCpWxfhrG417gOEZmMjvYVdcS3l5A1WnVgO8NuzV3tin+w21qLrR1 1JluDtBQ/aOUj0zyY65DK6TrxyhzC2Ahl1ZHOs5SNF9gWgB6QXwJuxGSeUphou0YH+AX vKMJ7BuWUjt5f9x42YeiAdmFTIQ1zPyDiK+iZ8Pxu+q6JDj2w23/D7+iytM6MVqxc2Lr u2f2CvgFkcJs+pTZ+a8sc8C18nKWtsxDWWvXvWIGi3PEJeAQjan6nVRe9dMWlRMMZYXY wxcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/4kUSHiFCpPL9qQ3UOiS3LaHR+iaHi7L4Tr6+QKuD7g=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=KmSmXVvC6X839lVjTt+FGhsuf8GyNDpT580vvBTVRWDyhn5C75Gli2Ej4x+qUmq/z1 lA2XhONIIzKUreyCl+0Uw4ojPe1K0mmknH78OR0dxiB4N5WMrpXLbCf6ZnW9RUXSKA6x 8dCwxOOS2nfxEDzAL8Rld+K5sAoM0IULOIeblMpWn4LQyxqORBq3Ns230EhjCKk6lmpY 9DRomvQ42S5mee7AXiXbDVwgfRRpJaTdfjXt2BuZqsgN1WBVBR2aAY5fWhT1a6bkp69R w0teozYgDZXRStKvPoTy5ZaKINL66CvyT2lNxguABGQlOUv0my9GIQWWowz+SgnSlYOe qKDg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=h3+muNBK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 09/15] tcg/s390x: Do not accept immediate operand for andc, orc Date: Tue, 12 Mar 2024 04:38:33 -1000 Message-Id: <20240312143839.136408-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The transformations with inverted immediate are now done generically and need not be handled by the backend. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 56 ++++++-------------------------------- 1 file changed, 8 insertions(+), 48 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index ad587325fc..b9a3e6e56a 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -2216,31 +2216,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_andc_i32: - a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; - if (const_args[2]) { - tcg_out_mov(s, TCG_TYPE_I32, a0, a1); - tgen_andi(s, TCG_TYPE_I32, a0, (uint32_t)~a2); - } else { - tcg_out_insn(s, RRFa, NCRK, a0, a1, a2); - } + tcg_out_insn(s, RRFa, NCRK, args[0], args[1], args[2]); break; case INDEX_op_orc_i32: - a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; - if (const_args[2]) { - tcg_out_mov(s, TCG_TYPE_I32, a0, a1); - tgen_ori(s, a0, (uint32_t)~a2); - } else { - tcg_out_insn(s, RRFa, OCRK, a0, a1, a2); - } + tcg_out_insn(s, RRFa, OCRK, args[0], args[1], args[2]); break; case INDEX_op_eqv_i32: - a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; - if (const_args[2]) { - tcg_out_mov(s, TCG_TYPE_I32, a0, a1); - tcg_out_insn(s, RIL, XILF, a0, ~a2); - } else { - tcg_out_insn(s, RRFa, NXRK, a0, a1, a2); - } + tcg_out_insn(s, RRFa, NXRK, args[0], args[1], args[2]); break; case INDEX_op_nand_i32: tcg_out_insn(s, RRFa, NNRK, args[0], args[1], args[2]); @@ -2517,31 +2499,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_andc_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_mov(s, TCG_TYPE_I64, a0, a1); - tgen_andi(s, TCG_TYPE_I64, a0, ~a2); - } else { - tcg_out_insn(s, RRFa, NCGRK, a0, a1, a2); - } + tcg_out_insn(s, RRFa, NCGRK, args[0], args[1], args[2]); break; case INDEX_op_orc_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_mov(s, TCG_TYPE_I64, a0, a1); - tgen_ori(s, a0, ~a2); - } else { - tcg_out_insn(s, RRFa, OCGRK, a0, a1, a2); - } + tcg_out_insn(s, RRFa, OCGRK, args[0], args[1], args[2]); break; case INDEX_op_eqv_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_mov(s, TCG_TYPE_I64, a0, a1); - tgen_xori(s, a0, ~a2); - } else { - tcg_out_insn(s, RRFa, NXGRK, a0, a1, a2); - } + tcg_out_insn(s, RRFa, NXGRK, args[0], args[1], args[2]); break; case INDEX_op_nand_i64: tcg_out_insn(s, RRFa, NNGRK, args[0], args[1], args[2]); @@ -3244,15 +3208,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) return C_O1_I2(r, r, rK); case INDEX_op_andc_i32: - case INDEX_op_orc_i32: - case INDEX_op_eqv_i32: - return C_O1_I2(r, r, ri); case INDEX_op_andc_i64: - return C_O1_I2(r, r, rKR); + case INDEX_op_orc_i32: case INDEX_op_orc_i64: + case INDEX_op_eqv_i32: case INDEX_op_eqv_i64: - return C_O1_I2(r, r, rNK); - case INDEX_op_nand_i32: case INDEX_op_nand_i64: case INDEX_op_nor_i32: From patchwork Tue Mar 12 14:38:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 779757 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2058007wrt; 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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 10/15] tcg/riscv: Do not accept immediate operand for andc, orc, eqv Date: Tue, 12 Mar 2024 04:38:34 -1000 Message-Id: <20240312143839.136408-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The transformations with inverted immediate are now done generically and need not be handled by the backend. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 1 - tcg/riscv/tcg-target-con-str.h | 1 - tcg/riscv/tcg-target.c.inc | 36 +++++++--------------------------- 3 files changed, 7 insertions(+), 31 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index aac5ceee2b..0f72281a08 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -15,7 +15,6 @@ C_O0_I2(rZ, rZ) C_O1_I1(r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) -C_O1_I2(r, r, rJ) C_O1_I2(r, rZ, rN) C_O1_I2(r, rZ, rZ) C_N1_I2(r, r, rM) diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h index d5c419dff1..6f1cfb976c 100644 --- a/tcg/riscv/tcg-target-con-str.h +++ b/tcg/riscv/tcg-target-con-str.h @@ -15,7 +15,6 @@ REGS('r', ALL_GENERAL_REGS) * CONST(letter, TCG_CT_CONST_* bit set) */ CONST('I', TCG_CT_CONST_S12) -CONST('J', TCG_CT_CONST_J12) CONST('N', TCG_CT_CONST_N12) CONST('M', TCG_CT_CONST_M12) CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 639363039b..2b889486e4 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -138,7 +138,6 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) #define TCG_CT_CONST_S12 0x200 #define TCG_CT_CONST_N12 0x400 #define TCG_CT_CONST_M12 0x800 -#define TCG_CT_CONST_J12 0x1000 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) @@ -176,13 +175,6 @@ static bool tcg_target_const_match(int64_t val, int ct, if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) { return 1; } - /* - * Inverse of sign extended from 12 bits: ~[-0x800, 0x7ff]. - * Used to map ANDN back to ANDI, etc. - */ - if ((ct & TCG_CT_CONST_J12) && ~val >= -0x800 && ~val <= 0x7ff) { - return 1; - } return 0; } @@ -1610,27 +1602,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_andc_i32: case INDEX_op_andc_i64: - if (c2) { - tcg_out_opc_imm(s, OPC_ANDI, a0, a1, ~a2); - } else { - tcg_out_opc_reg(s, OPC_ANDN, a0, a1, a2); - } + tcg_out_opc_reg(s, OPC_ANDN, a0, a1, a2); break; case INDEX_op_orc_i32: case INDEX_op_orc_i64: - if (c2) { - tcg_out_opc_imm(s, OPC_ORI, a0, a1, ~a2); - } else { - tcg_out_opc_reg(s, OPC_ORN, a0, a1, a2); - } + tcg_out_opc_reg(s, OPC_ORN, a0, a1, a2); break; case INDEX_op_eqv_i32: case INDEX_op_eqv_i64: - if (c2) { - tcg_out_opc_imm(s, OPC_XORI, a0, a1, ~a2); - } else { - tcg_out_opc_reg(s, OPC_XNOR, a0, a1, a2); - } + tcg_out_opc_reg(s, OPC_XNOR, a0, a1, a2); break; case INDEX_op_not_i32: @@ -1963,18 +1943,16 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_negsetcond_i64: return C_O1_I2(r, r, rI); + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + return C_O1_I2(r, rZ, rN); + case INDEX_op_andc_i32: case INDEX_op_andc_i64: case INDEX_op_orc_i32: case INDEX_op_orc_i64: case INDEX_op_eqv_i32: case INDEX_op_eqv_i64: - return C_O1_I2(r, r, rJ); - - case INDEX_op_sub_i32: - case INDEX_op_sub_i64: - return C_O1_I2(r, rZ, rN); - case INDEX_op_mul_i32: case INDEX_op_mulsh_i32: case INDEX_op_muluh_i32: From patchwork Tue Mar 12 14:38:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 779754 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2057127wrt; Tue, 12 Mar 2024 07:42:49 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWptNTV7yn4V3p/Yyq0Sh9MfGdaC/K4HcGJsRi9IIBhJHNY95bgZ875aDkHX9Q61YKbIUIkuLiM3sgDI8yclFRM X-Google-Smtp-Source: AGHT+IFD8bdCodaWgVSxYWTaVcFpq79d4Mbxhj88K+eq6nd2VwD8kyHi8lSMyreMzmQQwHR1T1LO X-Received: by 2002:a05:622a:5c7:b0:42e:d04a:4c85 with SMTP id d7-20020a05622a05c700b0042ed04a4c85mr14202916qtb.66.1710254569052; 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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 11/15] tcg/riscv: Do not accept immediate operands for sub Date: Tue, 12 Mar 2024 04:38:35 -1000 Message-Id: <20240312143839.136408-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The transformations to neg and add immediate are now done generically and need not be handled by the backend. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 2 +- tcg/riscv/tcg-target-con-str.h | 1 - tcg/riscv/tcg-target.c.inc | 24 ++++-------------------- 3 files changed, 5 insertions(+), 22 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index 0f72281a08..13a383aeb1 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -13,9 +13,9 @@ C_O0_I1(r) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) C_O1_I1(r, r) +C_O1_I2(r, r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) -C_O1_I2(r, rZ, rN) C_O1_I2(r, rZ, rZ) C_N1_I2(r, r, rM) C_O1_I4(r, r, rI, rM, rM) diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h index 6f1cfb976c..a8d57c0e37 100644 --- a/tcg/riscv/tcg-target-con-str.h +++ b/tcg/riscv/tcg-target-con-str.h @@ -15,6 +15,5 @@ REGS('r', ALL_GENERAL_REGS) * CONST(letter, TCG_CT_CONST_* bit set) */ CONST('I', TCG_CT_CONST_S12) -CONST('N', TCG_CT_CONST_N12) CONST('M', TCG_CT_CONST_M12) CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 2b889486e4..6b28f2f85d 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -136,8 +136,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) #define TCG_CT_CONST_ZERO 0x100 #define TCG_CT_CONST_S12 0x200 -#define TCG_CT_CONST_N12 0x400 -#define TCG_CT_CONST_M12 0x800 +#define TCG_CT_CONST_M12 0x400 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) @@ -160,13 +159,6 @@ static bool tcg_target_const_match(int64_t val, int ct, if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) { return 1; } - /* - * Sign extended from 12 bits, negated: [-0x7ff, 0x800]. - * Used for subtraction, where a constant must be handled by ADDI. - */ - if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) { - return 1; - } /* * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff]. * Used by addsub2 and movcond, which may need the negative value, @@ -1559,18 +1551,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_sub_i32: - if (c2) { - tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, -a2); - } else { - tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2); - } + tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2); break; case INDEX_op_sub_i64: - if (c2) { - tcg_out_opc_imm(s, OPC_ADDI, a0, a1, -a2); - } else { - tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2); - } + tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2); break; case INDEX_op_and_i32: @@ -1945,7 +1929,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return C_O1_I2(r, rZ, rN); + return C_O1_I2(r, r, r); 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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 12/15] tcg/riscv: Do not accept zero operands for logicals, multiply or divide Date: Tue, 12 Mar 2024 04:38:36 -1000 Message-Id: <20240312143839.136408-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Trust that the optimizer has folded all of these away. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 1 - tcg/riscv/tcg-target.c.inc | 4 +--- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index 13a383aeb1..527d2fd4d9 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -16,7 +16,6 @@ C_O1_I1(r, r) C_O1_I2(r, r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) -C_O1_I2(r, rZ, rZ) C_N1_I2(r, r, rM) C_O1_I4(r, r, rI, rM, rM) C_O2_I4(r, r, rZ, rZ, rM, rM) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 6b28f2f85d..0dc1b2d8f7 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1929,8 +1929,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return C_O1_I2(r, r, r); - case INDEX_op_andc_i32: case INDEX_op_andc_i64: case INDEX_op_orc_i32: @@ -1951,7 +1949,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_divu_i64: case INDEX_op_rem_i64: case INDEX_op_remu_i64: - return C_O1_I2(r, rZ, rZ); + return C_O1_I2(r, r, r); case INDEX_op_shl_i32: case INDEX_op_shr_i32: From patchwork Tue Mar 12 14:38:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 779753 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2057087wrt; Tue, 12 Mar 2024 07:42:42 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUPw64uhZTz8K5hh8GCXPMdMxZy0XSJ8k6b2dw2LybpFE1wj5uj/07yGJYuAnhoxyJOCdbAjC0IaeVSLGzRTWnG X-Google-Smtp-Source: AGHT+IGw4fF3js3pXpUOMIDjF7Qu7dOcgCDFoUPQlJ82C0bQYpqTw4LBQ+CS3vrIFb3WnUhfpsl/ X-Received: by 2002:a0c:fe09:0:b0:690:c3ed:b15d with SMTP id x9-20020a0cfe09000000b00690c3edb15dmr452830qvr.22.1710254562392; Tue, 12 Mar 2024 07:42:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1710254562; cv=none; d=google.com; s=arc-20160816; b=wYRZoVhnjpSaD5BaHmDsOWH79z+dBiV/d0HqlWLMOURkx5y+S1DbEZzetsAAX0u3pd /TArQFzok6QmYQEF+VU7DBATrPH5jCfNGsAvaAOA70EMGlhoDcH5vgIk8shzHVu1pzAX hYsB6ljkSb/1lUf5ge90p2LZfc3KRJL5e+7juzLHAUhfnncLSbbLwuLuo1otNGqZKvbD 3jrGrJ7gzflSrum8IcM2QsoMJkE2tTsFHL58pkkEuk/ce4r8hyl7/85cxHanSYMLKtZv E8JBI57ubMFOxSZN5Lpf07I7PupI+DSLGmRAD1haBQoO9XXY7KZPbpnG9SQcAIb6Nt/h FQtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5KtrDk5IPnNDG0tAWNMkEiXDVZJDwN45mTz+TeCGBQA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Cv+aSl/vLhW4sxVgjbqYwZ7D8yrlQ/6NbzhEYIapUrMmB8otRPVBzleWZ2q+552Jr6 zdVteQc0ntIttV5IAT/LTb9whjVl5W3ghDbmosXLvFgvJfQSVEmCJnqumTs/gzgyPhYI hAUiu6l7KXpvzUcxhs2X7VBT85EPS4P1bbZsSJn9n+QxwUj51qUnY7Fqk6MFQhV7dv1r 49jD99xl3CegoeS16db+Nug1Gvt0y1XdvJCOJkTBiGr7qD9pLpVbT1PUcaSbbaVfweJu amUpvOW3x4qEq2M7S7yMfbxsk4XWoDEBfGSrLxJRVXdVcrv1j42nCzQOQvbmrVz6TXvM G6Bg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GdMEGvaU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.39.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:39:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 13/15] tcg/optimize: Fold and to extu during optimize Date: Tue, 12 Mar 2024 04:38:37 -1000 Message-Id: <20240312143839.136408-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/optimize.c | 43 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 39 insertions(+), 4 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index c6b0ab35c8..39bcd32f72 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1300,11 +1300,46 @@ static bool fold_and(OptContext *ctx, TCGOp *op) ctx->s_mask = arg_info(op->args[1])->s_mask & arg_info(op->args[2])->s_mask; - /* - * Known-zeros does not imply known-ones. Therefore unless - * arg2 is constant, we can't infer affected bits from it. - */ if (arg_is_const(op->args[2])) { + TCGOpcode ext8 = 0, ext16 = 0, ext32 = 0; + + /* Canonicalize as zero-extend, if supported. */ + switch (ctx->type) { + case TCG_TYPE_I32: + ext8 = TCG_TARGET_HAS_ext8u_i32 ? INDEX_op_ext8u_i32 : 0; + ext16 = TCG_TARGET_HAS_ext16u_i32 ? INDEX_op_ext16u_i32 : 0; + break; + case TCG_TYPE_I64: + ext8 = TCG_TARGET_HAS_ext8u_i64 ? INDEX_op_ext8u_i64 : 0; + ext16 = TCG_TARGET_HAS_ext16u_i64 ? INDEX_op_ext16u_i64 : 0; + ext32 = TCG_TARGET_HAS_ext32u_i64 ? INDEX_op_ext32u_i64 : 0; + break; + default: + break; + } + + switch (arg_info(op->args[2])->val) { + case 0xff: + if (ext8) { + op->opc = ext8; + } + break; + case 0xffff: + if (ext16) { + op->opc = ext16; + } + break; + case UINT32_MAX: + if (ext32) { + op->opc = ext32; + } + break; + } + + /* + * Known-zeros does not imply known-ones. Therefore unless + * arg2 is constant, we can't infer affected bits from it. + */ ctx->a_mask = z1 & ~z2; } From patchwork Tue Mar 12 14:38:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 779756 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2057967wrt; Tue, 12 Mar 2024 07:44:33 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXtxOF+eTfc1iXaKVlkWXpSHm0pXVNsq9TneYAp/5kuDrzA8+4j8ARluMCac52OOjx4/eQ87XOOUIoRUZFUl2EH X-Google-Smtp-Source: AGHT+IGblmU8w2jwZ5svQMXguCqb5z3NaRT65pHeWxX+N8tZnGIFtTtuLHT0ytFSTUdFME3ZEKQi X-Received: by 2002:ad4:514a:0:b0:690:c568:8dad with SMTP id g10-20020ad4514a000000b00690c5688dadmr591373qvq.16.1710254672966; Tue, 12 Mar 2024 07:44:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1710254672; cv=none; d=google.com; s=arc-20160816; b=jVAjfu9GJEyuYPSL3af8XqVdLb0DMaaU/IxUhpHXr+nHKcUx0YHHqPPFXNvbTyQI48 IMbvIXqRIcdMs0PiEzjO2MgSAUs7pOyIILlCf3R92oElw8Tt9RdxJtMc8mI3XpkUSHDJ EhN0nu8b+/wpRN6lhGrZ/QYIEDZDMylAqq8xcGy64Mxlrm+HjZhF/sp9zxwtUtuKZSK8 MuHw7TGyNQHpKNgScZMDZQQqDZ/OAd+OJf/qle6vZezY6lmmAFdc1mWTerF5gZNBrS1M lbvn/xWpgjnX+zp5ehArBu08wlmcNr0WU4Ktom6h9BWdFF2m4VMvDnkwID3bUW6uGQOw BuNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4kGtxvZdOI4O7h397wt7Rdsn7HhdcYY3ZpxBI2vFnmQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Ij/P53vpdC2ISK5wbFsEv0bnY70jKXS+3acwDYoAKhXYyy3QMGlg9wWftT4PU4GH7Q kYte1H0CouCNz45NK/A6qBGT1K835B9kDMEhIQPp4xTl33fNilBl43NTVb7GM60UJ3Pa SoCclreSQyjqhhzshRR3T9h0fK1Jf4U1Gu2sJa4lW5tVb4jj6PBNNeWiG8O+U/xvAEBF MSGa9kcV8sYo3fvMGRwGk5nsxoWQjqEQSPnZSFe5X2/0403fiOLTHObT/hRSyEMPWIZR VVlf5k2B1ZqhAv+O1VOfYemyrT0bk+gTw9zEMuTzVT1hqVb/nexnRYD2JpCEzggGjmlZ gvvA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ddrgLnUh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.39.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:39:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 14/15] tcg: Use arg_is_const_val in fold_sub_to_neg Date: Tue, 12 Mar 2024 04:38:38 -1000 Message-Id: <20240312143839.136408-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/optimize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 39bcd32f72..f3867ce9e6 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2451,7 +2451,7 @@ static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op) TCGOpcode neg_op; bool have_neg; - if (!arg_is_const(op->args[1]) || arg_info(op->args[1])->val != 0) { + if (!arg_is_const_val(op->args[1], 0)) { return false; } From patchwork Tue Mar 12 14:38:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 779752 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2056938wrt; Tue, 12 Mar 2024 07:42:26 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWqo70VFom3uDAkcNmlC/aOk9ld8AaDpRlIT1leiWxNM9J9F9IrCnlLh3SFxNF60iRy/fyUhus/EPLQpIzSUU4Y X-Google-Smtp-Source: AGHT+IFkD2GRqmuHruLI9tXETkFKsfFH1g/UA8qBXM+14JmAvd3oknl5e2JGjnYxJwBURSqPruTW X-Received: by 2002:ac8:5956:0:b0:42e:f5f8:eaa6 with SMTP id 22-20020ac85956000000b0042ef5f8eaa6mr565721qtz.37.1710254546020; Tue, 12 Mar 2024 07:42:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1710254545; cv=none; d=google.com; s=arc-20160816; b=RCcFZFaARnhNnkgmTrDvUuGrrOT7f4Z43V4NW0VW3alEOuZoIpoLDimRMPITZzsKJ/ wyT1Y3AaoUkVGfK9uALVZHVqPfLiw4+qa4Dwcqaawkz1pVa1XnAxqjVVhY0stQVm6YTm xdrVX3+ALw3wPtPakq5F8PJudcs0/T8LZ2yXEuKZUJdeZbxxCwZFYdeiAITuTF5gdE93 x+sqUq6xyXhFjoVYRHdVidz1Zj6IfaTOUeOcFwL+9Sqq6Gi8NOWrMfazRa/YZauOwlPl tvR0cy4HkW+EpG3w7S5+Q/m4SAdciXf4ofbMWvgQbfbLrr2lucx26TqjCYhQHPVyKOQi ZtnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ICGHco8N2bsqwCEhCf7Urzzd713nkLezWtvD//1fvW4=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=hZTKBt46Cm06vxIs6U1gJVAIquariGZhFIOmmovJuLHBKEGThung+kVUjh6oW8hEYP N57cd3m9sirHgDLl4sY+HWLXkjI6CInG9NyO/z6m9/OWojZtenJIoJAgxTQdGDDtU0fk L1QIK8czRJgU0prdAWy81ALSBpUt42NEX6iBnsIJgR6W4o3YJY4ErGlw2wXwb4B4ibKk A3DBVDKODd4EzznOH92j69eak1J582/BLGMxlfbLOsRxnlgTvUk2AXZ4RcSYTicyTJnQ 9dFAAcLqvzX/Myq4Vws3+TwLWqxlY7CpvSArA1Y6j4oCCvECOFF909IFany+Wx7L85d5 vhMw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Vu7pLF/I"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.39.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:39:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 15/15] tcg/optimize: Lower unsupported deposit during optimize Date: Tue, 12 Mar 2024 04:38:39 -1000 Message-Id: <20240312143839.136408-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The expansions that we chose in tcg-op.c may be less than optimial. Delay lowering until optimize, so that we have propagated constants and have computed known zero masks. Signed-off-by: Richard Henderson --- tcg/optimize.c | 231 +++++++++++++++++++++++++++++++++++++++++----- tcg/tcg-op.c | 244 ++++++++++++------------------------------------- 2 files changed, 266 insertions(+), 209 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index f3867ce9e6..ce1dbab097 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1632,51 +1632,234 @@ static bool fold_ctpop(OptContext *ctx, TCGOp *op) static bool fold_deposit(OptContext *ctx, TCGOp *op) { - TCGOpcode and_opc; + TCGOpcode and_opc, or_opc, ex2_opc, shl_opc, rotl_opc; + TCGOp *op2; + TCGArg ret = op->args[0]; + TCGArg arg1 = op->args[1]; + TCGArg arg2 = op->args[2]; + int ofs = op->args[3]; + int len = op->args[4]; + int width; + uint64_t type_mask; + bool valid; - if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { - uint64_t t1 = arg_info(op->args[1])->val; - uint64_t t2 = arg_info(op->args[2])->val; + if (arg_is_const(arg1) && arg_is_const(arg2)) { + uint64_t t1 = arg_info(arg1)->val; + uint64_t t2 = arg_info(arg2)->val; - t1 = deposit64(t1, op->args[3], op->args[4], t2); - return tcg_opt_gen_movi(ctx, op, op->args[0], t1); + t1 = deposit64(t1, ofs, len, t2); + return tcg_opt_gen_movi(ctx, op, ret, t1); } switch (ctx->type) { case TCG_TYPE_I32: and_opc = INDEX_op_and_i32; + or_opc = INDEX_op_or_i32; + shl_opc = INDEX_op_shl_i32; + ex2_opc = TCG_TARGET_HAS_extract2_i32 ? INDEX_op_extract2_i32 : 0; + rotl_opc = TCG_TARGET_HAS_rot_i32 ? INDEX_op_rotl_i32 : 0; + valid = (TCG_TARGET_HAS_deposit_i32 && + TCG_TARGET_deposit_i32_valid(ofs, len)); + width = 32; + type_mask = UINT32_MAX; break; case TCG_TYPE_I64: and_opc = INDEX_op_and_i64; + or_opc = INDEX_op_or_i64; + shl_opc = INDEX_op_shl_i64; + ex2_opc = TCG_TARGET_HAS_extract2_i64 ? INDEX_op_extract2_i64 : 0; + rotl_opc = TCG_TARGET_HAS_rot_i64 ? INDEX_op_rotl_i64 : 0; + valid = (TCG_TARGET_HAS_deposit_i64 && + TCG_TARGET_deposit_i64_valid(ofs, len)); + width = 64; + type_mask = UINT64_MAX; break; default: g_assert_not_reached(); } - /* Inserting a value into zero at offset 0. */ - if (arg_is_const_val(op->args[1], 0) && op->args[3] == 0) { - uint64_t mask = MAKE_64BIT_MASK(0, op->args[4]); + if (arg_is_const(arg2)) { + uint64_t val = arg_info(arg2)->val; + uint64_t mask = MAKE_64BIT_MASK(0, len); - op->opc = and_opc; - op->args[1] = op->args[2]; - op->args[2] = arg_new_constant(ctx, mask); - ctx->z_mask = mask & arg_info(op->args[1])->z_mask; - return false; + /* Inserting all-zero into a value. */ + if ((val & mask) == 0) { + op->opc = and_opc; + op->args[2] = arg_new_constant(ctx, ~(mask << ofs)); + return fold_and(ctx, op); + } + + /* Inserting all-one into a value. */ + if ((val & mask) == mask) { + op->opc = or_opc; + op->args[2] = arg_new_constant(ctx, mask << ofs); + goto done; + } + + /* Lower invalid deposit of constant as AND + OR. */ + if (!valid) { + op2 = tcg_op_insert_before(ctx->tcg, op, and_opc, 3); + op2->args[0] = ret; + op2->args[1] = arg1; + op2->args[2] = arg_new_constant(ctx, ~(mask << ofs)); + fold_and(ctx, op2); /* fold to ext*u */ + + op->opc = or_opc; + op->args[1] = ret; + op->args[2] = arg_new_constant(ctx, (val & mask) << ofs); + goto done; + } } - /* Inserting zero into a value. */ - if (arg_is_const_val(op->args[2], 0)) { - uint64_t mask = deposit64(-1, op->args[3], op->args[4], 0); + /* Inserting a value into zero. */ + if (arg_is_const_val(arg1, 0)) { + uint64_t mask = MAKE_64BIT_MASK(0, len); + uint64_t need_mask = arg_info(arg2)->z_mask & ~mask & type_mask; - op->opc = and_opc; - op->args[2] = arg_new_constant(ctx, mask); - ctx->z_mask = mask & arg_info(op->args[1])->z_mask; - return false; + /* Always lower deposit into zero at 0 as AND. */ + if (ofs == 0) { + if (!need_mask) { + return tcg_opt_gen_mov(ctx, op, ret, arg2); + } + op->opc = and_opc; + op->args[1] = arg2; + op->args[2] = arg_new_constant(ctx, mask); + return fold_and(ctx, op); + } + + /* If no mask required, fold as SHL. */ + if (!((need_mask << ofs) & type_mask)) { + op->opc = shl_opc; + op->args[1] = arg2; + op->args[2] = arg_new_constant(ctx, ofs); + goto done; + } + + /* Lower invalid deposit into zero as AND + SHL. */ + if (!valid) { + /* + * ret = arg2 & mask + * ret = ret << ofs + */ + TCGOpcode ext_second_opc = 0; + + switch (ofs + len) { + case 8: + ext_second_opc = + (ctx->type == TCG_TYPE_I32 + ? (TCG_TARGET_HAS_ext8u_i32 ? INDEX_op_ext8u_i32 : 0) + : (TCG_TARGET_HAS_ext8u_i64 ? INDEX_op_ext8u_i64 : 0)); + break; + case 16: + ext_second_opc = + (ctx->type == TCG_TYPE_I32 + ? (TCG_TARGET_HAS_ext16u_i32 ? INDEX_op_ext16u_i32 : 0) + : (TCG_TARGET_HAS_ext16u_i64 ? INDEX_op_ext16u_i64 : 0)); + break; + case 32: + ext_second_opc = + TCG_TARGET_HAS_ext32u_i64 ? INDEX_op_ext32u_i64 : 0; + break; + } + + if (ext_second_opc) { + op2 = tcg_op_insert_before(ctx->tcg, op, shl_opc, 3); + op2->args[0] = ret; + op2->args[1] = arg2; + op2->args[2] = arg_new_constant(ctx, ofs); + + op->opc = ext_second_opc; + op->args[1] = ret; + } else { + op2 = tcg_op_insert_before(ctx->tcg, op, and_opc, 3); + op2->args[0] = ret; + op2->args[1] = arg2; + op2->args[2] = arg_new_constant(ctx, mask); + fold_and(ctx, op2); + + op->opc = shl_opc; + op->args[1] = ret; + op->args[2] = arg_new_constant(ctx, ofs); + } + goto done; + } } - ctx->z_mask = deposit64(arg_info(op->args[1])->z_mask, - op->args[3], op->args[4], - arg_info(op->args[2])->z_mask); + /* After special cases, lower invalid deposit. */ + if (!valid) { + uint64_t mask = MAKE_64BIT_MASK(0, len); + TCGArg tmp; + + /* + * ret = arg2:arg1 >> len + * ret = rotl(ret, len) + */ + if (ex2_opc && rotl_opc && ofs == 0) { + op2 = tcg_op_insert_before(ctx->tcg, op, ex2_opc, 4); + op2->args[0] = ret; + op2->args[1] = arg1; + op2->args[2] = arg2; + op2->args[3] = len; + + op->opc = rotl_opc; + op->args[1] = ret; + op->args[2] = arg_new_constant(ctx, len); + goto done; + } + + /* + * tmp = arg1 << len + * ret = arg2:tmp >> len + */ + if (ex2_opc && ofs + len == width) { + tmp = ret == arg2 ? arg_new_temp(ctx) : ret; + + op2 = tcg_op_insert_before(ctx->tcg, op, shl_opc, 4); + op2->args[0] = tmp; + op2->args[1] = arg1; + op2->args[2] = arg_new_constant(ctx, len); + + op->opc = ex2_opc; + op->args[0] = ret; + op->args[1] = tmp; + op->args[2] = arg2; + op->args[3] = len; + goto done; + } + + /* + * tmp = arg2 & mask + * ret = arg1 & ~(mask << ofs) + * tmp = tmp << ofs + * ret = ret | tmp + */ + tmp = arg_new_temp(ctx); + + op2 = tcg_op_insert_before(ctx->tcg, op, and_opc, 3); + op2->args[0] = tmp; + op2->args[1] = arg2; + op2->args[2] = arg_new_constant(ctx, mask); + fold_and(ctx, op2); + + op2 = tcg_op_insert_before(ctx->tcg, op, shl_opc, 3); + op2->args[0] = tmp; + op2->args[1] = tmp; + op2->args[2] = arg_new_constant(ctx, ofs); + + op2 = tcg_op_insert_before(ctx->tcg, op, and_opc, 3); + op2->args[0] = ret; + op2->args[1] = arg1; + op2->args[2] = arg_new_constant(ctx, ~(mask << ofs)); + fold_and(ctx, op2); + + op->opc = or_opc; + op->args[1] = ret; + op->args[2] = tmp; + } + + done: + ctx->z_mask = deposit64(arg_info(arg1)->z_mask, ofs, len, + arg_info(arg2)->z_mask); return false; } diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index aa6bc6f57d..76a1f5e296 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -874,9 +874,6 @@ void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, unsigned int ofs, unsigned int len) { - uint32_t mask; - TCGv_i32 t1; - tcg_debug_assert(ofs < 32); tcg_debug_assert(len > 0); tcg_debug_assert(len <= 32); @@ -886,37 +883,7 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, tcg_gen_mov_i32(ret, arg2); return; } - if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) { - tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len); - return; - } - - t1 = tcg_temp_ebb_new_i32(); - - if (TCG_TARGET_HAS_extract2_i32) { - if (ofs + len == 32) { - tcg_gen_shli_i32(t1, arg1, len); - tcg_gen_extract2_i32(ret, t1, arg2, len); - goto done; - } - if (ofs == 0) { - tcg_gen_extract2_i32(ret, arg1, arg2, len); - tcg_gen_rotli_i32(ret, ret, len); - goto done; - } - } - - mask = (1u << len) - 1; - if (ofs + len < 32) { - tcg_gen_andi_i32(t1, arg2, mask); - tcg_gen_shli_i32(t1, t1, ofs); - } else { - tcg_gen_shli_i32(t1, arg2, ofs); - } - tcg_gen_andi_i32(ret, arg1, ~(mask << ofs)); - tcg_gen_or_i32(ret, ret, t1); - done: - tcg_temp_free_i32(t1); + tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len); } void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, @@ -931,48 +898,9 @@ void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, tcg_gen_shli_i32(ret, arg, ofs); } else if (ofs == 0) { tcg_gen_andi_i32(ret, arg, (1u << len) - 1); - } else if (TCG_TARGET_HAS_deposit_i32 - && TCG_TARGET_deposit_i32_valid(ofs, len)) { + } else { TCGv_i32 zero = tcg_constant_i32(0); tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, zero, arg, ofs, len); - } else { - /* To help two-operand hosts we prefer to zero-extend first, - which allows ARG to stay live. */ - switch (len) { - case 16: - if (TCG_TARGET_HAS_ext16u_i32) { - tcg_gen_ext16u_i32(ret, arg); - tcg_gen_shli_i32(ret, ret, ofs); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i32) { - tcg_gen_ext8u_i32(ret, arg); - tcg_gen_shli_i32(ret, ret, ofs); - return; - } - break; - } - /* Otherwise prefer zero-extension over AND for code size. */ - switch (ofs + len) { - case 16: - if (TCG_TARGET_HAS_ext16u_i32) { - tcg_gen_shli_i32(ret, arg, ofs); - tcg_gen_ext16u_i32(ret, ret); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i32) { - tcg_gen_shli_i32(ret, arg, ofs); - tcg_gen_ext8u_i32(ret, ret); - return; - } - break; - } - tcg_gen_andi_i32(ret, arg, (1u << len) - 1); - tcg_gen_shli_i32(ret, ret, ofs); } } @@ -2611,9 +2539,6 @@ void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, unsigned int ofs, unsigned int len) { - uint64_t mask; - TCGv_i64 t1; - tcg_debug_assert(ofs < 64); tcg_debug_assert(len > 0); tcg_debug_assert(len <= 64); @@ -2623,52 +2548,41 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, tcg_gen_mov_i64(ret, arg2); return; } - if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) { + + if (TCG_TARGET_REG_BITS == 64) { tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len); - return; - } - - if (TCG_TARGET_REG_BITS == 32) { - if (ofs >= 32) { - tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), - TCGV_LOW(arg2), ofs - 32, len); - tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); - return; - } - if (ofs + len <= 32) { - tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1), - TCGV_LOW(arg2), ofs, len); - tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1)); - return; - } - } - - t1 = tcg_temp_ebb_new_i64(); - - if (TCG_TARGET_HAS_extract2_i64) { - if (ofs + len == 64) { - tcg_gen_shli_i64(t1, arg1, len); - tcg_gen_extract2_i64(ret, t1, arg2, len); - goto done; - } - if (ofs == 0) { - tcg_gen_extract2_i64(ret, arg1, arg2, len); - tcg_gen_rotli_i64(ret, ret, len); - goto done; - } - } - - mask = (1ull << len) - 1; - if (ofs + len < 64) { - tcg_gen_andi_i64(t1, arg2, mask); - tcg_gen_shli_i64(t1, t1, ofs); + } else if (ofs >= 32) { + tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), + TCGV_LOW(arg2), ofs - 32, len); + tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); + } else if (ofs + len <= 32) { + tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1), + TCGV_LOW(arg2), ofs, len); + tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1)); + } else if (ofs == 0) { + tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), + TCGV_HIGH(arg2), 0, len - 32); + tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg2)); } else { - tcg_gen_shli_i64(t1, arg2, ofs); + /* The 64-bit deposit is split across the 32-bit halves. */ + unsigned lo_len = 32 - ofs; + unsigned hi_len = len - lo_len; + TCGv_i32 tl = tcg_temp_ebb_new_i32(); + TCGv_i32 th = tcg_temp_ebb_new_i32(); + + tcg_gen_deposit_i32(tl, TCGV_LOW(arg1), TCGV_LOW(arg2), ofs, lo_len); + if (len <= 32) { + tcg_gen_shri_i32(th, TCGV_LOW(arg2), lo_len); + } else { + tcg_gen_extract2_i32(th, TCGV_LOW(arg2), TCGV_HIGH(arg2), lo_len); + } + tcg_gen_deposit_i32(th, TCGV_HIGH(arg1), th, 0, hi_len); + + tcg_gen_mov_i32(TCGV_LOW(ret), tl); + tcg_gen_mov_i32(TCGV_HIGH(ret), th); + tcg_temp_free_i32(tl); + tcg_temp_free_i32(th); } - tcg_gen_andi_i64(ret, arg1, ~(mask << ofs)); - tcg_gen_or_i64(ret, ret, t1); - done: - tcg_temp_free_i64(t1); } void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, @@ -2683,75 +2597,35 @@ void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, tcg_gen_shli_i64(ret, arg, ofs); } else if (ofs == 0) { tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); - } else if (TCG_TARGET_HAS_deposit_i64 - && TCG_TARGET_deposit_i64_valid(ofs, len)) { + } else if (TCG_TARGET_REG_BITS == 64) { TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, zero, arg, ofs, len); + } else if (ofs >= 32) { + tcg_gen_deposit_z_i32(TCGV_HIGH(ret), TCGV_LOW(arg), ofs - 32, len); + tcg_gen_movi_i32(TCGV_LOW(ret), 0); + } else if (ofs + len <= 32) { + tcg_gen_deposit_z_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, len); + tcg_gen_movi_i32(TCGV_HIGH(ret), 0); + } else if (ofs == 0) { + tcg_gen_deposit_z_i32(TCGV_HIGH(ret), TCGV_HIGH(arg), 0, len - 32); + tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); } else { - if (TCG_TARGET_REG_BITS == 32) { - if (ofs >= 32) { - tcg_gen_deposit_z_i32(TCGV_HIGH(ret), TCGV_LOW(arg), - ofs - 32, len); - tcg_gen_movi_i32(TCGV_LOW(ret), 0); - return; - } - if (ofs + len <= 32) { - tcg_gen_deposit_z_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, len); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - return; - } + /* The 64-bit deposit is split across the 32-bit halves. */ + unsigned lo_len = 32 - ofs; + unsigned hi_len = len - lo_len; + TCGv_i32 tl = tcg_temp_ebb_new_i32(); + TCGv_i32 th = TCGV_HIGH(ret); + + tcg_gen_deposit_z_i32(tl, TCGV_LOW(arg), ofs, lo_len); + if (len <= 32) { + tcg_gen_shri_i32(th, TCGV_LOW(arg), lo_len); + } else { + tcg_gen_extract2_i32(th, TCGV_LOW(arg), TCGV_HIGH(arg), lo_len); } - /* To help two-operand hosts we prefer to zero-extend first, - which allows ARG to stay live. */ - switch (len) { - case 32: - if (TCG_TARGET_HAS_ext32u_i64) { - tcg_gen_ext32u_i64(ret, arg); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - break; - case 16: - if (TCG_TARGET_HAS_ext16u_i64) { - tcg_gen_ext16u_i64(ret, arg); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i64) { - tcg_gen_ext8u_i64(ret, arg); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - break; - } - /* Otherwise prefer zero-extension over AND for code size. */ - switch (ofs + len) { - case 32: - if (TCG_TARGET_HAS_ext32u_i64) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_ext32u_i64(ret, ret); - return; - } - break; - case 16: - if (TCG_TARGET_HAS_ext16u_i64) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_ext16u_i64(ret, ret); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i64) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_ext8u_i64(ret, ret); - return; - } - break; - } - tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); - tcg_gen_shli_i64(ret, ret, ofs); + tcg_gen_deposit_z_i32(th, th, 0, hi_len); + + tcg_gen_mov_i32(TCGV_LOW(ret), tl); + tcg_temp_free_i32(tl); } }