From patchwork Fri Mar 8 16:27:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 779283 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6ABC23BBE0; Fri, 8 Mar 2024 16:29:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709915373; cv=none; b=aSZEJL297zZa2HjVMlH8VVVur6VFIjyElAcBb9vAgm1j9o0ZJ0Y3RhDzyEJRQGUZtB9CINLW+yXimVDXqH0ygLOvWsR+NdePNoSsj0N63czIom93nNRwBIW9Nntz/h4r7sT/pJ6Jsy50xy54uhBD0pM56wnJN0kcNrO8nMsbVDc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709915373; c=relaxed/simple; bh=fIeQk5Wp5I84wTiwz4DvoHCEPwiTAvPIYfShGQ0P904=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=F/Sh8k/4wv8GEfYc9oxKGeRat6JtMB67hKAOjOLyc34U6uzrmgdpPRQ0cf//VAN8PhmuV9SLHdYywAkaDIcOcdCnCuKL2mg0Z/H2INh2j3rGWwtWulgwaEqOcMixW1mVxTDi37cAvCAK1YYIp9Vx+vbzM3WK3deIPRDbF8OvcNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TN37HMDF; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TN37HMDF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709915373; x=1741451373; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fIeQk5Wp5I84wTiwz4DvoHCEPwiTAvPIYfShGQ0P904=; b=TN37HMDFGaY/u98w+SRRk0i7k/0O4ZndpJuAcc7L7tymr4ItlPLl8sRs HU9PxnBOBH9BZqwT6/f1FH8aZZBBw0z0JTJSE1JU6lo3rjqdaaHGgpvlC vohe025GliQ87EKjLTUW0APzSSuvYlONVTM61bI9U+XU0x2LIgZBiQeqU BKvLkk13+6v4zPJGwCxKQWHzEzk9Gn32PU0nTE+VaZpCZ/3IszgIUJN9Q OvTp3+kh3ydbAL4VxMo9NkHXh7kKX3DQ+SjLpw/V9RX2an2vfikNXlmlO RVmIffepsoTcfO6eL6IS36EpkTcqU3MuFtthx/z1kf9S3uhjxHPhgBLSK w==; X-IronPort-AV: E=McAfee;i="6600,9927,11007"; a="4806761" X-IronPort-AV: E=Sophos;i="6.07,110,1708416000"; d="scan'208";a="4806761" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2024 08:29:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,11007"; a="937047684" X-IronPort-AV: E=Sophos;i="6.07,110,1708416000"; d="scan'208";a="937047684" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 08 Mar 2024 08:29:26 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id AE67C86; Fri, 8 Mar 2024 18:29:25 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mark Brown , Michal Simek Subject: [PATCH v2 1/3] spi: xilinx: Fix kernel documentation in the xilinx_spi.h Date: Fri, 8 Mar 2024 18:27:46 +0200 Message-ID: <20240308162920.46816-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1.gbec44491f096 In-Reply-To: <20240308162920.46816-1-andriy.shevchenko@linux.intel.com> References: <20240308162920.46816-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 While updating the data structure layout the kernel documentation became outdated. Synchronize kernel documentation with the actual data structure layout. Fixes: 1dd46599f83a ("spi: xilinx: add force_irq for QSPI mode") Fixes: 082339bc63cc ("spi: spi-xilinx: Add run run-time endian detection") Reviewed-by: Michal Simek Signed-off-by: Andy Shevchenko --- include/linux/spi/xilinx_spi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/spi/xilinx_spi.h b/include/linux/spi/xilinx_spi.h index 3934ce789d87..fd6add419e94 100644 --- a/include/linux/spi/xilinx_spi.h +++ b/include/linux/spi/xilinx_spi.h @@ -5,10 +5,10 @@ /** * struct xspi_platform_data - Platform data of the Xilinx SPI driver * @num_chipselect: Number of chip select by the IP. - * @little_endian: If registers should be accessed little endian or not. * @bits_per_word: Number of bits per word. * @devices: Devices to add when the driver is probed. * @num_devices: Number of devices in the devices array. + * @force_irq: If set, forces QSPI transaction requirements. */ struct xspi_platform_data { u16 num_chipselect; From patchwork Fri Mar 8 16:27:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 779114 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D11138DF9; Fri, 8 Mar 2024 16:29:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709915374; cv=none; b=Gibvp9KujpbEz71D5a/RPv0Pn8fbvFqx9rnLHTEsIuvxVIpIVJS+qmvdDKfAbZy2lwngpVxCsKZY8tr1Y0K/f+BT/w0rkxmfLGa7qjL99hgSbXkbvn3RxESXZGGR675gq1HihiaLkG3Hz/CDAYDVYqZPg0ckIZXmFwa0HXv4kLo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709915374; c=relaxed/simple; bh=XXvje3DsPXFomNyXuJGV+9j2nWWkci2XhBpIRqsHwDM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=L/iWVze2OuOsVsm623goSUkskGtJ7gfZ4xEIQV4biHAEovif2FchzLe3POWXm7qh7MpN1Px3b8FZ+dldG24TBfbE+gslNi6yKpQ25kakadGqI928IxfZ4gFvaOobXWsbduoxgU73V/qi0TLkdZ5zNgiTR44wg69KSA9vB4YpquM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=OhP+f60Y; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="OhP+f60Y" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709915373; x=1741451373; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XXvje3DsPXFomNyXuJGV+9j2nWWkci2XhBpIRqsHwDM=; b=OhP+f60YfOyVYY72Ea0xl0cFzEMEVM7Ow9HY9KyO/yiXAK5c+3nxwVYl lrczekFWljkGAzqfmnwYbaHbmJKyxIHO9p/gGmkfWn1QH1F22cl/umUsj iKDUDBmmlcXvAkXZ8h5/YoeDkjezNw5ymRVEDzLL0rBw2i7KRP/WL/USU 84zspYRxBXfhhX7Vv5oPonHQlKWq0790Z/lmyhyXAi9p6EyPjTrcAUCG/ 1whZhbcdZgKHgoTDWbewXyXVxdzj0y67yuMO+IPieIRmsmu2tEWu3WIPP F5k48+D6h0AfWWqE/GzEtjPcmCSQsPUPMBaM5aEpQx1l8BWrMDmuU9li7 g==; X-IronPort-AV: E=McAfee;i="6600,9927,11007"; a="4806765" X-IronPort-AV: E=Sophos;i="6.07,110,1708416000"; d="scan'208";a="4806765" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2024 08:29:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,11007"; a="937047685" X-IronPort-AV: E=Sophos;i="6.07,110,1708416000"; d="scan'208";a="937047685" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 08 Mar 2024 08:29:26 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id B631921A; Fri, 8 Mar 2024 18:29:25 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mark Brown , Michal Simek Subject: [PATCH v2 2/3] spi: xilinx: Add necessary inclusion and forward declaration Date: Fri, 8 Mar 2024 18:27:47 +0200 Message-ID: <20240308162920.46816-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1.gbec44491f096 In-Reply-To: <20240308162920.46816-1-andriy.shevchenko@linux.intel.com> References: <20240308162920.46816-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 xilinx_spi.h is mnissing inclusion and forward declaration, add them. Signed-off-by: Andy Shevchenko --- include/linux/spi/xilinx_spi.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/linux/spi/xilinx_spi.h b/include/linux/spi/xilinx_spi.h index fd6add419e94..4ba8f53ce570 100644 --- a/include/linux/spi/xilinx_spi.h +++ b/include/linux/spi/xilinx_spi.h @@ -2,6 +2,10 @@ #ifndef __LINUX_SPI_XILINX_SPI_H #define __LINUX_SPI_XILINX_SPI_H +#include + +struct spi_board_info; + /** * struct xspi_platform_data - Platform data of the Xilinx SPI driver * @num_chipselect: Number of chip select by the IP. From patchwork Fri Mar 8 16:27:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 779115 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D93D92D058; Fri, 8 Mar 2024 16:29:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709915372; cv=none; b=STGqCLnWvrB4lWZuYEKL5jqlWhBziSat1beasLw2TRJFSR3cW1mqPMgF5uwK3MstZcwVNsHpl/73/5oxVKuqvbDsJy90pPh+SMI6XQ30UBkqPrCMYefSCZjSE1RDg+ChrPEuxrUhtzf/NZUZ6mQi7t8kjzE9XB1X1ETN0OU09Ps= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709915372; c=relaxed/simple; bh=5/XZC3z+eM8wwJ1lF4j9tR0kE6krkAhcW+WKtsojmIg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Uu/gX4kWLEx/lmWDj+B07xCR/TK8LmYAXzZep+kkmUKiKnv0ZrByY67X+mNnz9dxYNWn29n8apTrqdpW8HBuL26X/fhmZATECujfHgSceqAqhxY+HAgKeJirtahN1Odi9jFrU6euCCBe13v0KsOXdBz6aBEZPH6FHhPq70ZGdKE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=c7UoKGdJ; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="c7UoKGdJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709915371; x=1741451371; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5/XZC3z+eM8wwJ1lF4j9tR0kE6krkAhcW+WKtsojmIg=; b=c7UoKGdJ8B8uT9N5UBK1oMlKyuK7qC0ieuRQy3MMD0Qi/95zxCLfctbX 7Q+0yux2TxBefMlAGKeSx6vMvghY8i/QDbJvFyNpZ3VV/0a5KNLzhFMD+ +1HUF/aoQJ7o1rlxpYYQzxIHGcbqUAIoeH0Fwyt4RBRzbkdQ1v+33rugF MiE3xK1Hs/oLJtO3nKVx7eRMRsib0iQCCYhBIHJDM6fOVr52aabrcX0/k GKCvnhUksJ2m0hZiB3I/v1/8WAOD6r2UEb3NPvb8AIsXgpsbpqRohgeg+ k1ZkRR2i4co8D32hwzFgjwjHOa4cQ9FiePQfavKBejcTiks9qVQG0Oy+y A==; X-IronPort-AV: E=McAfee;i="6600,9927,11007"; a="4806750" X-IronPort-AV: E=Sophos;i="6.07,110,1708416000"; d="scan'208";a="4806750" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2024 08:29:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,11007"; a="937047682" X-IronPort-AV: E=Sophos;i="6.07,110,1708416000"; d="scan'208";a="937047682" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 08 Mar 2024 08:29:26 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id C7F7D369; Fri, 8 Mar 2024 18:29:25 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mark Brown , Michal Simek Subject: [PATCH v2 3/3] spi: xilinx: Make num_chipselect 8-bit in the struct xspi_platform_data Date: Fri, 8 Mar 2024 18:27:48 +0200 Message-ID: <20240308162920.46816-4-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1.gbec44491f096 In-Reply-To: <20240308162920.46816-1-andriy.shevchenko@linux.intel.com> References: <20240308162920.46816-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 There is no use for whole 16-bit for the number of chip select pins. Drop it to 8 bits and reshuffle the data structure layout to avoid unnecessary paddings. Signed-off-by: Andy Shevchenko Reviewed-by: Michal Simek --- include/linux/spi/xilinx_spi.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/linux/spi/xilinx_spi.h b/include/linux/spi/xilinx_spi.h index 4ba8f53ce570..1b8d984668b6 100644 --- a/include/linux/spi/xilinx_spi.h +++ b/include/linux/spi/xilinx_spi.h @@ -8,17 +8,17 @@ struct spi_board_info; /** * struct xspi_platform_data - Platform data of the Xilinx SPI driver - * @num_chipselect: Number of chip select by the IP. - * @bits_per_word: Number of bits per word. * @devices: Devices to add when the driver is probed. * @num_devices: Number of devices in the devices array. + * @num_chipselect: Number of chip select by the IP. + * @bits_per_word: Number of bits per word. * @force_irq: If set, forces QSPI transaction requirements. */ struct xspi_platform_data { - u16 num_chipselect; - u8 bits_per_word; struct spi_board_info *devices; u8 num_devices; + u8 num_chipselect; + u8 bits_per_word; bool force_irq; };