From patchwork Wed Mar 6 21:24:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 778413 Received: from 2.mo550.mail-out.ovh.net (2.mo550.mail-out.ovh.net [178.32.119.250]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3CF51AAD0 for ; Wed, 6 Mar 2024 21:25:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.32.119.250 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709760347; cv=none; b=gwE4Tzcan8lsvSWS3k3duzW5BcVFl30GwwkLcGotDtxeU/fUUn+hM297DRVxsIiJ6mtu5xjZHgmyA4CyEaOPUH3u2lFpvS+RMRPTG2F6X6DFcpyOKm09923CowPMnAxzV2PCiE6fMAtk4vAEReIuXuAszMSy3gVK0xIY/OpBTkE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709760347; c=relaxed/simple; bh=N4bjMymLOb6Yrre2TAwpscAUQ+afxkGrB1+Z+/zWx6M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tG6ZsNRS11yn9AFvyFioAFOYePNQE9T4awLdMMxTie8H7yprC9B/fz61oI+Bav2524gUdDOIi+pv+FsDH8Fn5clump98MYhgh9MqBV7k6EJfN9qiFzQO/aXG/R2U7IpNrGRgUy2HhCHIH0cxaDD04wzARADLM6YfMw9afJ+Qvng= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org; spf=pass smtp.mailfrom=etezian.org; arc=none smtp.client-ip=178.32.119.250 Authentication-Results: smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=etezian.org Received: from director1.ghost.mail-out.ovh.net (unknown [10.109.176.70]) by mo550.mail-out.ovh.net (Postfix) with ESMTP id 4TqlpZ5R1Sz1HmZ for ; Wed, 6 Mar 2024 21:25:42 +0000 (UTC) Received: from ghost-submission-6684bf9d7b-l5cp9 (unknown [10.110.168.168]) by director1.ghost.mail-out.ovh.net (Postfix) with ESMTPS id 206841FDEF; Wed, 6 Mar 2024 21:25:41 +0000 (UTC) Received: from etezian.org ([37.59.142.97]) by ghost-submission-6684bf9d7b-l5cp9 with ESMTPSA id p3RZOFXf6GXdLwAA7QAJSA (envelope-from ); Wed, 06 Mar 2024 21:25:41 +0000 Authentication-Results: garm.ovh; auth=pass (GARM-97G002f5882272-5ef6-4535-afa9-a133dcf8b378, 62DEF991EB217AB86F953B10C2782167B22AFEEB) smtp.auth=andi@etezian.org X-OVh-ClientIp: 89.217.109.169 From: Andi Shyti To: Hans Hu , linux-i2c@vger.kernel.org Cc: wsa@kernel.org, cobechen@zhaoxin.com, hanshu@zhaoxin.com, Andi Shyti Subject: [PATCH v9 4/6] i2c: wmt: fix a bug when thread blocked Date: Wed, 6 Mar 2024 22:24:11 +0100 Message-ID: <20240306212413.1850236-5-andi.shyti@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240306212413.1850236-1-andi.shyti@kernel.org> References: <20240306212413.1850236-1-andi.shyti@kernel.org> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Ovh-Tracer-Id: 16093050322633361991 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: 0 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvledriedugddugeegucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucenucfjughrpefhvfevufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpeetnhguihcuufhhhihtihcuoegrnhguihdrshhhhihtiheskhgvrhhnvghlrdhorhhgqeenucggtffrrghtthgvrhhnpefgudevjeetgeetlefhteeuteehgeefhefhkedtvdelheethfehveekudelueeuveenucfkphepuddvjedrtddrtddruddpkeelrddvudejrddutdelrdduieelpdefjedrheelrddugedvrdeljeenucevlhhushhtvghrufhiiigvpedunecurfgrrhgrmhepihhnvghtpeduvdejrddtrddtrddupdhmrghilhhfrhhomheprghnughisegvthgviihirghnrdhorhhgpdhnsggprhgtphhtthhopedupdhrtghpthhtoheplhhinhhugidqihdvtgesvhhgvghrrdhkvghrnhgvlhdrohhrghdpoffvtefjohhsthepmhhoheehtddpmhhouggvpehsmhhtphhouhht From: Hans Hu During each byte access, the host performs clock stretching. To reduce the host performs clock stretching, move most of the per-msg processing to the interrupt context. Signed-off-by: Hans Hu Suggested-by: Wolfram Sang Reviewed-by: Wolfram Sang Signed-off-by: Andi Shyti --- drivers/i2c/busses/i2c-viai2c-common.c | 139 ++++++++++++------------- drivers/i2c/busses/i2c-viai2c-common.h | 6 +- 2 files changed, 73 insertions(+), 72 deletions(-) diff --git a/drivers/i2c/busses/i2c-viai2c-common.c b/drivers/i2c/busses/i2c-viai2c-common.c index 3e565d5ee4c7c..30405205ba3a0 100644 --- a/drivers/i2c/busses/i2c-viai2c-common.c +++ b/drivers/i2c/busses/i2c-viai2c-common.c @@ -18,37 +18,18 @@ int viai2c_wait_bus_not_busy(struct viai2c *i2c) return 0; } -int viai2c_check_status(struct viai2c *i2c) -{ - int ret = 0; - unsigned long time_left; - - time_left = wait_for_completion_timeout(&i2c->complete, - msecs_to_jiffies(500)); - if (!time_left) - return -ETIMEDOUT; - - if (i2c->cmd_status & VIAI2C_ISR_NACK_ADDR) - ret = -EIO; - - if (i2c->cmd_status & VIAI2C_ISR_SCL_TIMEOUT) - ret = -ETIMEDOUT; - - return ret; -} - static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, int last) { u16 val, tcr_val = i2c->tcr; - int ret; - int xfer_len = 0; + + i2c->last = last; if (pmsg->len == 0) { /* * We still need to run through the while (..) once, so * start at -1 and break out early from the loop */ - xfer_len = -1; + i2c->xfered_len = -1; writew(0, i2c->base + VIAI2C_REG_CDR); } else { writew(pmsg->buf[0] & 0xFF, i2c->base + VIAI2C_REG_CDR); @@ -73,43 +54,15 @@ static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, int last) writew(val, i2c->base + VIAI2C_REG_CR); } - while (xfer_len < pmsg->len) { - ret = viai2c_check_status(i2c); - if (ret) - return ret; - - xfer_len++; - - val = readw(i2c->base + VIAI2C_REG_CSR); - if (val & VIAI2C_CSR_RCV_NOT_ACK) { - dev_dbg(i2c->dev, "write RCV NACK error\n"); - return -EIO; - } - - if (pmsg->len == 0) { - val = VIAI2C_CR_TX_END | VIAI2C_CR_CPU_RDY | VIAI2C_CR_ENABLE; - writew(val, i2c->base + VIAI2C_REG_CR); - break; - } - - if (xfer_len == pmsg->len) { - if (last != 1) - writew(VIAI2C_CR_ENABLE, i2c->base + VIAI2C_REG_CR); - } else { - writew(pmsg->buf[xfer_len] & 0xFF, i2c->base + VIAI2C_REG_CDR); - writew(VIAI2C_CR_CPU_RDY | VIAI2C_CR_ENABLE, - i2c->base + VIAI2C_REG_CR); - } - } + if (!wait_for_completion_timeout(&i2c->complete, VIAI2C_TIMEOUT)) + return -ETIMEDOUT; - return 0; + return i2c->ret; } static int viai2c_read(struct viai2c *i2c, struct i2c_msg *pmsg) { u16 val, tcr_val = i2c->tcr; - int ret; - u32 xfer_len = 0; val = readw(i2c->base + VIAI2C_REG_CR); val &= ~(VIAI2C_CR_TX_END | VIAI2C_CR_RX_END); @@ -134,21 +87,10 @@ static int viai2c_read(struct viai2c *i2c, struct i2c_msg *pmsg) writew(val, i2c->base + VIAI2C_REG_CR); } - while (xfer_len < pmsg->len) { - ret = viai2c_check_status(i2c); - if (ret) - return ret; - - pmsg->buf[xfer_len] = readw(i2c->base + VIAI2C_REG_CDR) >> 8; - xfer_len++; - - val = readw(i2c->base + VIAI2C_REG_CR) | VIAI2C_CR_CPU_RDY; - if (xfer_len == pmsg->len - 1) - val |= VIAI2C_CR_RX_END; - writew(val, i2c->base + VIAI2C_REG_CR); - } + if (!wait_for_completion_timeout(&i2c->complete, VIAI2C_TIMEOUT)) + return -ETIMEDOUT; - return 0; + return i2c->ret; } int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) @@ -166,6 +108,9 @@ int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) return ret; } + i2c->msg = pmsg; + i2c->xfered_len = 0; + if (pmsg->flags & I2C_M_RD) ret = viai2c_read(i2c, pmsg); else @@ -175,15 +120,69 @@ int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) return (ret < 0) ? ret : i; } +static int viai2c_irq_xfer(struct viai2c *i2c) +{ + u16 val; + struct i2c_msg *msg = i2c->msg; + u8 read = msg->flags & I2C_M_RD; + void __iomem *base = i2c->base; + + if (read) { + msg->buf[i2c->xfered_len] = readw(base + VIAI2C_REG_CDR) >> 8; + + val = readw(base + VIAI2C_REG_CR) | VIAI2C_CR_CPU_RDY; + if (i2c->xfered_len == msg->len - 2) + val |= VIAI2C_CR_RX_END; + writew(val, base + VIAI2C_REG_CR); + } else { + + val = readw(base + VIAI2C_REG_CSR); + if (val & VIAI2C_CSR_RCV_NOT_ACK) { + dev_dbg_ratelimited(i2c->dev, "write RCV NACK error\n"); + return -EIO; + } + + if (msg->len == 0) { + val = VIAI2C_CR_TX_END | VIAI2C_CR_CPU_RDY | VIAI2C_CR_ENABLE; + writew(val, base + VIAI2C_REG_CR); + return 0; + } + + if ((i2c->xfered_len + 1) == msg->len) { + if (!i2c->last) + writew(VIAI2C_CR_ENABLE, base + VIAI2C_REG_CR); + } else { + writew(msg->buf[i2c->xfered_len + 1] & 0xFF, base + VIAI2C_REG_CDR); + writew(VIAI2C_CR_CPU_RDY | VIAI2C_CR_ENABLE, base + VIAI2C_REG_CR); + } + } + + i2c->xfered_len++; + + return i2c->xfered_len == msg->len; +} + static irqreturn_t viai2c_isr(int irq, void *data) { struct viai2c *i2c = data; + u8 status; /* save the status and write-clear it */ - i2c->cmd_status = readw(i2c->base + VIAI2C_REG_ISR); - writew(i2c->cmd_status, i2c->base + VIAI2C_REG_ISR); + status = readw(i2c->base + VIAI2C_REG_ISR); + writew(status, i2c->base + VIAI2C_REG_ISR); + + i2c->ret = 0; + if (status & VIAI2C_ISR_NACK_ADDR) + i2c->ret = -EIO; + + if (status & VIAI2C_ISR_SCL_TIMEOUT) + i2c->ret = -ETIMEDOUT; + + if (!i2c->ret) + i2c->ret = viai2c_irq_xfer(i2c); - complete(&i2c->complete); + if (i2c->ret) + complete(&i2c->complete); return IRQ_HANDLED; } diff --git a/drivers/i2c/busses/i2c-viai2c-common.h b/drivers/i2c/busses/i2c-viai2c-common.h index 28799e7e97f0b..c92e054ac7e73 100644 --- a/drivers/i2c/busses/i2c-viai2c-common.h +++ b/drivers/i2c/busses/i2c-viai2c-common.h @@ -58,11 +58,13 @@ struct viai2c { struct clk *clk; u16 tcr; int irq; - u16 cmd_status; + u16 xfered_len; + struct i2c_msg *msg; + int ret; + bool last; }; int viai2c_wait_bus_not_busy(struct viai2c *i2c); -int viai2c_check_status(struct viai2c *i2c); int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num); int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c); From patchwork Wed Mar 6 21:24:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 778411 Received: from 5.mo560.mail-out.ovh.net (5.mo560.mail-out.ovh.net [87.98.181.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12F251B968 for ; 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dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=etezian.org Received: from director11.ghost.mail-out.ovh.net (unknown [10.108.2.55]) by mo560.mail-out.ovh.net (Postfix) with ESMTP id 4Tqlpd4mD7z1G1D for ; Wed, 6 Mar 2024 21:25:45 +0000 (UTC) Received: from ghost-submission-6684bf9d7b-74c7m (unknown [10.110.96.108]) by director11.ghost.mail-out.ovh.net (Postfix) with ESMTPS id E30EE1FE99; Wed, 6 Mar 2024 21:25:43 +0000 (UTC) Received: from etezian.org ([37.59.142.109]) by ghost-submission-6684bf9d7b-74c7m with ESMTPSA id of61IVff6GV+DQAAvg/sBA (envelope-from ); Wed, 06 Mar 2024 21:25:43 +0000 Authentication-Results: garm.ovh; auth=pass (GARM-109S0036571fc3b-4779-4baf-81d5-95fce6c60466, 62DEF991EB217AB86F953B10C2782167B22AFEEB) smtp.auth=andi@etezian.org X-OVh-ClientIp: 89.217.109.169 From: Andi Shyti To: Hans Hu , linux-i2c@vger.kernel.org Cc: wsa@kernel.org, cobechen@zhaoxin.com, hanshu@zhaoxin.com, Andi Shyti Subject: [PATCH v9 5/6] i2c: wmt: add platform type VIAI2C_PLAT_WMT Date: Wed, 6 Mar 2024 22:24:12 +0100 Message-ID: <20240306212413.1850236-6-andi.shyti@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240306212413.1850236-1-andi.shyti@kernel.org> References: <20240306212413.1850236-1-andi.shyti@kernel.org> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Ovh-Tracer-Id: 16093894744656185927 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: 0 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvledriedugddugeegucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucenucfjughrpefhvfevufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpeetnhguihcuufhhhihtihcuoegrnhguihdrshhhhihtiheskhgvrhhnvghlrdhorhhgqeenucggtffrrghtthgvrhhnpefgudevjeetgeetlefhteeuteehgeefhefhkedtvdelheethfehveekudelueeuveenucfkphepuddvjedrtddrtddruddpkeelrddvudejrddutdelrdduieelpdefjedrheelrddugedvrddutdelnecuvehluhhsthgvrhfuihiivgepudenucfrrghrrghmpehinhgvthepuddvjedrtddrtddruddpmhgrihhlfhhrohhmpegrnhguihesvghtvgiiihgrnhdrohhrghdpnhgspghrtghpthhtohepuddprhgtphhtthhopehlihhnuhigqdhivdgtsehvghgvrhdrkhgvrhhnvghlrdhorhhgpdfovfetjfhoshhtpehmohehiedtpdhmohguvgepshhmthhpohhuth From: Hans Hu Enumeration variables are added to differentiate between different platforms. Signed-off-by: Hans Hu Acked-by: Wolfram Sang Signed-off-by: Andi Shyti --- drivers/i2c/busses/i2c-viai2c-common.c | 33 ++++++++++++++++---------- drivers/i2c/busses/i2c-viai2c-common.h | 7 +++++- drivers/i2c/busses/i2c-viai2c-wmt.c | 2 +- 3 files changed, 28 insertions(+), 14 deletions(-) diff --git a/drivers/i2c/busses/i2c-viai2c-common.c b/drivers/i2c/busses/i2c-viai2c-common.c index 30405205ba3a0..75663a3e3fe57 100644 --- a/drivers/i2c/busses/i2c-viai2c-common.c +++ b/drivers/i2c/busses/i2c-viai2c-common.c @@ -35,7 +35,7 @@ static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, int last) writew(pmsg->buf[0] & 0xFF, i2c->base + VIAI2C_REG_CDR); } - if (!(pmsg->flags & I2C_M_NOSTART)) { + if (i2c->platform == VIAI2C_PLAT_WMT && !(pmsg->flags & I2C_M_NOSTART)) { val = readw(i2c->base + VIAI2C_REG_CR); val &= ~VIAI2C_CR_TX_END; val |= VIAI2C_CR_CPU_RDY; @@ -48,7 +48,7 @@ static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, int last) writew(tcr_val, i2c->base + VIAI2C_REG_TCR); - if (pmsg->flags & I2C_M_NOSTART) { + if (i2c->platform == VIAI2C_PLAT_WMT && pmsg->flags & I2C_M_NOSTART) { val = readw(i2c->base + VIAI2C_REG_CR); val |= VIAI2C_CR_CPU_RDY; writew(val, i2c->base + VIAI2C_REG_CR); @@ -67,7 +67,7 @@ static int viai2c_read(struct viai2c *i2c, struct i2c_msg *pmsg) val = readw(i2c->base + VIAI2C_REG_CR); val &= ~(VIAI2C_CR_TX_END | VIAI2C_CR_RX_END); - if (!(pmsg->flags & I2C_M_NOSTART)) + if (i2c->platform == VIAI2C_PLAT_WMT && !(pmsg->flags & I2C_M_NOSTART)) val |= VIAI2C_CR_CPU_RDY; if (pmsg->len == 1) @@ -81,7 +81,7 @@ static int viai2c_read(struct viai2c *i2c, struct i2c_msg *pmsg) writew(tcr_val, i2c->base + VIAI2C_REG_TCR); - if (pmsg->flags & I2C_M_NOSTART) { + if (i2c->platform == VIAI2C_PLAT_WMT && (pmsg->flags & I2C_M_NOSTART)) { val = readw(i2c->base + VIAI2C_REG_CR); val |= VIAI2C_CR_CPU_RDY; writew(val, i2c->base + VIAI2C_REG_CR); @@ -102,7 +102,8 @@ int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) for (i = 0; ret >= 0 && i < num; i++) { pmsg = &msgs[i]; - if (!(pmsg->flags & I2C_M_NOSTART)) { + if ((i2c->platform == VIAI2C_PLAT_WMT) + && !(pmsg->flags & I2C_M_NOSTART)) { ret = viai2c_wait_bus_not_busy(i2c); if (ret < 0) return ret; @@ -149,7 +150,7 @@ static int viai2c_irq_xfer(struct viai2c *i2c) } if ((i2c->xfered_len + 1) == msg->len) { - if (!i2c->last) + if (i2c->platform == VIAI2C_PLAT_WMT && !i2c->last) writew(VIAI2C_CR_ENABLE, base + VIAI2C_REG_CR); } else { writew(msg->buf[i2c->xfered_len + 1] & 0xFF, base + VIAI2C_REG_CDR); @@ -175,7 +176,7 @@ static irqreturn_t viai2c_isr(int irq, void *data) if (status & VIAI2C_ISR_NACK_ADDR) i2c->ret = -EIO; - if (status & VIAI2C_ISR_SCL_TIMEOUT) + if (i2c->platform == VIAI2C_PLAT_WMT && (status & VIAI2C_ISR_SCL_TIMEOUT)) i2c->ret = -ETIMEDOUT; if (!i2c->ret) @@ -187,9 +188,10 @@ static irqreturn_t viai2c_isr(int irq, void *data) return IRQ_HANDLED; } -int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c) +int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c, int plat) { int err; + int irq_flags; struct viai2c *i2c; struct device_node *np = pdev->dev.of_node; @@ -201,12 +203,19 @@ int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c) if (IS_ERR(i2c->base)) return PTR_ERR(i2c->base); - i2c->irq = irq_of_parse_and_map(np, 0); - if (!i2c->irq) - return -EINVAL; + if (plat == VIAI2C_PLAT_WMT) { + irq_flags = 0; + i2c->irq = irq_of_parse_and_map(np, 0); + if (!i2c->irq) + return -EINVAL; + } else { + return dev_err_probe(&pdev->dev, -EINVAL, "wrong platform type\n"); + } + + i2c->platform = plat; err = devm_request_irq(&pdev->dev, i2c->irq, viai2c_isr, - 0, pdev->name, i2c); + irq_flags, pdev->name, i2c); if (err) return dev_err_probe(&pdev->dev, err, "failed to request irq %i\n", i2c->irq); diff --git a/drivers/i2c/busses/i2c-viai2c-common.h b/drivers/i2c/busses/i2c-viai2c-common.h index c92e054ac7e73..cfe5ab2bd7792 100644 --- a/drivers/i2c/busses/i2c-viai2c-common.h +++ b/drivers/i2c/busses/i2c-viai2c-common.h @@ -50,6 +50,10 @@ #define VIAI2C_TIMEOUT (msecs_to_jiffies(1000)) +enum { + VIAI2C_PLAT_WMT, +}; + struct viai2c { struct i2c_adapter adapter; struct completion complete; @@ -62,10 +66,11 @@ struct viai2c { struct i2c_msg *msg; int ret; bool last; + unsigned int platform; }; int viai2c_wait_bus_not_busy(struct viai2c *i2c); int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num); -int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c); +int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c, int plat); #endif diff --git a/drivers/i2c/busses/i2c-viai2c-wmt.c b/drivers/i2c/busses/i2c-viai2c-wmt.c index 07fd954f1d008..aa6c34a78b1e4 100644 --- a/drivers/i2c/busses/i2c-viai2c-wmt.c +++ b/drivers/i2c/busses/i2c-viai2c-wmt.c @@ -80,7 +80,7 @@ static int wmt_i2c_probe(struct platform_device *pdev) int err; u32 clk_rate; - err = viai2c_init(pdev, &i2c); + err = viai2c_init(pdev, &i2c, VIAI2C_PLAT_WMT); if (err) return err; From patchwork Wed Mar 6 21:24:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 778412 Received: from 9.mo561.mail-out.ovh.net (9.mo561.mail-out.ovh.net [87.98.184.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EA821B275 for ; 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dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=etezian.org Received: from director11.ghost.mail-out.ovh.net (unknown [10.109.139.93]) by mo561.mail-out.ovh.net (Postfix) with ESMTP id 4Tqlpj148dz1KD9 for ; Wed, 6 Mar 2024 21:25:49 +0000 (UTC) Received: from ghost-submission-6684bf9d7b-kldvg (unknown [10.110.168.23]) by director11.ghost.mail-out.ovh.net (Postfix) with ESMTPS id C339F1FE9E; Wed, 6 Mar 2024 21:25:47 +0000 (UTC) Received: from etezian.org ([37.59.142.107]) by ghost-submission-6684bf9d7b-kldvg with ESMTPSA id EBC1Hlvf6GX0VgMAZb1J2Q (envelope-from ); Wed, 06 Mar 2024 21:25:47 +0000 Authentication-Results: garm.ovh; auth=pass (GARM-107S00152830bff-e16b-447f-b04d-0bfea763efee, 62DEF991EB217AB86F953B10C2782167B22AFEEB) smtp.auth=andi@etezian.org X-OVh-ClientIp: 89.217.109.169 From: Andi Shyti To: Hans Hu , linux-i2c@vger.kernel.org Cc: wsa@kernel.org, cobechen@zhaoxin.com, hanshu@zhaoxin.com, Andi Shyti Subject: [PATCH v9 6/6] i2c: add zhaoxin i2c controller driver Date: Wed, 6 Mar 2024 22:24:13 +0100 Message-ID: <20240306212413.1850236-7-andi.shyti@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240306212413.1850236-1-andi.shyti@kernel.org> References: <20240306212413.1850236-1-andi.shyti@kernel.org> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Ovh-Tracer-Id: 16095020646170167879 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: 0 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvledriedugddugeegucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucenucfjughrpefhvfevufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpeetnhguihcuufhhhihtihcuoegrnhguihdrshhhhihtiheskhgvrhhnvghlrdhorhhgqeenucggtffrrghtthgvrhhnpeetgfejuefffeevheelgfegudetfffggfegfeeflefhvdffueeihfeuvedvteefhfenucffohhmrghinhepiihhrghogihinhdrtghomhenucfkphepuddvjedrtddrtddruddpkeelrddvudejrddutdelrdduieelpdefjedrheelrddugedvrddutdejnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehinhgvthepuddvjedrtddrtddruddpmhgrihhlfhhrohhmpegrnhguihesvghtvgiiihgrnhdrohhrghdpnhgspghrtghpthhtohepuddprhgtphhtthhopehlihhnuhigqdhivdgtsehvghgvrhdrkhgvrhhnvghlrdhorhhgpdfovfetjfhoshhtpehmohehiedupdhmohguvgepshhmthhpohhuth From: Hans Hu Add Zhaoxin I2C controller driver. It provides the access to the i2c busses, which connects to the touchpad, eeprom, I2S, etc. Zhaoxin I2C controller has two separate busses, so may accommodate up to two I2C adapters. Those adapters are listed in the ACPI namespace with the "IIC1D17" HID, and probed by a platform driver. The driver works with IRQ mode, and supports basic I2C features. Flags I2C_AQ_NO_ZERO_LEN and I2C_AQ_COMB_WRITE_THEN_READ are used to limit the unsupported access. Signed-off-by: Hans Hu Acked-by: Wolfram Sang Signed-off-by: Andi Shyti --- MAINTAINERS | 8 + drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile | 2 + drivers/i2c/busses/i2c-viai2c-common.c | 31 ++- drivers/i2c/busses/i2c-viai2c-common.h | 9 + drivers/i2c/busses/i2c-viai2c-zhaoxin.c | 299 ++++++++++++++++++++++++ 6 files changed, 354 insertions(+), 5 deletions(-) create mode 100644 drivers/i2c/busses/i2c-viai2c-zhaoxin.c diff --git a/MAINTAINERS b/MAINTAINERS index b1bb0feb0d33e..00c003c86e991 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10158,6 +10158,14 @@ L: linux-i2c@vger.kernel.org F: Documentation/i2c/busses/i2c-ismt.rst F: drivers/i2c/busses/i2c-ismt.c +I2C/SMBUS ZHAOXIN DRIVER +M: Hans Hu +L: linux-i2c@vger.kernel.org +S: Maintained +W: https://www.zhaoxin.com +F: drivers/i2c/busses/i2c-viai2c-common.c +F: drivers/i2c/busses/i2c-viai2c-zhaoxin.c + I2C/SMBUS STUB DRIVER M: Jean Delvare L: linux-i2c@vger.kernel.org diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 97989c914260f..cc781f8ec7141 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -336,6 +336,16 @@ config I2C_VIAPRO if ACPI +config I2C_ZHAOXIN + tristate "Zhaoxin I2C Interface" + depends on PCI || COMPILE_TEST + help + If you say yes to this option, support will be included for the + ZHAOXIN I2C interface + + This driver can also be built as a module. If so, the module + will be called i2c-zhaoxin. + comment "ACPI drivers" config I2C_SCMI diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 63c7bbad8134f..3d65934f5eb48 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -29,6 +29,8 @@ obj-$(CONFIG_I2C_SIS630) += i2c-sis630.o obj-$(CONFIG_I2C_SIS96X) += i2c-sis96x.o obj-$(CONFIG_I2C_VIA) += i2c-via.o obj-$(CONFIG_I2C_VIAPRO) += i2c-viapro.o +i2c-zhaoxin-objs := i2c-viai2c-zhaoxin.o i2c-viai2c-common.o +obj-$(CONFIG_I2C_ZHAOXIN) += i2c-zhaoxin.o # Mac SMBus host controller drivers obj-$(CONFIG_I2C_HYDRA) += i2c-hydra.o diff --git a/drivers/i2c/busses/i2c-viai2c-common.c b/drivers/i2c/busses/i2c-viai2c-common.c index 75663a3e3fe57..05b6151444420 100644 --- a/drivers/i2c/busses/i2c-viai2c-common.c +++ b/drivers/i2c/busses/i2c-viai2c-common.c @@ -60,7 +60,7 @@ static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, int last) return i2c->ret; } -static int viai2c_read(struct viai2c *i2c, struct i2c_msg *pmsg) +static int viai2c_read(struct viai2c *i2c, struct i2c_msg *pmsg, bool first) { u16 val, tcr_val = i2c->tcr; @@ -81,7 +81,8 @@ static int viai2c_read(struct viai2c *i2c, struct i2c_msg *pmsg) writew(tcr_val, i2c->base + VIAI2C_REG_TCR); - if (i2c->platform == VIAI2C_PLAT_WMT && (pmsg->flags & I2C_M_NOSTART)) { + if ((i2c->platform == VIAI2C_PLAT_WMT && (pmsg->flags & I2C_M_NOSTART)) + || (i2c->platform == VIAI2C_PLAT_ZHAOXIN && !first)) { val = readw(i2c->base + VIAI2C_REG_CR); val |= VIAI2C_CR_CPU_RDY; writew(val, i2c->base + VIAI2C_REG_CR); @@ -100,6 +101,7 @@ int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) int ret = 0; struct viai2c *i2c = i2c_get_adapdata(adap); + i2c->mode = VIAI2C_BYTE_MODE; for (i = 0; ret >= 0 && i < num; i++) { pmsg = &msgs[i]; if ((i2c->platform == VIAI2C_PLAT_WMT) @@ -113,7 +115,7 @@ int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) i2c->xfered_len = 0; if (pmsg->flags & I2C_M_RD) - ret = viai2c_read(i2c, pmsg); + ret = viai2c_read(i2c, pmsg, i == 0); else ret = viai2c_write(i2c, pmsg, (i + 1) == num); } @@ -152,6 +154,8 @@ static int viai2c_irq_xfer(struct viai2c *i2c) if ((i2c->xfered_len + 1) == msg->len) { if (i2c->platform == VIAI2C_PLAT_WMT && !i2c->last) writew(VIAI2C_CR_ENABLE, base + VIAI2C_REG_CR); + else if (i2c->platform == VIAI2C_PLAT_ZHAOXIN && i2c->last) + writeb(VIAI2C_CR_TX_END, base + VIAI2C_REG_CR); } else { writew(msg->buf[i2c->xfered_len + 1] & 0xFF, base + VIAI2C_REG_CDR); writew(VIAI2C_CR_CPU_RDY | VIAI2C_CR_ENABLE, base + VIAI2C_REG_CR); @@ -163,6 +167,11 @@ static int viai2c_irq_xfer(struct viai2c *i2c) return i2c->xfered_len == msg->len; } +int __weak viai2c_fifo_irq_xfer(struct viai2c *i2c, bool irq) +{ + return 0; +} + static irqreturn_t viai2c_isr(int irq, void *data) { struct viai2c *i2c = data; @@ -170,6 +179,9 @@ static irqreturn_t viai2c_isr(int irq, void *data) /* save the status and write-clear it */ status = readw(i2c->base + VIAI2C_REG_ISR); + if (!status && i2c->platform == VIAI2C_PLAT_ZHAOXIN) + return IRQ_NONE; + writew(status, i2c->base + VIAI2C_REG_ISR); i2c->ret = 0; @@ -179,8 +191,12 @@ static irqreturn_t viai2c_isr(int irq, void *data) if (i2c->platform == VIAI2C_PLAT_WMT && (status & VIAI2C_ISR_SCL_TIMEOUT)) i2c->ret = -ETIMEDOUT; - if (!i2c->ret) - i2c->ret = viai2c_irq_xfer(i2c); + if (!i2c->ret) { + if (i2c->mode == VIAI2C_BYTE_MODE) + i2c->ret = viai2c_irq_xfer(i2c); + else + i2c->ret = viai2c_fifo_irq_xfer(i2c, true); + } if (i2c->ret) complete(&i2c->complete); @@ -208,6 +224,11 @@ int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c, int plat) i2c->irq = irq_of_parse_and_map(np, 0); if (!i2c->irq) return -EINVAL; + } else if (plat == VIAI2C_PLAT_ZHAOXIN) { + irq_flags = IRQF_SHARED; + i2c->irq = platform_get_irq(pdev, 0); + if (i2c->irq < 0) + return i2c->irq; } else { return dev_err_probe(&pdev->dev, -EINVAL, "wrong platform type\n"); } diff --git a/drivers/i2c/busses/i2c-viai2c-common.h b/drivers/i2c/busses/i2c-viai2c-common.h index cfe5ab2bd7792..81e827c544347 100644 --- a/drivers/i2c/busses/i2c-viai2c-common.h +++ b/drivers/i2c/busses/i2c-viai2c-common.h @@ -52,6 +52,12 @@ enum { VIAI2C_PLAT_WMT, + VIAI2C_PLAT_ZHAOXIN +}; + +enum { + VIAI2C_BYTE_MODE, + VIAI2C_FIFO_MODE }; struct viai2c { @@ -66,11 +72,14 @@ struct viai2c { struct i2c_msg *msg; int ret; bool last; + unsigned int mode; unsigned int platform; + void *pltfm_priv; }; int viai2c_wait_bus_not_busy(struct viai2c *i2c); int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num); int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c, int plat); +int viai2c_fifo_irq_xfer(struct viai2c *i2c, bool irq); #endif diff --git a/drivers/i2c/busses/i2c-viai2c-zhaoxin.c b/drivers/i2c/busses/i2c-viai2c-zhaoxin.c new file mode 100644 index 0000000000000..99db93caa4cb9 --- /dev/null +++ b/drivers/i2c/busses/i2c-viai2c-zhaoxin.c @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright(c) 2024 Shanghai Zhaoxin Semiconductor Corporation. + * All rights reserved. + */ + +#include +#include "i2c-viai2c-common.h" + +/* + * registers + */ +/* Zhaoxin specific register bit fields */ +/* REG_CR Bit fields */ +#define ZXI2C_CR_MST_RST BIT(7) +#define ZXI2C_CR_FIFO_MODE BIT(14) +/* REG_ISR/IMR Bit fields */ +#define ZXI2C_IRQ_FIFONACK BIT(4) +#define ZXI2C_IRQ_FIFOEND BIT(3) +#define ZXI2C_IRQ_MASK (VIAI2C_ISR_MASK_ALL \ + | ZXI2C_IRQ_FIFOEND \ + | ZXI2C_IRQ_FIFONACK) +/* Zhaoxin specific registers */ +#define ZXI2C_REG_CLK 0x10 +#define ZXI2C_CLK_50M BIT(0) +#define ZXI2C_REG_REV 0x11 +#define ZXI2C_REG_HCR 0x12 +#define ZXI2C_HCR_RST_FIFO GENMASK(1, 0) +#define ZXI2C_REG_HTDR 0x13 +#define ZXI2C_REG_HRDR 0x14 +#define ZXI2C_REG_HTLR 0x15 +#define ZXI2C_REG_HRLR 0x16 +#define ZXI2C_REG_HWCNTR 0x18 +#define ZXI2C_REG_HRCNTR 0x19 + +/* parameters Constants */ +#define ZXI2C_GOLD_FSTP_100K 0xF3 +#define ZXI2C_GOLD_FSTP_400K 0x38 +#define ZXI2C_GOLD_FSTP_1M 0x13 +#define ZXI2C_GOLD_FSTP_3400K 0x37 +#define ZXI2C_HS_MASTER_CODE (0x08 << 8) + +#define ZXI2C_FIFO_SIZE 32 + +struct viai2c_zhaoxin { + u8 hrv; + u16 tr; + u16 mcr; + u16 xfer_len; +}; + +/* 'irq == true' means in interrupt context */ +int viai2c_fifo_irq_xfer(struct viai2c *i2c, bool irq) +{ + u16 i; + u8 tmp; + struct i2c_msg *msg = i2c->msg; + void __iomem *base = i2c->base; + bool read = !!(msg->flags & I2C_M_RD); + struct viai2c_zhaoxin *priv = i2c->pltfm_priv; + + if (irq) { + /* get the received data */ + if (read) + for (i = 0; i < priv->xfer_len; i++) + msg->buf[i2c->xfered_len + i] = ioread8(base + ZXI2C_REG_HRDR); + + i2c->xfered_len += priv->xfer_len; + if (i2c->xfered_len == msg->len) + return 1; + } + + /* reset fifo buffer */ + tmp = ioread8(base + ZXI2C_REG_HCR); + iowrite8(tmp | ZXI2C_HCR_RST_FIFO, base + ZXI2C_REG_HCR); + + /* set xfer len */ + priv->xfer_len = min_t(u16, msg->len - i2c->xfered_len, ZXI2C_FIFO_SIZE); + if (read) { + iowrite8(priv->xfer_len - 1, base + ZXI2C_REG_HRLR); + } else { + iowrite8(priv->xfer_len - 1, base + ZXI2C_REG_HTLR); + /* set write data */ + for (i = 0; i < priv->xfer_len; i++) + iowrite8(msg->buf[i2c->xfered_len + i], base + ZXI2C_REG_HTDR); + } + + /* prepare to stop transmission */ + if (priv->hrv && msg->len == (i2c->xfered_len + priv->xfer_len)) { + tmp = ioread8(base + VIAI2C_REG_CR); + tmp |= read ? VIAI2C_CR_RX_END : VIAI2C_CR_TX_END; + iowrite8(tmp, base + VIAI2C_REG_CR); + } + + if (irq) { + /* continue transmission */ + tmp = ioread8(base + VIAI2C_REG_CR); + iowrite8(tmp |= VIAI2C_CR_CPU_RDY, base + VIAI2C_REG_CR); + } else { + u16 tcr_val = i2c->tcr; + + /* start transmission */ + tcr_val |= read ? VIAI2C_TCR_READ : 0; + writew(tcr_val | msg->addr, base + VIAI2C_REG_TCR); + } + + return 0; +} + +static int zxi2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) +{ + u8 tmp; + int ret; + struct viai2c *i2c = (struct viai2c *)i2c_get_adapdata(adap); + struct viai2c_zhaoxin *priv = i2c->pltfm_priv; + void __iomem *base = i2c->base; + + ret = viai2c_wait_bus_not_busy(i2c); + if (ret) + return ret; + + tmp = ioread8(base + VIAI2C_REG_CR); + tmp &= ~(VIAI2C_CR_RX_END | VIAI2C_CR_TX_END); + + if (num == 1 && msgs->len >= 2 && (priv->hrv || msgs->len <= ZXI2C_FIFO_SIZE)) { + /* enable fifo mode */ + iowrite16(ZXI2C_CR_FIFO_MODE | tmp, base + VIAI2C_REG_CR); + /* clear irq status */ + iowrite8(ZXI2C_IRQ_MASK, base + VIAI2C_REG_ISR); + /* enable fifo irq */ + iowrite8(VIAI2C_ISR_NACK_ADDR | ZXI2C_IRQ_FIFOEND, base + VIAI2C_REG_IMR); + + i2c->msg = msgs; + i2c->mode = VIAI2C_FIFO_MODE; + priv->xfer_len = i2c->xfered_len = 0; + + viai2c_fifo_irq_xfer(i2c, 0); + + if (!wait_for_completion_timeout(&i2c->complete, VIAI2C_TIMEOUT)) + return -ETIMEDOUT; + + ret = i2c->ret; + } else { + /* enable byte mode */ + iowrite16(tmp, base + VIAI2C_REG_CR); + /* clear irq status */ + iowrite8(ZXI2C_IRQ_MASK, base + VIAI2C_REG_ISR); + /* enable byte irq */ + iowrite8(VIAI2C_ISR_NACK_ADDR | VIAI2C_IMR_BYTE, base + VIAI2C_REG_IMR); + + ret = viai2c_xfer(adap, msgs, num); + if (ret == -ETIMEDOUT) + iowrite16(tmp | VIAI2C_CR_END_MASK, base + VIAI2C_REG_CR); + } + /* dis interrupt */ + iowrite8(0, base + VIAI2C_REG_IMR); + + return ret; +} + +static u32 zxi2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm zxi2c_algorithm = { + .master_xfer = zxi2c_master_xfer, + .functionality = zxi2c_func, +}; + +static const struct i2c_adapter_quirks zxi2c_quirks = { + .flags = I2C_AQ_NO_ZERO_LEN | I2C_AQ_COMB_WRITE_THEN_READ, +}; + +static const u32 zxi2c_speed_params_table[][3] = { + /* speed, ZXI2C_TCR, ZXI2C_FSTP */ + { I2C_MAX_STANDARD_MODE_FREQ, 0, ZXI2C_GOLD_FSTP_100K }, + { I2C_MAX_FAST_MODE_FREQ, VIAI2C_TCR_FAST, ZXI2C_GOLD_FSTP_400K }, + { I2C_MAX_FAST_MODE_PLUS_FREQ, VIAI2C_TCR_FAST, ZXI2C_GOLD_FSTP_1M }, + { I2C_MAX_HIGH_SPEED_MODE_FREQ, VIAI2C_TCR_HS_MODE | VIAI2C_TCR_FAST, + ZXI2C_GOLD_FSTP_3400K }, +}; + +static void zxi2c_set_bus_speed(struct viai2c *i2c) +{ + struct viai2c_zhaoxin *priv = i2c->pltfm_priv; + + iowrite16(priv->tr, i2c->base + VIAI2C_REG_TR); + iowrite8(ZXI2C_CLK_50M, i2c->base + ZXI2C_REG_CLK); + iowrite16(priv->mcr, i2c->base + VIAI2C_REG_MCR); +} + +static void zxi2c_get_bus_speed(struct viai2c *i2c) +{ + u8 i, count; + u8 fstp; + const u32 *params; + struct viai2c_zhaoxin *priv = i2c->pltfm_priv; + + u32 acpi_speed = i2c_acpi_find_bus_speed(i2c->dev); + + count = ARRAY_SIZE(zxi2c_speed_params_table); + for (i = 0; i < count; i++) + if (acpi_speed == zxi2c_speed_params_table[i][0]) + break; + /* if not found, use 400k as default */ + i = i < count ? i : 1; + + params = zxi2c_speed_params_table[i]; + fstp = ioread8(i2c->base + VIAI2C_REG_TR); + if (abs(fstp - params[2]) > 0x10) { + /* + * if BIOS setting value far from golden value, + * use golden value and warn user + */ + dev_warn(i2c->dev, "speed:%d, fstp:0x%x, golden:0x%x\n", + params[0], fstp, params[2]); + priv->tr = params[2] | 0xff00; + } else { + priv->tr = fstp | 0xff00; + } + + i2c->tcr = params[1]; + priv->mcr = ioread16(i2c->base + VIAI2C_REG_MCR); + /* for Hs-mode, use 0x80 as master code */ + if (params[0] == I2C_MAX_HIGH_SPEED_MODE_FREQ) + priv->mcr |= ZXI2C_HS_MASTER_CODE; + + dev_info(i2c->dev, "speed mode is %s\n", i2c_freq_mode_string(params[0])); +} + +static int zxi2c_probe(struct platform_device *pdev) +{ + int error; + struct viai2c *i2c; + struct i2c_adapter *adap; + struct viai2c_zhaoxin *priv; + + error = viai2c_init(pdev, &i2c, VIAI2C_PLAT_ZHAOXIN); + if (error) + return error; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + i2c->pltfm_priv = priv; + + zxi2c_get_bus_speed(i2c); + zxi2c_set_bus_speed(i2c); + + priv->hrv = ioread8(i2c->base + ZXI2C_REG_REV); + + adap = &i2c->adapter; + adap->owner = THIS_MODULE; + adap->algo = &zxi2c_algorithm; + adap->quirks = &zxi2c_quirks; + adap->dev.parent = &pdev->dev; + ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev)); + snprintf(adap->name, sizeof(adap->name), "zhaoxin-%s-%s", + dev_name(pdev->dev.parent), dev_name(i2c->dev)); + i2c_set_adapdata(adap, i2c); + + return devm_i2c_add_adapter(&pdev->dev, adap); +} + +static int __maybe_unused zxi2c_resume(struct device *dev) +{ + struct viai2c *i2c = dev_get_drvdata(dev); + + iowrite8(ZXI2C_CR_MST_RST, i2c->base + VIAI2C_REG_CR); + zxi2c_set_bus_speed(i2c); + + return 0; +} + +static const struct dev_pm_ops zxi2c_pm = { + SET_SYSTEM_SLEEP_PM_OPS(NULL, zxi2c_resume) +}; + +static const struct acpi_device_id zxi2c_acpi_match[] = { + {"IIC1D17", 0 }, + { } +}; +MODULE_DEVICE_TABLE(acpi, zxi2c_acpi_match); + +static struct platform_driver zxi2c_driver = { + .probe = zxi2c_probe, + .driver = { + .name = "i2c_zhaoxin", + .acpi_match_table = zxi2c_acpi_match, + .pm = &zxi2c_pm, + }, +}; + +module_platform_driver(zxi2c_driver); + +MODULE_AUTHOR("HansHu@zhaoxin.com"); +MODULE_DESCRIPTION("Shanghai Zhaoxin IIC driver"); +MODULE_LICENSE("GPL");