From patchwork Wed Mar 6 07:30:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Odelu Kukatla X-Patchwork-Id: 778360 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 127C85C5F7; Wed, 6 Mar 2024 07:30:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709710252; cv=none; b=HPwqeZLHJPgtU0cprMSKLoAZHPs0a1odJ86CVCORbRx9li9tiGdIgiJX1s+il+2fpaF3zmDhIZDno6ktL25R3z6gfkQTmiKOkC57Yttld3DhDFyIMefg4MXP8KIJnpJcjgo2wBfJ4ruqWI4GuVSRSWKRTVXv3TbUlPI5kEc5Rec= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709710252; c=relaxed/simple; bh=c1bftpDuIOmUwgy2gnxRjxmco5Z0u5DKZrGSG+jJz6w=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NWK1EPwwSf93QUko1VLeNBUYT53c6Mxp9eYZCx1iH5IQzjqJOUxbEckoTwHIotKKHXfVa6Bl67ZeE4TGzB8OQj/1C/xI6rGBs/pu93UqX/n4Z9Yk31RwNrXBy2o0BwYpsu0qTokiaAg0G/DtzNQlCmWBboWpftWi48BU+tUQhyk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=aSFzF0Io; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="aSFzF0Io" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42668cFV020915; Wed, 6 Mar 2024 07:30:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=qcppdkim1; bh=S10ty99sebGJdDg/EZze O5bavZLB9qCBiYbmsMoBeSo=; b=aSFzF0IoL1tiiOlaNgk4JIOciJsVE21iIe/N S9404WkbNe/U0ERmdOKQcqe1cefKXMCTGCGcvM405B5d2qut6052TDwAAO+5NJt4 duh7lA4/v/7F0YkRnxgN5nDJ9BXusagyvI8P6StsqxOanTPVqkAnam9+1gimpEZa zYJTV53JwnU3UcXTsP54soNIdnzLx1k1FYavo2ZAWVSrKM/IsIB7q4ygWdrcPvb3 d1gc3Xc4HuXbFeWnPxjLO+VCqdwFSClZFBEbJGWwi3LJ6VWR0EWNUHCVYuwzeeVA 7w1odt6PC1jLH8FCjm3P9M/awUR+rDwYjNadXkQ9ToL8faVSmg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3wpjy3r5mk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 06 Mar 2024 07:30:46 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4267Uivl023706 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 6 Mar 2024 07:30:44 GMT Received: from hu-okukatla-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 5 Mar 2024 23:30:39 -0800 From: Odelu Kukatla To: Bjorn Andersson , Konrad Dybcio , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Kees Cook , , "Gustavo A . R . Silva" , , , , , , , Subject: [PATCH v3 1/4] interconnect: qcom: icc-rpmh: Add QoS configuration support Date: Wed, 6 Mar 2024 13:00:13 +0530 Message-ID: <20240306073016.2163-2-quic_okukatla@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240306073016.2163-1-quic_okukatla@quicinc.com> References: <20240306073016.2163-1-quic_okukatla@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: -LPk5ON0g1L3tEQEuuEcfRSAIizXgoh- X-Proofpoint-ORIG-GUID: -LPk5ON0g1L3tEQEuuEcfRSAIizXgoh- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-06_04,2024-03-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 phishscore=0 malwarescore=0 mlxscore=0 spamscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2403060058 It adds QoS support for QNOC device and includes support for configuring priority, priority forward disable, urgency forwarding. This helps in priortizing the traffic originating from different interconnect masters at NoC(Network On Chip). Signed-off-by: Odelu Kukatla --- drivers/interconnect/qcom/icc-rpmh.c | 105 +++++++++++++++++++++++++++ drivers/interconnect/qcom/icc-rpmh.h | 32 ++++++++ 2 files changed, 137 insertions(+) diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c index c1aa265c1f4e..b4681849df80 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -1,19 +1,57 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include #include #include #include #include #include +#include #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" +/* QNOC QoS */ +#define QOSGEN_MAINCTL_LO(p, qp) (0x8 + (p->port_offsets[qp])) +#define QOS_SLV_URG_MSG_EN_MASK BIT_MASK(3) +#define QOS_DFLT_PRIO_MASK GENMASK(6, 4) +#define QOS_DISABLE_MASK BIT_MASK(24) + +/** + * qcom_icc_set_qos - initialize static QoS configurations + * @qp: qcom icc provider to which @node belongs + * @node: qcom icc node to operate on + */ +static void qcom_icc_set_qos(struct qcom_icc_provider *qp, + struct qcom_icc_node *node) +{ + const struct qcom_icc_qosbox *qos = node->qosbox; + int port; + + if (!qp->regmap || !qos) + return; + + for (port = 0; port < qos->num_ports; port++) { + regmap_update_bits(qp->regmap, QOSGEN_MAINCTL_LO(qos, port), + QOS_DISABLE_MASK, + FIELD_PREP(QOS_DISABLE_MASK, qos->prio_fwd_disable)); + + regmap_update_bits(qp->regmap, QOSGEN_MAINCTL_LO(qos, port), + QOS_DFLT_PRIO_MASK, + FIELD_PREP(QOS_DFLT_PRIO_MASK, qos->prio)); + + regmap_update_bits(qp->regmap, QOSGEN_MAINCTL_LO(qos, port), + QOS_SLV_URG_MSG_EN_MASK, + FIELD_PREP(QOS_SLV_URG_MSG_EN_MASK, qos->urg_fwd)); + } +} + /** * qcom_icc_pre_aggregate - cleans up stale values from prior icc_set * @node: icc node to operate on @@ -159,6 +197,36 @@ int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev) } EXPORT_SYMBOL_GPL(qcom_icc_bcm_init); +/** + * qcom_icc_rpmh_configure_qos - configure QoS parameters + * @qp: qcom icc provider associated with QoS endpoint nodes + * + * Return: 0 on success, or an error code otherwise + */ +static int qcom_icc_rpmh_configure_qos(struct qcom_icc_provider *qp) +{ + struct qcom_icc_node *qnode; + size_t i; + int ret; + + ret = clk_bulk_prepare_enable(qp->num_clks, qp->clks); + if (ret) + return ret; + + for (i = 0; i < qp->num_nodes; i++) { + qnode = qp->nodes[i]; + if (!qnode) + continue; + + if (qnode->qosbox) + qcom_icc_set_qos(qp, qnode); + } + + clk_bulk_disable_unprepare(qp->num_clks, qp->clks); + + return ret; +} + int qcom_icc_rpmh_probe(struct platform_device *pdev) { const struct qcom_icc_desc *desc; @@ -199,7 +267,9 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) qp->dev = dev; qp->bcms = desc->bcms; + qp->nodes = desc->nodes; qp->num_bcms = desc->num_bcms; + qp->num_nodes = desc->num_nodes; qp->voter = of_bcm_voter_get(qp->dev, NULL); if (IS_ERR(qp->voter)) @@ -229,6 +299,41 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) data->nodes[i] = node; } + if (desc->config) { + struct resource *res; + void __iomem *base; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_warn(dev, "Skipping QoS, failed to get resource\n"); + goto skip_qos_config; + } + + base = devm_ioremap(dev, res->start, resource_size(res)); + if (IS_ERR(base)) { + dev_warn(dev, "Skipping QoS, ioremap failed: %ld\n", PTR_ERR(base)); + goto skip_qos_config; + }; + + qp->regmap = devm_regmap_init_mmio(dev, base, desc->config); + + if (IS_ERR(qp->regmap)) { + dev_warn(dev, "Skipping QoS, regmap failed; %ld\n", PTR_ERR(qp->regmap)); + goto skip_qos_config; + } + + qp->num_clks = devm_clk_bulk_get_all(qp->dev, &qp->clks); + if (qp->num_clks < 0) { + dev_warn(dev, "Skipping QoS, failed to get clk: %d\n", qp->num_clks); + goto skip_qos_config; + } + + ret = qcom_icc_rpmh_configure_qos(qp); + if (ret) + dev_warn(dev, "Failed to program QoS: %d\n", ret); + } + +skip_qos_config: ret = icc_provider_register(provider); if (ret) goto err_remove_nodes; diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h index 2de29460e808..a0533d8aeffe 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -1,12 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPMH_H__ #define __DRIVERS_INTERCONNECT_QCOM_ICC_RPMH_H__ #include +#include #define to_qcom_provider(_provider) \ container_of(_provider, struct qcom_icc_provider, provider) @@ -18,6 +20,11 @@ * @bcms: list of bcms that maps to the provider * @num_bcms: number of @bcms * @voter: bcm voter targeted by this provider + * @nodes: list of icc nodes that maps to the provider + * @num_nodes: number of @nodes + * @regmap: used for QoS, register access + * @clks : clks required for register access + * @num_clks: number of @clks */ struct qcom_icc_provider { struct icc_provider provider; @@ -25,6 +32,11 @@ struct qcom_icc_provider { struct qcom_icc_bcm * const *bcms; size_t num_bcms; struct bcm_voter *voter; + struct qcom_icc_node * const *nodes; + size_t num_nodes; + struct regmap *regmap; + struct clk_bulk_data *clks; + int num_clks; }; /** @@ -41,6 +53,23 @@ struct bcm_db { u8 reserved; }; +/** + * struct qcom_icc_qosbox - Qualcomm specific QoS config + * @prio: priority value assigned to requests on the node + * @urg_fwd: whether to forward the urgency promotion issued by master(endpoint), or discard + * @prio_fwd_disable: whether to forward the priority driven by mster, or override by @prio + * @num_ports: number of @ports + * @port_offsets: qos register offsets + */ + +struct qcom_icc_qosbox { + const u32 prio; + const bool urg_fwd; + const bool prio_fwd_disable; + const u32 num_ports; + const u32 port_offsets[] __counted_by(num_ports); +}; + #define MAX_LINKS 128 #define MAX_BCMS 64 #define MAX_BCM_PER_NODE 3 @@ -58,6 +87,7 @@ struct bcm_db { * @max_peak: current max aggregate value of all peak bw requests * @bcms: list of bcms associated with this logical node * @num_bcms: num of @bcms + * @qosbox: qos config data associated with node */ struct qcom_icc_node { const char *name; @@ -70,6 +100,7 @@ struct qcom_icc_node { u64 max_peak[QCOM_ICC_NUM_BUCKETS]; struct qcom_icc_bcm *bcms[MAX_BCM_PER_NODE]; size_t num_bcms; + const struct qcom_icc_qosbox *qosbox; }; /** @@ -114,6 +145,7 @@ struct qcom_icc_fabric { }; struct qcom_icc_desc { + const struct regmap_config *config; struct qcom_icc_node * const *nodes; size_t num_nodes; struct qcom_icc_bcm * const *bcms; From patchwork Wed Mar 6 07:30:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Odelu Kukatla X-Patchwork-Id: 778584 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF79A5CDE0; Wed, 6 Mar 2024 07:30:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709710257; cv=none; b=pK6NdZfE/hrAXahgVpIkbysYrPKI9ik63yxZpao8w2Gk3EEhKO4Tl6jwOB6DxTlYbtbY6Ob0VhD+0WT40Zev8oymHHkRbtSUmIOh2dYpiLbse6QlNT2bn/e5nzcmO5O6A9mOInO1TiPV1XIX0J0wK5SZj6fo8kCYqP55RPL2ljA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709710257; c=relaxed/simple; bh=58Vii5USz2JDmZl/fAG+vKozHwYdZ+qXm1Wg65M7EZk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PETgax5eN8CLIn8x4caZbtnTHppd3bQD41oFee7XEcszSFl47jEPb/8UkZwuWJW0x0KvfzZvhWjCr/HgOPZcYPV83xNJcM9c9Z/lasLU59/3yet21X0dBGcWaVNyNSLneuta57ZPYaz+ogI76POpwqDjkwEyfQs3yqKzN34vADE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=g0OcPd6k; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="g0OcPd6k" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4264p4ou003564; Wed, 6 Mar 2024 07:30:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=qcppdkim1; bh=a9YjfQCTWPZojqkhdk+a pqVRe07gEl2O5k20A2X0xG4=; b=g0OcPd6kmaF8CPBCiTUjYPnAogazeLGuAMqV Vpe2CaLGQqDGm/sil0eAwNEIBLDPoBFIY2FmXur4fAI1hzLiQlGn6o+UiWiG9ycW m43wnWXtMlKqWKm6asoYnNz5YnoPcKJ8tvfeX2FHxcvCBXxGMNuoEkFiA1hCQL/g 4km5nx3RWzSDFMc4FtClX9cAPLVtdm+RMLpnSURy/y0kpTPnVpuQGZjrqdl2gYFU OOVB0iKYPrLwwtQZ6kESJY510X3TRnxYuO1x7n+ezmPYkLw5sBsy141VXsfx4WR9 SwBJt18lB1FcL5VxLeA5cERUsok+68gOBd+srZormT7LzDA96g== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3wp2bptc80-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 06 Mar 2024 07:30:50 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4267UoCV023761 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 6 Mar 2024 07:30:50 GMT Received: from hu-okukatla-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 5 Mar 2024 23:30:44 -0800 From: Odelu Kukatla To: Bjorn Andersson , Konrad Dybcio , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Kees Cook , , "Gustavo A . R . Silva" , , , , , , , Subject: [PATCH v3 2/4] interconnect: qcom: sc7280: enable QoS programming Date: Wed, 6 Mar 2024 13:00:14 +0530 Message-ID: <20240306073016.2163-3-quic_okukatla@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240306073016.2163-1-quic_okukatla@quicinc.com> References: <20240306073016.2163-1-quic_okukatla@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: z1t7-Cyh0tXgL3DQ7Mw6tYiVcOGEwL3Q X-Proofpoint-ORIG-GUID: z1t7-Cyh0tXgL3DQ7Mw6tYiVcOGEwL3Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-06_04,2024-03-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 mlxscore=0 phishscore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 clxscore=1015 malwarescore=0 spamscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2403060058 Enable QoS for the master ports with predefined values for priority and urgency. Signed-off-by: Odelu Kukatla --- drivers/interconnect/qcom/sc7280.c | 332 +++++++++++++++++++++++++++++ 1 file changed, 332 insertions(+) diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c index 7d33694368e8..1e1002c4d3d8 100644 --- a/drivers/interconnect/qcom/sc7280.c +++ b/drivers/interconnect/qcom/sc7280.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. * */ @@ -16,29 +17,53 @@ #include "icc-rpmh.h" #include "sc7280.h" +static const struct qcom_icc_qosbox qhm_qspi_qos = { + .num_ports = 1, + .port_offsets = { 0x7000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", .id = SC7280_MASTER_QSPI_0, .channels = 1, .buswidth = 4, + .qosbox = &qhm_qspi_qos, .num_links = 1, .links = { SC7280_SLAVE_A1NOC_SNOC }, }; +static const struct qcom_icc_qosbox qhm_qup0_qos = { + .num_ports = 1, + .port_offsets = { 0x11000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", .id = SC7280_MASTER_QUP_0, .channels = 1, .buswidth = 4, + .qosbox = &qhm_qup0_qos, .num_links = 1, .links = { SC7280_SLAVE_A1NOC_SNOC }, }; +static const struct qcom_icc_qosbox qhm_qup1_qos = { + .num_ports = 1, + .port_offsets = { 0x8000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", .id = SC7280_MASTER_QUP_1, .channels = 1, .buswidth = 4, + .qosbox = &qhm_qup1_qos, .num_links = 1, .links = { SC7280_SLAVE_A1NOC_SNOC }, }; @@ -52,38 +77,70 @@ static struct qcom_icc_node qnm_a1noc_cfg = { .links = { SC7280_SLAVE_SERVICE_A1NOC }, }; +static const struct qcom_icc_qosbox xm_sdc1_qos = { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_sdc1 = { .name = "xm_sdc1", .id = SC7280_MASTER_SDCC_1, .channels = 1, .buswidth = 8, + .qosbox = &xm_sdc1_qos, .num_links = 1, .links = { SC7280_SLAVE_A1NOC_SNOC }, }; +static const struct qcom_icc_qosbox xm_sdc2_qos = { + .num_ports = 1, + .port_offsets = { 0xe000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", .id = SC7280_MASTER_SDCC_2, .channels = 1, .buswidth = 8, + .qosbox = &xm_sdc2_qos, .num_links = 1, .links = { SC7280_SLAVE_A1NOC_SNOC }, }; +static const struct qcom_icc_qosbox xm_sdc4_qos = { + .num_ports = 1, + .port_offsets = { 0x9000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", .id = SC7280_MASTER_SDCC_4, .channels = 1, .buswidth = 8, + .qosbox = &xm_sdc4_qos, .num_links = 1, .links = { SC7280_SLAVE_A1NOC_SNOC }, }; +static const struct qcom_icc_qosbox xm_ufs_mem_qos = { + .num_ports = 1, + .port_offsets = { 0xa000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", .id = SC7280_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, + .qosbox = &xm_ufs_mem_qos, .num_links = 1, .links = { SC7280_SLAVE_A1NOC_SNOC }, }; @@ -97,20 +154,36 @@ static struct qcom_icc_node xm_usb2 = { .links = { SC7280_SLAVE_A1NOC_SNOC }, }; +static const struct qcom_icc_qosbox xm_usb3_0_qos = { + .num_ports = 1, + .port_offsets = { 0xb000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", .id = SC7280_MASTER_USB3_0, .channels = 1, .buswidth = 8, + .qosbox = &xm_usb3_0_qos, .num_links = 1, .links = { SC7280_SLAVE_A1NOC_SNOC }, }; +static const struct qcom_icc_qosbox qhm_qdss_bam_qos = { + .num_ports = 1, + .port_offsets = { 0x18000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", .id = SC7280_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, + .qosbox = &qhm_qdss_bam_qos, .num_links = 1, .links = { SC7280_SLAVE_A2NOC_SNOC }, }; @@ -124,29 +197,53 @@ static struct qcom_icc_node qnm_a2noc_cfg = { .links = { SC7280_SLAVE_SERVICE_A2NOC }, }; +static const struct qcom_icc_qosbox qnm_cnoc_datapath_qos = { + .num_ports = 1, + .port_offsets = { 0x1c000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node qnm_cnoc_datapath = { .name = "qnm_cnoc_datapath", .id = SC7280_MASTER_CNOC_A2NOC, .channels = 1, .buswidth = 8, + .qosbox = &qnm_cnoc_datapath_qos, .num_links = 1, .links = { SC7280_SLAVE_A2NOC_SNOC }, }; +static const struct qcom_icc_qosbox qxm_crypto_qos = { + .num_ports = 1, + .port_offsets = { 0x1d000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", .id = SC7280_MASTER_CRYPTO, .channels = 1, .buswidth = 8, + .qosbox = &qxm_crypto_qos, .num_links = 1, .links = { SC7280_SLAVE_A2NOC_SNOC }, }; +static const struct qcom_icc_qosbox qxm_ipa_qos = { + .num_ports = 1, + .port_offsets = { 0x10000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", .id = SC7280_MASTER_IPA, .channels = 1, .buswidth = 8, + .qosbox = &qxm_ipa_qos, .num_links = 1, .links = { SC7280_SLAVE_A2NOC_SNOC }, }; @@ -168,11 +265,19 @@ static struct qcom_icc_node xm_pcie3_1 = { .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC }, }; +static const struct qcom_icc_qosbox xm_qdss_etr_qos = { + .num_ports = 1, + .port_offsets = { 0x15000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", .id = SC7280_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, + .qosbox = &xm_qdss_etr_qos, .num_links = 1, .links = { SC7280_SLAVE_A2NOC_SNOC }, }; @@ -300,20 +405,36 @@ static struct qcom_icc_node qnm_cnoc_dc_noc = { .links = { SC7280_SLAVE_LLCC_CFG, SC7280_SLAVE_GEM_NOC_CFG }, }; +static const struct qcom_icc_qosbox alm_gpu_tcu_qos = { + .num_ports = 1, + .port_offsets = { 0xd7000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", .id = SC7280_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, + .qosbox = &alm_gpu_tcu_qos, .num_links = 2, .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, }; +static const struct qcom_icc_qosbox alm_sys_tcu_qos = { + .num_ports = 1, + .port_offsets = { 0xd6000 }, + .prio = 6, + .urg_fwd = 0, +}; + static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", .id = SC7280_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, + .qosbox = &alm_sys_tcu_qos, .num_links = 2, .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, }; @@ -328,11 +449,19 @@ static struct qcom_icc_node chm_apps = { SC7280_SLAVE_MEM_NOC_PCIE_SNOC }, }; +static const struct qcom_icc_qosbox qnm_cmpnoc_qos = { + .num_ports = 2, + .port_offsets = { 0x21000, 0x61000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_cmpnoc = { .name = "qnm_cmpnoc", .id = SC7280_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, + .qosbox = &qnm_cmpnoc_qos, .num_links = 2, .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, }; @@ -348,29 +477,53 @@ static struct qcom_icc_node qnm_gemnoc_cfg = { SC7280_SLAVE_SERVICE_GEM_NOC }, }; +static const struct qcom_icc_qosbox qnm_gpu_qos = { + .num_ports = 2, + .port_offsets = { 0x22000, 0x62000 }, + .prio = 0, + .urg_fwd = 0, +}; + static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", .id = SC7280_MASTER_GFX3D, .channels = 2, .buswidth = 32, + .qosbox = &qnm_gpu_qos, .num_links = 2, .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, }; +static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = { + .num_ports = 2, + .port_offsets = { 0x23000, 0x63000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", .id = SC7280_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, + .qosbox = &qnm_mnoc_hf_qos, .num_links = 1, .links = { SC7280_SLAVE_LLCC }, }; +static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = { + .num_ports = 1, + .port_offsets = { 0xcf000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", .id = SC7280_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, + .qosbox = &qnm_mnoc_sf_qos, .num_links = 2, .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, }; @@ -384,20 +537,36 @@ static struct qcom_icc_node qnm_pcie = { .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, }; +static const struct qcom_icc_qosbox qnm_snoc_gc_qos = { + .num_ports = 1, + .port_offsets = { 0xd3000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", .id = SC7280_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, + .qosbox = &qnm_snoc_gc_qos, .num_links = 1, .links = { SC7280_SLAVE_LLCC }, }; +static const struct qcom_icc_qosbox qnm_snoc_sf_qos = { + .num_ports = 1, + .port_offsets = { 0xd4000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", .id = SC7280_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, + .qosbox = &qnm_snoc_sf_qos, .num_links = 3, .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC, SC7280_SLAVE_MEM_NOC_PCIE_SNOC }, @@ -432,56 +601,104 @@ static struct qcom_icc_node qnm_mnoc_cfg = { .links = { SC7280_SLAVE_SERVICE_MNOC }, }; +static const struct qcom_icc_qosbox qnm_video0_qos = { + .num_ports = 1, + .port_offsets = { 0x14000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_video0 = { .name = "qnm_video0", .id = SC7280_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, + .qosbox = &qnm_video0_qos, .num_links = 1, .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, }; +static const struct qcom_icc_qosbox qnm_video_cpu_qos = { + .num_ports = 1, + .port_offsets = { 0x15000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_video_cpu = { .name = "qnm_video_cpu", .id = SC7280_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, + .qosbox = &qnm_video_cpu_qos, .num_links = 1, .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, }; +static const struct qcom_icc_qosbox qxm_camnoc_hf_qos = { + .num_ports = 2, + .port_offsets = { 0x10000, 0x10180 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qxm_camnoc_hf = { .name = "qxm_camnoc_hf", .id = SC7280_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, + .qosbox = &qxm_camnoc_hf_qos, .num_links = 1, .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC }, }; +static const struct qcom_icc_qosbox qxm_camnoc_icp_qos = { + .num_ports = 1, + .port_offsets = { 0x11000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qxm_camnoc_icp = { .name = "qxm_camnoc_icp", .id = SC7280_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, + .qosbox = &qxm_camnoc_icp_qos, .num_links = 1, .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, }; +static const struct qcom_icc_qosbox qxm_camnoc_sf_qos = { + .num_ports = 1, + .port_offsets = { 0x12000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", .id = SC7280_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, + .qosbox = &qxm_camnoc_sf_qos, .num_links = 1, .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, }; +static const struct qcom_icc_qosbox qxm_mdp0_qos = { + .num_ports = 1, + .port_offsets = { 0x16000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", .id = SC7280_MASTER_MDP0, .channels = 1, .buswidth = 32, + .qosbox = &qxm_mdp0_qos, .num_links = 1, .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC }, }; @@ -531,20 +748,36 @@ static struct qcom_icc_node qnm_snoc_cfg = { .links = { SC7280_SLAVE_SERVICE_SNOC }, }; +static const struct qcom_icc_qosbox qxm_pimem_qos = { + .num_ports = 1, + .port_offsets = { 0x8000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", .id = SC7280_MASTER_PIMEM, .channels = 1, .buswidth = 8, + .qosbox = &qxm_pimem_qos, .num_links = 1, .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC }, }; +static const struct qcom_icc_qosbox xm_gic_qos = { + .num_ports = 1, + .port_offsets = { 0xa000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_gic = { .name = "xm_gic", .id = SC7280_MASTER_GIC, .channels = 1, .buswidth = 8, + .qosbox = &xm_gic_qos, .num_links = 1, .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC }, }; @@ -1502,7 +1735,16 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, }; +static const struct regmap_config sc7280_aggre1_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1c080, + .fast_io = true, +}; + static const struct qcom_icc_desc sc7280_aggre1_noc = { + .config = &sc7280_aggre1_noc_regmap_config, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1513,6 +1755,14 @@ static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_ce0, }; +static const struct regmap_config sc7280_aggre2_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x2b080, + .fast_io = true, +}; + static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_QDSS_BAM] = &qhm_qdss_bam, [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, @@ -1525,6 +1775,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sc7280_aggre2_noc = { + .config = &sc7280_aggre2_noc_regmap_config, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1605,7 +1856,16 @@ static struct qcom_icc_node * const cnoc2_nodes[] = { [SLAVE_SNOC_CFG] = &qns_snoc_cfg, }; +static const struct regmap_config sc7280_cnoc2_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1000, + .fast_io = true, +}; + static const struct qcom_icc_desc sc7280_cnoc2 = { + .config = &sc7280_cnoc2_regmap_config, .nodes = cnoc2_nodes, .num_nodes = ARRAY_SIZE(cnoc2_nodes), .bcms = cnoc2_bcms, @@ -1637,7 +1897,16 @@ static struct qcom_icc_node * const cnoc3_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; +static const struct regmap_config sc7280_cnoc3_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1000, + .fast_io = true, +}; + static const struct qcom_icc_desc sc7280_cnoc3 = { + .config = &sc7280_cnoc3_regmap_config, .nodes = cnoc3_nodes, .num_nodes = ARRAY_SIZE(cnoc3_nodes), .bcms = cnoc3_bcms, @@ -1653,7 +1922,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, }; +static const struct regmap_config sc7280_dc_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x5080, + .fast_io = true, +}; + static const struct qcom_icc_desc sc7280_dc_noc = { + .config = &sc7280_dc_noc_regmap_config, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -1689,7 +1967,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, }; +static const struct regmap_config sc7280_gem_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xe2200, + .fast_io = true, +}; + static const struct qcom_icc_desc sc7280_gem_noc = { + .config = &sc7280_gem_noc_regmap_config, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1709,7 +1996,16 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, }; +static const struct regmap_config sc7280_lpass_ag_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xf080, + .fast_io = true, +}; + static const struct qcom_icc_desc sc7280_lpass_ag_noc = { + .config = &sc7280_lpass_ag_noc_regmap_config, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -1726,7 +2022,16 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { [SLAVE_EBI1] = &ebi, }; +static const struct regmap_config sc7280_mc_virt_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x4, + .fast_io = true, +}; + static const struct qcom_icc_desc sc7280_mc_virt = { + .config = &sc7280_mc_virt_regmap_config, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1753,7 +2058,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { [SLAVE_SERVICE_MNOC] = &srvc_mnoc, }; +static const struct regmap_config sc7280_mmss_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1e080, + .fast_io = true, +}; + static const struct qcom_icc_desc sc7280_mmss_noc = { + .config = &sc7280_mmss_noc_regmap_config, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1772,7 +2086,16 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = { [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, }; +static const struct regmap_config sc7280_nsp_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10000, + .fast_io = true, +}; + static const struct qcom_icc_desc sc7280_nsp_noc = { + .config = &sc7280_nsp_noc_regmap_config, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, @@ -1797,7 +2120,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = { [SLAVE_SERVICE_SNOC] = &srvc_snoc, }; +static const struct regmap_config sc7280_system_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x15480, + .fast_io = true, +}; + static const struct qcom_icc_desc sc7280_system_noc = { + .config = &sc7280_system_noc_regmap_config, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, From patchwork Wed Mar 6 07:30:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Odelu Kukatla X-Patchwork-Id: 778359 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A65625D46D; Wed, 6 Mar 2024 07:30:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709710261; cv=none; b=BwcS6T+ktbZ8rX6u/HD1GotN7sXa4Whn3YaBlD58agQ2HiaY+2VQqdF5rZvvGLpqSBpDkfm6Dzj7yYgB3tM+8Az2kVwOK3Hynnh4TVVeX7WNPrlgK1G28FRZFMbi1kff5XX/DJy4GyHCzm+iVL+RgPiONWGvzWumX/OZ38LCI98= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709710261; c=relaxed/simple; bh=J8rAfTB8Dz0cD0ouGjdO5KN4NNn2oSqBrYvKTdOIgjc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bVSFIbdlZ5h7cZPBg6U/NHAmh/LoA//3/wiVHSVD3i4L5nZ7cblm6/kZDp081uTeMSoARZpytflEE2gRyCNtU5Bg9TE7DLDBceze8nQ/KwB+m9ZGOKCVIjQTuPSxFwplFFkoAeQlBI3JN8unCMx0IhTsP6Iov2d4pv/qfO6WAMU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=euJqDinB; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="euJqDinB" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4264GgYL027191; Wed, 6 Mar 2024 07:30:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=qcppdkim1; bh=oZo2YnbccVAuXSnZc+lW Ut35fh0qCOdd/MVID34SqTg=; b=euJqDinB1JwTSflqIulR06dODlb5z/QDkVWy xAjqjdDylXfYEIQAEKqqpcGPX3indIM+q/3tp+4U8ZMGtSCc+iT9txDc8+WLpiAG WegMizqNFjuju98xOlS8viGYovSkOWh+qde1917jo395X7xVU38bftnx1+mrwNNH tvwnJJxruYfAwyc3Zy1volk9HfIQGFx44arePbgyeFnouCVPWjOyl7wCG7CD9rsg MctzqubUTbRfOuI5GJbb/8lXG/tXD6SKhOInIo7lN1fA2Fbt7Vp++ikYrsc2Ks/4 MqedFhiCeq7ueerpz2fHNjx4vfgSyjisostiALyHn6AmmQEknA== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3wp2bptc86-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 06 Mar 2024 07:30:55 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4267Utn3018903 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 6 Mar 2024 07:30:55 GMT Received: from hu-okukatla-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 5 Mar 2024 23:30:50 -0800 From: Odelu Kukatla To: Bjorn Andersson , Konrad Dybcio , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Kees Cook , , "Gustavo A . R . Silva" , , , , , , , Subject: [PATCH v3 3/4] dt-bindings: interconnect: add clock property to enable QOS on SC7280 Date: Wed, 6 Mar 2024 13:00:15 +0530 Message-ID: <20240306073016.2163-4-quic_okukatla@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240306073016.2163-1-quic_okukatla@quicinc.com> References: <20240306073016.2163-1-quic_okukatla@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: aBmVuAPHHo95AXST6M397EKHA1YvD0Bq X-Proofpoint-ORIG-GUID: aBmVuAPHHo95AXST6M397EKHA1YvD0Bq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-06_04,2024-03-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 mlxscore=0 phishscore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 clxscore=1015 malwarescore=0 spamscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2403060058 Added clock property to enable clocks required for accessing qos registers. Signed-off-by: Odelu Kukatla --- .../interconnect/qcom,sc7280-rpmh.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml index b135597d9489..758a6e924037 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml @@ -53,10 +53,50 @@ allOf: required: - reg + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-aggre2-noc + then: + properties: + clocks: + items: + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-aggre1-noc + - qcom,sc7280-aggre2-noc + then: + required: + - clocks + else: + properties: + clocks: false + unevaluatedProperties: false examples: - | + #include interconnect { compatible = "qcom,sc7280-clk-virt"; #interconnect-cells = <2>; @@ -69,3 +109,12 @@ examples: #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; + + interconnect@16e0000 { + reg = <0x016e0000 0x1c080>; + compatible = "qcom,sc7280-aggre1-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + }; From patchwork Wed Mar 6 07:30:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Odelu Kukatla X-Patchwork-Id: 778583 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECA735C91C; Wed, 6 Mar 2024 07:31:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709710266; cv=none; b=kWcyNBNWsaCm3Tf+XPNaw7+i8s5fb6tk9nAwSRAZ+K4KzWvYQfI5JJ70NzpO2jpEMe+USwbPm7AHzwGqDTvgsesx4DcXCG3JnqgttRmBa7eNvuBEFs2eY4TzQKsVyLsWiQnf/GXC2pvuhtJV3CnggocLza9VTg8X5U8dHCmbACM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709710266; c=relaxed/simple; bh=SNSEkGY4kQ3s9M8b7X9I+IIVDxto5d7ri1uoIzQCEFI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TXPBmuMwuVNP0qz+MS3r9tMIWFT4ahVVodtJcbXFnoy37Xz04I4PzFL3WYILvBas2hyu1+KxVBFgyCKr7KuzcOIWsyC2VR6VnPRWfHTEKwOaIw+kq04LO8SWqST2XEO9rn//6ikNVjQEObzcTyxkH9s4nr37GAHfyaXUWk1Se/U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=WzILONoW; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="WzILONoW" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42677nLi030225; Wed, 6 Mar 2024 07:31:01 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=qcppdkim1; bh=6rAJW/h3885Nr/rnSGzJ 8U/YAZnDo33NgvDYU1YLb8I=; b=WzILONoWir410R/V0jlcvGJlvfW1nCUNf4PZ bDaH0mCToDJB8GALIZPGQZbRl4owFbfosv6OzwgiYSDppA95VFwVvO6khCUh/lay WoFaRm7YWo4JCBlTrsyLcvu6Saf8BlP3rTqT94aPu6unV97xOnA9tALh/tFos3Xo K0Ao/DdeY661FendvPnl1xKH05EaIgXKV/8LZQE2rMXCSL8Nq7XwVgc5eLZlcvs9 62BRyWReohHm4JMLk40NFbZKYe6m3wELlfoLvgRUwpCmB8PoZ4xsrDHtW5G0N+qW 8TyIVaDDpVK2YH2GgZDNqaGdPGH22rKPWNLm2dsXo35FkSij1g== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3wpktpr1pc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 06 Mar 2024 07:31:01 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4267V0ae003911 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 6 Mar 2024 07:31:00 GMT Received: from hu-okukatla-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 5 Mar 2024 23:30:55 -0800 From: Odelu Kukatla To: Bjorn Andersson , Konrad Dybcio , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Kees Cook , , "Gustavo A . R . Silva" , , , , , , , Subject: [PATCH v3 4/4] arm64: dts: qcom: sc7280: Add clocks for QOS configuration Date: Wed, 6 Mar 2024 13:00:16 +0530 Message-ID: <20240306073016.2163-5-quic_okukatla@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240306073016.2163-1-quic_okukatla@quicinc.com> References: <20240306073016.2163-1-quic_okukatla@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: h82VgwHg5JhEsd0D82HAq4ROj_Ih23wi X-Proofpoint-ORIG-GUID: h82VgwHg5JhEsd0D82HAq4ROj_Ih23wi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-06_04,2024-03-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 spamscore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 suspectscore=0 impostorscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2403060058 Add handles for required clocks to be enabled for configuring QoS on sc7280. Signed-off-by: Odelu Kukatla --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 7e7f0f0fb41b..e1d8fb6afae8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2129,6 +2129,8 @@ reg = <0 0x016e0000 0 0x1c080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; }; aggre2_noc: interconnect@1700000 { @@ -2136,6 +2138,7 @@ compatible = "qcom,sc7280-aggre2-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&rpmhcc RPMH_IPA_CLK>; }; mmss_noc: interconnect@1740000 {