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a=openpgp-sha256; l=2666; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=xjis6bKP+1qp95+QiF0S2jYEGfXq9eU6iywX/YRTDxg=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl6EPQZYQ7XCCOMknukdVYfL87jQ5oeOCLcgbMh Gxe1UwQzA2JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZehD0AAKCRBVnxHm/pHO 9e3CB/9thwGh4M1yb5s6awK8BCruwq7nQy2+QdrPvMtxU9se6LakPl3/a+HfykMFDkeU0oy8OYd 92/K35muS3jQ4OTWAkaIIGbrm/0cs+VCfXwkom3xHEk6KBK9g3ORDZKI46JrTplcE0WXxbitbca rTa9S3gqc7kHv5oWPB4TxvnWw+Oh8S65767iNU7Z3e7e2QFsbEjSU5L5ETar348B5/d6JS/12tZ 6VwVZlna0k7+Zg5tbbVvlq4s6xcdpoDJsMVJjjcFbvGVwq8UualWrUCJ7xd/J634UCH6GZph597 FOQfFfR3AfuxUYAa2GddMrOiBawCEGdVQkrnA6GXMFS1ZzB5 X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 In order to add support for Hyper DMA (HDMA), let's refactor the existing dw_pcie_edma_find_chip() API by moving the common code to separate functions. No functional change. Suggested-by: Serge Semin Reviewed-by: Siddharth Vadapalli Reviewed-by: Frank Li Signed-off-by: Manivannan Sadhasivam Reviewed-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/pcie-designware.c | 40 +++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 250cf7f40b85..3a26dfc5368f 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -880,7 +880,17 @@ static struct dw_edma_plat_ops dw_pcie_edma_ops = { .irq_vector = dw_pcie_edma_irq_vector, }; -static int dw_pcie_edma_find_chip(struct dw_pcie *pci) +static void dw_pcie_edma_init_data(struct dw_pcie *pci) +{ + pci->edma.dev = pci->dev; + + if (!pci->edma.ops) + pci->edma.ops = &dw_pcie_edma_ops; + + pci->edma.flags |= DW_EDMA_CHIP_LOCAL; +} + +static int dw_pcie_edma_find_mf(struct dw_pcie *pci) { u32 val; @@ -902,8 +912,6 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci) if (val == 0xFFFFFFFF && pci->edma.reg_base) { pci->edma.mf = EDMA_MF_EDMA_UNROLL; - - val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL); } else if (val != 0xFFFFFFFF) { pci->edma.mf = EDMA_MF_EDMA_LEGACY; @@ -912,12 +920,17 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci) return -ENODEV; } - pci->edma.dev = pci->dev; + return 0; +} - if (!pci->edma.ops) - pci->edma.ops = &dw_pcie_edma_ops; +static int dw_pcie_edma_find_channels(struct dw_pcie *pci) +{ + u32 val; - pci->edma.flags |= DW_EDMA_CHIP_LOCAL; + if (pci->edma.mf == EDMA_MF_EDMA_LEGACY) + val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); + else + val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL); pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); @@ -930,6 +943,19 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci) return 0; } +static int dw_pcie_edma_find_chip(struct dw_pcie *pci) +{ + int ret; + + dw_pcie_edma_init_data(pci); + + ret = dw_pcie_edma_find_mf(pci); + if (ret) + return ret; + + return dw_pcie_edma_find_channels(pci); +} + static int dw_pcie_edma_irq_verify(struct dw_pcie *pci) { struct platform_device *pdev = to_platform_device(pci->dev); From patchwork Wed Mar 6 10:21:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 778351 Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79B9B5FB84 for ; Wed, 6 Mar 2024 10:22:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709720548; cv=none; b=t4Ip6msy2Ei6FCY5HLyP3eZQoz27PczAedpASW9wI8kCtoZ7B92nnKrnFyq80Hom3mrpcH4b30ZKnQupZnJ8bA2mPWcWozccwMFqrgu2+Vs0FsZb7W2rZ8fPG5e2bqMnlJEwAhX11LuNJLEiTCITiw12ttrCQyM4U24cSO7814k= ARC-Message-Signature: i=1; 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Wed, 06 Mar 2024 02:22:25 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 06 Mar 2024 15:51:58 +0530 Subject: [PATCH v4 2/5] PCI: dwc: Skip finding eDMA channels count for HDMA platforms Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240306-dw-hdma-v4-2-9fed506e95be@linaro.org> References: <20240306-dw-hdma-v4-0-9fed506e95be@linaro.org> In-Reply-To: <20240306-dw-hdma-v4-0-9fed506e95be@linaro.org> To: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Kishon Vijay Abraham I Cc: Serge Semin , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev, Manivannan Sadhasivam , Siddharth Vadapalli , Frank Li X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2114; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=mLMfdy6vJ8u6UFYqXs9q+faj+NP8cJu4pP+nxeyn4zg=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl6EPQyESvJ4GkYeWVdmmhe/LYWOiSlTkv9PB2U Ak4oVW39WeJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZehD0AAKCRBVnxHm/pHO 9bkJB/43VwynoOjr97Hyn4f9NAAsXZ3g5Coo4C/ThVnpEziOI1xQJCQgrUNQfLsvsMPSRNT5txj jZAj4BHz+obZAtt0RrAz6pHTKuUVSwwfLvHxUd2XuiKp4i7LzPoaSnrvC9JHzazPLqoqylPDTZl hRb8ja1BR1OXakF0l3Iy1jYinK03yHOk7JkwzsLfBxGaXFaneH/w8W7yqofD9m/K+SBjS6NMOw3 Fp2n9LLIR1YhMnopygSQgHS8GVRR/hGiYv0W8wWzAjaS0oh+S+urGsuXT/LXIHxjety2o83Hy/u IJShgwoeEN2PLdo/PCu4NaA6x++MXluNt8CJQ7pM4OqXLsqA X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 In the case of Hyper DMA (HDMA) present in DWC controllers, there is no way the drivers can auto detect the number of read/write channels as like its predecessor embedded DMA (eDMA). So the glue drivers making use of HDMA have to pass the channels count during probe. To accommodate that, let's skip the existing auto detection of channels count procedure for HDMA based platforms. If the channels count passed by the glue drivers were wrong in any form, then the existing sanity check will catch it. Suggested-by: Serge Semin Reviewed-by: Siddharth Vadapalli Reviewed-by: Frank Li Signed-off-by: Manivannan Sadhasivam Reviewed-by: Yoshihiro Shimoda Reviewed-by: Serge Semin --- drivers/pci/controller/dwc/pcie-designware.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 3a26dfc5368f..599991b7ffb2 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -927,13 +927,18 @@ static int dw_pcie_edma_find_channels(struct dw_pcie *pci) { u32 val; - if (pci->edma.mf == EDMA_MF_EDMA_LEGACY) - val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); - else + /* + * Autodetect the read/write channels count only for non-HDMA platforms. + * HDMA platforms doesn't support autodetect, so the glue drivers should've + * passed the valid count already. If not, the below sanity check will + * catch it. + */ + if (pci->edma.mf != EDMA_MF_HDMA_NATIVE) { val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL); - pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); - pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); + pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); + pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); + } /* Sanity check the channels count if the mapping was incorrect */ if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH || From patchwork Wed Mar 6 10:21:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 778574 Received: from mail-pg1-f173.google.com (mail-pg1-f173.google.com [209.85.215.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F487604CB for ; Wed, 6 Mar 2024 10:22:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 06 Mar 2024 02:22:30 -0800 (PST) Received: from [127.0.1.1] ([117.248.1.194]) by smtp.gmail.com with ESMTPSA id li17-20020a17090b48d100b0029ab96b13ebsm13339320pjb.40.2024.03.06.02.22.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Mar 2024 02:22:30 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 06 Mar 2024 15:51:59 +0530 Subject: [PATCH v4 3/5] PCI: dwc: Pass the eDMA mapping format flag directly from glue drivers Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240306-dw-hdma-v4-3-9fed506e95be@linaro.org> References: <20240306-dw-hdma-v4-0-9fed506e95be@linaro.org> In-Reply-To: <20240306-dw-hdma-v4-0-9fed506e95be@linaro.org> To: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Kishon Vijay Abraham I Cc: Serge Semin , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev, Manivannan Sadhasivam , Siddharth Vadapalli X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3424; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=GNg1QejkcoZ5fK4swcrLBbBe1IA73m5a3pHFG5FA1Sc=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl6EPQdbpcSFeeqHfUcnEzcW09XZpqMwjds4rW7 ouUkY/9IMKJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZehD0AAKCRBVnxHm/pHO 9d3JB/49m7E14UAaGxtNaUW/tGfbFfFeT7L9Hqxa5OvwPAi/pI5Oh2VrUZbziA/w+y5CL5y2uRq MfIhLMAbL4Bmiw3W+GTGLoZa1OpuxjLc8rB8nMJf8SHxRT4yrP7M6buZQ2keE1vpet7zl4IexM/ b+DbyZvsMTgRg4bCCoFb388eVZiRUTEsVtwE0MFRwaoDmtJ+a9L3Vz3S05Et39FePV+70ySWySe TjADU8T3jb7KIirsSxu6Bht3kQtDeldVIdek/NRmQd+pwRbQTc7nPQgSF8i0CCD0aOHcsJV7UEV tH/A38ghBvN2d+OceSAfnqCYrnScGl3GuIgwg0w61wycWg7H X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 Instead of maintaining a separate capability for glue drivers that cannot support auto detection of the eDMA mapping format, let's pass the mapping format directly from them. This will simplify the code and also allow adding HDMA support that also doesn't support auto detection of mapping format. Suggested-by: Serge Semin Reviewed-by: Siddharth Vadapalli Reviewed-by: Serge Semin Signed-off-by: Manivannan Sadhasivam Reviewed-by: Yoshihiro Shimoda Tested-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/pcie-designware.c | 16 +++++++++------- drivers/pci/controller/dwc/pcie-designware.h | 5 ++--- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +- 3 files changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 599991b7ffb2..c59b2876e5d4 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -894,18 +894,20 @@ static int dw_pcie_edma_find_mf(struct dw_pcie *pci) { u32 val; + /* + * Bail out finding the mapping format if it is already set by the glue + * driver. Also ensure that the edma.reg_base is pointing to a valid + * memory region. + */ + if (pci->edma.mf != EDMA_MF_EDMA_LEGACY) + return pci->edma.reg_base ? 0 : -ENODEV; + /* * Indirect eDMA CSRs access has been completely removed since v5.40a * thus no space is now reserved for the eDMA channels viewport and * former DMA CTRL register is no longer fixed to FFs. - * - * Note that Renesas R-Car S4-8's PCIe controllers for unknown reason - * have zeros in the eDMA CTRL register even though the HW-manual - * explicitly states there must FFs if the unrolled mapping is enabled. - * For such cases the low-level drivers are supposed to manually - * activate the unrolled mapping to bypass the auto-detection procedure. */ - if (dw_pcie_ver_is_ge(pci, 540A) || dw_pcie_cap_is(pci, EDMA_UNROLL)) + if (dw_pcie_ver_is_ge(pci, 540A)) val = 0xFFFFFFFF; else val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 26dae4837462..995805279021 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -51,9 +51,8 @@ /* DWC PCIe controller capabilities */ #define DW_PCIE_CAP_REQ_RES 0 -#define DW_PCIE_CAP_EDMA_UNROLL 1 -#define DW_PCIE_CAP_IATU_UNROLL 2 -#define DW_PCIE_CAP_CDM_CHECK 3 +#define DW_PCIE_CAP_IATU_UNROLL 1 +#define DW_PCIE_CAP_CDM_CHECK 2 #define dw_pcie_cap_is(_pci, _cap) \ test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c index e9166619b1f9..3c535ef5ea91 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -255,7 +255,7 @@ static struct rcar_gen4_pcie *rcar_gen4_pcie_alloc(struct platform_device *pdev) rcar->dw.ops = &dw_pcie_ops; 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Wed, 06 Mar 2024 02:22:36 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 06 Mar 2024 15:52:00 +0530 Subject: [PATCH v4 4/5] PCI: qcom-ep: Add HDMA support for SA8775P SoC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240306-dw-hdma-v4-4-9fed506e95be@linaro.org> References: <20240306-dw-hdma-v4-0-9fed506e95be@linaro.org> In-Reply-To: <20240306-dw-hdma-v4-0-9fed506e95be@linaro.org> To: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Kishon Vijay Abraham I Cc: Serge Semin , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev, Manivannan Sadhasivam , Mrinmay Sarkar , Siddharth Vadapalli , Frank Li X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2836; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=P0A1uqJu0LyM0UHwxugMbNA2eTzT8rsr5vWTX7qvQq0=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl6EPQbIMh5HjM5LP7GgjMmJHMg31rPfk/zEMb6 pHHFEm8fUOJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZehD0AAKCRBVnxHm/pHO 9efXB/9M4qLkv1lPrTQ+6yhvUAYgowFbhtqPznIjzdaHKRCNYTVj5/vpBv+DqAngkReu7ClI+5+ HeppdovvBrasp169dG1oOaZsCZQzHWu4iAfvmtjEV2N+oWByZrNiR8Fw8KR0ysf7cFIgm0HvFaI wiH1QaC4mI0+pii3ZvjC6hyc8BuOVZDAFmbRzSn3RcKkmVj8FlEADMTzAqvdl2oxdt6dXk12T5h vO7qCx/215TN6LKm6HsY/AAVZhwNEAmGcbNC29gcLRa59amz316daG19OTZp1X8ReTwV89mx24g bSUcNd3pNl+UL1T428oI0D5UD+9+cQm1VU9o7KC5koMDuYUJ X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 From: Mrinmay Sarkar SA8775P SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP. Let's add support for it by passing the mapping format and the number of read/write channels count. The PCIe EP controller used on this SoC is of version 1.34.0, so a separate config struct is introduced for the sake of enabling HDMA conditionally. It should be noted that for the eDMA support (predecessor of HDMA), there are no mapping format and channels count specified. That is because eDMA supports auto detection of both parameters, whereas HDMA doesn't. Signed-off-by: Mrinmay Sarkar [mani: Reworded commit message, added kdoc, and minor cleanups] Reviewed-by: Siddharth Vadapalli Reviewed-by: Frank Li Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 45008e054e31..89d06a3e6e06 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -149,6 +149,14 @@ enum qcom_pcie_ep_link_status { QCOM_PCIE_EP_LINK_DOWN, }; +/** + * struct qcom_pcie_ep_cfg - Per SoC config struct + * @hdma_support: HDMA support on this SoC + */ +struct qcom_pcie_ep_cfg { + bool hdma_support; +}; + /** * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller * @pci: Designware PCIe controller struct @@ -803,6 +811,7 @@ static const struct dw_pcie_ep_ops pci_ep_ops = { static int qcom_pcie_ep_probe(struct platform_device *pdev) { + const struct qcom_pcie_ep_cfg *cfg; struct device *dev = &pdev->dev; struct qcom_pcie_ep *pcie_ep; char *name; @@ -816,6 +825,14 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev) pcie_ep->pci.ops = &pci_ops; pcie_ep->pci.ep.ops = &pci_ep_ops; pcie_ep->pci.edma.nr_irqs = 1; + + cfg = of_device_get_match_data(dev); + if (cfg && cfg->hdma_support) { + pcie_ep->pci.edma.ll_wr_cnt = 8; + pcie_ep->pci.edma.ll_rd_cnt = 8; + pcie_ep->pci.edma.mf = EDMA_MF_HDMA_NATIVE; + } + platform_set_drvdata(pdev, pcie_ep); ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); @@ -874,8 +891,12 @@ static void qcom_pcie_ep_remove(struct platform_device *pdev) qcom_pcie_disable_resources(pcie_ep); } +static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { + .hdma_support = true, +}; + static const struct of_device_id qcom_pcie_ep_match[] = { - { .compatible = "qcom,sa8775p-pcie-ep", }, + { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, { .compatible = "qcom,sdx55-pcie-ep", }, { .compatible = "qcom,sm8450-pcie-ep", }, { } From patchwork Wed Mar 6 10:22:01 2024 Content-Type: text/plain; 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a=openpgp-sha256; l=1016; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=HBFaoOrEPY28OgpXbosd8HC8b9IU9rla4yFX01mozG0=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl6EPR3LjKVzSqhLSTX52Xj52sP8auulr1YRKUA e7kAGWdmt+JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZehD0QAKCRBVnxHm/pHO 9ZXBB/4x+EAhH/4vRq8jl6l9OTtS8TpJ1OWU+CL5k04aHCII7oiapzr6jT0TU56ExlM0Fp+KVwx MvcGTaBu1oPvRhvxxi8Ya0sxBNxjDrGkJujhLtueKz1fJRKpfweL17BtDkn2t8qksxOBrRA9TUA UwBHwB6/HKXAKsCjctTYcuxmeAgj21s/GzhVoxR+HCrOSgR2C91gaGtINfsqZ6lz8Uf8ZBKZ3Sk lAMxv9bKabKiDJX8XvNAv30QxGagZ88OT1LtImQiQn2+0+PE1LDFdtvmUN6Pw901+KTTqA6vYOS iJ+AOF/p/jv6dYsAsJKaL5QiupeN0cZHqOwtJWFR0hDmtXQh X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 From: Mrinmay Sarkar SA8775P SoC supports Hyper DMA (HDMA) DMA Engine present in the DWC IP. So, let's enable it in the EPF driver so that the DMA Engine APIs can be used for data transfer. Signed-off-by: Mrinmay Sarkar [mani: reworded commit message] Reviewed-by: Siddharth Vadapalli Reviewed-by: Frank Li Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c index 2c54d80107cf..570c1d1fb12e 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -137,6 +137,7 @@ static const struct pci_epf_mhi_ep_info sa8775p_info = { .epf_flags = PCI_BASE_ADDRESS_MEM_TYPE_32, .msi_count = 32, .mru = 0x8000, + .flags = MHI_EPF_USE_DMA, }; struct pci_epf_mhi {