From patchwork Thu Sep 26 11:29:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174461 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1919818ill; Thu, 26 Sep 2019 04:30:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqzG+XmyqKxPE6L5GVm/YPnRK0ot7gIU6Fw66Cg925k+GHGVDvjTjrk0cpzwgnLA3w2lM2KG X-Received: by 2002:a17:906:fc02:: with SMTP id ov2mr2575893ejb.273.1569497457283; Thu, 26 Sep 2019 04:30:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569497457; cv=none; d=google.com; s=arc-20160816; b=Mnu66g7pqj4zlfFe8bollCseqN5EKDRGChRi5C0Bk5RdV9Z4yQLo1ZZtQab444VgQu 1xRtTS48NpGKqKTmrwktkCkbov5AC99rX07E2wyE/tzHw0RqG26MkdHts1eMk/maDarb bHgnS1YItuvWbR0cXcS4SWlIAJ3GtyMMeQoXdvJyk08wtHy4awunp6AF4dyLTXMZzdlP GNtlXY4RxIPrEX2jsFo++xesCN2rYVH0ldvcwpnOZDNEmb/3N2vWytZtJTM5Hu5ObPZF KtAPJ1+UBjuctDPPJvdRRYp5EgfXthgqJZd5ZfZy9ANnlrki1XvfG+0owcnhvOBF7Eig Ba3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=kAwPRxdL1IzoZOayvlUYSsrr9LV2V6bEEofoVpSjJg8=; b=tI2V9iQp6AlQElUoFSkLuRLMjkENxdXFY92CqprznhW+EU9uGiztAJI2PC5PjBjWW9 5NIwBN7xw1l2ydH6rthcKGTFxWkdp5DYlI02P/rnZgJITNnIpvEroUvvL2zj5VKNyBer TVrGL/JPs+cA1q5EicbELBbuVzzcWKEIJwLC54q8qgZEpi/kVyPcOKOzewtvdENS7AaD mICW58p5hLsRkdnywwLrZrmvoCjdwmbRjolLESuFiBkZ6AoOndBQiBtRP/Zkkn4EYOGw 4lsjPSvXEpk/mJigXLMvKEeJaWrzFXcUqskYkmBGlRnKvDAzNRTGEUvHZwKm0mwUVUSo 6OJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TI7jM4Nw; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z11si1195081edl.1.2019.09.26.04.30.56; Thu, 26 Sep 2019 04:30:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TI7jM4Nw; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726248AbfIZLaz (ORCPT + 8 others); Thu, 26 Sep 2019 07:30:55 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:50088 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725554AbfIZLaz (ORCPT ); Thu, 26 Sep 2019 07:30:55 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8QBUkYQ025811; Thu, 26 Sep 2019 06:30:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569497446; bh=kAwPRxdL1IzoZOayvlUYSsrr9LV2V6bEEofoVpSjJg8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TI7jM4NwXQzoUFUPR2HA2qpvyu4JpjUhuP8P5O5nsWLXjiWgTfmVtUU2EsCHicYhR F+TUSEIBBeRj1XEDjN9qThsAcEidjvenuTCwJ5Jl+Jyg9RH+xnENXNC4wWk/sQIvxt MCd+AwLGSz4XDg/pFG6XBKxv+WMLgaOv1eaYg9WY= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBUkLZ013299; Thu, 26 Sep 2019 06:30:46 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 26 Sep 2019 06:30:46 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 26 Sep 2019 06:30:46 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBUTju069017; Thu, 26 Sep 2019 06:30:42 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jonathan Corbet , Rob Herring , Jon Mason , Dave Jiang , Allen Hubbe , Lorenzo Pieralisi CC: Mark Rutland , , , , , , Subject: [RFC PATCH 03/21] dt-bindings: PCI: Endpoint: Add DT bindings for PCI EPF NTB Device Date: Thu, 26 Sep 2019 16:59:15 +0530 Message-ID: <20190926112933.8922-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190926112933.8922-1-kishon@ti.com> References: <20190926112933.8922-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree bindings for PCI endpoint NTB function device. Signed-off-by: Kishon Vijay Abraham I --- .../bindings/pci/endpoint/pci-epf-ntb.txt | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/endpoint/pci-epf-ntb.txt -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/endpoint/pci-epf-ntb.txt b/Documentation/devicetree/bindings/pci/endpoint/pci-epf-ntb.txt new file mode 100644 index 000000000000..e7896932423e --- /dev/null +++ b/Documentation/devicetree/bindings/pci/endpoint/pci-epf-ntb.txt @@ -0,0 +1,31 @@ +PCI Endpoint NTB Function Device + +This describes the bindings to be used when a NTB device has to be +exposed to the remote host over PCIe. + +Required Properties: + - compatible: Should be "pci-epf-ntb" + - epcs: As defined in generic pci-epf bindings defined in pci-epf.txt + - epc-names: As defined in generic pci-epf bindings defined in pci-epf.txt + - vendor-id: As defined in generic pci-epf bindings defined in pci-epf.txt + - device-id: As defined in generic pci-epf bindings defined in pci-epf.txt + - num-mws: Specify the number of memory windows. Should not be more than 4. + - mws-size: List of 'num-mws' entries containing size of each memory window. + +Optional Properties: + - spad-count: Specify the number of scratchpad registers to be supported + - db-count: Specify the number of doorbell interrupts to be supported. Must + not be greater than 32. + +Example: +Following is an example of NTB device exposed to the remote host. + +ntb { + compatible = "pci-epf-ntb"; + epcs = <&pcie0_ep>, <&pcie1_ep>; + epc-names = "primary", "secondary"; + vendor-id = /bits/ 16 <0x104c>; + device-id = /bits/ 16 <0xb00d>; + num-mws = <4>; + mws-size = <0x100000>, <0x100000>, <0x100000>, <0x100000>; +}; From patchwork Thu Sep 26 11:29:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174462 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1919986ill; Thu, 26 Sep 2019 04:31:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqx1u4L+fAIeUPJ6cx+1/HE5hdCK82SGOrWOdX5QffkU8wI1/vLmbLV5dbvkezQK7v1jYlYy X-Received: by 2002:a17:906:5957:: with SMTP id g23mr2556322ejr.312.1569497465088; Thu, 26 Sep 2019 04:31:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569497465; cv=none; d=google.com; s=arc-20160816; b=sCb9EP/mR5F15IM4Gjj20v5p+A8eNMKEW8qodl5SVhgockSakw4597aFLiOHM9a+NK txJNN8qVrKy+2dmvwdoPNzDc5O54WEp3RRJEW22myVxIYHv53Z9fF2cBiSQkoAH7fyeV ZnGKjTtAY3qKwlzrCe23WcDHV0pPoopQ6gnhGxLRLRV12ozGGZdGZ3B7alZ9rFKT0Awi /C8BySJLpDBsfxWT2mjSOut/HNgkt1GhKWQfMKZS9TlBd4cMA5Vvle4gVvfKoAJsz51W WtbJuBRe5mCn4+kzIUP1tgtUxNebKCr93wxAJ4uvRuUMhz20pFbgy763krDgFVlZh9gS CNuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=uX1YkPL7404jLtW7fYO1D38yxXb3bNzkptt0RmFhIZk=; b=yBvsB54zDtSXDxLiMSCay2zGZxbQ0pdkr2xJyzfW0Hm2WswqJ20ZwuQiki35kYhMRH 2DLR8MG/gy+hicYo/nDInimNxZGlorEErsifGoDjxx8zRe7visA6FJKlLJplDOI9M5hk AFmL64na3UUAqyvzODhXA2lj4HElRJ461pnsPng5aWji/KaP6HdRJwvmbU3/Nueq/VR7 m3bD1QsskUi1dtQ0hXpeF0GYShEFFMBtCrf43sMWLHdst6dMo8s3+BljYMzu7pec4xp1 vtl5My7oldtklfL3JhvtzAWFqlavvRqPGBNaIeRsNXoujTZi7buH/BjyaE/twLonfoe8 Hicw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=NjUJXVkb; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The endpoint function driver and the host PCI driver should be created based on this specification. Signed-off-by: Kishon Vijay Abraham I --- Documentation/PCI/endpoint/pci-test-ntb.txt | 315 ++++++++++++++++++++ 1 file changed, 315 insertions(+) create mode 100644 Documentation/PCI/endpoint/pci-test-ntb.txt -- 2.17.1 diff --git a/Documentation/PCI/endpoint/pci-test-ntb.txt b/Documentation/PCI/endpoint/pci-test-ntb.txt new file mode 100644 index 000000000000..c8bfe9dbfd8b --- /dev/null +++ b/Documentation/PCI/endpoint/pci-test-ntb.txt @@ -0,0 +1,315 @@ + PCI NTB FUNCTION + Kishon Vijay Abraham I + +PCI NTB Function allows two different systems (or hosts) to communicate +with each other by configurig the endpoint instances in such a way that +transactions from one system is routed to the other system. + +In the below diagram, PCI NTB function configures the SoC with multiple +PCIe Endpoint (EP) instances in such a way that transaction from one EP +controller is routed to the other EP controller. Once PCI NTB function +configures the SoC with multiple EP instances, HOST1 and HOST2 can +communicate with each other using SoC as a bridge. + + +-------------+ +-------------+ + | | | | + | HOST1 | | HOST2 | + | | | | + +------^------+ +------^------+ + | | + | | ++---------|-------------------------------------------------|---------+ +| +------v------+ +------v------+ | +| | | | | | +| | EP | | EP | | +| | CONTROLLER1 | | CONTROLLER2 | | +| | <-----------------------------------> | | +| | | | | | +| | | | | | +| | | SoC With Multiple EP Instances | | | +| | | (Configured using NTB Function) | | | +| +-------------+ +-------------+ | ++---------------------------------------------------------------------+ + +Constructs used for Implementing NTB: + + *) Config Region + *) Self Scratchpad Registers + *) Peer Scratchpad Registers + *) Doorbell Registers + *) Memory Window + +Modeling Constructs: + + There are 5 or more distinct regions (config, self scratchpad, peer +scratchpad, doorbell, one or more memory windows) to be modeled to achieve +NTB functionality. Atleast one memory window is required while more than +one is permitted. All these regions should be mapped to BAR for hosts to +access these regions. + +If one 32-bit BAR is allocated for each of these regions, the scheme would +look like + BAR0 -> Config Region + BAR1 -> Self Scratchpad + BAR2 -> Peer Scratchpad + BAR3 -> Doorbell + BAR4 -> Memory Window 1 + BAR5 -> Memory Window 2 + +However if we allocate a separate BAR for each of the region, there would not +be enough BARs for all the regions in a platform that supports only 64-bit +BAR. + +In order to be be supported by most of the platforms, the regions should be +packed and mapped to BARs in a way that provides NTB functionality and +also making sure the hosts doesn't access any region that it is not supposed +to. + +The following scheme is used in EPF NTB Function + + BAR0 -> Config Region + Self Scratchpad + BAR1 -> Peer Scratchpad + BAR2 -> Doorbell + Memory Window 1 + BAR3 -> Memory Window 2 + BAR4 -> Memory Window 3 + BAR4 -> Memory Window 4 + +With this scheme, for the basic NTB functionality 3 BARs should be sufficient. + +Modeling Config/Scratchpad Region: + ++-----------------+------->+------------------+ +-----------------+ +| BAR0 | | CONFIG REGION | | BAR0 | ++-----------------+----+ +------------------+<-------+-----------------+ +| BAR1 | | |SCRATCHPAD REGION | | BAR1 | ++-----------------+ +-->+------------------+<-------+-----------------+ +| BAR2 | Local Memory | BAR2 | ++-----------------+ +-----------------+ +| BAR3 | | BAR3 | ++-----------------+ +-----------------+ +| BAR4 | | BAR4 | ++-----------------+ +-----------------+ +| BAR5 | | BAR5 | ++-----------------+ +-----------------+ + EP CONTROLLER 1 EP CONTROLLER 2 + +Above diagram shows Config region + Scratchpad region for HOST1 (connected to +EP controller 1) allocated in local memory. The HOST1 can access the config +region and scratchpad region (self scratchpad) using BAR0 of EP controller 1. +The peer host (HOST2 connected to EP controller 2) can also access this +scratchpad region (peer scratchpad) using BAR1 of EP controller 2. This +diagram shows the case where Config region and Scratchpad region is allocated +for HOST1, however the same is applicable for HOST2. + +Modeling Doorbell/Memory Window 1: + ++-----------------+ +----->+----------------+-----------+-----------------+ +| BAR0 | | | Doorbell 1 +-----------> MSI|X ADDRESS 1 | ++-----------------+ | +----------------+ +-----------------+ +| BAR1 | | | Doorbell 2 +---------+ | | ++-----------------+ | +----------------+ | | | +| BAR2 | | | Doorbell 3 +-------+ | +-----------------+ ++-----------------+ | +----------------+ | +-> MSI|X ADDRESS 2 | +| BAR3 | | | Doorbell 4 +-----+ | +-----------------+ ++----------------------+ +----------------+ | | | | +| BAR4 | | | | | +-----------------+ ++----------------------+ | MW1 +---+ | +-->+ MSI|X ADDRESS 3|| +| BAR5 | | | | | | +-----------------+ ++-----------------+ +----->-----------------+ | | | | + EP CONTROLLER 1 | | | | +-----------------+ + | | | +---->+ MSI|X ADDRESS 4 | + +----------------+ | +-----------------+ + EP CONTROLLER 2 | | | + (OB SPACE) | | | + +-------> MW1 | + | | + | | + +-----------------+ + | | + | | + | | + | | + | | + +-----------------+ + PCI Address Space + (Managed by HOST2) + +Above diagram shows how the doorbell and memory window 1 is mapped so that +HOST1 can raise doorbell interrupt on HOST2 and also how HOST1 can access +buffers exposed by HOST2 using memory window1 (MW1). Here doorbell and +memory window 1 regions are allocated in EP controller 2 outbound (OB) address +space. Allocating and configuring BARs for doorbell and memory window1 +is done during the initialization phase of NTB endpoint function driver. +Mapping from EP controller 2 OB space to PCI address space is done when HOST2 +sends CMD_CONFIGURE_MW/CMD_CONFIGURE_DOORBELL. The commands are explained +below. + +Modeling Optional Memory Windows: + +This is modeled the same was as MW1 but each of the additional memory windows +is mapped to separate BARs. + +Config Region: + +Config Region is a construct that is specific to NTB implemented using NTB +Endpoint Function Driver. The host and endpoint side NTB function driver will +exchange informatio with each other using this region. Config Region has +Control/Status Registers for configuring the Endpoint Controller. Host can +write into this region for configuring the outbound ATU and to indicate the +link status. Endpoint can indicate the status of commands issued be host in +this region. Endpoint can also indicate the scratchpad offset, number of +memory windows to the host using this region. + +The format of Config Region is given below. Each of the fields here are 32 +bits. + + +------------------------+ + | COMMAND | + +------------------------+ + | ARGUMENT | + +------------------------+ + | STATUS | + +------------------------+ + | TOPOLOGY | + +------------------------+ + | ADDRESS (LOWER 32) | + +------------------------+ + | ADDRESS (UPPER 32) | + +------------------------+ + | SIZE | + +------------------------+ + | MEMORY WINDOW1 OFFSET | + +------------------------+ + | NO OF MEMORY WINDOW | + +------------------------+ + | SPAD OFFSET | + +------------------------+ + | SPAD COUNT | + +------------------------+ + | DB ENTRY SIZE | + +------------------------+ + | DB DATA | + +------------------------+ + | : | + +------------------------+ + | : | + +------------------------+ + | DB DATA | + +------------------------+ + + + COMMAND: + + NTB function supports three commands: + + CMD_CONFIGURE_DOORBELL (0x1): Command to configure doorbell. Before + invoking this command, the host should allocate and initialize + MSI/MSI-X vectors (i.e initialize the MSI/MSI-X capability in the + Endpoint). The endpoint on receiving this command will configure + the outbound ATU such that transaction to DB BAR will be routed + to the MSI/MSI-X address programmed by the host. The ARGUMENT + register should be populated with number of DBs to configure (in the + lower 16 bits) and if MSI or MSI-X should be configured (BIT 16). + (TODO: Add support for MSI-X). + + CMD_CONFIGURE_MW (0x2): Command to configure memory window. The + host invokes this command after allocating a buffer that can be + accessed by remote host. The allocated address should be programmed + in the ADDRESS register (64 bit), the size should be programmed in + the SIZE register and the memory window index should be programmed + in the ARGUMENT register. The endpoint on receiving this command + will configure the outbound ATU such that trasaction to MW BAR + will be routed to the address provided by the host. + + CMD_LINK_UP (0x3): Command to indicate an NTB application is + bound to the EP device on the host side. Once the endpoint + receives this command from both the hosts, the endpoint will + raise an LINK_UP event to both the hosts to indicate the hosts + can start communicating with each other. + + ARGUMENT: + + The value of this register is based on the commands issued in + command register. See COMMAND section for more information. + + configuring memory window and to indicate the host side NTB application + has initialized. + + TOPOLOGY: + + Set to NTB_TOPO_B2B_USD for Primary interface + Set to NTB_TOPO_B2B_DSD for Secondary interface + + ADDRESS/SIZE: + + Address and Size to be used while configuring the memory window. + See "CMD_CONFIGURE_MW" for more info. + + MEMORY WINDOW1 OFFSET: + + Memory Window 1 and Doorbell registers are packed together in the + same BAR. The initial portion of the region will have doorbell + registers and the latter portion of the region is for memory window 1. + This register will specify the offset of the memory window 1. + + NO OF MEMORY WINDOW: + + Specifies the number of memory windows supported by the NTB device. + + SPAD OFFSET: + + Self scratchpad region and config region are packed together in the + same BAR. The initial portion of the will have config region and + the latter portion of the region is for self scratchpad. This + register will specify the offset of the self scratchpad registers. + + SPAD COUNT: + + Specifies the number of scratchpad registers supported by the NTB + device. + + DB ENTRY SIZE: + + Used to determine the offset within the DB BAR that should be written + in order to raise doorbell. EPF NTB can use either MSI/MSI-X to + ring doorbell (MSI-X support will be added later). MSI uses same + address for all the interrupts and MSI-X can provide different + addresses for different interrupts. The MSI/MSI-X address is provided + by the host and the address it gives is based on the MSI/MSI-X + implementation supported by the host. For instance, ARM platform + using GIC ITS will have same MSI-X address for all the interrupts. + In order to support all the combinations and use the same mechanism + for both MSI and MSI-X, EPF NTB allocates separate region in the + Outbound Address Space for each of the interrupts. This region will + be mapped to the MSI/MSI-X address provided by the host. If a host + provides the same address for all the interrupts, all the regions + will be translated to the same address. If a host provides different + address, the regions will be translated to different address. This + will ensure there is no difference while raising the doorbell. + + DB DATA: + + EPF NTB supports 32 interrupts. So there are 32 DB DATA registers. + This holds the MSI/MSI-X data that has to be written to MSI address + for raising doorbell interrupt. This will be populated by EPF NTB + while invoking CMD_CONFIGURE_MW. + +Scratchpad Registers: + + Each host has it's own register space allocated in the memory of NTB EPC. + They are both readable and writable from both sides of the bridge. They + are used by applications built over NTB and can be used to pass control + and status information between both sides of a device. + + Scratchpad registers has 2 parts + 1) Self Scratchpad: Host's own register space + 2) Peer Scratchpad: Remote host's register space. + +Doorbell Registers: + + Registers using which one host can interrupt the other host. + +Memory Window: + + Actual transfer of data between the two hosts will happen using the + memory window. From patchwork Thu Sep 26 11:29:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174465 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1920210ill; Thu, 26 Sep 2019 04:31:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqy8egCTNtG13DyMxTdycOBWuSjSPZM0zaIcLTeDqZ4Sy/syaJ+P4hnjK2OBZNC3AYPKRF+S X-Received: by 2002:aa7:dcca:: with SMTP id w10mr2986075edu.183.1569497475335; Thu, 26 Sep 2019 04:31:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569497475; cv=none; d=google.com; s=arc-20160816; b=fO53oLf7BjMp6izQgswjV9O1vXoyA+EuyBkRLtBJqumGVA06/NFncBiqq7iceO/Mn9 2hLvyrtnuKgPtZLFqe55GqVliJqRVLE9P5ahmSkmKxwYWgMvlUyvcUlKb/0pEJCuk8NV fv7nHEqM0eMHHM7uxsXFpxaPmKRe1ab96qWIoVRgBGPg/hYtU/4ZCihorO88LA/jKdce Pbq5xDfR4ERczIvU/Gm1QuQyViMqE0wP0NbqChk8XwwsqbUI53ziJGyTLH7nFRrXhV/d Z7bvuB1jrUvH5TlBQWMmyKeb+iByojZ5KuES0XtMuzjXlpa5ukbP/lJpWSb9+0m34P5g 7Nag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=iaR4/VPvHXdgGcChNIDAglMw0NIfiR18nZfC93JIGCk=; b=nkP3sNtnoyn5tbSmXZbWWh9UH3xlQ1FdZKCU46MCgvUawW+fypEGGEasOaXUQRgJX/ mjrFcCPh03AM5h5AzQVF3AXVVhGcDBVWiFEBAvLjr5rHZLJO7KLNUiAo+iyRVD4qpm8v I7zuo21Z2BoKvE8cPHyZnpa1m37VpJ6PeeYGVhiny961vn0vkgOYqG6dEbWsSUbzicYj upHUknXwZbWNCx3loy2G0UmUBTuuuNEv31cimGBt19FbXoSiPBrC/iZ8Sj0YW7lbFNff gTjQKulj+pRTAgOdXHPFqtHxGMYOxV2V3qkhnjIU7uJnTM4f6MXFEnRMhfNorOqigbRb qxaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=CH27UaMC; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q10si1135490eda.293.2019.09.26.04.31.15; Thu, 26 Sep 2019 04:31:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=CH27UaMC; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726440AbfIZLbL (ORCPT + 8 others); Thu, 26 Sep 2019 07:31:11 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:50980 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726435AbfIZLbL (ORCPT ); Thu, 26 Sep 2019 07:31:11 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8QBV3MU042367; Thu, 26 Sep 2019 06:31:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569497463; bh=iaR4/VPvHXdgGcChNIDAglMw0NIfiR18nZfC93JIGCk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=CH27UaMC6h0DmkS/FvOR0OXtMzqrOiA4EgMLJdoReHAUiONQmSOzpuLtbABypp3Iw w/ESVD+sCX1JrOR7laHlkzAgYhoNJa6Zw08UycuCcMR1zJ2w4JkmUlHEaW/Fj0+KmC 5im6Y6NehNR8k3OTnupdbYv/73HI5Uox2WOn9WRI= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8QBV3B5050162 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 26 Sep 2019 06:31:03 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 26 Sep 2019 06:31:03 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 26 Sep 2019 06:31:03 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBUTk0069017; Thu, 26 Sep 2019 06:30:59 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jonathan Corbet , Rob Herring , Jon Mason , Dave Jiang , Allen Hubbe , Lorenzo Pieralisi CC: Mark Rutland , , , , , , Subject: [RFC PATCH 07/21] PCI: endpoint: Add "pci-epf-bus" driver Date: Thu, 26 Sep 2019 16:59:19 +0530 Message-ID: <20190926112933.8922-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190926112933.8922-1-kishon@ti.com> References: <20190926112933.8922-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add "pci-epf-bus" driver that helps to create EPF device from device tree. This is added in order to define an endpoint function completely from device tree. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/Makefile | 3 +- drivers/pci/endpoint/pci-epf-bus.c | 54 ++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+), 1 deletion(-) create mode 100644 drivers/pci/endpoint/pci-epf-bus.c -- 2.17.1 diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile index 95b2fe47e3b0..36cf33cf975c 100644 --- a/drivers/pci/endpoint/Makefile +++ b/drivers/pci/endpoint/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_PCI_ENDPOINT_CONFIGFS) += pci-ep-cfs.o obj-$(CONFIG_PCI_ENDPOINT) += pci-epc-core.o pci-epf-core.o\ - pci-epc-mem.o functions/ + pci-epc-mem.o pci-epf-bus.o \ + functions/ diff --git a/drivers/pci/endpoint/pci-epf-bus.c b/drivers/pci/endpoint/pci-epf-bus.c new file mode 100644 index 000000000000..c47eeae7fe7a --- /dev/null +++ b/drivers/pci/endpoint/pci-epf-bus.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * PCI Endpoint *Function* Bus Driver + * + * Copyright (C) 2019 Texas Instruments + * Author: Kishon Vijay Abraham I + */ + +#include +#include +#include +#include +#include + +static int pci_epf_bus_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = of_node_get(dev->of_node); + struct device_node *child; + struct pci_epf *epf; + + for_each_child_of_node(node, child) { + epf = devm_pci_epf_of_create(dev, child); + if (IS_ERR(epf)) { + dev_err(dev, "Failed to create PCI EPF device %s\n", + node->full_name); + of_node_put(child); + break; + } + } + of_node_put(node); + + return 0; +} + +static const struct of_device_id pci_epf_bus_id_table[] = { + { .compatible = "pci-epf-bus" }, + {} +}; +MODULE_DEVICE_TABLE(of, pci_epf_bus_id_table); + +static struct platform_driver pci_epf_bus_driver = { + .probe = pci_epf_bus_probe, + .driver = { + .name = "pci-epf-bus", + .of_match_table = of_match_ptr(pci_epf_bus_id_table), + }, +}; + +module_platform_driver(pci_epf_bus_driver); + +MODULE_AUTHOR("Texas Instruments Inc."); +MODULE_DESCRIPTION("PCI EPF Bus Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Thu Sep 26 11:29:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174467 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1920389ill; Thu, 26 Sep 2019 04:31:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqzwtLZTAh+Lo/ybLsQMYwj14MSA04Jtk0JzlqGBJkMc25bW04k1dYYRCeCgkR443zG8kogS X-Received: by 2002:a17:906:9703:: with SMTP id k3mr2515173ejx.159.1569497483463; Thu, 26 Sep 2019 04:31:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569497483; cv=none; d=google.com; s=arc-20160816; b=nJDRYZoRixA6LilkvQXKWyop1vlsn3C57BqNliQr15AU+0Nry0B9lwcX6H5nqu6m3A UaRJ3Fc/YGjlroApzu/2IsWjb19gzcfIaBDPNgqRcN7HHJ4x2mn2Uyxpj20bNU+QymJt PNTtJIxz1pZ4bTdEBnody4dNpttf7ZLVw3afvKSFDQOmoiA0tSf7mkoUysv3G6cvMv2O bzgBW/nx7AlLNCQ56xT+ytiO3e8Kcco/SNXhZYYbjlA0Cn8FjAPYVXNzjgGdc0y7GNpD nEUzrjdWpRSn7vPx06Jr9++aLx4saXKdnxXlqJUAr+j7U5txVlgICy93hgEO/RbzKTLI teFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=WN6zQz22SKDDpOt20zGyRCD7tAdq3OZmA5JGj+CItiA=; b=UYksCV0D7qfdaCmxHa2KanDKAyhdBu55FlMew1p3wwk9CDqM8Iza1ULXi2iJkfSVky 24cMyxrcQM0KlJGh1iuehzRpaQAUS0SMeXKBl4ljOK4C/U5QP3We0U5WvT9hgxGDVqpJ qXS+C8JjCV33WE7kK/j/QG2mVsyP9McYkHskFg0kdBDu33358dwJcOrIAVQKQQsGP8X8 8o/EaHsf0n7AowgyneF18kDnUrNhNObICmfxiFjeUqM2eC0OdBP/0SnFLrfhlBlCQisz JLQenBOVkkBTOelFO+RZkJkqkz8pSVFQ8oeJATwIfZDoojUE4Ypw+RIk/r1hisJSKMcA PRTQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RQUZDPwN; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-epc-core.c | 26 ++++++++++++++++++++++---- include/linux/pci-epc.h | 2 ++ 2 files changed, 24 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 7eae7dcaebf9..49bdff217777 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -147,17 +147,36 @@ EXPORT_SYMBOL_GPL(of_pci_epc_get_by_name); * pci_epc_get_first_free_bar() - helper to get first unreserved BAR * @epc_features: pci_epc_features structure that holds the reserved bar bitmap * - * Invoke to get the first unreserved BAR that can be used for endpoint + * Invoke to get the first unreserved BAR that can be used by the endpoint * function. For any incorrect value in reserved_bar return '0'. */ unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features) +{ + return pci_epc_get_next_free_bar(epc_features, BAR_0); +} +EXPORT_SYMBOL_GPL(pci_epc_get_first_free_bar); + +/** + * pci_epc_get_next_free_bar() - helper to get unreserved BAR starting from @bar + * @epc_features: pci_epc_features structure that holds the reserved bar bitmap + * @bar: the starting BAR number from where unreserved BAR should be searched + * + * Invoke to get the next unreserved BAR starting from @bar that can be used + * for endpoint function. For any incorrect value in reserved_bar return '0'. + */ +unsigned int pci_epc_get_next_free_bar(const struct pci_epc_features + *epc_features, enum pci_barno bar) { unsigned long free_bar; if (!epc_features) return 0; + /* If 'bar - 1' is a 64-bit BAR, move to the next BAR */ + if ((epc_features->bar_fixed_64bit << 1) & 1 << bar) + bar++; + /* Find if the reserved BAR is also a 64-bit BAR */ free_bar = epc_features->reserved_bar & epc_features->bar_fixed_64bit; @@ -165,14 +184,13 @@ unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features free_bar <<= 1; free_bar |= epc_features->reserved_bar; - /* Now find the free BAR */ - free_bar = ffz(free_bar); + free_bar = find_next_zero_bit(&free_bar, 6, bar); if (free_bar > 5) return 0; return free_bar; } -EXPORT_SYMBOL_GPL(pci_epc_get_first_free_bar); +EXPORT_SYMBOL_GPL(pci_epc_get_next_free_bar); /** * pci_epc_get_features() - get the features supported by EPC diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index ef6531af6ed2..993b1a55a239 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -200,6 +200,8 @@ const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no); unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features); +unsigned int pci_epc_get_next_free_bar(const struct pci_epc_features + *epc_features, enum pci_barno bar); struct pci_epc *pci_epc_get(const char *epc_name); void pci_epc_put(struct pci_epc *epc); struct pci_epc *of_pci_epc_get(struct device_node *node, int index); From patchwork Thu Sep 26 11:29:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174468 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1920468ill; Thu, 26 Sep 2019 04:31:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqymaglXbJTGLpWeJrk6HvXsDZTcBY+VCV0Zz5XLZSgO0m/1VuLRVZdeTZjZvUFCiQv0bhLT X-Received: by 2002:a50:cd1a:: with SMTP id z26mr2943027edi.75.1569497487249; Thu, 26 Sep 2019 04:31:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569497487; cv=none; d=google.com; s=arc-20160816; b=HgX7P564QDsOpFBF3dVSi+uBnLo9ODwQ/vY3mBLcn0JMv/tdi8CEdcCqBv36jEyouR c1I7hxCOH4njkgQHVcrindwXm06VDBCAzOrrhLN/mB3T09Kg6VryxkEUBMJ9G21Lnhzy hMeBBN27lxzbHp0ojhtiLAN02xxRGb7DWR5vU2M4a6m8LYtf9zAd53v5rSXh4YoCVXw/ QoGf5gdoJWQOJwZvsKA2zo2DE5JaUALrgUrWgwv/kpTelB0TgAUYVYBagHhqrK76vd9G kydK55xYzQ4lDW5zOnf26O61oBa4IEEKa0om2t9uT9hYjm18DRyaAgK9Vu7mDzpTSBWd X/TQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=E2GTTExAvbZbBjqJm7peVu26RwtsAEY0HmYYy9aUZio=; b=kFWIMvn/o0YcXm4SnQgAxAVj0jdUjK94AYGO+9/sYcjSRJs23YxC2OFCZ+1lT5cMAU G9KEUlORedOIJv+1ll0BmbIfnWV4OChHjEJ2Sg8lNa3VPv3mt2awTLLoqaYUMcHE8u/M CZW2tNJy4iQjEo1kWCWh20RStK4RcDUHtSVWnArkDrX8ddDZg03YJ+8qoLlzeeaGUdtJ xx8kKjpzYWwyio23rH14KguIZvwHHGmqKrNicQRbnkgxT52blfavZ0aiChv6Ka8pOaR/ 2Hyl9efn7OfKIgPHTvs0f4KbiOXv1UBUlS81RBu7jZhx7Za+MqZ7l3Mrg4TGg52yPrLR cW1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="Sc6WLz/r"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s21si855087eja.226.2019.09.26.04.31.27; Thu, 26 Sep 2019 04:31:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="Sc6WLz/r"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726505AbfIZLb0 (ORCPT + 8 others); Thu, 26 Sep 2019 07:31:26 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:51028 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726030AbfIZLbX (ORCPT ); Thu, 26 Sep 2019 07:31:23 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8QBVGt5042493; Thu, 26 Sep 2019 06:31:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569497476; bh=E2GTTExAvbZbBjqJm7peVu26RwtsAEY0HmYYy9aUZio=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Sc6WLz/rgCEjTalAjHyyN/dl7vJRBPT5G+xMCus7Zdk+xUmOS/jli4Wl1k39juA5g NqqLx7JqQXazDe/Uwihqes0fkvz0VlyzEoKmz7611/wgXt1IJjHEjjIhu9ci208c0R K0uutCj06xnxsrpSCNJxwnjOpoe43EMooUR/B+is= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBVGH3013966; Thu, 26 Sep 2019 06:31:16 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 26 Sep 2019 06:31:15 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 26 Sep 2019 06:31:08 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBUTk3069017; Thu, 26 Sep 2019 06:31:12 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jonathan Corbet , Rob Herring , Jon Mason , Dave Jiang , Allen Hubbe , Lorenzo Pieralisi CC: Mark Rutland , , , , , , Subject: [RFC PATCH 10/21] PCI: endpoint: Make pci_epf_driver ops optional Date: Thu, 26 Sep 2019 16:59:22 +0530 Message-ID: <20190926112933.8922-11-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190926112933.8922-1-kishon@ti.com> References: <20190926112933.8922-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org pci_epf_driver had two ops for bind and unbind which will be invoked when an endpoint controller is bound to an endpoint function (using configfs). Now that endpoint core has support to define an endpoint function using device tree alone, the bind and unbind ops can be optional. Make pci_epf_driver ops optional here. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-epf-core.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c index c74c7cc6d8bd..67015c66d09f 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -446,11 +446,9 @@ int __pci_epf_register_driver(struct pci_epf_driver *driver, { int ret; - if (!driver->ops) - return -EINVAL; - - if (!driver->ops->bind || !driver->ops->unbind) - return -EINVAL; + if (!driver->ops || !driver->ops->bind || !driver->ops->unbind) + pr_debug("%s: Supports only pci_epf device created using DT\n", + driver->driver.name); driver->driver.bus = &pci_epf_bus_type; driver->driver.owner = owner; From patchwork Thu Sep 26 11:29:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174471 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1920728ill; Thu, 26 Sep 2019 04:31:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqyk601TGUKGYvk8VxtGhcB3BliKpmP2lsnIB64K4hwkScmYSd8JsPyeDxPjXwCYkmDL+TQS X-Received: by 2002:a50:a57d:: with SMTP id z58mr2993271edb.115.1569497500625; Thu, 26 Sep 2019 04:31:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569497500; cv=none; d=google.com; s=arc-20160816; b=h4j4XaB8wA5WpEWcSOCiQ5Z3rS15EhB3x6eiMSHwhvH7eLM2NGYLCgGms7TZOffFYf Py6KEDuH37Bx3jSNOkn+y7l6BMPisLpNzxN7F41b1UjmtC4YiNcNAQpmjZoVfw6DQnjQ iEf/DGv9wxOTznS61lxIBGgIRiEENIVxszR5UDPaK/hJn3EaYa7Z559dOY9j6G4WKvRt Jemb7QoA3P3GTnPIEp9E8dn9T84uWhYBHP6QjYzMEmElo8xZjtjgDrp4RCwhJBaHAgyK JWpzOWX9KqjdybYyP/u3Y5PnuzxhE9Q5MVs0C7+wBXSRcC8FnO86b+Z48iH5F5qiTFB9 L8Cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=1e8ivCO58tj7yZejWhSGbZsRTueBDWvOfW2EVwnBC3Q=; b=HV6Lld2ZKn3QEJ4lOBqIQ7vMSUxvDwYW9UMiBGQNy+NyiMuwTJbEwb+RggxqIT8AyX QA5WhwIN0wdOlg0oP8nAmLsK7MXayjRGDYNiNjaiAT9H1np0+DfIKUFcPw9dyMkzC8A2 /lmPx+HJYDRUCAL/Ot32S5WIw3s7449bQqNdgGIravJhFDxEGtTD8Wc6EVgeLwKEqHJZ 5fJ5ZQDsZlaMFBNVSx40Uf45Z+j3NpspnYbCUnD5XjsqCCsQUzuv1v0+swaxwAVK9yp2 4yMx241TGZFnpHXqcTSBqmnYhSGFk/7MwZNJEpsQ9ryR7yqoiu5Z5D99BAsz54gZXYsk Jsfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=aSr1crur; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The physical address is an address in the outbound region. This is required to implement doorbell functionality of NTB (non transparent bridge) wherein EPC on either side of the interface (primary and secondary) can directly write to the physical address (in outbound region) of the other interface to ring doorbell using MSI. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-epc-core.c | 40 +++++++++++++++++++++++++++++ include/linux/pci-epc.h | 7 +++++ 2 files changed, 47 insertions(+) -- 2.17.1 diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 42085fcc746d..797e5d323998 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -363,6 +363,46 @@ int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no, } EXPORT_SYMBOL_GPL(pci_epc_raise_irq); +/** + * pci_epc_map_msi_irq() - Map physical address to MSI address and return + * MSI data + * @epc: the EPC device which has the MSI capability + * @func_no: the physical endpoint function number in the EPC device + * @vfunc_no: the virtual endpoint function number in the physical function + * @phys_addr: the physical address of the outbound region + * @interrupt_num: the MSI interrupt number + * @entry_size: Size of Outbound address region for each interrupt + * @msi_data: the data that should be written in order to raise MSI interrupt + * with interrupt number as 'interrupt num' + * + * Invoke to map physical address to MSI address and return MSI data. The + * physical address should be an address in the outbound region. This is + * required to implement doorbell functionality of NTB wherein EPC on either + * side of the interface (primary and secondary) can directly write to the + * physical address (in outbound region) of the other interface to ring + * doorbell. + */ +int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + phys_addr_t phys_addr, u8 interrupt_num, u32 entry_size, + u32 *msi_data) +{ + int ret; + + if (IS_ERR_OR_NULL(epc)) + return -EINVAL; + + if (!epc->ops->map_msi_irq) + return -EINVAL; + + mutex_lock(&epc->lock); + ret = epc->ops->map_msi_irq(epc, func_no, vfunc_no, phys_addr, + interrupt_num, entry_size, msi_data); + mutex_unlock(&epc->lock); + + return ret; +} +EXPORT_SYMBOL_GPL(pci_epc_map_msi_irq); + /** * pci_epc_get_msi() - get the number of MSI interrupt numbers allocated * @epc: the EPC device to which MSI interrupts was requested diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 91d5cbaabc8f..0632a4d4714d 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -57,6 +57,7 @@ pci_epc_interface_string(enum pci_epc_interface_type type) * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC * from the MSI-X capability register * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt + * @map_msi_irq: ops to map physical address to MSI address and return MSI data * @start: ops to start the PCI link * @stop: ops to stop the PCI link * @owner: the module owner containing the ops @@ -85,6 +86,9 @@ struct pci_epc_ops { int (*get_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no); int (*raise_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, enum pci_epc_irq_type type, u16 interrupt_num); + int (*map_msi_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + phys_addr_t phys_addr, u8 interrupt_num, + u32 entry_size, u32 *msi_data); int (*start)(struct pci_epc *epc); void (*stop)(struct pci_epc *epc); const struct pci_epc_features* (*get_features)(struct pci_epc *epc, @@ -212,6 +216,9 @@ int pci_epc_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no); int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u16 interrupts); int pci_epc_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no); +int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + phys_addr_t phys_addr, u8 interrupt_num, + u32 entry_size, u32 *msi_data); int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no, enum pci_epc_irq_type type, u16 interrupt_num); int pci_epc_start(struct pci_epc *epc); From patchwork Thu Sep 26 11:29:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174475 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1921085ill; Thu, 26 Sep 2019 04:31:58 -0700 (PDT) X-Google-Smtp-Source: APXvYqyV2Nkcjpg2KOhavseXJtCIhIU8cAFymxdYP9dDgC5Jk5SvY3PnabxivSPxi1Xm7QsanhjG X-Received: by 2002:a50:9734:: with SMTP id c49mr3016970edb.93.1569497518322; Thu, 26 Sep 2019 04:31:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569497518; cv=none; d=google.com; s=arc-20160816; b=XZlBhcomNr14CMFRIo2gJVeDE3aJcPiaQOErANqlizeW00VuW0VGS1lqlqxi57ooxF JY/bYzVssEtUX3C6Q63dafWcpRn/zHAO8Ct1+SkV4EdxBCT6XrAAbbq2gUBgJ1nEYr6f LAXDiSz2Ceu6nkzYmGOtTz8p87xC3YXiYrdgZ2mLvsCux7NawEog9gsIiuY294YY7ALp GG16Dopy4yNvCWpT0rgD7Z2ptORAfryfZgY/FT5wyUGt1mdVxplCq9ZvPx3f0uDbLD5q q3p4QuQbVTPV/uHC2V0MIDDj02qCrn06omJauijM2hwJIbLRNyomCgaoyRWNGZosw64Z b5aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=CVQLahlcO/peyrVMGcW0P4vLEQL8s6mVGnyOrqGBh9U=; b=zhAjzQf44hkxt+nvOgJGdPfWn1LyKhVL1aGqCv1NbpLscQtKHURB9v+3UpIl1De0b1 ZB33gUSXVgSf+LX7jPJa+alxIiiC5p/57i8uhrpzsw5Myi5VWU0CcbbzBrPsKKfD+9D4 psFOOiqZvUqD/fFGOpE7e7EeoniJ0mCbJU16uuSenXiuzhFj+zs/eNFbHh9NRF+rNDqn vxX1SWT0Oh8RG85e0/zVUUEl8LbtL1exy5Aq6/q+0lg1Qpeiw0XUC35UqR7/97hyAxy5 CKAH3ai8gQMVco0ZWJFnhPi76870Me1j8G6vKoG6ti05JkHJQV0kMqMGvnclbhnu2T/y fXhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jpWByUMO; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-epc-core.c | 9 ++++----- include/linux/pci-epc.h | 7 +++---- 2 files changed, 7 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 33c745546a42..a93c78488bca 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -173,8 +173,7 @@ EXPORT_SYMBOL_GPL(of_pci_epc_get_by_name); * Invoke to get the first unreserved BAR that can be used by the endpoint * function. For any incorrect value in reserved_bar return '0'. */ -unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features - *epc_features) +int pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features) { return pci_epc_get_next_free_bar(epc_features, BAR_0); } @@ -188,8 +187,8 @@ EXPORT_SYMBOL_GPL(pci_epc_get_first_free_bar); * Invoke to get the next unreserved BAR starting from @bar that can be used * for endpoint function. For any incorrect value in reserved_bar return '0'. */ -unsigned int pci_epc_get_next_free_bar(const struct pci_epc_features - *epc_features, enum pci_barno bar) +int pci_epc_get_next_free_bar(const struct pci_epc_features + *epc_features, enum pci_barno bar) { unsigned long free_bar; @@ -209,7 +208,7 @@ unsigned int pci_epc_get_next_free_bar(const struct pci_epc_features free_bar = find_next_zero_bit(&free_bar, 6, bar); if (free_bar > 5) - return 0; + return -EINVAL; return free_bar; } diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 0632a4d4714d..ad8021b0efb7 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -227,10 +227,9 @@ void pci_epc_of_parse_header(struct device_node *node, struct pci_epf_header *header); const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no); -unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features - *epc_features); -unsigned int pci_epc_get_next_free_bar(const struct pci_epc_features - *epc_features, enum pci_barno bar); +int pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features); +int pci_epc_get_next_free_bar(const struct pci_epc_features + *epc_features, enum pci_barno bar); struct pci_epc *pci_epc_get(const char *epc_name); void pci_epc_put(struct pci_epc *epc); struct pci_epc *of_pci_epc_get(struct device_node *node, int index); From patchwork Thu Sep 26 11:29:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174479 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1921542ill; Thu, 26 Sep 2019 04:32:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqygfLpvQgY+sGlZ++dxbWIsl1d1RrOzNt10qxBTvyEgBPUCvDoJMzEx1R9lLJsetAfx3LJE X-Received: by 2002:a17:906:168f:: with SMTP id s15mr2514498ejd.109.1569497534898; Thu, 26 Sep 2019 04:32:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569497534; cv=none; d=google.com; s=arc-20160816; b=zTH6iXwCTeXDCEI/Kj46xZdNkZczgNkAF2GJgyxXTlT8Bk1Z0y3JrLP78tn0H/cnqj jg26gBU44/rSoNC2IPBhBgDBxVCJD/SIu9eUxNvfOCGIyGMFMxOwteeBGECbbbOuGWVl z3t9+XriTuQ0L738XZ83yEhtNXFMIs/5CSc6Obe/m3eM5rIigd56vJJVFeqR/nP6CmZg qVspbBNokSJ1+EnkLzSdHVnb9ujIvvtRt4hnOCBjD3mqk/zB1Spsu3lO1TU2lQ8qQjET UzkhekTkh4Uaowc118vbv4JxdXW4JN95rh6PZAa3VgFjyKVYUbCqD0VN7G8oaGEKVfBE qlWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=88Xv9IRV7+oNSxAgr2jq3XB2+SHFQvDvj39xR9Z58mQ=; b=TFqhJmez6vCk/xWuSfOjq8u0nUUKn+aHEauRYYZd+hwpK/gKpbUEKaFj5klwr4yRUY UoQaybcgcd1yQ4Ir1gFdH4Vj7lGom2XEB19uG5ERx7kDXIDsaVHGtHHIyHQHVHc3Grfm aC0RnXrgZ3MJNlskdYAiSLCcFLgswJo7bOZ5ehZqg6gcrCT2Gw2gFm03JYznP9yrmMNX Q57M8mkagYiQNZpDpvOSSjvFAS/S/3UDd5KwH15Ydc047BsUinAA2XczgvJiSvxcSB9v yovUpwkX+xFcZH5g723l3TW2X9r/54DhygernQQXaRAd2JQC6gm+p61jry0hVoRYtR0f 4tuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=eyZNqkD+; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id um16si880941ejb.12.2019.09.26.04.32.14; Thu, 26 Sep 2019 04:32:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=eyZNqkD+; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726935AbfIZLcN (ORCPT + 8 others); Thu, 26 Sep 2019 07:32:13 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:57298 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725787AbfIZLcJ (ORCPT ); Thu, 26 Sep 2019 07:32:09 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8QBW1d1026527; Thu, 26 Sep 2019 06:32:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569497521; bh=88Xv9IRV7+oNSxAgr2jq3XB2+SHFQvDvj39xR9Z58mQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eyZNqkD+oH2zsbe88+Ktakn1JXraKUrcBJUMmBPftF8+Ry1V36N0LmBeo8NhyMzsr NsqdZJ9Cbl3tcy85cp1uGVuJ5vkqfLZ4abIP2F+abI4YsOJ0NPn4skrL4ro/kBCybP VFuPC3aepTsuTunrzfK/bKrjRW8jkJwx7chGJ4Pc= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8QBW1NA032455 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 26 Sep 2019 06:32:01 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 26 Sep 2019 06:32:01 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 26 Sep 2019 06:31:54 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBUTkE069017; Thu, 26 Sep 2019 06:31:57 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jonathan Corbet , Rob Herring , Jon Mason , Dave Jiang , Allen Hubbe , Lorenzo Pieralisi CC: Mark Rutland , , , , , , Subject: [RFC PATCH 21/21] NTB: tool: Enable the NTB/PCIe link on the local or remote side of bridge Date: Thu, 26 Sep 2019 16:59:33 +0530 Message-ID: <20190926112933.8922-22-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190926112933.8922-1-kishon@ti.com> References: <20190926112933.8922-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Invoke ntb_link_enable() to enable the NTB/PCIe link on the local or remote side of the bridge. Signed-off-by: Kishon Vijay Abraham I --- drivers/ntb/test/ntb_tool.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/drivers/ntb/test/ntb_tool.c b/drivers/ntb/test/ntb_tool.c index d592c0ffbd19..04138e6a371b 100644 --- a/drivers/ntb/test/ntb_tool.c +++ b/drivers/ntb/test/ntb_tool.c @@ -1638,6 +1638,7 @@ static int tool_probe(struct ntb_client *self, struct ntb_dev *ntb) tool_setup_dbgfs(tc); + ntb_link_enable(ntb, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); return 0; err_clear_mws: