From patchwork Thu Sep 26 11:29:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174459 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1919664ill; Thu, 26 Sep 2019 04:30:49 -0700 (PDT) X-Google-Smtp-Source: APXvYqwwAu+zWo405xOKNUhZZbMy0vTA3IuOp5URYdJ08I66bJOtx0/l4aoYwlOhyRbDng+USeCp X-Received: by 2002:a50:eb41:: with SMTP id z1mr2975943edp.261.1569497449521; Thu, 26 Sep 2019 04:30:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569497449; cv=none; d=google.com; s=arc-20160816; b=ypyJE5w/CDVPxYd5lYltvOPYf1+OWFHTcxyjHNlUMAy01dgVZF5HJJ8S2/fs74d0HK 1HkRlF4Ueh1RkEng2Fmz0/kal+faP9OyF8FdcIC8Xn24tSqXbDjQ5VeEbJMETayQed6+ HkM5zUVKBIB2GEMtBY9w6w49xA1tOjSamzkEB9s5k7nwIQ5Jf9HGBnd5Un6be3RUZxQJ /S40Oy6zPJ0iQMInaiGgYcjO7PIFFH4fP+Th4EdWVWf2OS2aOJByPLbv3PZwtxAvsvi4 j8xW9NsM5sfhv3Vbc5DYFTGxstFGCVpAvdTmGC3n5iaqZZ0tzdvqWYKYZ/EdJRuwdyTb fazw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=x66YoPfkVrSslDYTR1it1VZ0fOMT2dXKRxNtTuO8skc=; b=pdrR5nVj1eekNPOfNrE6cPTdl+iih2VJPbW8GRrqhOuSu/7ksAARQrWH6yvfqaKfii ELDuqWsHGCtxoX54r2w3QqU6uidbzDodeXFVP6fv8onmCGv18D1vZuG5XG3fdFFfbgkQ JGJTWDp8e3h0bZjJ2Jts0Z3+Mb1lF1IX+wJmQb6aTUKBbNgV0ctQhnEhcN3HHJWTURuS NbIkZlEF28z4rUmBxZ1MZplFrVn1WVi5HgkxHzXHF/82JIatOhct55H63hOwT/pxJdQx Qbr2+jQSXscZ2S67NGCupgpZjySBoNgeybFA/D6LCUdJYB9XtgjBkDJvAFC3sxPlRXNz jQTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TmjtRAWb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w12si1148913edx.223.2019.09.26.04.30.49; Thu, 26 Sep 2019 04:30:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TmjtRAWb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726191AbfIZLas (ORCPT + 26 others); Thu, 26 Sep 2019 07:30:48 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:57100 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725554AbfIZLaq (ORCPT ); Thu, 26 Sep 2019 07:30:46 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8QBUcr9026304; Thu, 26 Sep 2019 06:30:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569497438; bh=x66YoPfkVrSslDYTR1it1VZ0fOMT2dXKRxNtTuO8skc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TmjtRAWbIZKJfVZ26xthEV/qMcEchITjWlq+rtNw//czY8az0TSdTWyfakfAgprvy 6+uywSjIeSNxuOlsf11Anmw5+bQMyL21Nmqtc+WAJ6w2Dn2O4QL57T2qNX9gmDcTL7 sSN7h3HQu8Ly4IT83pwr0Q7gmtkGVsPrBQHHeB38= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8QBUcWY049632 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 26 Sep 2019 06:30:38 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 26 Sep 2019 06:30:38 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 26 Sep 2019 06:30:31 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBUTjs069017; Thu, 26 Sep 2019 06:30:34 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jonathan Corbet , Rob Herring , Jon Mason , Dave Jiang , Allen Hubbe , Lorenzo Pieralisi CC: Mark Rutland , , , , , , Subject: [RFC PATCH 01/21] dt-bindings: PCI: Endpoint: Add DT bindings for PCI EPF Bus Date: Thu, 26 Sep 2019 16:59:13 +0530 Message-ID: <20190926112933.8922-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190926112933.8922-1-kishon@ti.com> References: <20190926112933.8922-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add device tree bindings for PCI endpoint function bus to which endpoint function devices should be attached. Signed-off-by: Kishon Vijay Abraham I --- .../bindings/pci/endpoint/pci-epf-bus.txt | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/endpoint/pci-epf-bus.txt -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/endpoint/pci-epf-bus.txt b/Documentation/devicetree/bindings/pci/endpoint/pci-epf-bus.txt new file mode 100644 index 000000000000..16727ddf01f5 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/endpoint/pci-epf-bus.txt @@ -0,0 +1,27 @@ +PCI Endpoint Function Bus + +This describes the bindings for endpoint function bus to which endpoint +function devices should be attached. + +Required Properties: + - compatible: Should be "pci-epf-bus" + +One or more subnodes representing PCIe endpoint function device exposed +to the remote host. + +Example: +Following is an example of NTB device exposed to the remote host. + +epf_bus { + compatible = "pci-epf-bus"; + + ntb { + compatible = "pci-epf-ntb"; + epcs = <&pcie0_ep>, <&pcie1_ep>; + epc-names = "primary", "secondary"; + vendor-id = /bits/ 16 <0x104c>; + device-id = /bits/ 16 <0xb00d>; + num-mws = <4>; + mws-size = <0x100000>, <0x100000>, <0x100000>, <0x100000>; + }; +}; From patchwork Thu Sep 26 11:29:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174460 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1919809ill; Thu, 26 Sep 2019 04:30:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqzEXAOIWubXN2pbupa0Ejqw05dAN4sB42w8qyjPdEqRrxPg+5Ci1Dw72z3PjxFNL/OgRjag X-Received: by 2002:a50:fa9a:: with SMTP id w26mr2964154edr.227.1569497456731; Thu, 26 Sep 2019 04:30:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569497456; cv=none; d=google.com; s=arc-20160816; b=OJv0Pn77Dvq27hij6g6lf9hS3XfcCa0e2vc+18RcpdULaYpm50jraV8Q+UawiJ2w0L 0S0ztqxBRUKvUBO/Bv2l1Rr5bJY4lt4k+KaJd+Wc+exm/vpg3EhU0eNP1wxbj0SrU4p9 StIQ4QBthRPLsqxV9OEZ7osMs2Pi9EBQJEi1NWsTY0R22YHYvo8Q0QKI42YrRKmFUZ0d 7TpMFNeKSYh2gyd4mqZ++Z73x1U39PyVvuoGzO80U/MJU+FN8u7HdnP8EZekpb0nUb4z En6GMO6he04n35Vs+P8H/ngaogielLnHNrE3vhTarwk+LaUoE8htpzCHdgNi02GzEqD/ 6gjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=w4V1m2OIe5LxeaAVTxkVjAlE3hYEXz8xzCprrL6Lk3E=; b=rtQWGq5qs2wUIop2p21NL27CYD0lMkgw9xyMZjrAh2e1kJ8yhmzne5CBay7ee4i/4a iR0LPRZP7a/rxZKOkLWNZ3hhh3dQqouh9Uy4c0FjxOPhFKGRETbtkeXXXTYgkp8rDsAd 3IvNwR5NcaU8qgCKYDMZTtpyJZeFo0Fk2DGLpBflSFhO+RUlagF3iWNDi8UDuMT5Nfnj mrcjM7PhSGSxJDKwPC2MGuHh2DibG09C0L3BfFBAzf+Hi6YMpqZnwxN5mlOenImKz15j +zsdYEhqfr+LuSLD4/pbAPJcgnnrmGB/TcsBvz9hmf7L0Wpsp/5DH2vyL3+xmg9EBYtm 7zVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Uf7JmbNG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The nodes for PCI endpoint function device should be attached to PCI endpoint function bus. Signed-off-by: Kishon Vijay Abraham I --- .../bindings/pci/endpoint/pci-epf.txt | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/endpoint/pci-epf.txt -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/endpoint/pci-epf.txt b/Documentation/devicetree/bindings/pci/endpoint/pci-epf.txt new file mode 100644 index 000000000000..f006395fd526 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/endpoint/pci-epf.txt @@ -0,0 +1,28 @@ +PCI Endpoint Function Device + +This describes the generic bindings to be used when a device has to be +exposed to the remote host over PCIe. The device could be an actual +peripheral in the platform or a virtual device created by the software. + +epcs : phandle to the endpoint controller device +epc-names : the names of the endpoint controller device corresponding + to the EPCs present in the *epcs* phandle +vendor-id: used to identify device manufacturer +device-id: used to identify a particular device +baseclass-code: used to classify the type of function the device performs +subclass-code: used to identify more specifically the function of the device +subsys-vendor-id: used to identify vendor of the add-in card or subsystem +subsys-id: used to specify an id that is specific to a vendor + +Example: +Following is an example of NTB device exposed to the remote host. + +ntb { + compatible = "pci-epf-ntb"; + epcs = <&pcie0_ep>, <&pcie1_ep>; + epc-names = "primary", "secondary"; + vendor-id = /bits/ 16 <0x104c>; + device-id = /bits/ 16 <0xb00d>; + num-mws = <4>; + mws-size = <0x100000>, <0x100000>, <0x100000>, <0x100000>; +}; From patchwork Thu Sep 26 11:29:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174463 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1920022ill; Thu, 26 Sep 2019 04:31:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqwkNWTiIDyKD67BUT5ZXMqgy6r9hE7RkH2cow6nwswSS/amwLEPyrUkPUkuIS2OmVHKbTYI X-Received: by 2002:a50:93a4:: with SMTP id o33mr3123787eda.0.1569497466290; Thu, 26 Sep 2019 04:31:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569497466; cv=none; d=google.com; s=arc-20160816; b=AWYT113G8Ck5e4UpPRaNndjSrudrJMBRPIqu0tV5SSpEnQcmEFi26+tLIhiNmd/IeV nWDxMg2gxq4h9prAfe4xOJVQJrbVp5tqUdRbUIVQbqn7TBQiSjKYs744HNpibGYE0d3Y Sr7X6dYu8D3EI8IC6VpWs7AdFt1ACRYmkOv0Lrp/jECFNtBhc70bklLUYeXbOrV6g2m8 RkMiT1tfnEOv/+E0IiwxLP11dQ17Ti/fbjlDaUuWw8nn5KM/6AiUllkvKIn5MbNdLBbg sXvmmPVjN4QVAPVJNaDs55eWo9fWX9tVtiVEvbq/+ODbymAg23zy2IBHo44kVCo2dfZT wzcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=4zHnlcPjrtmbIQZ9Yub799bUIN/qndEfK5n4s1oKXSI=; b=rbuWMcXxx1rxxf2typrMIcLMMM7ChjPvzW7E0w720y5O/f2/fcERWWsL5Iw388eEjB 1Nf97B565397f7NBoAcp+hvdYFAyY4Ov2PF+Cis4GA/3LMOoyISb4o/MZx8S1zMi9BUJ n8oRFSn1WmEl5QdLk8Rrt+DDFUEP6Bws9/OsxiC6TMcVCq3jpAc5euvS9UEc6Eektd95 vpCuiC7hNVuzKg0kC7DkyQyGt/EzsQjG459pI7YsiPe8AYkHxU76hKjkhkbXb8eowRn1 QLXIckLKpE/f/jDPzulsv7dVA3KhpfDCjGQ/Nuzwkmnk3LwfI58i+dFz7VaC9206tVIk MUoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=OXXAw2TF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This is added in preparation to define an endpoint function from device tree. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-epc-core.c | 61 +++++++++++++++++++++++++++++ include/linux/pci-epc.h | 4 +- 2 files changed, 64 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 5bc094093a47..0c2fdd39090c 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -83,6 +83,66 @@ struct pci_epc *pci_epc_get(const char *epc_name) } EXPORT_SYMBOL_GPL(pci_epc_get); +/** + * of_pci_epc_get() - get PCI endpoint controller from device node and index + * @node: device node which contains the phandle to endpoint controller + * @index: index of the endpoint controller in "epcs" property + * + * Returns the EPC corresponding to the _index_ entry in "epcs" property + * present in device node, after getting a refcount to it or -ENODEV if + * there is no such EPC or -EPROBE_DEFER if there is a phandle to the phy, + * but the device is not yet loaded. + */ +struct pci_epc *of_pci_epc_get(struct device_node *node, int index) +{ + struct device_node *epc_node; + struct class_dev_iter iter; + struct pci_epc *epc; + struct device *dev; + + epc_node = of_parse_phandle(node, "epcs", index); + if (!epc_node) + return ERR_PTR(-ENODEV); + + class_dev_iter_init(&iter, pci_epc_class, NULL, NULL); + while ((dev = class_dev_iter_next(&iter))) { + epc = to_pci_epc(dev); + if (epc_node != epc->dev.of_node) + continue; + + of_node_put(epc_node); + class_dev_iter_exit(&iter); + get_device(&epc->dev); + return epc; + } + + of_node_put(node); + class_dev_iter_exit(&iter); + return ERR_PTR(-EPROBE_DEFER); +} +EXPORT_SYMBOL_GPL(of_pci_epc_get); + +/** + * of_pci_epc_get_by_name() - get PCI endpoint controller from device node + * and string + * @node: device node which contains the phandle to endpoint controller + * @epc_name: name of endpoint controller as present in "epc-names" property + * + * Returns the EPC corresponding to the epc_name in "epc-names" property + * present in device node. + */ +struct pci_epc *of_pci_epc_get_by_name(struct device_node *node, + const char *epc_name) +{ + int index = 0; + + if (epc_name) + index = of_property_match_string(node, "epc-names", epc_name); + + return of_pci_epc_get(node, index); +} +EXPORT_SYMBOL_GPL(of_pci_epc_get_by_name); + /** * pci_epc_get_first_free_bar() - helper to get first unreserved BAR * @epc_features: pci_epc_features structure that holds the reserved bar bitmap @@ -661,6 +721,7 @@ __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, device_initialize(&epc->dev); epc->dev.class = pci_epc_class; epc->dev.parent = dev; + epc->dev.of_node = dev->of_node; epc->ops = ops; ret = dev_set_name(&epc->dev, "%s", dev_name(dev)); diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 0fff52675a6b..ef6531af6ed2 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -202,7 +202,9 @@ unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features); struct pci_epc *pci_epc_get(const char *epc_name); void pci_epc_put(struct pci_epc *epc); - +struct pci_epc *of_pci_epc_get(struct device_node *node, int index); +struct pci_epc *of_pci_epc_get_by_name(struct device_node *node, + const char *epc_name); int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_addr, size_t size, size_t page_size); void pci_epc_mem_exit(struct pci_epc *epc); From patchwork Thu Sep 26 11:29:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174464 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1920196ill; Thu, 26 Sep 2019 04:31:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqxtHJ2y+qxSnsfg9cOzWchcb5ouG8FsKsXceeauTzjWNWWQzkRrdjl7Co8O++E0f4mSDf+g X-Received: by 2002:a17:906:e251:: with SMTP id gq17mr2576302ejb.85.1569497474903; Thu, 26 Sep 2019 04:31:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569497474; cv=none; d=google.com; s=arc-20160816; b=BskflnqXlPmcQypqx5GW7Wl06PE+Qxjm/9yWfhgsbsHQQs43pt0/cNB99VRL56BLxB Z9WPpGr7zcnu8adTbJjIC2iEwXzR69+vMaY/EqmABgIjxgWqwOiOJKQSKiX8wCdhU0xX 3VQLkA3DPlnmk/fcnyqnVvjlNtl4c4eJs4L274FvGFEX4GvoQKtSSJXhnVZy1IhJXiPh DBKOILxyCBXqa0FpNeWR27rXR0WwivDGgE5xD0oz2rRLg0bsPSKuLNKgqtGwmKO2PaJB Yt2yt/Y83H3Y0aL6jIXPzXOJOAjBaLpZj8GOAqfXGn88kJRyts2pyyFnHS4l7jVZ4NtO u3iQ== ARC-Message-Signature: i=1; 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This is added in order to define an endpoint function completely from device tree. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-epf-core.c | 68 +++++++++++++++++++++++++++++ include/linux/pci-epf.h | 6 +++ 2 files changed, 74 insertions(+) -- 2.17.1 diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c index 16feff8cad50..c74c7cc6d8bd 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -529,6 +529,73 @@ struct pci_epf *pci_epf_create(const char *name) } EXPORT_SYMBOL_GPL(pci_epf_create); +/** + * pci_epf_of_create() - create a new PCI EPF device from device tree node + * @node: the device node of the PCI EPF device. + * + * Invoke to create a new PCI EPF device by providing a device tree node + * with compatible property. + */ +struct pci_epf *pci_epf_of_create(struct device_node *node) +{ + struct pci_epf *epf; + const char *compat; + int ret; + + of_node_get(node); + + ret = of_property_read_string(node, "compatible", &compat); + if (ret) { + of_node_put(node); + return ERR_PTR(ret); + } + + epf = pci_epf_create(compat); + if (!IS_ERR(epf)) + epf->node = node; + + return epf; +} +EXPORT_SYMBOL_GPL(pci_epf_of_create); + +static void devm_epf_release(struct device *dev, void *res) +{ + struct pci_epf *epf = *(struct pci_epf **)res; + + pci_epf_destroy(epf); +} + +/** + * devm_pci_epf_of_create() - create a new PCI EPF device from device tree node + * @dev: device that is creating the new EPF + * @node: the device node of the PCI EPF device. + * + * Invoke to create a new PCI EPF device by providing a device tree node with + * compatible property. While at that, it also associates the device with the + * EPF using devres. On driver detach, release function is invoked on the devres + * data, where devres data is freed. + */ +struct pci_epf *devm_pci_epf_of_create(struct device *dev, + struct device_node *node) +{ + struct pci_epf **ptr, *epf; + + ptr = devres_alloc(devm_epf_release, sizeof(*ptr), GFP_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + epf = pci_epf_of_create(node); + if (!IS_ERR(epf)) { + *ptr = epf; + devres_add(dev, ptr); + } else { + devres_free(ptr); + } + + return epf; +} +EXPORT_SYMBOL_GPL(devm_pci_epf_of_create); + const struct pci_epf_device_id * pci_epf_match_device(const struct pci_epf_device_id *id, struct pci_epf *epf) { @@ -549,6 +616,7 @@ static void pci_epf_dev_release(struct device *dev) { struct pci_epf *epf = to_pci_epf(dev); + of_node_put(epf->node); kfree(epf->name); kfree(epf); } diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index 02090eb41563..7e997fb656fb 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -11,6 +11,7 @@ #include #include +#include #include struct pci_epf; @@ -101,6 +102,7 @@ struct pci_epf_bar { /** * struct pci_epf - represents the PCI EPF device * @dev: the PCI EPF device + * @node: the device tree node of the PCI EPF device * @name: the name of the PCI EPF device * @header: represents standard configuration header * @bar: represents the BAR of EPF device @@ -125,6 +127,7 @@ struct pci_epf_bar { */ struct pci_epf { struct device dev; + struct device_node *node; const char *name; struct pci_epf_header *header; struct pci_epf_bar bar[6]; @@ -167,6 +170,9 @@ static inline void *epf_get_drvdata(struct pci_epf *epf) const struct pci_epf_device_id * pci_epf_match_device(const struct pci_epf_device_id *id, struct pci_epf *epf); struct pci_epf *pci_epf_create(const char *name); +struct pci_epf *pci_epf_of_create(struct device_node *node); +struct pci_epf *devm_pci_epf_of_create(struct device *dev, + struct device_node *node); void pci_epf_destroy(struct pci_epf *epf); int __pci_epf_register_driver(struct pci_epf_driver *driver, struct module *owner); From patchwork Thu Sep 26 11:29:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174466 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1920319ill; Thu, 26 Sep 2019 04:31:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqxk5/XJvkf08+FGw7cwh/mZZ6lK+euYftdbC5JiUvDGQR8pL3+J3CQ7oYCkNDt+uzc6w11o X-Received: by 2002:a17:906:7798:: with SMTP id s24mr2606480ejm.211.1569497480503; Thu, 26 Sep 2019 04:31:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569497480; cv=none; d=google.com; s=arc-20160816; b=apv7qYG4tWLA3yNsEEaro66N/tpNu+ulAFJBxPragd4+RbaQeYUZCzrLYfj+Wio4nd t/YBsQmdtWVIqkfstW/rZ67+HLzGjoU4RH3p0w0zwYPU+ZQRlNffUu3ARWIXVtJyaOEv zh6XpaGrU/g4FkiS1sgUplABLdOXOkrOuQIu+a+H43mBPSfMnvE+1wicX6O7xjnFUofm jXlYpuAjCLdzpeet/o5/5YnqUrWRQ+pty+rjCIrYXFjcuy1Z6VFS013E8SZYyxS2oSto LZA8gqV/S8cU+wjlPLl4sKHkbr8rVyOwyIAcC6BQq9f5vTFwoQIL1M88cyr6tnDGqpwQ Kd/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=1Pg02YjtJWenOS8TSc+kZXfjbcewS60naZ8ogDPEpQ0=; b=rQx2troIEILx4lOtLGxXWv1Tg8N4HF7Ql2SdYHmbn6/Sn434y9bHDTZHOPTn0I/+wF 76xQVufcSej1KHPQilidRZHgkCPp4Qc17EPNqNwPjElZWAoKPE/c9dn+diNTYaJCRgIr xW3yKUxUNEdjIf+pHfPOZTGajdKlFtFJI7QRzHA2wnQAJZQ/ipVLqFvig2h9LIkFyKk/ WFfZlJL7TP4P+GorukafN8pjBA34phfbpepiSnVS+2ebnUE0r+7FIx5SyWiQ4psls5vc 3TymqU+Kb3LO98BTnHLopxp1oYHqH9NxHauU+24CkuNLfGePP9hMvp9cvurfOC/pQeIA tTHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=oJoWYIr7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q10si1135490eda.293.2019.09.26.04.31.20; Thu, 26 Sep 2019 04:31:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=oJoWYIr7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726515AbfIZLbT (ORCPT + 26 others); Thu, 26 Sep 2019 07:31:19 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:57180 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726435AbfIZLbQ (ORCPT ); Thu, 26 Sep 2019 07:31:16 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8QBV7V5026389; Thu, 26 Sep 2019 06:31:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569497467; bh=1Pg02YjtJWenOS8TSc+kZXfjbcewS60naZ8ogDPEpQ0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oJoWYIr7EsDX2IEqmzdUO07/fyqW/bTeExyro+qKR3oV9FgpHXuNnBT1HRnq9vv3m GUNHuTI5N98HjIZvjbO2c2fAgHYBiPDNsza3/tzRMfH6ch6+JQmvUpr03KIrsj/arT RFtsW2mTTMr+24QZb2QClokOA/91cAhcvRViDiRk= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8QBV7st050327 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 26 Sep 2019 06:31:07 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 26 Sep 2019 06:31:00 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 26 Sep 2019 06:30:59 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBUTk1069017; Thu, 26 Sep 2019 06:31:03 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jonathan Corbet , Rob Herring , Jon Mason , Dave Jiang , Allen Hubbe , Lorenzo Pieralisi CC: Mark Rutland , , , , , , Subject: [RFC PATCH 08/21] PCI: endpoint: Make *_get_first_free_bar() take into account 64 bit BAR Date: Thu, 26 Sep 2019 16:59:20 +0530 Message-ID: <20190926112933.8922-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190926112933.8922-1-kishon@ti.com> References: <20190926112933.8922-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org pci_epc_get_first_free_bar() uses only "reserved_bar" member in epc_features to get the first unreserved BAR. However if the reserved BAR is also a 64-bit BAR, then the next BAR shouldn't be returned (since 64-bit BAR uses two BARs). Make pci_epc_get_first_free_bar() take into account 64 bit BAR while returning the first free unreserved BAR. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-epc-core.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 0c2fdd39090c..7eae7dcaebf9 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -153,12 +153,20 @@ EXPORT_SYMBOL_GPL(of_pci_epc_get_by_name); unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features) { - int free_bar; + unsigned long free_bar; if (!epc_features) return 0; - free_bar = ffz(epc_features->reserved_bar); + /* Find if the reserved BAR is also a 64-bit BAR */ + free_bar = epc_features->reserved_bar & epc_features->bar_fixed_64bit; + + /* Set the adjacent bit if the reserved BAR is also a 64-bit BAR */ + free_bar <<= 1; + free_bar |= epc_features->reserved_bar; + + /* Now find the free BAR */ + free_bar = ffz(free_bar); if (free_bar > 5) return 0; From patchwork Thu Sep 26 11:29:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174469 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1920540ill; Thu, 26 Sep 2019 04:31:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqwmc29wkJQ+HUOhnXUphU670ba1fQfWzxrNk47Buu7T9L4tmOoElFlp1RIyRUVHWXjamagx X-Received: by 2002:a17:906:d97a:: with SMTP id rp26mr2604576ejb.251.1569497491516; Thu, 26 Sep 2019 04:31:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569497491; cv=none; d=google.com; s=arc-20160816; b=LSwNWstsmm8RSFVHWmepazquLQf+WvkEIn0apgZrD74QSCdJE9pe8YFdrvKiRlBDrp IA+CBLm8F8mymj/YGMBSxqAhBIqJlu+MH0oYhWd9Zas2Ef0qG0oqNa56ihza/t4IWMEY xZ61JQLl2RDDlCKyCbfuJJvz2bPlSFJR/Nnihvmp1qp8mDYPn0cMhHuQ159Q0WI/96uN jn5I34OF08htB5wJo3ED5q2OWz1h/RgVIkJP6bzRLSt3auGIMvA0DY48ep7XMqslPiag 8sfvntjz4MSjEtJTZOQ8h+2DnuIfTJMGBgLZ69jc64GZMgSqomtVS5A+BP7tmrE7Vfop ZPKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=5g6TwgnGUlfofXhn+QvD8y+MT6lDfC7QwOU9sIuCmvU=; b=XZbZna1pfnxsER5ZSIdaS7OwEQBm9M6JJj5PRfEeqogAHTT3EiuTBFEtuZ6ZUDPhbt TutOn/r+pusEhO4quHtAFdoF0Y5+4uNOQIKShMoaUNkBDejPXCf6JYgY9chSCmSzT+T/ DVGugj/KJpCpiQseILk8JleQ6Sl9VTdcvaukFZmFbQ3bl/NgLquN8w+wHuTSGvDUWevY /gayphxg4ARSEBNz2gnPpzJbqCxlif1mKgwI/dhrka/JfV1Kc6Mm0ViNi5jk3Oi1UhCA RxA3GQhhyz0h8y9QmaZCwv2OSFwsdk8YA4CLrpBZ9DX6B3/+5k5cP+LMoDqJ0LGk0/3b scYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=EKRJWt69; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l23si1083784eds.310.2019.09.26.04.31.31; Thu, 26 Sep 2019 04:31:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=EKRJWt69; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726619AbfIZLba (ORCPT + 26 others); Thu, 26 Sep 2019 07:31:30 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:52970 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726573AbfIZLb1 (ORCPT ); Thu, 26 Sep 2019 07:31:27 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8QBVKGg016189; Thu, 26 Sep 2019 06:31:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569497480; bh=5g6TwgnGUlfofXhn+QvD8y+MT6lDfC7QwOU9sIuCmvU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EKRJWt69th/MO9ynM8MWbD0RpM+vv+pbGpzNW/t2BbTlgvntevwY28WOnN0R7ex8a a5wDsuZXuiwtzpMZ8CC5I8iCPB82iH7dxOEqoZ3LIceK1RCgiYfJZInqAwJz1AYA96 q9/IMij7CgtySeLwZK/EbKAHKsd3xn40AnOesDYU= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8QBVK37031817 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 26 Sep 2019 06:31:20 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 26 Sep 2019 06:31:12 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 26 Sep 2019 06:31:12 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBUTk4069017; Thu, 26 Sep 2019 06:31:16 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jonathan Corbet , Rob Herring , Jon Mason , Dave Jiang , Allen Hubbe , Lorenzo Pieralisi CC: Mark Rutland , , , , , , Subject: [RFC PATCH 11/21] PCI: endpoint: Add helper API to populate header with values from DT Date: Thu, 26 Sep 2019 16:59:23 +0530 Message-ID: <20190926112933.8922-12-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190926112933.8922-1-kishon@ti.com> References: <20190926112933.8922-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add helper API pci_epc_of_parse_header() to populate header with values from device tree. These values will be written to the configuration space header in the endpoint controller. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-epc-core.c | 23 +++++++++++++++++++++++ include/linux/pci-epc.h | 2 ++ 2 files changed, 25 insertions(+) -- 2.17.1 diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 49bdff217777..98acadbfc934 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -31,6 +31,29 @@ static int devm_pci_epc_match(struct device *dev, void *res, void *match_data) return *epc == match_data; } +/** + * pci_epc_of_parse_header() - parse the device tree to get PCI config space + * header + * @node: The device tree node (of endpoint function) which has the PCI config + * space header values + * @header: standard configuration space header fields that has to be populated + * + * Invoke to populate *header* with the PCI configuration space values populated + * in device tree. + */ +void pci_epc_of_parse_header(struct device_node *node, + struct pci_epf_header *header) +{ + of_property_read_u16(node, "vendor-id", &header->vendorid); + of_property_read_u16(node, "device-id", &header->deviceid); + of_property_read_u8(node, "baseclass-code", &header->baseclass_code); + of_property_read_u8(node, "subclass-code", &header->subclass_code); + of_property_read_u16(node, "subsys-vendor-id", + &header->subsys_vendor_id); + of_property_read_u16(node, "subsys-id", &header->subsys_id); +} +EXPORT_SYMBOL_GPL(pci_epc_of_parse_header); + /** * pci_epc_put() - release the PCI endpoint controller * @epc: epc returned by pci_epc_get() diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 993b1a55a239..18fff589a881 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -196,6 +196,8 @@ int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no, enum pci_epc_irq_type type, u16 interrupt_num); int pci_epc_start(struct pci_epc *epc); void pci_epc_stop(struct pci_epc *epc); +void pci_epc_of_parse_header(struct device_node *node, + struct pci_epf_header *header); const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no); unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features From patchwork Thu Sep 26 11:29:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174470 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1920669ill; Thu, 26 Sep 2019 04:31:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqy/GMp34aytAQaKUcL6/GTjqKGqlgnAOSKRtQzy8SEsxjXFnWuiZv94Nw+/LnXK3RX0569h X-Received: by 2002:aa7:d883:: with SMTP id u3mr2924255edq.281.1569497497272; Thu, 26 Sep 2019 04:31:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569497497; cv=none; d=google.com; s=arc-20160816; b=kZHoqTVjvHuRR8BGL9sWOK8N7PxGAvXIdq03YlVLwcvQx6SuDPrAC8HFX1IZRy3cg/ jlJ3ylAb+Y7QP+weFq7k0zQHNVPvQfu4CvgqOHTvkGORwFibVPF+dYd+zA2bzrk+6DDg lldqbgpu18w5uUyCJZ8/Ev6iZAoFTq6OQfwf7ORcXip3VTIycQf9/wZPH0S9NBVPizDl 0JY+zA7ISkG8wj8CJCpAIUz2o2aybZF8qovAhpH1qg8/Wnkx4Qsk0B9o7MlHlFMb8hvH 3JdIQujKwlNskpP+b2gic1C71Nw09oCGR4Dy/8X60KAOUoYCJp/sp1LacOZrOXK2Fxzv j8Ig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=3sdI1gAKkc5Zac7j8y4aRg9vrN5qKf7YsqkqweAnmQM=; b=lSGHVM80s4XjdoK2ZTS/fC32yeuKquYGt49z3NCaEF7RoyuUna3YQgfzQD3BYtoP7f wkM5zJoEpBgxH15Qp+FSajFjUCn26Xg2OcSNc2+KGKj9cuo7Vs5q/tt3TeFuYlVO78bC ZGB0w7A+MM4bNTtyJ4tHE5Sqh+kYbw9hFLgPCrvWQZ/ehh9ZUnKWOE7znYlkkYWpJSmQ lH7SNBtVF+N5q2jQ4xev+HGUXzhexNdAkXWWypWlFbJInO7jJwEdZEG2+76zMVxe0u6R 6uEFA+NOeDcGZnxha8GWiGLk37jaOuTxN6Q0upSvgbpdH6hcloZIinmdA/QBbFeeJly7 s6OQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=u+cVJyl7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l23si1083784eds.310.2019.09.26.04.31.36; Thu, 26 Sep 2019 04:31:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=u+cVJyl7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726683AbfIZLbg (ORCPT + 26 others); Thu, 26 Sep 2019 07:31:36 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:51066 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726640AbfIZLbc (ORCPT ); Thu, 26 Sep 2019 07:31:32 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8QBVOkN042534; Thu, 26 Sep 2019 06:31:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569497484; bh=3sdI1gAKkc5Zac7j8y4aRg9vrN5qKf7YsqkqweAnmQM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=u+cVJyl7xka0SanQOnwhwvIDuazIuFVAe/2Ba2iFqH8LzplC9KU51VP5ZqYqSH3Un JAOmTiyO5Y6DAUj7+MlOQSIfRLUkqOTh2FqokY72qtRjGrwU6wVGZEWA5WhVX+C+QR sV9qGfYN5pwRqc2ykzd0dbn7hxQaYhR2VJeCXx4Y= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8QBVOKm031869 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 26 Sep 2019 06:31:24 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 26 Sep 2019 06:31:24 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 26 Sep 2019 06:31:24 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBUTk5069017; Thu, 26 Sep 2019 06:31:20 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jonathan Corbet , Rob Herring , Jon Mason , Dave Jiang , Allen Hubbe , Lorenzo Pieralisi CC: Mark Rutland , , , , , , Subject: [RFC PATCH 12/21] PCI: endpoint: Add support to associate secondary EPC with EPF Date: Thu, 26 Sep 2019 16:59:24 +0530 Message-ID: <20190926112933.8922-13-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190926112933.8922-1-kishon@ti.com> References: <20190926112933.8922-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In the case of standard endpoint functions, only one endpoint controller (EPC) will be associated with an endpoint function (EPF). However for providing NTB (non transparent bridge) functionality, two EPCs should be associated with a single EPF. Add support to associate secondary EPC with EPF. This is in preparation for adding NTB endpoint function driver. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/functions/pci-epf-test.c | 12 +++-- drivers/pci/endpoint/pci-ep-cfs.c | 6 +-- drivers/pci/endpoint/pci-epc-core.c | 47 ++++++++++++---- drivers/pci/endpoint/pci-epf-core.c | 53 ++++++++++++++----- include/linux/pci-epc.h | 24 ++++++++- include/linux/pci-epf.h | 27 +++++++++- 6 files changed, 135 insertions(+), 34 deletions(-) -- 2.17.1 diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index 608545aaf7c8..c7003c2dbbb2 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -484,7 +484,8 @@ static void pci_epf_test_unbind(struct pci_epf *epf) epf_bar = &epf->bar[bar]; if (epf_test->reg[bar]) { - pci_epf_free_space(epf, epf_test->reg[bar], bar); + pci_epf_free_space(epf, epf_test->reg[bar], bar, + PRIMARY_INTERFACE); pci_epc_clear_bar(epc, epf->func_no, epf->vfunc_no, epf_bar); } @@ -514,7 +515,8 @@ static int pci_epf_test_set_bar(struct pci_epf *epf) ret = pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no, epf_bar); if (ret) { - pci_epf_free_space(epf, epf_test->reg[bar], bar); + pci_epf_free_space(epf, epf_test->reg[bar], bar, + PRIMARY_INTERFACE); dev_err(dev, "Failed to set BAR%d\n", bar); if (bar == test_reg_bar) return ret; @@ -544,7 +546,8 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf) epc_features = epf_test->epc_features; base = pci_epf_alloc_space(epf, sizeof(struct pci_epf_test_reg), - test_reg_bar, epc_features->align); + test_reg_bar, epc_features->align, + PRIMARY_INTERFACE); if (!base) { dev_err(dev, "Failed to allocated register space\n"); return -ENOMEM; @@ -560,7 +563,8 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf) continue; base = pci_epf_alloc_space(epf, bar_size[bar], bar, - epc_features->align); + epc_features->align, + PRIMARY_INTERFACE); if (!base) dev_err(dev, "Failed to allocate space for BAR%d\n", bar); diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c index c18ef626ada5..f274a5b6ee10 100644 --- a/drivers/pci/endpoint/pci-ep-cfs.c +++ b/drivers/pci/endpoint/pci-ep-cfs.c @@ -93,13 +93,13 @@ static int pci_epc_epf_link(struct config_item *epc_item, struct pci_epc *epc = epc_group->epc; struct pci_epf *epf = epf_group->epf; - ret = pci_epc_add_epf(epc, epf); + ret = pci_epc_add_epf(epc, epf, PRIMARY_INTERFACE); if (ret) return ret; ret = pci_epf_bind(epf); if (ret) { - pci_epc_remove_epf(epc, epf); + pci_epc_remove_epf(epc, epf, PRIMARY_INTERFACE); return ret; } @@ -119,7 +119,7 @@ static void pci_epc_epf_unlink(struct config_item *epc_item, epc = epc_group->epc; epf = epf_group->epf; pci_epf_unbind(epf); - pci_epc_remove_epf(epc, epf); + pci_epc_remove_epf(epc, epf, PRIMARY_INTERFACE); } static struct configfs_item_operations pci_epc_item_ops = { diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 98acadbfc934..42085fcc746d 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -634,17 +634,21 @@ EXPORT_SYMBOL_GPL(pci_epc_write_header); * pci_epc_add_epf() - bind PCI endpoint function to an endpoint controller * @epc: the EPC device to which the endpoint function should be added * @epf: the endpoint function to be added + * @type: Identifies if the EPC is connected to the primary or secondary + * interface of EPF * * A PCI endpoint device can have one or more functions. In the case of PCIe, * the specification allows up to 8 PCIe endpoint functions. Invoke * pci_epc_add_epf() to add a PCI endpoint function to an endpoint controller. */ -int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf) +int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf, + enum pci_epc_interface_type type) { + struct list_head *list; u32 func_no = 0; - if (epf->epc || epf->is_vf) - return -EBUSY; + if (epf->is_vf) + return -EINVAL; if (IS_ERR(epc)) return -EINVAL; @@ -652,6 +656,12 @@ int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf) if (epf->func_no > epc->max_functions - 1) return -EINVAL; + if (type == PRIMARY_INTERFACE && epf->epc) + return -EBUSY; + + if (type == SECONDARY_INTERFACE && epf->sec_epc) + return -EBUSY; + mutex_lock(&epc->lock); func_no = find_first_zero_bit(&epc->function_num_map, BITS_PER_LONG); @@ -659,10 +669,17 @@ int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf) return -EINVAL; set_bit(func_no, &epc->function_num_map); - epf->func_no = func_no; - epf->epc = epc; + if (type == PRIMARY_INTERFACE) { + epf->func_no = func_no; + epf->epc = epc; + list = &epf->list; + } else { + epf->sec_epc_func_no = func_no; + epf->sec_epc = epc; + list = &epf->sec_epc_list; + } - list_add_tail(&epf->list, &epc->pci_epf); + list_add_tail(list, &epc->pci_epf); mutex_unlock(&epc->lock); return 0; @@ -676,14 +693,26 @@ EXPORT_SYMBOL_GPL(pci_epc_add_epf); * * Invoke to remove PCI endpoint function from the endpoint controller. */ -void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf) +void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf, + enum pci_epc_interface_type type) { + struct list_head *list; + u32 func_no = 0; + if (!epc || IS_ERR(epc)) return; + if (type == PRIMARY_INTERFACE) { + func_no = epf->func_no; + list = &epf->list; + } else { + func_no = epf->sec_epc_func_no; + list = &epf->sec_epc_list; + } + mutex_lock(&epc->lock); - clear_bit(epf->func_no, &epc->function_num_map); - list_del(&epf->list); + clear_bit(func_no, &epc->function_num_map); + list_del(list); mutex_unlock(&epc->lock); } EXPORT_SYMBOL_GPL(pci_epc_remove_epf); diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c index 67015c66d09f..388966faf17a 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -320,23 +320,36 @@ EXPORT_SYMBOL_GPL(pci_epf_remove_vepf); * pci_epf_free_space() - free the allocated PCI EPF register space * @addr: the virtual address of the PCI EPF register space * @bar: the BAR number corresponding to the register space + * @type: Identifies if the allocated space is for primary EPC or secondary EPC * * Invoke to free the allocated PCI EPF register space. */ -void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar) +void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar, + enum pci_epc_interface_type type) { struct device *dev = epf->epc->dev.parent; + struct pci_epf_bar *epf_bar; + struct pci_epc *epc; if (!addr) return; - dma_free_coherent(dev, epf->bar[bar].size, addr, - epf->bar[bar].phys_addr); + if (type == PRIMARY_INTERFACE) { + epc = epf->epc; + epf_bar = epf->bar; + } else { + epc = epf->sec_epc; + epf_bar = epf->sec_epc_bar; + } + + dev = epc->dev.parent; + dma_free_coherent(dev, epf_bar[bar].size, addr, + epf_bar[bar].phys_addr); - epf->bar[bar].phys_addr = 0; - epf->bar[bar].size = 0; - epf->bar[bar].barno = 0; - epf->bar[bar].flags = 0; + epf_bar[bar].phys_addr = 0; + epf_bar[bar].size = 0; + epf_bar[bar].barno = 0; + epf_bar[bar].flags = 0; } EXPORT_SYMBOL_GPL(pci_epf_free_space); @@ -345,15 +358,18 @@ EXPORT_SYMBOL_GPL(pci_epf_free_space); * @size: the size of the memory that has to be allocated * @bar: the BAR number corresponding to the allocated register space * @align: alignment size for the allocation region + * @type: Identifies if the allocation is for primary EPC or secondary EPC * * Invoke to allocate memory for the PCI EPF register space. */ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, - size_t align) + size_t align, enum pci_epc_interface_type type) { - void *space; - struct device *dev = epf->epc->dev.parent; + struct pci_epf_bar *epf_bar; dma_addr_t phys_addr; + struct pci_epc *epc; + struct device *dev; + void *space; if (size < 128) size = 128; @@ -363,16 +379,25 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, else size = roundup_pow_of_two(size); + if (type == PRIMARY_INTERFACE) { + epc = epf->epc; + epf_bar = epf->bar; + } else { + epc = epf->sec_epc; + epf_bar = epf->sec_epc_bar; + } + + dev = epc->dev.parent; space = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL); if (!space) { dev_err(dev, "failed to allocate mem space\n"); return NULL; } - epf->bar[bar].phys_addr = phys_addr; - epf->bar[bar].size = size; - epf->bar[bar].barno = bar; - epf->bar[bar].flags |= upper_32_bits(size) ? + epf_bar[bar].phys_addr = phys_addr; + epf_bar[bar].size = size; + epf_bar[bar].barno = bar; + epf_bar[bar].flags |= upper_32_bits(size) ? PCI_BASE_ADDRESS_MEM_TYPE_64 : PCI_BASE_ADDRESS_MEM_TYPE_32; diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 18fff589a881..91d5cbaabc8f 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -13,6 +13,11 @@ struct pci_epc; +enum pci_epc_interface_type { + PRIMARY_INTERFACE, + SECONDARY_INTERFACE, +}; + enum pci_epc_irq_type { PCI_EPC_IRQ_UNKNOWN, PCI_EPC_IRQ_LEGACY, @@ -20,6 +25,19 @@ enum pci_epc_irq_type { PCI_EPC_IRQ_MSIX, }; +static inline const char * +pci_epc_interface_string(enum pci_epc_interface_type type) +{ + switch (type) { + case PRIMARY_INTERFACE: + return "primary"; + case SECONDARY_INTERFACE: + return "secondary"; + default: + return "UNKNOWN interface"; + } +} + /** * struct pci_epc_ops - set of function pointers for performing EPC operations * @epf_init: ops to perform EPC specific initialization @@ -172,9 +190,11 @@ __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, struct module *owner); void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc); void pci_epc_destroy(struct pci_epc *epc); -int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf); +int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf, + enum pci_epc_interface_type type); void pci_epc_linkup(struct pci_epc *epc); -void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf); +void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf, + enum pci_epc_interface_type type); int pci_epc_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_header *hdr); int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index 7e997fb656fb..b5075119f3ad 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -15,6 +15,7 @@ #include struct pci_epf; +enum pci_epc_interface_type; enum pci_barno { BAR_0, @@ -124,6 +125,18 @@ struct pci_epf_bar { * @is_vf: true - virtual function, false - physical function * @vfunction_num_map: bitmap to manage virtual function number * @pci_vepf: list of virtual endpoint function associated with this function + * @sec_epc: the secondary EPC device to which this EPF device is bound + * @sec_epc_list: to add pci_epf as list of PCI endpoint functions to secondary + * EPC device + * @sec_epc_bar: represents the BAR of EPF device associated with secondary EPC + * @sec_epc_func_no: unique (physical) function number within the secondary EPC + * @sec_epc_vfunc_no: unique virtual function number within a physical function + * associated with secondary EPC + * @sec_epc_vfunction_num_map: bitmap to manage virtual function number + * associated with the physical function of the + * secondary EPC + * @sec_epc_pci_vepf: list of virtual endpoint function associated with the + * physical function of the secondary EPC */ struct pci_epf { struct device dev; @@ -150,6 +163,15 @@ struct pci_epf { unsigned int is_vf; unsigned long vfunction_num_map; struct list_head pci_vepf; + + /* Below members are to attach secondary EPC to an endpoint function */ + struct pci_epc *sec_epc; + struct list_head sec_epc_list; + struct pci_epf_bar sec_epc_bar[6]; + u8 sec_epc_func_no; + u8 sec_epc_vfunc_no; + unsigned long sec_epc_vfunction_num_map; + struct list_head sec_epc_pci_vepf; }; #define to_pci_epf(epf_dev) container_of((epf_dev), struct pci_epf, dev) @@ -178,8 +200,9 @@ int __pci_epf_register_driver(struct pci_epf_driver *driver, struct module *owner); void pci_epf_unregister_driver(struct pci_epf_driver *driver); void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, - size_t align); -void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar); + size_t align, enum pci_epc_interface_type type); +void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar, + enum pci_epc_interface_type type); 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[209.132.180.67]) by mx.google.com with ESMTP id d1si834656ejt.354.2019.09.26.04.31.44; Thu, 26 Sep 2019 04:31:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=uIgiau8g; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726766AbfIZLbn (ORCPT + 26 others); Thu, 26 Sep 2019 07:31:43 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:51114 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726710AbfIZLbk (ORCPT ); Thu, 26 Sep 2019 07:31:40 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8QBVWSB042677; Thu, 26 Sep 2019 06:31:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569497492; bh=tbRN2tGGOS4J9as4hsMn2//ML/lFksocvN+yrl5Z71o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=uIgiau8g5GYqXIzu+IlUCpdfylbmI+bJ+SdSlpJ0mAFi31xOECUOcOwHd1L29+dVX 1ckTVu9X4hbc7KhZ1jztsJ2T2qYm7WohPF9kPlgtys6ohnhdnXzl6A1giQk5Y7MVkd 26xJ5HU+jpsMoVioUhxOG3mUJsDiltf0r8dP3WF8= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8QBVWXE032069 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 26 Sep 2019 06:31:32 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 26 Sep 2019 06:31:32 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 26 Sep 2019 06:31:32 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBUTk7069017; Thu, 26 Sep 2019 06:31:28 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jonathan Corbet , Rob Herring , Jon Mason , Dave Jiang , Allen Hubbe , Lorenzo Pieralisi CC: Mark Rutland , , , , , , Subject: [RFC PATCH 14/21] PCI: cadence: Implement ->msi_map_irq() ops Date: Thu, 26 Sep 2019 16:59:26 +0530 Message-ID: <20190926112933.8922-15-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190926112933.8922-1-kishon@ti.com> References: <20190926112933.8922-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Implement ->msi_map_irq() ops in order to map physical address to MSI address and return MSI data. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/pcie-cadence-ep.c | 59 ++++++++++++++++++++++++ 1 file changed, 59 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c index ff4b4b8eb017..5d41c892177f 100644 --- a/drivers/pci/controller/pcie-cadence-ep.c +++ b/drivers/pci/controller/pcie-cadence-ep.c @@ -517,6 +517,64 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, return 0; } +static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, + phys_addr_t addr, u8 interrupt_num, + u32 entry_size, u32 *msi_data) +{ + u32 sriov_cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; + struct cdns_pcie_ep *ep = epc_get_drvdata(epc); + u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + struct cdns_pcie *pcie = &ep->pcie; + u16 flags, mme, data, data_mask; + u32 first_vf_offset, stride; + u8 msi_count; + u64 pci_addr; + int ret; + int i; + + if (vfn > 0) { + first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, sriov_cap + + PCI_SRIOV_VF_OFFSET); + stride = cdns_pcie_ep_fn_readw(pcie, fn, sriov_cap + + PCI_SRIOV_VF_STRIDE); + fn = fn + first_vf_offset + ((vfn - 1) * stride); + } + + /* Check whether the MSI feature has been enabled by the PCI host. */ + flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + if (!(flags & PCI_MSI_FLAGS_ENABLE)) + return -EINVAL; + + /* Get the number of enabled MSIs */ + mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4; + msi_count = 1 << mme; + if (!interrupt_num || interrupt_num > msi_count) + return -EINVAL; + + /* Compute the data value to be written. */ + data_mask = msi_count - 1; + data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64); + data = data & ~data_mask; + + /* Get the PCI address where to write the data into. */ + pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI); + pci_addr <<= 32; + pci_addr |= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO); + pci_addr &= GENMASK_ULL(63, 2); + + for (i = 0; i < interrupt_num; i++) { + ret = cdns_pcie_ep_map_addr(epc, fn, vfn, addr, pci_addr, + entry_size); + if (ret) + return ret; + addr = addr + entry_size; + } + + *msi_data = data; + + return 0; +} + static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, u16 interrupt_num) { @@ -678,6 +736,7 @@ static const struct pci_epc_ops cdns_pcie_epc_ops = { .set_msix = cdns_pcie_ep_set_msix, .get_msix = cdns_pcie_ep_get_msix, .raise_irq = cdns_pcie_ep_raise_irq, + .map_msi_irq = cdns_pcie_ep_map_msi_irq, .start = cdns_pcie_ep_start, .get_features = cdns_pcie_ep_get_features, }; From patchwork Thu Sep 26 11:29:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174473 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1920891ill; Thu, 26 Sep 2019 04:31:49 -0700 (PDT) X-Google-Smtp-Source: APXvYqwaFfm+9dmbllS/EhLyTE2HWjEkyOAnDLoQ3qf9xKG2NNgQ+er16qUMwsNbgDnzKvoqcNfo X-Received: by 2002:a05:6402:696:: with SMTP id f22mr2985823edy.216.1569497509537; Thu, 26 Sep 2019 04:31:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569497509; cv=none; d=google.com; s=arc-20160816; b=qGq1HVZo6Ge9lvFxSwB65f6nb4drhcEj+IcGC4UU6qVg/O1kMlhWV2NepdaHpVQd1r ZXxMCZB/j5vXzev8pzqTxjDP9OgagbRbWkJnFN/2JAgsK5XVh27mBRcxEwCjiZNKtRBD O3MKtReELs+UXaAJhltdsymbAGMwyWZCoBwjV1RvsKkcBTHN+MgpJCg5sd7at5iGbF7L tJXrfyAJlBHzC2JsN/a3P62M3Q47Np5eXwgQ3+dCB6Fj5Ry2YT3soVoDVxE6PhLGV70q fk839JgwFU0hbJJzqVf/ik+aGfANf5UNsa1nJlm9pAXKatS/gTtT26dVEk36ctfBQnBS NQzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=zjdKeRfFg26NOLGmk6yPz1vY8BAAv5jWqap9n0vA/hI=; b=OVi4jNoy/BlaRO1LqtG7yccHCVJNluNSoUQhfkGcLCzHR0GAK6lJjwbTLlKkqYUJRY IlU7fAt7xfmVs5Brr8VZZzO85FMjMWkB4YF7ZxABWdGfmphK8/VcA+Z+jRdP3lN9w9Ao N6m1ioMzRhoOCsRsp1ogaufTHdE/gnOPZTDiDEzcEodbw3s/xtlr1TqiAoGo9MxvDIC/ aXnUGyaOBc9KCgV6iLGDIrzfT1y0izGGZ+lvpDp6i9fMJv8SbH+lscq1sJUu3GrpittD Jd96IcR7YGMj+uB+v5EXMzK/H4kn5iDKL4tGQQ87WzvGh78KlH/9nwTlyw49aTGwCTOD A09g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=q0MxyEK3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Thu, 26 Sep 2019 06:31:29 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBUTk8069017; Thu, 26 Sep 2019 06:31:32 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jonathan Corbet , Rob Herring , Jon Mason , Dave Jiang , Allen Hubbe , Lorenzo Pieralisi CC: Mark Rutland , , , , , , Subject: [RFC PATCH 15/21] PCI: endpoint: Remove unused pci_epf_match_device() Date: Thu, 26 Sep 2019 16:59:27 +0530 Message-ID: <20190926112933.8922-16-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190926112933.8922-1-kishon@ti.com> References: <20190926112933.8922-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Remove unused pci_epf_match_device() function added in pci-epf-core.c Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-epf-core.c | 16 ---------------- include/linux/pci-epf.h | 2 -- 2 files changed, 18 deletions(-) -- 2.17.1 diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c index 388966faf17a..9fa4d8d4d829 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -619,22 +619,6 @@ struct pci_epf *devm_pci_epf_of_create(struct device *dev, } EXPORT_SYMBOL_GPL(devm_pci_epf_of_create); -const struct pci_epf_device_id * -pci_epf_match_device(const struct pci_epf_device_id *id, struct pci_epf *epf) -{ - if (!id || !epf) - return NULL; - - while (*id->name) { - if (strcmp(epf->name, id->name) == 0) - return id; - id++; - } - - return NULL; -} -EXPORT_SYMBOL_GPL(pci_epf_match_device); - static void pci_epf_dev_release(struct device *dev) { struct pci_epf *epf = to_pci_epf(dev); diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index b5075119f3ad..80505106c770 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -189,8 +189,6 @@ static inline void *epf_get_drvdata(struct pci_epf *epf) return dev_get_drvdata(&epf->dev); } -const struct pci_epf_device_id * -pci_epf_match_device(const struct pci_epf_device_id *id, struct pci_epf *epf); struct pci_epf *pci_epf_create(const char *name); struct pci_epf *pci_epf_of_create(struct device_node *node); struct pci_epf *devm_pci_epf_of_create(struct device *dev, From patchwork Thu Sep 26 11:29:28 2019 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id k2si1140171ede.311.2019.09.26.04.31.56; Thu, 26 Sep 2019 04:31:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=B5a+RGTk; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726823AbfIZLbx (ORCPT + 26 others); Thu, 26 Sep 2019 07:31:53 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:53026 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726014AbfIZLbv (ORCPT ); Thu, 26 Sep 2019 07:31:51 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8QBVffv016260; Thu, 26 Sep 2019 06:31:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569497501; bh=NsBIGvSBpp7lUk2avEDthRUDCLoNlQ7B/MXYwZ1hE5A=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=B5a+RGTkuOC1CLJiLCiAVIJcE7HlSJuBgKSlVVgBJZZ5yP3cv1LebqLJhNi3Lb+k3 Fui+vfi4UONozDcjlyXFFY7e42pU3FlxZeeiCLtxe+4GTirYzqRtM8OAwr7o4V/nWT cM89+LDDSawlxV+n6Wny0Grt2E6OKihR6+d40GTM= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8QBVfmw050949 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 26 Sep 2019 06:31:41 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 26 Sep 2019 06:31:33 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 26 Sep 2019 06:31:40 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBUTk9069017; Thu, 26 Sep 2019 06:31:37 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jonathan Corbet , Rob Herring , Jon Mason , Dave Jiang , Allen Hubbe , Lorenzo Pieralisi CC: Mark Rutland , , , , , , Subject: [RFC PATCH 16/21] PCI: endpoint: Fix missing mutex_unlock in error case Date: Thu, 26 Sep 2019 16:59:28 +0530 Message-ID: <20190926112933.8922-17-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190926112933.8922-1-kishon@ti.com> References: <20190926112933.8922-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There is a missing mutex_unlock() in pci_epc_add_epf() in one of the error scenarios. Fix it here. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-epc-core.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 797e5d323998..33c745546a42 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -686,6 +686,7 @@ int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf, { struct list_head *list; u32 func_no = 0; + int ret = 0; if (epf->is_vf) return -EINVAL; @@ -705,8 +706,10 @@ int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf, mutex_lock(&epc->lock); func_no = find_first_zero_bit(&epc->function_num_map, BITS_PER_LONG); - if (func_no >= BITS_PER_LONG) - return -EINVAL; + if (func_no >= BITS_PER_LONG) { + ret = -EINVAL; + goto err; + } set_bit(func_no, &epc->function_num_map); if (type == PRIMARY_INTERFACE) { @@ -720,9 +723,11 @@ int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf, } list_add_tail(list, &epc->pci_epf); + +err: mutex_unlock(&epc->lock); - return 0; + return ret; } EXPORT_SYMBOL_GPL(pci_epc_add_epf); From patchwork Thu Sep 26 11:29:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174476 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1921252ill; Thu, 26 Sep 2019 04:32:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqxKVsih89d0WzzcHIa5BL2vqF5Wtlnad7tmn5PQiyxZwv9A4LOWxlOJmgXWIqNEs1SjRTbj X-Received: by 2002:a05:6402:65a:: with SMTP id u26mr3029544edx.86.1569497524800; Thu, 26 Sep 2019 04:32:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569497524; cv=none; d=google.com; s=arc-20160816; b=Bwrgj40LwROEy/imVx/VwN4c+xrLtS7NAsPhIKmT+ovDd6MlEd6J6H0aNm8SmzsVdE Ff0gMOJCRloU05yhrZmqbvlIGWGUCiUj2QPjOiwc6QZv1rPX+wFDs/Nv6iPuQ8vJH03s yyQUAbL29mRDO0Jt8Z8QTJC1TSY8ORITRu29mYoafWG+N7bd22+ZgWKF5EfKSvzoStLE fR3EwWYiHzK6RHErlrSGfAdtXbtX9AwuR4G772ZHHCNxYUlGSaKlfAWxtfXxrpTlkRX3 /gUoTZO0yXAyFhgbvZolZLCntnk75Xkgul1sZ13G/L/oW2dhZA6siUnPVmg+f6P9eI7P D/AQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=ng+JuiPXXN1Km6Y2NxLN6mT9lfjCEFK/4Th3ibsGWNo=; b=vxiYXqe3YP89AK5gtLesDWwwlpOjZW1cePPbXFIyRqu7Z7XDLk58pI74wD0hhkPKp7 z8JwFnSqsKiUOnElw/Hk07MDfrRX+afelNIxtvAM9Qhzr8rSjaA1pz8qjV/9LLQbYYAe /FtYXFpYbhl62yiTPFqeO4buKVj+gGkJTdeOm6ucHeg5G/1rzMH0Y13ZiScWizCHoW+8 7DuinmO1Rg8mYmmnod82JK/AuV7kZx3+s4z32h2fu31lNTmMfo+NgO25h00UbbAVcx/I amHVGCcvwQ+kGDwVPcrIUVgFfbAqqVnEov9wugqD6VgZkhzdDUP+27QoROB004KLQmyQ yggw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="YGXT/KoG"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n2si1155879edq.264.2019.09.26.04.32.04; Thu, 26 Sep 2019 04:32:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="YGXT/KoG"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726881AbfIZLcD (ORCPT + 26 others); Thu, 26 Sep 2019 07:32:03 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:51166 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726833AbfIZLb6 (ORCPT ); Thu, 26 Sep 2019 07:31:58 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8QBVnbN042719; Thu, 26 Sep 2019 06:31:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569497509; bh=ng+JuiPXXN1Km6Y2NxLN6mT9lfjCEFK/4Th3ibsGWNo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=YGXT/KoG0ajeWU0IS8FfMsJSAVt2C8/VDEQ3cKAygxGb1dT/DJzrLOqwUNe+gyvhB sl4IET9fTvQUFGaFsi/IMTFOobQIE4Tp8HTRBdTGWSq6GD0aDtjIl1negMOEuRn0iI glocfiQ8Z5+LNqoCx4zCAgYQaOu3pSAVKl2hwfek= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBVnO3014516; Thu, 26 Sep 2019 06:31:49 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 26 Sep 2019 06:31:49 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 26 Sep 2019 06:31:41 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBUTkB069017; Thu, 26 Sep 2019 06:31:45 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jonathan Corbet , Rob Herring , Jon Mason , Dave Jiang , Allen Hubbe , Lorenzo Pieralisi CC: Mark Rutland , , , , , , Subject: [RFC PATCH 18/21] PCI: endpoint: Add EP function driver to provide NTB functionality Date: Thu, 26 Sep 2019 16:59:30 +0530 Message-ID: <20190926112933.8922-19-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190926112933.8922-1-kishon@ti.com> References: <20190926112933.8922-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a new endpoint function driver to provide NTB functionality using multiple PCIe endpoint instances. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/functions/Kconfig | 12 + drivers/pci/endpoint/functions/Makefile | 1 + drivers/pci/endpoint/functions/pci-epf-ntb.c | 1143 ++++++++++++++++++ 3 files changed, 1156 insertions(+) create mode 100644 drivers/pci/endpoint/functions/pci-epf-ntb.c -- 2.17.1 diff --git a/drivers/pci/endpoint/functions/Kconfig b/drivers/pci/endpoint/functions/Kconfig index 8820d0f7ec77..55ac7bb2d469 100644 --- a/drivers/pci/endpoint/functions/Kconfig +++ b/drivers/pci/endpoint/functions/Kconfig @@ -12,3 +12,15 @@ config PCI_EPF_TEST for PCI Endpoint. If in doubt, say "N" to disable Endpoint test driver. + +config PCI_EPF_NTB + tristate "PCI Endpoint NTB driver" + depends on PCI_ENDPOINT + help + Select this configuration option to enable the NTB driver + for PCI Endpoint. NTB driver implements NTB controller + functionality using multiple PCIe endpoint instances. It + can support NTB endpoint function devices created using + device tree. + + If in doubt, say "N" to disable Endpoint NTB driver. diff --git a/drivers/pci/endpoint/functions/Makefile b/drivers/pci/endpoint/functions/Makefile index d6fafff080e2..96ab932a537a 100644 --- a/drivers/pci/endpoint/functions/Makefile +++ b/drivers/pci/endpoint/functions/Makefile @@ -4,3 +4,4 @@ # obj-$(CONFIG_PCI_EPF_TEST) += pci-epf-test.o +obj-$(CONFIG_PCI_EPF_NTB) += pci-epf-ntb.o diff --git a/drivers/pci/endpoint/functions/pci-epf-ntb.c b/drivers/pci/endpoint/functions/pci-epf-ntb.c new file mode 100644 index 000000000000..14b3862fc780 --- /dev/null +++ b/drivers/pci/endpoint/functions/pci-epf-ntb.c @@ -0,0 +1,1143 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Endpoint Function Driver to implement Non-Transparent Bridge functionality + * + * Copyright (C) 2019 Texas Instruments + * Author: Kishon Vijay Abraham I + */ + +#include +#include +#include +#include + +#include +#include + +static struct workqueue_struct *kpcintb_workqueue; + +#define COMMAND_CONFIGURE_DOORBELL 1 +#define COMMAND_CONFIGURE_MW 2 +#define COMMAND_LINK_UP 3 + +#define COMMAND_STATUS_OK BIT(0) +#define LINK_STATUS_UP BIT(1) + +#define SPAD_COUNT 64 +#define DB_COUNT 4 +#define NTB_MW_OFFSET 2 +#define DB_COUNT_MASK GENMASK(15, 0) +#define MSIX_ENABLE BIT(16) +#define MAX_DB_COUNT 32 +#define MAX_MW 4 + +enum epf_ntb_bar { + BAR_CONFIG, + BAR_PEER_SPAD, + BAR_DB_MW1, + BAR_MW2, + BAR_MW3, + BAR_MW4, +}; + +struct epf_ntb { + u32 num_mws; + u32 *mws_size; + u32 db_count; + u32 spad_count; + struct pci_epf *epf; + struct epf_ntb_epc *epc[2]; +}; + +struct epf_ntb_epc { + u8 func_no; + u8 vfunc_no; + bool linkup; + u32 spad_size; + struct pci_epc *epc; + struct epf_ntb *epf_ntb; + void __iomem *mw_addr[6]; + struct epf_ntb_ctrl *reg; + struct pci_epf_bar *epf_bar; + enum pci_barno epf_ntb_bar[6]; + struct delayed_work cmd_handler; + enum pci_epc_interface_type type; + const struct pci_epc_features *epc_features; +}; + +struct epf_ntb_ctrl { + u32 command; + u32 argument; + u32 status; + u32 topology; + u64 addr; + u32 size; + u32 mw1_offset; + u32 num_mws; + u32 spad_offset; + u32 spad_count; + u32 db_entry_size; + u32 db_data[MAX_DB_COUNT]; +} __packed; + +static struct pci_epf_header epf_ntb_header = { + .vendorid = PCI_ANY_ID, + .deviceid = PCI_ANY_ID, + .baseclass_code = PCI_BASE_CLASS_MEMORY, + .interrupt_pin = PCI_INTERRUPT_INTA, +}; + +static void epf_ntb_link_up(struct epf_ntb *ntb) +{ + enum pci_epc_interface_type type; + struct epf_ntb_epc *ntb_epc; + struct epf_ntb_ctrl *ctrl; + u8 vfunc_no, func_no; + + for (type = PRIMARY_INTERFACE; type <= SECONDARY_INTERFACE; type++) { + ntb_epc = ntb->epc[type]; + func_no = ntb_epc->func_no; + vfunc_no = ntb_epc->vfunc_no; + ctrl = ntb_epc->reg; + ctrl->status |= LINK_STATUS_UP; + pci_epc_raise_irq(ntb_epc->epc, func_no, vfunc_no, + PCI_EPC_IRQ_MSI, 1); + } +} + +static void +epf_ntb_configure_mw(struct epf_ntb *ntb, enum pci_epc_interface_type type, + u32 mw) +{ + struct epf_ntb_epc *peer_ntb_epc; + struct pci_epf_bar *peer_epf_bar; + struct epf_ntb_epc *ntb_epc; + enum pci_barno peer_barno; + struct epf_ntb_ctrl *ctrl; + phys_addr_t phys_addr; + u8 vfunc_no, func_no; + struct pci_epc *epc; + u64 addr; + u32 size; + int ret; + + ntb_epc = ntb->epc[type]; + epc = ntb_epc->epc; + + peer_ntb_epc = ntb->epc[!type]; + peer_barno = peer_ntb_epc->epf_ntb_bar[mw + NTB_MW_OFFSET]; + peer_epf_bar = &peer_ntb_epc->epf_bar[peer_barno]; + + phys_addr = peer_epf_bar->phys_addr; + ctrl = ntb_epc->reg; + addr = ctrl->addr; + size = ctrl->size; + if (mw + NTB_MW_OFFSET == BAR_DB_MW1) + phys_addr += ctrl->mw1_offset; + + func_no = ntb_epc->func_no; + vfunc_no = ntb_epc->vfunc_no; + + ret = pci_epc_map_addr(epc, func_no, vfunc_no, phys_addr, addr, size); + WARN(ret < 0, "%s intf: Failed to map memory window %d address\n", + pci_epc_interface_string(type), mw); +} + +static void +epf_ntb_configure_db(struct epf_ntb *ntb, enum pci_epc_interface_type type, + u16 db_count, bool msix) +{ + struct epf_ntb_epc *peer_ntb_epc; + struct pci_epf_bar *peer_epf_bar; + struct epf_ntb_ctrl *peer_ctrl; + struct epf_ntb_epc *ntb_epc; + enum pci_barno peer_barno; + phys_addr_t phys_addr; + u8 vfunc_no, func_no; + struct pci_epc *epc; + u32 db_entry_size; + u32 db_data; + int ret, i; + + ntb_epc = ntb->epc[type]; + epc = ntb_epc->epc; + + peer_ntb_epc = ntb->epc[!type]; + peer_barno = peer_ntb_epc->epf_ntb_bar[BAR_DB_MW1]; + peer_epf_bar = &peer_ntb_epc->epf_bar[peer_barno]; + peer_ctrl = peer_ntb_epc->reg; + db_entry_size = peer_ctrl->db_entry_size; + + phys_addr = peer_epf_bar->phys_addr; + func_no = ntb_epc->func_no; + vfunc_no = ntb_epc->vfunc_no; + + ret = pci_epc_map_msi_irq(epc, func_no, vfunc_no, phys_addr, db_count, + db_entry_size, &db_data); + WARN(ret < 0, "%s intf: Failed to map MSI IRQ\n", + pci_epc_interface_string(type)); + for (i = 0; i < db_count; i++) + peer_ctrl->db_data[i] = db_data | i; +} + +static void epf_ntb_cmd_handler(struct work_struct *work) +{ + enum pci_epc_interface_type type; + struct epf_ntb_epc *ntb_epc; + struct epf_ntb_ctrl *ctrl; + u32 command, argument; + struct epf_ntb *ntb; + struct device *dev; + u16 db_count; + bool is_msix; + + ntb_epc = container_of(work, struct epf_ntb_epc, cmd_handler.work); + ctrl = ntb_epc->reg; + command = ctrl->command; + if (!command) + goto reset_handler; + argument = ctrl->argument; + + ctrl->command = 0; + ctrl->argument = 0; + + ctrl = ntb_epc->reg; + type = ntb_epc->type; + ntb = ntb_epc->epf_ntb; + dev = &ntb->epf->dev; + + switch (command) { + case COMMAND_CONFIGURE_DOORBELL: + db_count = argument & DB_COUNT_MASK; + is_msix = argument & MSIX_ENABLE; + epf_ntb_configure_db(ntb, type, db_count, is_msix); + ctrl->status |= COMMAND_STATUS_OK; + break; + case COMMAND_CONFIGURE_MW: + epf_ntb_configure_mw(ntb, type, argument); + ctrl->status |= COMMAND_STATUS_OK; + break; + case COMMAND_LINK_UP: + ntb_epc->linkup = true; + if (ntb->epc[PRIMARY_INTERFACE]->linkup && + ntb->epc[SECONDARY_INTERFACE]->linkup) + epf_ntb_link_up(ntb); + ctrl->status |= COMMAND_STATUS_OK; + break; + default: + dev_err(dev, "UNKNOWN command: %d\n", command); + break; + } + +reset_handler: + queue_delayed_work(kpcintb_workqueue, &ntb_epc->cmd_handler, + msecs_to_jiffies(5)); +} + +static void epf_ntb_peer_spad_bar_clear(struct epf_ntb_epc *ntb_epc) +{ + struct pci_epf_bar *epf_bar; + enum pci_barno barno; + u8 vfunc_no, func_no; + struct pci_epc *epc; + + epc = ntb_epc->epc; + func_no = ntb_epc->func_no; + vfunc_no = ntb_epc->vfunc_no; + barno = ntb_epc->epf_ntb_bar[BAR_PEER_SPAD]; + epf_bar = &ntb_epc->epf_bar[barno]; + pci_epc_clear_bar(epc, func_no, vfunc_no, epf_bar); +} + +static int +epf_ntb_peer_spad_bar_set(struct epf_ntb *ntb, enum pci_epc_interface_type type) +{ + struct epf_ntb_epc *peer_ntb_epc; + struct pci_epf_bar *peer_epf_bar; + struct epf_ntb_epc *ntb_epc; + struct pci_epf_bar *epf_bar; + enum pci_barno peer_barno; + u32 peer_spad_offset; + enum pci_barno barno; + u8 vfunc_no, func_no; + struct pci_epc *epc; + struct device *dev; + int ret; + + dev = &ntb->epf->dev; + + peer_ntb_epc = ntb->epc[!type]; + peer_barno = peer_ntb_epc->epf_ntb_bar[BAR_CONFIG]; + peer_epf_bar = &peer_ntb_epc->epf_bar[peer_barno]; + + ntb_epc = ntb->epc[type]; + barno = ntb_epc->epf_ntb_bar[BAR_PEER_SPAD]; + epf_bar = &ntb_epc->epf_bar[barno]; + func_no = ntb_epc->func_no; + vfunc_no = ntb_epc->vfunc_no; + epc = ntb_epc->epc; + + peer_spad_offset = peer_ntb_epc->reg->spad_offset; + epf_bar->phys_addr = peer_epf_bar->phys_addr + peer_spad_offset; + epf_bar->size = peer_ntb_epc->spad_size; + epf_bar->barno = barno; + epf_bar->flags = PCI_BASE_ADDRESS_MEM_TYPE_32; + + ret = pci_epc_set_bar(ntb_epc->epc, func_no, vfunc_no, epf_bar); + if (ret) { + dev_err(dev, "%s intf: peer SPAD BAR set failed\n", + pci_epc_interface_string(type)); + return ret; + } + + return 0; +} + +static void epf_ntb_config_sspad_bar_clear(struct epf_ntb_epc *ntb_epc) +{ + struct pci_epf_bar *epf_bar; + u8 vfunc_no, func_no; + enum pci_barno barno; + struct pci_epc *epc; + + epc = ntb_epc->epc; + func_no = ntb_epc->func_no; + vfunc_no = ntb_epc->vfunc_no; + barno = ntb_epc->epf_ntb_bar[BAR_CONFIG]; + epf_bar = &ntb_epc->epf_bar[barno]; + pci_epc_clear_bar(epc, func_no, vfunc_no, epf_bar); +} + +static int epf_ntb_config_sspad_bar_set(struct epf_ntb_epc *ntb_epc) +{ + struct pci_epf_bar *epf_bar; + enum pci_barno barno; + u8 vfunc_no, func_no; + struct epf_ntb *ntb; + struct pci_epc *epc; + struct device *dev; + int ret; + + ntb = ntb_epc->epf_ntb; + dev = &ntb->epf->dev; + + epc = ntb_epc->epc; + func_no = ntb_epc->func_no; + vfunc_no = ntb_epc->vfunc_no; + barno = ntb_epc->epf_ntb_bar[BAR_CONFIG]; + epf_bar = &ntb_epc->epf_bar[barno]; + + ret = pci_epc_set_bar(epc, func_no, vfunc_no, epf_bar); + if (ret) { + dev_err(dev, "%s inft: Config/Status/SPAD BAR set failed\n", + pci_epc_interface_string(ntb_epc->type)); + return ret; + } + + return 0; +} + +static void epf_ntb_config_spad_bar_free(struct epf_ntb *ntb) +{ + enum pci_epc_interface_type type; + struct epf_ntb_epc *ntb_epc; + enum pci_barno barno; + struct pci_epf *epf; + + epf = ntb->epf; + for (type = PRIMARY_INTERFACE; type <= SECONDARY_INTERFACE; type++) { + ntb_epc = ntb->epc[type]; + barno = ntb_epc->epf_ntb_bar[BAR_CONFIG]; + if (ntb_epc->reg) + pci_epf_free_space(epf, ntb_epc->reg, barno, type); + } +} + +static int +epf_ntb_config_spad_bar_alloc_interface(struct epf_ntb *ntb, + enum pci_epc_interface_type type) +{ + const struct pci_epc_features *peer_epc_features; + const struct pci_epc_features *epc_features; + struct epf_ntb_epc *peer_ntb_epc; + struct epf_ntb_epc *ntb_epc; + struct epf_ntb_ctrl *ctrl; + enum pci_barno peer_barno; + struct device_node *node; + u32 spad_size, ctrl_size; + enum pci_barno barno; + u64 size, peer_size; + struct pci_epc *epc; + struct pci_epf *epf; + struct device *dev; + u32 spad_count; + size_t align; + void *base; + + epf = ntb->epf; + node = epf->node; + dev = &epf->dev; + ntb_epc = ntb->epc[type]; + epc = ntb_epc->epc; + + epc_features = ntb_epc->epc_features; + barno = ntb_epc->epf_ntb_bar[BAR_CONFIG]; + size = epc_features->bar_fixed_size[barno]; + align = epc_features->align; + + peer_ntb_epc = ntb->epc[!type]; + peer_epc_features = peer_ntb_epc->epc_features; + peer_barno = ntb_epc->epf_ntb_bar[BAR_PEER_SPAD]; + peer_size = peer_epc_features->bar_fixed_size[barno]; + + /* Check if epc_features is populated incorrectly */ + if ((!IS_ALIGNED(size, align))) + return -EINVAL; + + spad_count = SPAD_COUNT; + of_property_read_u32(node, "spad-count", &spad_count); + + ctrl_size = sizeof(struct epf_ntb_ctrl); + spad_size = spad_count * 4; + + if (!align) { + ctrl_size = roundup_pow_of_two(ctrl_size); + spad_size = roundup_pow_of_two(spad_size); + } else { + ctrl_size = ALIGN(ctrl_size, align); + spad_size = ALIGN(spad_size, align); + } + + if (peer_size) { + if (peer_size < spad_size) + spad_count = peer_size / 4; + spad_size = peer_size; + } + + /* + * In order to make sure SPAD offset is aligned to its size, + * expand control region size to the size of SPAD if SPAD size + * is greater than control region size. + */ + if (spad_size > ctrl_size) + ctrl_size = spad_size; + + if (!size) + size = ctrl_size + spad_size; + else if (size < ctrl_size + spad_size) + return -EINVAL; + + base = pci_epf_alloc_space(epf, size, barno, align, type); + if (!base) { + dev_err(dev, "%s intf: Config/Status/SPAD alloc region fail\n", + pci_epc_interface_string(type)); + return -ENOMEM; + } + + ntb_epc->reg = base; + + ctrl = ntb_epc->reg; + ctrl->spad_offset = ctrl_size; + ctrl->spad_count = spad_count; + ctrl->num_mws = ntb->num_mws; + ctrl->db_entry_size = align ? align : 4; + ntb_epc->spad_size = spad_size; + + return 0; +} + +static int epf_ntb_config_spad_bar_alloc(struct epf_ntb *ntb) +{ + enum pci_epc_interface_type type; + struct device *dev; + int ret; + + dev = &ntb->epf->dev; + + for (type = PRIMARY_INTERFACE; type <= SECONDARY_INTERFACE; type++) { + ret = epf_ntb_config_spad_bar_alloc_interface(ntb, type); + if (ret) { + dev_err(dev, "%s intf: Config/SPAD BAR alloc failed\n", + pci_epc_interface_string(type)); + goto err_config_spad_bar_alloc; + } + } + + return 0; + +err_config_spad_bar_alloc: + epf_ntb_config_spad_bar_free(ntb); + + return ret; +} + +static void epf_ntb_free_peer_mem(struct epf_ntb_epc *ntb_epc) +{ + struct pci_epf_bar *epf_bar; + void __iomem *mw_addr; + phys_addr_t phys_addr; + enum epf_ntb_bar bar; + enum pci_barno barno; + struct pci_epc *epc; + size_t size; + + epc = ntb_epc->epc; + + for (bar = BAR_DB_MW1; bar < BAR_MW4; bar++) { + barno = ntb_epc->epf_ntb_bar[bar]; + mw_addr = ntb_epc->mw_addr[barno]; + epf_bar = &ntb_epc->epf_bar[barno]; + phys_addr = epf_bar->phys_addr; + size = epf_bar->size; + if (mw_addr) { + pci_epc_mem_free_addr(epc, phys_addr, mw_addr, size); + ntb_epc->mw_addr[barno] = NULL; + } + } +} + +static void epf_ntb_db_mw_bar_clear(struct epf_ntb_epc *ntb_epc) +{ + struct pci_epf_bar *epf_bar; + enum epf_ntb_bar bar; + enum pci_barno barno; + u8 vfunc_no, func_no; + struct pci_epc *epc; + + epc = ntb_epc->epc; + + func_no = ntb_epc->func_no; + vfunc_no = ntb_epc->vfunc_no; + + for (bar = BAR_DB_MW1; bar < BAR_MW4; bar++) { + barno = ntb_epc->epf_ntb_bar[bar]; + epf_bar = &ntb_epc->epf_bar[barno]; + pci_epc_clear_bar(epc, func_no, vfunc_no, epf_bar); + } +} + +static void epf_ntb_db_mw_bar_cleanup(struct epf_ntb_epc *ntb_epc, + struct epf_ntb_epc *peer_ntb_epc) +{ + epf_ntb_db_mw_bar_clear(ntb_epc); + epf_ntb_free_peer_mem(peer_ntb_epc); +} + +static int +epf_ntb_alloc_peer_mem(struct device *dev, struct epf_ntb_epc *ntb_epc, + enum epf_ntb_bar bar, struct epf_ntb_epc *peer_ntb_epc, + size_t size) +{ + const struct pci_epc_features *epc_features; + struct pci_epf_bar *epf_bar; + struct pci_epc *peer_epc; + phys_addr_t phys_addr; + void __iomem *mw_addr; + enum pci_barno barno; + size_t align; + + epc_features = ntb_epc->epc_features; + align = epc_features->align; + + if (size < 128) + size = 128; + + if (align) + size = ALIGN(size, align); + else + size = roundup_pow_of_two(size); + + peer_epc = peer_ntb_epc->epc; + mw_addr = pci_epc_mem_alloc_addr(peer_epc, &phys_addr, size); + if (!mw_addr) { + dev_err(dev, "%s intf: Failed to allocate OB address\n", + pci_epc_interface_string(peer_ntb_epc->type)); + return -ENOMEM; + } + + barno = ntb_epc->epf_ntb_bar[bar]; + epf_bar = &ntb_epc->epf_bar[barno]; + ntb_epc->mw_addr[barno] = mw_addr; + + epf_bar->phys_addr = phys_addr; + epf_bar->size = size; + epf_bar->barno = barno; + epf_bar->flags = PCI_BASE_ADDRESS_MEM_TYPE_32; + + return 0; +} + +static int epf_ntb_configure_interrupt(struct epf_ntb *ntb, + enum pci_epc_interface_type type) +{ + const struct pci_epc_features *epc_features; + bool msix_capable, msi_capable; + struct epf_ntb_epc *ntb_epc; + struct device_node *node; + u8 vfunc_no, func_no; + struct pci_epc *epc; + struct device *dev; + u32 db_count; + int ret; + + ntb_epc = ntb->epc[type]; + dev = &ntb->epf->dev; + node = ntb->epf->node; + + epc_features = ntb_epc->epc_features; + msix_capable = epc_features->msix_capable; + msi_capable = epc_features->msi_capable; + + if (!(msix_capable || msi_capable)) { + dev_err(dev, "MSI or MSI-X is required for doorbell\n"); + return -EINVAL; + } + + func_no = ntb_epc->func_no; + vfunc_no = ntb_epc->vfunc_no; + + db_count = DB_COUNT; + of_property_read_u32(node, "db-count", &db_count); + if (db_count > MAX_DB_COUNT) { + dev_err(dev, "DB count cannot be more than %d\n", MAX_DB_COUNT); + return -EINVAL; + } + + ntb->db_count = db_count; + epc = ntb_epc->epc; + + if (msi_capable) { + ret = pci_epc_set_msi(epc, func_no, vfunc_no, db_count); + if (ret) { + dev_err(dev, "%s intf: MSI configuration failed\n", + pci_epc_interface_string(type)); + return ret; + } + } + + if (msix_capable) { + ret = pci_epc_set_msix(epc, func_no, vfunc_no, db_count); + if (ret) { + dev_err(dev, "MSI configuration failed\n"); + return ret; + } + } + + return 0; +} + +static int epf_ntb_db_mw_bar_init(struct epf_ntb *ntb, + enum pci_epc_interface_type type) +{ + const struct pci_epc_features *epc_features; + struct epf_ntb_epc *peer_ntb_epc; + struct epf_ntb_epc *ntb_epc; + struct pci_epf_bar *epf_bar; + struct epf_ntb_ctrl *ctrl; + enum epf_ntb_bar bar; + u8 vfunc_no, func_no; + enum pci_barno barno; + struct pci_epc *epc; + struct device *dev; + u32 num_mws, size; + u32 db_count; + size_t align; + int ret; + int i; + + ntb_epc = ntb->epc[type]; + peer_ntb_epc = ntb->epc[!type]; + + dev = &ntb->epf->dev; + epc_features = ntb_epc->epc_features; + align = epc_features->align; + func_no = ntb_epc->func_no; + vfunc_no = ntb_epc->vfunc_no; + epc = ntb_epc->epc; + num_mws = ntb->num_mws; + db_count = ntb->db_count; + + for (bar = BAR_DB_MW1, i = 0; i < num_mws; bar++, i++) { + if (bar == BAR_DB_MW1) { + align = align ? align : 4; + size = db_count * align; + size = ALIGN(size, ntb->mws_size[i]); + ctrl = ntb_epc->reg; + ctrl->mw1_offset = size; + size += ntb->mws_size[i]; + } else { + size = ntb->mws_size[i]; + } + + ret = epf_ntb_alloc_peer_mem(dev, ntb_epc, bar, + peer_ntb_epc, size); + if (ret) + goto err_alloc_peer_mem; + + barno = ntb_epc->epf_ntb_bar[bar]; + epf_bar = &ntb_epc->epf_bar[barno]; + + ret = pci_epc_set_bar(epc, func_no, vfunc_no, epf_bar); + if (ret) { + dev_err(dev, "%s intf: DoorBell BAR set failed\n", + pci_epc_interface_string(type)); + goto err_alloc_peer_mem; + } + } + + return 0; + +err_alloc_peer_mem: + epf_ntb_db_mw_bar_cleanup(ntb_epc, peer_ntb_epc); + + return ret; +} + +static void epf_ntb_epc_destroy(struct epf_ntb *ntb) +{ + enum pci_epc_interface_type type; + struct epf_ntb_epc *ntb_epc; + struct pci_epc *epc; + struct pci_epf *epf; + + epf = ntb->epf; + for (type = PRIMARY_INTERFACE; type <= SECONDARY_INTERFACE; type++) { + ntb_epc = ntb->epc[type]; + if (!ntb_epc) + return; + epc = ntb_epc->epc; + pci_epc_remove_epf(epc, epf, type); + pci_epc_put(epc); + } +} + +static int +epf_ntb_epc_create_interface(struct epf_ntb *ntb, struct pci_epc *epc, + enum pci_epc_interface_type type) +{ + const struct pci_epc_features *epc_features; + struct pci_epf_bar *epf_bar; + struct epf_ntb_epc *ntb_epc; + u8 vfunc_no, func_no; + struct pci_epf *epf; + struct device *dev; + + dev = &ntb->epf->dev; + + ntb_epc = devm_kzalloc(dev, sizeof(*ntb_epc), GFP_KERNEL); + if (!ntb_epc) + return -ENOMEM; + + epf = ntb->epf; + if (type == PRIMARY_INTERFACE) { + func_no = epf->func_no; + vfunc_no = epf->vfunc_no; + epf_bar = epf->bar; + } else { + func_no = epf->sec_epc_func_no; + vfunc_no = epf->sec_epc_vfunc_no; + epf_bar = epf->sec_epc_bar; + } + + ntb_epc->linkup = false; + ntb_epc->epc = epc; + ntb_epc->func_no = func_no; + ntb_epc->vfunc_no = vfunc_no; + ntb_epc->type = type; + ntb_epc->epf_bar = epf_bar; + ntb_epc->epf_ntb = ntb; + + epc_features = pci_epc_get_features(epc, func_no, vfunc_no); + ntb_epc->epc_features = epc_features; + + ntb->epc[type] = ntb_epc; + + return 0; +} + +static int epf_ntb_epc_create(struct epf_ntb *ntb) +{ + enum pci_epc_interface_type type; + struct device_node *node; + const char *epc_name; + struct pci_epc *epc; + struct pci_epf *epf; + struct device *dev; + int ret; + + epf = ntb->epf; + node = epf->node; + dev = &epf->dev; + + for (type = PRIMARY_INTERFACE; type <= SECONDARY_INTERFACE; type++) { + epc_name = pci_epc_interface_string(type); + + epc = of_pci_epc_get_by_name(node, epc_name); + if (IS_ERR(epc)) { + if (PTR_ERR(epc) != -EPROBE_DEFER) + dev_err(dev, "%s intf: Failed to get EPC\n", + epc_name); + ret = PTR_ERR(epc); + goto err_epc_get; + } + + ret = pci_epc_add_epf(epc, epf, type); + if (ret) { + dev_err(dev, "%s intf: Fail to add EPF to EPC\n", + epc_name); + goto err_epc_get; + } + + ret = epf_ntb_epc_create_interface(ntb, epc, type); + if (ret) { + dev_err(dev, "%s intf: Fail to create NTB EPC\n", + epc_name); + goto err_epc_get; + } + } + + return 0; + +err_epc_get: + epf_ntb_epc_destroy(ntb); + + return ret; +} + +static int epf_ntb_init_epc_bar_interface(struct epf_ntb *ntb, + enum pci_epc_interface_type type) +{ + const struct pci_epc_features *epc_features; + struct epf_ntb_epc *ntb_epc; + enum pci_barno barno; + enum epf_ntb_bar bar; + struct device *dev; + u32 num_mws; + int i; + + barno = BAR_0; + ntb_epc = ntb->epc[type]; + num_mws = ntb->num_mws; + dev = &ntb->epf->dev; + epc_features = ntb_epc->epc_features; + + /* These are required BARs which are mandatory for NTB functionality */ + for (bar = BAR_CONFIG; bar <= BAR_DB_MW1; bar++, barno++) { + barno = pci_epc_get_next_free_bar(epc_features, barno); + if (barno < 0) { + dev_err(dev, "%s intf: Fail to get NTB function BAR\n", + pci_epc_interface_string(type)); + return barno; + } + ntb_epc->epf_ntb_bar[bar] = barno; + } + + /* These are optional BARs which doesn't impact NTB functionality */ + for (bar = BAR_MW2, i = 1; i < num_mws; bar++, barno++, i++) { + barno = pci_epc_get_next_free_bar(epc_features, barno); + if (barno < 0) { + ntb->num_mws = i; + dev_dbg(dev, "BAR not available for > MW%d\n", i + 1); + } + ntb_epc->epf_ntb_bar[bar] = barno; + } + + return 0; +} + +static int epf_ntb_init_epc_bar(struct epf_ntb *ntb) +{ + enum pci_epc_interface_type type; + struct device *dev; + int ret; + + dev = &ntb->epf->dev; + for (type = PRIMARY_INTERFACE; type <= SECONDARY_INTERFACE; type++) { + ret = epf_ntb_init_epc_bar_interface(ntb, type); + if (ret) { + dev_err(dev, "Fail to init EPC bar for %s interface\n", + pci_epc_interface_string(type)); + return ret; + } + } + + return 0; +} + +static int epf_ntb_epc_init_interface(struct epf_ntb *ntb, + enum pci_epc_interface_type type) +{ + struct epf_ntb_epc *ntb_epc; + u8 vfunc_no, func_no; + struct pci_epc *epc; + struct pci_epf *epf; + struct device *dev; + int ret; + + ntb_epc = ntb->epc[type]; + epf = ntb->epf; + dev = &epf->dev; + epc = ntb_epc->epc; + func_no = ntb_epc->func_no; + vfunc_no = ntb_epc->vfunc_no; + + ret = epf_ntb_config_sspad_bar_set(ntb->epc[type]); + if (ret) { + dev_err(dev, "%s intf: Config/self SPAD BAR init failed\n", + pci_epc_interface_string(type)); + return ret; + } + + ret = epf_ntb_peer_spad_bar_set(ntb, type); + if (ret) { + dev_err(dev, "%s intf: Peer SPAD BAR init failed\n", + pci_epc_interface_string(type)); + goto err_peer_spad_bar_init; + } + + ret = epf_ntb_configure_interrupt(ntb, type); + if (ret) { + dev_err(dev, "%s intf: Interrupt configuration failed\n", + pci_epc_interface_string(type)); + goto err_peer_spad_bar_init; + } + + ret = epf_ntb_db_mw_bar_init(ntb, type); + if (ret) { + dev_err(dev, "%s intf: DB/MW BAR init failed\n", + pci_epc_interface_string(type)); + goto err_db_mw_bar_init; + } + + ret = pci_epc_write_header(epc, func_no, vfunc_no, epf->header); + if (ret) { + dev_err(dev, "%s intf: Configuration header write failed\n", + pci_epc_interface_string(type)); + goto err_write_header; + } + + INIT_DELAYED_WORK(&ntb->epc[type]->cmd_handler, epf_ntb_cmd_handler); + queue_work(kpcintb_workqueue, &ntb->epc[type]->cmd_handler.work); + + return 0; + +err_write_header: + epf_ntb_db_mw_bar_cleanup(ntb->epc[type], ntb->epc[!type]); + +err_db_mw_bar_init: + epf_ntb_peer_spad_bar_clear(ntb->epc[type]); + +err_peer_spad_bar_init: + epf_ntb_config_sspad_bar_clear(ntb->epc[type]); + + return ret; +} + +static void epf_ntb_epc_cleanup(struct epf_ntb *ntb) +{ + enum pci_epc_interface_type type; + struct epf_ntb_epc *peer_ntb_epc; + struct epf_ntb_epc *ntb_epc; + + for (type = PRIMARY_INTERFACE; type <= SECONDARY_INTERFACE; type++) { + ntb_epc = ntb->epc[type]; + peer_ntb_epc = ntb->epc[!type]; + cancel_delayed_work(&ntb_epc->cmd_handler); + epf_ntb_db_mw_bar_cleanup(ntb_epc, peer_ntb_epc); + epf_ntb_peer_spad_bar_clear(ntb_epc); + epf_ntb_config_sspad_bar_clear(ntb_epc); + } +} + +static int epf_ntb_epc_init(struct epf_ntb *ntb) +{ + enum pci_epc_interface_type type; + struct device *dev; + int ret; + + dev = &ntb->epf->dev; + + for (type = PRIMARY_INTERFACE; type <= SECONDARY_INTERFACE; type++) { + ret = epf_ntb_epc_init_interface(ntb, type); + if (ret) { + dev_err(dev, "%s intf: Failed to initialize\n", + pci_epc_interface_string(type)); + goto err_init_type; + } + } + + return 0; + +err_init_type: + epf_ntb_epc_cleanup(ntb); + + return ret; +} + +static int epf_ntb_of_parse_mw(struct epf_ntb *ntb, struct device_node *node) +{ + struct device *dev; + u32 *mws_size; + u32 num_mws; + int ret; + + dev = &ntb->epf->dev; + ret = of_property_read_u32(node, "num-mws", &num_mws); + if (ret) { + dev_err(dev, "Failed to get num-mws dt property\n"); + return ret; + } + + if (num_mws > MAX_MW) { + dev_err(dev, "Cannot support more than 4 memory window\n"); + return ret; + } + + mws_size = devm_kzalloc(dev, sizeof(*mws_size) * num_mws, GFP_KERNEL); + if (!mws_size) + return -ENOMEM; + + ret = of_property_read_u32_array(node, "mws-size", mws_size, + num_mws); + if (ret) { + dev_err(dev, "Failed to get mws-size dt property\n"); + return ret; + } + + ntb->num_mws = num_mws; + ntb->mws_size = mws_size; + + return 0; +} + +static int pci_epf_ntb_of_parse(struct epf_ntb *ntb) +{ + struct device_node *node; + struct pci_epf *epf; + struct device *dev; + int ret; + + epf = ntb->epf; + node = epf->node; + dev = &epf->dev; + + epf->header = &epf_ntb_header; + pci_epc_of_parse_header(node, epf->header); + + ret = epf_ntb_of_parse_mw(ntb, node); + if (ret) { + dev_err(dev, "Invalid memory window configuration in DT\n"); + return ret; + } + + return 0; +} + +static int pci_epf_ntb_probe(struct pci_epf *epf) +{ + struct epf_ntb *ntb; + struct device *dev; + int ret; + + dev = &epf->dev; + + ntb = devm_kzalloc(dev, sizeof(*ntb), GFP_KERNEL); + if (!ntb) + return -ENOMEM; + + ntb->epf = epf; + + ret = pci_epf_ntb_of_parse(ntb); + if (ret) { + dev_err(dev, "Failed to parse NTB DT node\n"); + return ret; + } + + ret = epf_ntb_epc_create(ntb); + if (ret) { + dev_err(dev, "Failed to create NTB EPC\n"); + return ret; + } + + ret = epf_ntb_init_epc_bar(ntb); + if (ret) { + dev_err(dev, "Failed to create NTB EPC\n"); + goto err_bar_init; + } + + ret = epf_ntb_config_spad_bar_alloc(ntb); + if (ret) { + dev_err(dev, "Failed to allocate BAR memory\n"); + goto err_bar_init; + } + + ret = epf_ntb_epc_init(ntb); + if (ret) { + dev_err(dev, "Failed to initialize EPC\n"); + goto err_epc_init; + } + + epf_set_drvdata(epf, ntb); + + return 0; + +err_epc_init: + epf_ntb_config_spad_bar_free(ntb); + +err_bar_init: + epf_ntb_epc_destroy(ntb); + + return ret; +} + +static int pci_epf_ntb_remove(struct pci_epf *epf) +{ + struct epf_ntb *ntb = epf_get_drvdata(epf); + + epf_ntb_epc_cleanup(ntb); + epf_ntb_config_spad_bar_free(ntb); + epf_ntb_epc_destroy(ntb); + + return 0; +} + +static const struct pci_epf_device_id pci_epf_ntb_ids[] = { + { + .name = "pci-epf-ntb", + }, + {}, +}; + +static struct pci_epf_driver epf_ntb_driver = { + .driver.name = "pci_epf_ntb", + .probe = pci_epf_ntb_probe, + .remove = pci_epf_ntb_remove, + .id_table = pci_epf_ntb_ids, + .owner = THIS_MODULE, +}; + +static int __init pci_epf_ntb_init(void) +{ + int ret; + + kpcintb_workqueue = alloc_workqueue("kpcintb", WQ_MEM_RECLAIM | + WQ_HIGHPRI, 0); + ret = pci_epf_register_driver(&epf_ntb_driver); + if (ret) { + pr_err("Failed to register pci epf ntb driver --> %d\n", ret); + return ret; + } + + return 0; +} +module_init(pci_epf_ntb_init); + +static void __exit pci_epf_ntb_exit(void) +{ + pci_epf_unregister_driver(&epf_ntb_driver); +} +module_exit(pci_epf_ntb_exit); + +MODULE_DESCRIPTION("PCI EPF NTB DRIVER"); +MODULE_AUTHOR("Kishon Vijay Abraham I "); +MODULE_LICENSE("GPL v2"); From patchwork Thu Sep 26 11:29:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174477 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1921299ill; Thu, 26 Sep 2019 04:32:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqwNXWs/joEEMieIUIPqvIfT35+Qfi6b5otJqGE1ERAbU6hacHajmlbTW1Xtc/N/CbvYnKZ2 X-Received: by 2002:a17:906:4a5a:: with SMTP id a26mr2613739ejv.154.1569497527810; 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[209.132.180.67]) by mx.google.com with ESMTP id n2si1155879edq.264.2019.09.26.04.32.07; Thu, 26 Sep 2019 04:32:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=BDmf43rN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726903AbfIZLcG (ORCPT + 26 others); Thu, 26 Sep 2019 07:32:06 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:50232 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725787AbfIZLcB (ORCPT ); Thu, 26 Sep 2019 07:32:01 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8QBVrtj026112; Thu, 26 Sep 2019 06:31:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569497513; bh=Ba73hC2payjMjY03QA69XQlD3F4Pdv4g16+/XfFLTUM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BDmf43rNJSaHQkluwVqBGE1qfkyvb890yrFOLNyTfWcm9X+2UXBpfkctm+ZKH4zMd PQt8BrVqPcvsKnXooOQyA5INTn5E6YFYQ/adpHH6omH/Sga0IkDZqSyR3vQhgnPNOh wsNT62/a4VoErlLYpuZ465bUoxSgEbt8M2r6n2nY= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8QBVrE4032357 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 26 Sep 2019 06:31:53 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 26 Sep 2019 06:31:45 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 26 Sep 2019 06:31:45 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBUTkC069017; Thu, 26 Sep 2019 06:31:49 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jonathan Corbet , Rob Herring , Jon Mason , Dave Jiang , Allen Hubbe , Lorenzo Pieralisi CC: Mark Rutland , , , , , , Subject: [RFC PATCH 19/21] PCI: Add TI J721E device to pci ids Date: Thu, 26 Sep 2019 16:59:31 +0530 Message-ID: <20190926112933.8922-20-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190926112933.8922-1-kishon@ti.com> References: <20190926112933.8922-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add TI J721E device to the pci id database. Since this device has a configurable PCIe endpoint, it could be used with different drivers. Signed-off-by: Kishon Vijay Abraham I --- include/linux/pci_ids.h | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index d157983b84cf..b2820a834a5e 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -868,6 +868,7 @@ #define PCI_DEVICE_ID_TI_X620 0xac8d #define PCI_DEVICE_ID_TI_X420 0xac8e #define PCI_DEVICE_ID_TI_XX20_FM 0xac8f +#define PCI_DEVICE_ID_TI_J721E 0xb00d #define PCI_DEVICE_ID_TI_DRA74x 0xb500 #define PCI_DEVICE_ID_TI_DRA72x 0xb501 From patchwork Thu Sep 26 11:29:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 174478 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1921436ill; Thu, 26 Sep 2019 04:32:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqw6xRxIyaGCR0gBY116BEWfW+W/FYjjVpfDaEnU7oTjGT5TcSWM7TkR+OIxVug5T7Rf2msM X-Received: by 2002:a17:906:960d:: with SMTP id s13mr2624403ejx.166.1569497533190; Thu, 26 Sep 2019 04:32:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569497533; cv=none; d=google.com; s=arc-20160816; b=oGO0BvsJondNipx1wUpfjJ4EK9Kcc5ixe5EMhkjj25TcJ1HbCYC+QqV0T7LVAcnbm7 9Uanjp48L6uCnJhwgDuw0Ri7tehyk5fdpqrks7w3oTO6Kn3QDO/RNKE67gHqaOc/5iNg gyH2aaa/lxmfutN22Vc5TniYvRsn4w6k3fy8mmbQWOuB+IhChHg+uA45v4fKMdevUitR +cLgPu94KI2vBCYfW9pzA5F0tn4Ye0m2W+1utMm+94pNLFjhAdPdTMdKUQA+//a4KbWg onyMmZ4qU5I2kI0AJy4f5rX6uI5GCAo+1r9mCT2JpU2uncXUzuxheJyy+1U/s2FYGOuv Cdgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=uF0byY1IfglseGEElkZaZLGLoF4whqdkbdVKcK/38gk=; b=mlbll17/XV3Y/pEu1bnmL8IKKpbF42DEEU/gvopPXwooz7YpNlxbZZ+mxH5qomnPVR BI0qSQ5zXCYn8ellHVcNI2j3gNJpN2Bn05B8Q7fbYo4LgdCY++z7D040/9K2jGsWyMwI ZAiiEbab3M3Bq0nqYnqFW3ansWzDa420dvM1NQEpT3qdGPpbbj46rCEsRqpyK5dPimH7 VFea6QE9FM3ifqGYnc74APJq6Y/hqh9fLSYmqEsz3ppEQVSBQjqRKTw57iG0RE0rc2OH pldkilfK/1pjpCsyC+3qZmIKqCxlq0Tt0aMJnNjIj37EJNoqnfsYnB4dvoPedWeLVatN 2hxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gh0FdGaI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id um16si880941ejb.12.2019.09.26.04.32.12; Thu, 26 Sep 2019 04:32:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gh0FdGaI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726931AbfIZLcK (ORCPT + 26 others); Thu, 26 Sep 2019 07:32:10 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:50262 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726902AbfIZLcH (ORCPT ); Thu, 26 Sep 2019 07:32:07 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8QBVvmd026123; Thu, 26 Sep 2019 06:31:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569497517; bh=uF0byY1IfglseGEElkZaZLGLoF4whqdkbdVKcK/38gk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gh0FdGaIO4IIqh/23ZK8bi8JcqiDKTkAIsO6MKe9qwyBe8oVPBCgcbwxq4ShW7GU9 z5qRg5PgkK+GbMcqjwsoMuC0fchE8dtHF+Y6qDsn2AsILR9xfqX8hWcA3NZ5hoBKOe EZx4uO+f6nCvgsW90QERGDXF1m9LEKZj3VDSs+S8= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8QBVv3X032399 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 26 Sep 2019 06:31:57 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 26 Sep 2019 06:31:57 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 26 Sep 2019 06:31:57 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBUTkD069017; Thu, 26 Sep 2019 06:31:53 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jonathan Corbet , Rob Herring , Jon Mason , Dave Jiang , Allen Hubbe , Lorenzo Pieralisi CC: Mark Rutland , , , , , , Subject: [RFC PATCH 20/21] NTB: Add support for EPF PCI-Express Non-Transparent Bridge Date: Thu, 26 Sep 2019 16:59:32 +0530 Message-ID: <20190926112933.8922-21-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190926112933.8922-1-kishon@ti.com> References: <20190926112933.8922-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for EPF PCI-Express Non-Transparent Bridge (NTB) device. This driver is platform independent and could be used by any platform which have multiple PCIe endpoint instances configured using the pci-epf-ntb driver. The driver connnects to the standard NTB sub-system interface. The EPF NTB device has configurable number of memory windows (Max 4), configurable number of doorbell (Max 32), and configurable number of scratch-pad registers. Signed-off-by: Kishon Vijay Abraham I --- drivers/ntb/hw/Kconfig | 1 + drivers/ntb/hw/Makefile | 1 + drivers/ntb/hw/epf/Kconfig | 5 + drivers/ntb/hw/epf/Makefile | 1 + drivers/ntb/hw/epf/ntb_hw_epf.c | 648 ++++++++++++++++++++++++++++++++ 5 files changed, 656 insertions(+) create mode 100644 drivers/ntb/hw/epf/Kconfig create mode 100644 drivers/ntb/hw/epf/Makefile create mode 100644 drivers/ntb/hw/epf/ntb_hw_epf.c -- 2.17.1 diff --git a/drivers/ntb/hw/Kconfig b/drivers/ntb/hw/Kconfig index e51b581fd102..623d43a2bec0 100644 --- a/drivers/ntb/hw/Kconfig +++ b/drivers/ntb/hw/Kconfig @@ -1,4 +1,5 @@ source "drivers/ntb/hw/amd/Kconfig" source "drivers/ntb/hw/idt/Kconfig" source "drivers/ntb/hw/intel/Kconfig" +source "drivers/ntb/hw/epf/Kconfig" source "drivers/ntb/hw/mscc/Kconfig" diff --git a/drivers/ntb/hw/Makefile b/drivers/ntb/hw/Makefile index 923c442db750..48f672ca857a 100644 --- a/drivers/ntb/hw/Makefile +++ b/drivers/ntb/hw/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_NTB_AMD) += amd/ obj-$(CONFIG_NTB_IDT) += idt/ obj-$(CONFIG_NTB_INTEL) += intel/ +obj-$(CONFIG_NTB_EPF) += epf/ obj-$(CONFIG_NTB_SWITCHTEC) += mscc/ diff --git a/drivers/ntb/hw/epf/Kconfig b/drivers/ntb/hw/epf/Kconfig new file mode 100644 index 000000000000..314485574bf8 --- /dev/null +++ b/drivers/ntb/hw/epf/Kconfig @@ -0,0 +1,5 @@ +config NTB_EPF + tristate "Generic EPF Non-Transparent Bridge support" + help + This driver supports EPF NTB on configurable endpoint. + If unsure, say N. diff --git a/drivers/ntb/hw/epf/Makefile b/drivers/ntb/hw/epf/Makefile new file mode 100644 index 000000000000..2f560a422bc6 --- /dev/null +++ b/drivers/ntb/hw/epf/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_NTB_EPF) += ntb_hw_epf.o diff --git a/drivers/ntb/hw/epf/ntb_hw_epf.c b/drivers/ntb/hw/epf/ntb_hw_epf.c new file mode 100644 index 000000000000..fba3d88886f2 --- /dev/null +++ b/drivers/ntb/hw/epf/ntb_hw_epf.c @@ -0,0 +1,648 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Host side endpoint driver to implement Non-Transparent Bridge functionality + * + * Copyright (C) 2019 Texas Instruments + * Author: Kishon Vijay Abraham I + */ + +#include +#include +#include +#include +#include + +#define NTB_EPF_COMMAND 0x0 +#define CMD_CONFIGURE_DOORBELL 1 +#define CMD_CONFIGURE_MW 2 +#define CMD_LINK_UP 3 + +#define NTB_EPF_ARGUMENT 0x4 + +#define NTB_EPF_STATUS 0x8 +#define COMMAND_STATUS_OK BIT(0) +#define LINK_STATUS_UP BIT(1) + +#define NTB_EPF_TOPOLOGY 0xc +#define NTB_EPF_ADDR 0x10 +#define NTB_EPF_SIZE 0x18 +#define NTB_EPF_MW1_OFFSET 0x1c +#define NTB_EPF_MW_COUNT 0x20 +#define NTB_EPF_SPAD_OFFSET 0x24 +#define NTB_EPF_SPAD_COUNT 0x28 +#define NTB_EPF_DB_ENTRY_SIZE 0x2c +#define NTB_EPF_DB_DATA(n) (0x30 + (n) * 4) + +#define NTB_MIN_DB_COUNT 2 +#define NTB_MAX_DB_COUNT 32 +#define NTB_MW_OFFSET 2 + +enum pci_barno { + BAR_0, + BAR_1, + BAR_2, + BAR_3, + BAR_4, + BAR_5, +}; + +struct ntb_epf_dev { + struct ntb_dev ntb; + + enum pci_barno ctrl_reg_bar; + enum pci_barno peer_spad_reg_bar; + enum pci_barno db_reg_bar; + + unsigned int mw_count; + unsigned int spad_count; + unsigned int db_count; + + void __iomem *ctrl_reg; + void __iomem *db_reg; + void __iomem *peer_spad_reg; + + unsigned int self_spad; + unsigned int peer_spad; + + int db_val; + u64 db_valid_mask; +}; + +#define ntb_ndev(__ntb) container_of(__ntb, struct ntb_epf_dev, ntb) + +struct ntb_epf_data { + /* BAR that contains both control region and self spad region */ + enum pci_barno ctrl_reg_bar; + /* BAR that contains peer spad region */ + enum pci_barno peer_spad_reg_bar; + /* BAR that contains Doorbell region and Memory window '1' */ + enum pci_barno db_reg_bar; +}; + +static inline u32 ntb_epf_ctrl_readl(struct ntb_epf_dev *ndev, u32 offset) +{ + return readl(ndev->ctrl_reg + offset); +} + +static inline void ntb_epf_ctrl_writel(struct ntb_epf_dev *ndev, u32 offset, + u32 val) +{ + return writel(val, ndev->ctrl_reg + offset); +} + +static int ntb_epf_send_command(struct ntb_epf_dev *ndev, u32 command, + u32 argument) +{ + ktime_t timeout; + bool timedout; + u32 status; + + ntb_epf_ctrl_writel(ndev, NTB_EPF_ARGUMENT, argument); + ntb_epf_ctrl_writel(ndev, NTB_EPF_COMMAND, command); + + /* wait 50ms */ + timeout = ktime_add_ms(ktime_get(), 50); + while (1) { + timedout = ktime_after(ktime_get(), timeout); + status = ntb_epf_ctrl_readl(ndev, NTB_EPF_STATUS); + + if (status & COMMAND_STATUS_OK) + break; + + if (WARN_ON(timedout)) + return -ETIMEDOUT; + + usleep_range(5, 10); + } + + ntb_epf_ctrl_writel(ndev, NTB_EPF_STATUS, status & ~COMMAND_STATUS_OK); + + return 0; +} + +static int ntb_epf_mw_to_bar(struct ntb_epf_dev *ndev, int idx) +{ + if (idx < 0 || idx > ndev->mw_count) + return -EINVAL; + + return idx + 2; +} + +static int ntb_epf_mw_count(struct ntb_dev *ntb, int pidx) +{ + if (pidx != NTB_DEF_PEER_IDX) + return -EINVAL; + + return ntb_ndev(ntb)->mw_count; +} + +static int ntb_epf_mw_get_align(struct ntb_dev *ntb, int pidx, int idx, + resource_size_t *addr_align, + resource_size_t *size_align, + resource_size_t *size_max) +{ + struct ntb_epf_dev *ndev = ntb_ndev(ntb); + int bar; + + if (pidx != NTB_DEF_PEER_IDX) + return -EINVAL; + + bar = ntb_epf_mw_to_bar(ndev, idx); + if (bar < 0) + return bar; + + if (addr_align) + *addr_align = SZ_4K; + + if (size_align) + *size_align = 1; + + if (size_max) + *size_max = pci_resource_len(ndev->ntb.pdev, bar); + + return 0; +} + +static u64 ntb_epf_link_is_up(struct ntb_dev *ntb, + enum ntb_speed *speed, + enum ntb_width *width) +{ + struct ntb_epf_dev *ndev = ntb_ndev(ntb); + u32 status; + + status = ntb_epf_ctrl_readl(ndev, NTB_EPF_STATUS); + + return !!(status & LINK_STATUS_UP); +} + +static u32 ntb_epf_spad_read(struct ntb_dev *ntb, int idx) +{ + struct ntb_epf_dev *ndev = ntb_ndev(ntb); + u32 offset; + + if (idx < 0 || idx >= ndev->spad_count) + return 0; + + offset = ntb_epf_ctrl_readl(ndev, NTB_EPF_SPAD_OFFSET); + offset += (idx << 2); + + return ntb_epf_ctrl_readl(ndev, offset); +} + +static int ntb_epf_spad_write(struct ntb_dev *ntb, + int idx, u32 val) +{ + struct ntb_epf_dev *ndev = ntb_ndev(ntb); + u32 offset; + + if (idx < 0 || idx >= ndev->spad_count) + return -EINVAL; + + offset = ntb_epf_ctrl_readl(ndev, NTB_EPF_SPAD_OFFSET); + offset += (idx << 2); + ntb_epf_ctrl_writel(ndev, offset, val); + + return 0; +} + +static u32 ntb_epf_peer_spad_read(struct ntb_dev *ntb, int pidx, int idx) +{ + struct ntb_epf_dev *ndev = ntb_ndev(ntb); + u32 offset; + + if (idx < 0 || idx >= ndev->spad_count) + return -EINVAL; + + offset = (idx << 2); + return readl(ndev->peer_spad_reg + offset); +} + +static int ntb_epf_peer_spad_write(struct ntb_dev *ntb, int pidx, + int idx, u32 val) +{ + struct ntb_epf_dev *ndev = ntb_ndev(ntb); + u32 offset; + + if (idx < 0 || idx >= ndev->spad_count) + return -EINVAL; + + offset = (idx << 2); + writel(val, ndev->peer_spad_reg + offset); + + return 0; +} + +static int ntb_epf_link_enable(struct ntb_dev *ntb, + enum ntb_speed max_speed, + enum ntb_width max_width) +{ + struct ntb_epf_dev *ndev = ntb_ndev(ntb); + struct device *dev = &ntb->pdev->dev; + int ret; + + ret = ntb_epf_send_command(ndev, CMD_LINK_UP, 0); + if (ret) { + dev_err(dev, "Fail to enable link\n"); + return ret; + } + + return 0; +} + +static int ntb_epf_link_disable(struct ntb_dev *ntb) +{ + return 0; +} + +static irqreturn_t ndev_vec_isr(int irq, void *dev) +{ + struct ntb_epf_dev *ndev = dev; + int irq_no; + + irq_no = irq - ndev->ntb.pdev->irq; + ndev->db_val = irq_no + 1; + + if (irq_no == 0) + ntb_link_event(&ndev->ntb); + else + ntb_db_event(&ndev->ntb, irq_no); + + return IRQ_HANDLED; +} + +static int ntb_epf_init_isr(struct ntb_epf_dev *ndev, int msi_min, int msi_max) +{ + struct pci_dev *pdev = ndev->ntb.pdev; + struct device *dev = &pdev->dev; + int irq; + int ret; + int i; + + irq = pci_alloc_irq_vectors(pdev, msi_min, msi_max, PCI_IRQ_MSI); + if (irq < 0) { + dev_err(dev, "Failed to get MSI interrupts\n"); + return irq; + } + + for (i = 0; i < irq; i++) { + ret = devm_request_irq(&pdev->dev, pci_irq_vector(pdev, i), + ndev_vec_isr, IRQF_SHARED, "ntb_epf", + ndev); + if (ret) { + dev_err(dev, "Failed to request irq\n"); + goto err_request_irq; + } + } + + ndev->db_count = irq; + + ret = ntb_epf_send_command(ndev, CMD_CONFIGURE_DOORBELL, irq); + if (ret) { + dev_err(dev, "Failed to configure doorbell\n"); + goto err_request_irq; + } + + return 0; + +err_request_irq: + pci_free_irq_vectors(pdev); + + return ret; +} + +static int ntb_epf_peer_mw_count(struct ntb_dev *ntb) +{ + return ntb_ndev(ntb)->mw_count; +} + +static int ntb_epf_spad_count(struct ntb_dev *ntb) +{ + return ntb_ndev(ntb)->spad_count; +} + +static u64 ntb_epf_db_valid_mask(struct ntb_dev *ntb) +{ + return ntb_ndev(ntb)->db_valid_mask; +} + +static int ntb_epf_db_set_mask(struct ntb_dev *ntb, u64 db_bits) +{ + return 0; +} + +static int ntb_epf_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx, + dma_addr_t addr, resource_size_t size) +{ + struct ntb_epf_dev *ndev = ntb_ndev(ntb); + struct device *dev = &ntb->pdev->dev; + resource_size_t mw_size; + int bar; + + if (pidx != NTB_DEF_PEER_IDX) + return -EINVAL; + + bar = idx + NTB_MW_OFFSET; + + mw_size = pci_resource_len(ntb->pdev, bar); + + if (size > mw_size) { + dev_err(dev, "Size is greater than the MW size\n"); + return -EINVAL; + } + + ntb_epf_ctrl_writel(ndev, NTB_EPF_ADDR, addr); + ntb_epf_ctrl_writel(ndev, NTB_EPF_SIZE, size); + ntb_epf_send_command(ndev, CMD_CONFIGURE_MW, idx); + + return 0; +} + +static int ntb_epf_peer_mw_get_addr(struct ntb_dev *ntb, int idx, + phys_addr_t *base, resource_size_t *size) +{ + struct ntb_epf_dev *ndev = ntb_ndev(ntb); + u32 offset = 0; + int bar; + + if (idx == 0) + offset = ntb_epf_ctrl_readl(ndev, NTB_EPF_MW1_OFFSET); + + bar = idx + NTB_MW_OFFSET; + + if (base) + *base = pci_resource_start(ndev->ntb.pdev, bar) + offset; + + if (size) + *size = pci_resource_len(ndev->ntb.pdev, bar) - offset; + + return 0; +} + +static int ntb_epf_peer_db_set(struct ntb_dev *ntb, u64 db_bits) +{ + struct ntb_epf_dev *ndev = ntb_ndev(ntb); + u32 interrupt_num = ffs(db_bits) + 1; + u32 db_entry_size; + u32 db_data; + + if (interrupt_num > ndev->db_count) + return -EINVAL; + + db_entry_size = ntb_epf_ctrl_readl(ndev, NTB_EPF_DB_ENTRY_SIZE); + + db_data = readl(ndev->ctrl_reg + NTB_EPF_DB_DATA(interrupt_num)); + writel(db_data, ndev->db_reg + (db_entry_size * interrupt_num)); + + return 0; +} + +static u64 ntb_epf_db_read(struct ntb_dev *ntb) +{ + struct ntb_epf_dev *ndev = ntb_ndev(ntb); + + return ndev->db_val; +} + +static int ntb_epf_db_clear_mask(struct ntb_dev *ntb, u64 db_bits) +{ + return 0; +} + +static int ntb_epf_db_clear(struct ntb_dev *ntb, u64 db_bits) +{ + struct ntb_epf_dev *ndev = ntb_ndev(ntb); + + ndev->db_val = 0; + + return 0; +} + +static const struct ntb_dev_ops ntb_epf_ops = { + .mw_count = ntb_epf_mw_count, + .spad_count = ntb_epf_spad_count, + .peer_mw_count = ntb_epf_peer_mw_count, + .db_valid_mask = ntb_epf_db_valid_mask, + .db_set_mask = ntb_epf_db_set_mask, + .mw_set_trans = ntb_epf_mw_set_trans, + .peer_mw_get_addr = ntb_epf_peer_mw_get_addr, + .link_enable = ntb_epf_link_enable, + .spad_read = ntb_epf_spad_read, + .spad_write = ntb_epf_spad_write, + .peer_spad_read = ntb_epf_peer_spad_read, + .peer_spad_write = ntb_epf_peer_spad_write, + .peer_db_set = ntb_epf_peer_db_set, + .db_read = ntb_epf_db_read, + .mw_get_align = ntb_epf_mw_get_align, + .link_is_up = ntb_epf_link_is_up, + .db_clear_mask = ntb_epf_db_clear_mask, + .db_clear = ntb_epf_db_clear, + .link_disable = ntb_epf_link_disable, +}; + +static inline void ntb_epf_init_struct(struct ntb_epf_dev *ndev, + struct pci_dev *pdev) +{ + ndev->ntb.pdev = pdev; + ndev->ntb.topo = NTB_TOPO_NONE; + ndev->ntb.ops = &ntb_epf_ops; +} + +static int ntb_epf_init_dev(struct ntb_epf_dev *ndev) +{ + struct pci_dev *pdev = ndev->ntb.pdev; + struct device *dev = &pdev->dev; + int ret; + + ret = ntb_epf_init_isr(ndev, NTB_MIN_DB_COUNT, NTB_MAX_DB_COUNT); + if (ret) { + dev_err(dev, "Failed to init ISR\n"); + return ret; + } + + ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1; + ndev->mw_count = ntb_epf_ctrl_readl(ndev, NTB_EPF_MW_COUNT); + ndev->spad_count = ntb_epf_ctrl_readl(ndev, NTB_EPF_SPAD_COUNT); + + return 0; +} + +static int ntb_epf_init_pci(struct ntb_epf_dev *ndev, + struct pci_dev *pdev) +{ + struct device *dev = &pdev->dev; + int ret; + + pci_set_drvdata(pdev, ndev); + + ret = pci_enable_device(pdev); + if (ret) { + dev_err(dev, "Cannot enable PCI device\n"); + goto err_pci_enable; + } + + ret = pci_request_regions(pdev, "ntb"); + if (ret) { + dev_err(dev, "Cannot obtain PCI resources\n"); + goto err_pci_regions; + } + + pci_set_master(pdev); + + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); + if (ret) { + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); + if (ret) { + dev_err(dev, "Cannot set DMA mask\n"); + goto err_dma_mask; + } + dev_warn(&pdev->dev, "Cannot DMA highmem\n"); + } + + ret = dma_coerce_mask_and_coherent(&ndev->ntb.dev, + dma_get_mask(&pdev->dev)); + if (ret) { + dev_err(dev, "Cannot set DMA mask\n"); + goto err_dma_mask; + } + + ndev->ctrl_reg = pci_iomap(pdev, 0, 0); + if (!ndev->ctrl_reg) { + ret = -EIO; + goto err_dma_mask; + } + + ndev->peer_spad_reg = pci_iomap(pdev, 1, 0); + if (!ndev->peer_spad_reg) { + ret = -EIO; + goto err_dma_mask; + } + + ndev->db_reg = pci_iomap(pdev, 2, 0); + if (!ndev->db_reg) { + ret = -EIO; + goto err_dma_mask; + } + + return 0; + +err_dma_mask: + pci_clear_master(pdev); + +err_pci_regions: + pci_disable_device(pdev); + +err_pci_enable: + pci_set_drvdata(pdev, NULL); + + return ret; +} + +static void ntb_epf_deinit_pci(struct ntb_epf_dev *ndev) +{ + struct pci_dev *pdev = ndev->ntb.pdev; + + pci_iounmap(pdev, ndev->ctrl_reg); + pci_iounmap(pdev, ndev->peer_spad_reg); + pci_iounmap(pdev, ndev->db_reg); + + pci_clear_master(pdev); + pci_release_regions(pdev); + pci_disable_device(pdev); + pci_set_drvdata(pdev, NULL); +} + +static int ntb_epf_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + enum pci_barno peer_spad_reg_bar = BAR_1; + enum pci_barno ctrl_reg_bar = BAR_0; + enum pci_barno db_reg_bar = BAR_2; + struct device *dev = &pdev->dev; + struct ntb_epf_data *data; + struct ntb_epf_dev *ndev; + int ret; + + ndev = devm_kzalloc(dev, sizeof(*ndev), GFP_KERNEL); + if (!ndev) + return -ENOMEM; + + data = (struct ntb_epf_data *)id->driver_data; + if (data) { + if (data->peer_spad_reg_bar) + peer_spad_reg_bar = data->peer_spad_reg_bar; + if (data->ctrl_reg_bar) + ctrl_reg_bar = data->ctrl_reg_bar; + if (data->db_reg_bar) + db_reg_bar = data->db_reg_bar; + } + + ndev->peer_spad_reg_bar = peer_spad_reg_bar; + ndev->ctrl_reg_bar = ctrl_reg_bar; + ndev->db_reg_bar = db_reg_bar; + + ntb_epf_init_struct(ndev, pdev); + + ret = ntb_epf_init_pci(ndev, pdev); + if (ret) { + dev_err(dev, "Failed to init PCI\n"); + return ret; + } + + ret = ntb_epf_init_dev(ndev); + if (ret) { + dev_err(dev, "Failed to init device\n"); + goto err_init_dev; + } + + ret = ntb_register_device(&ndev->ntb); + if (ret) { + dev_err(dev, "Failed to register NTB device\n"); + goto err_register_dev; + } + + return 0; + +err_register_dev: + pci_free_irq_vectors(pdev); + +err_init_dev: + ntb_epf_deinit_pci(ndev); + + return ret; +} + +static void ntb_epf_pci_remove(struct pci_dev *pdev) +{ + struct ntb_epf_dev *ndev = pci_get_drvdata(pdev); + + ntb_unregister_device(&ndev->ntb); + pci_free_irq_vectors(pdev); + kfree(ndev); +} + +static const struct ntb_epf_data j721e_data = { + .ctrl_reg_bar = BAR_0, + .peer_spad_reg_bar = BAR_1, + .db_reg_bar = BAR_2, +}; + +static const struct pci_device_id ntb_epf_pci_tbl[] = { + { + PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E), + .driver_data = (kernel_ulong_t)&j721e_data, + }, + { }, +}; +MODULE_DEVICE_TABLE(pci, ntb_epf_pci_tbl); + +static struct pci_driver ntb_epf_pci_driver = { + .name = KBUILD_MODNAME, + .id_table = ntb_epf_pci_tbl, + .probe = ntb_epf_pci_probe, + .remove = ntb_epf_pci_remove, +}; +module_pci_driver(ntb_epf_pci_driver); + +MODULE_DESCRIPTION("PCI ENDPOINT NTB HOST DRIVER"); +MODULE_AUTHOR("Kishon Vijay Abraham I "); +MODULE_LICENSE("GPL v2");