From patchwork Tue Feb 27 15:53:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mukesh Ojha X-Patchwork-Id: 776323 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACE291474B0; Tue, 27 Feb 2024 15:53:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709049217; cv=none; b=NbYEMzAZKdHhuHKFpwTGudBDl6xYmWfN/6vs8AfD20ZqE9gPtFTHTBmHSz3SiD2N2RtXQ+gOAHdmfYwKErIJu5YbhTZdd/4yMxAY+tzwlCoQxke+IqyFHIWn7V4qFSCT8an+y8HIFBn3iWa9l+2uy6q9tvMYZdFxVwvTwbVHBXM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709049217; c=relaxed/simple; bh=sQ2CJTGlHNoB9WmLGpGyTeqk7Y9gIegE3u6Fo9P3dpw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SwfX7iXW9bijG/iKReOPWXo59T80pmoIdobQSsFCx/zwSCzRNWQbtA4tlYMZOs7bYlAPjPXwgWV8go1e7HqbJCdCeEJwq7rTTrsHcTBKczDg1o73yzeKwjgWAnv+7dSmxU07Oa1CG+gY+q3ql7G2KlBiPkzhee+1yOStw3+4p98= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=NpZBAkLR; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="NpZBAkLR" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41R9XvuI030790; Tue, 27 Feb 2024 15:53:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=CY0FaMU4wnVsLsp43Ffy9Z005ivffcYHL55Q9T5ds0I=; b=Np ZBAkLRKQPHL+rMvc8JN7dZZkQV9HtRU10KNyuMxJcdj82No1iSgVKKCRBt+ELkU8 XoOnEGSQDM75/zgrrd3tIsWEIEcBjARNePMNhFcKWiEfu+x+GWtFYEGrQ68cvqlp K7+YnTIx1OasNHjvOOWc7GoPSFNaHr8QM2D8QP+zDlTynmL6ZNlT11HJKjiO9CwF 7DzulVGXpZzp/fpWUefJt1VhN7hdf8B1xmeO7ntv2X23Eyg/743AoO5vp+FRYIb0 jHYFe3M3PCmsjN1ygEUjTim5/Y2E+CJ1j/nggchstG5XENARbDVSnTKgbOUlC4Qz caqrlBmFdkRLtphramtg== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3wh6nrhqvq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Feb 2024 15:53:32 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41RFrVOF028519 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Feb 2024 15:53:31 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 27 Feb 2024 07:53:28 -0800 From: Mukesh Ojha To: , CC: , , , , Mukesh Ojha Subject: [PATCH v12 1/9] firmware: qcom: scm: Rename scm_query_lock to scm_lock Date: Tue, 27 Feb 2024 21:23:00 +0530 Message-ID: <20240227155308.18395-2-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.43.0.254.ga26002b62827 In-Reply-To: <20240227155308.18395-1-quic_mojha@quicinc.com> References: <20240227155308.18395-1-quic_mojha@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 4n1UIskjC0S9WQu48wQhmjLTyl4s4iLX X-Proofpoint-ORIG-GUID: 4n1UIskjC0S9WQu48wQhmjLTyl4s4iLX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-27_01,2024-02-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 phishscore=0 clxscore=1015 suspectscore=0 bulkscore=0 adultscore=0 malwarescore=0 mlxlogscore=999 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402270123 scm_query_lock is global spin lock and only used for query purpose with trustzone and that too for one time to get the convention of scm communication. It is possible that, it can reused for other purpose. Rename scm_query_lock to scm_lock. Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 520de9b5633a..2d0ba529cf56 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -193,7 +193,7 @@ static void qcom_scm_bw_disable(void) } enum qcom_scm_convention qcom_scm_convention = SMC_CONVENTION_UNKNOWN; -static DEFINE_SPINLOCK(scm_query_lock); +static DEFINE_SPINLOCK(scm_lock); static enum qcom_scm_convention __get_convention(void) { @@ -250,14 +250,14 @@ static enum qcom_scm_convention __get_convention(void) probed_convention = SMC_CONVENTION_LEGACY; found: - spin_lock_irqsave(&scm_query_lock, flags); + spin_lock_irqsave(&scm_lock, flags); if (probed_convention != qcom_scm_convention) { qcom_scm_convention = probed_convention; pr_info("qcom_scm: convention: %s%s\n", qcom_scm_convention_names[qcom_scm_convention], forced ? " (forced)" : ""); } - spin_unlock_irqrestore(&scm_query_lock, flags); + spin_unlock_irqrestore(&scm_lock, flags); return qcom_scm_convention; } From patchwork Tue Feb 27 15:53:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mukesh Ojha X-Patchwork-Id: 776602 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32582146012; Tue, 27 Feb 2024 15:53:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709049220; cv=none; b=aIXSjkCslx14CfMSDeS0D0mPeqK971+ItaVmjPjvb0cTQyS8Y2Nwhb+1avyGcZV79NbAmrnNzhnwFMpYsCaQ4avf5CBHBgL3qm4H9IQTpYKT+7+Ysg6rhE+Wr1JsEl6/Hala7yijBBEJKPFIUs9QsrhqwK20RbA1nPoTlYgjiSY= ARC-Message-Signature: i=1; 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Tue, 27 Feb 2024 15:53:34 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 27 Feb 2024 07:53:31 -0800 From: Mukesh Ojha To: , CC: , , , , Mukesh Ojha , Srinivas Kandagatla , Kathiravan Thirumoorthy Subject: [PATCH v12 2/9] firmware: qcom: scm: provide a read-modify-write function Date: Tue, 27 Feb 2024 21:23:01 +0530 Message-ID: <20240227155308.18395-3-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.43.0.254.ga26002b62827 In-Reply-To: <20240227155308.18395-1-quic_mojha@quicinc.com> References: <20240227155308.18395-1-quic_mojha@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: aSHyXBmahNJyxya09-AOGp953LnYpJp1 X-Proofpoint-GUID: aSHyXBmahNJyxya09-AOGp953LnYpJp1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-27_01,2024-02-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1011 bulkscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 mlxlogscore=910 priorityscore=1501 adultscore=0 phishscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402270123 It is possible that different bits of a secure register is used for different purpose and currently, there is no such available function from SCM driver to do that; one similar usage was pointed by Srinivas K. inside pinctrl-msm where interrupt configuration register lying in secure region and written via read-modify-write operation. Export qcom_scm_io_rmw() to do read-modify-write operation on secure register and reuse it wherever applicable, also document scm_lock to convey its usage. Suggested-by: Srinivas Kandagatla Signed-off-by: Mukesh Ojha Tested-by: Kathiravan Thirumoorthy # IPQ9574 and IPQ5332 --- drivers/firmware/qcom/qcom_scm.c | 33 ++++++++++++++++++++++++++ include/linux/firmware/qcom/qcom_scm.h | 1 + 2 files changed, 34 insertions(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 2d0ba529cf56..8f766fce5f7c 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -193,6 +193,11 @@ static void qcom_scm_bw_disable(void) } enum qcom_scm_convention qcom_scm_convention = SMC_CONVENTION_UNKNOWN; +/* + * scm_lock to serialize call to query SMC convention and + * to atomically operate(read-modify-write) on different + * bits of secure register. + */ static DEFINE_SPINLOCK(scm_lock); static enum qcom_scm_convention __get_convention(void) @@ -481,6 +486,34 @@ static int qcom_scm_disable_sdi(void) return ret ? : res.result[0]; } +int qcom_scm_io_rmw(phys_addr_t addr, unsigned int mask, unsigned int val) +{ + unsigned long flags; + unsigned int old; + unsigned int new; + int ret; + + if (!__scm) + return -EPROBE_DEFER; + + /* + * Lock to atomically do rmw operation on different bits + * of secure register + */ + spin_lock_irqsave(&scm_lock, flags); + ret = qcom_scm_io_readl(addr, &old); + if (ret) + goto unlock; + + new = (old & ~mask) | (val & mask); + + ret = qcom_scm_io_writel(addr, new); +unlock: + spin_unlock_irqrestore(&scm_lock, flags); + return ret; +} +EXPORT_SYMBOL_GPL(qcom_scm_io_rmw); + static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) { struct qcom_scm_desc desc = { diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index ccaf28846054..3a8bb2e603b3 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -82,6 +82,7 @@ bool qcom_scm_pas_supported(u32 peripheral); int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); +int qcom_scm_io_rmw(phys_addr_t addr, unsigned int mask, unsigned int val); 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Tue, 27 Feb 2024 15:53:37 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 27 Feb 2024 07:53:34 -0800 From: Mukesh Ojha To: , CC: , , , , Mukesh Ojha , Poovendhan Selvaraj , Kathiravan Thirumoorthy , Dmitry Baryshkov , Elliot Berman Subject: [PATCH v12 3/9] firmware: qcom: scm: Modify only the download bits in TCSR register Date: Tue, 27 Feb 2024 21:23:02 +0530 Message-ID: <20240227155308.18395-4-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.43.0.254.ga26002b62827 In-Reply-To: <20240227155308.18395-1-quic_mojha@quicinc.com> References: <20240227155308.18395-1-quic_mojha@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: MR5MoUEM4sVeJM8UpoTgttk7pznD7OVU X-Proofpoint-GUID: MR5MoUEM4sVeJM8UpoTgttk7pznD7OVU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-27_01,2024-02-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 bulkscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 adultscore=0 phishscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402270123 Crashdump collection is done based on DLOAD bits of TCSR register. To retain other bits, scm driver need to read the register and modify only the DLOAD bits, as other bits in TCSR may have their own significance. Co-developed-by: Poovendhan Selvaraj Signed-off-by: Poovendhan Selvaraj Signed-off-by: Mukesh Ojha Tested-by: Kathiravan Thirumoorthy # IPQ9574 and IPQ5332 Reviewed-by: Dmitry Baryshkov Reviewed-by: Elliot Berman --- drivers/firmware/qcom/qcom_scm.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 8f766fce5f7c..bd6bfdf2d828 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -4,6 +4,8 @@ */ #include +#include +#include #include #include #include @@ -114,6 +116,12 @@ static const u8 qcom_scm_cpu_warm_bits[QCOM_SCM_BOOT_MAX_CPUS] = { #define QCOM_SMC_WAITQ_FLAG_WAKE_ONE BIT(0) #define QCOM_SMC_WAITQ_FLAG_WAKE_ALL BIT(1) +#define QCOM_DLOAD_MASK GENMASK(5, 4) +enum qcom_dload_mode { + QCOM_DLOAD_NODUMP = 0, + QCOM_DLOAD_FULLDUMP = 1, +}; + static const char * const qcom_scm_convention_names[] = { [SMC_CONVENTION_UNKNOWN] = "unknown", [SMC_CONVENTION_ARM_32] = "smc arm 32", @@ -531,6 +539,7 @@ static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) static void qcom_scm_set_download_mode(bool enable) { + u32 val = enable ? QCOM_DLOAD_FULLDUMP : QCOM_DLOAD_NODUMP; bool avail; int ret = 0; @@ -540,8 +549,9 @@ static void qcom_scm_set_download_mode(bool enable) if (avail) { ret = __qcom_scm_set_dload_mode(__scm->dev, enable); } else if (__scm->dload_mode_addr) { - ret = qcom_scm_io_writel(__scm->dload_mode_addr, - enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); + ret = qcom_scm_io_rmw(__scm->dload_mode_addr, + QCOM_DLOAD_MASK, + FIELD_PREP(QCOM_DLOAD_MASK, val)); } else { dev_err(__scm->dev, "No available mechanism for setting download mode\n"); From patchwork Tue Feb 27 15:53:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mukesh Ojha X-Patchwork-Id: 776601 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AAA57149000; Tue, 27 Feb 2024 15:53:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709049227; cv=none; b=rm7XwQTeiI72bnT9PSfO/RBJu7trW+UeBk12piJSym/CvlNYbLS8j/b/P2UhzG+tLG+9BDJCUuxFHM2/a11o9MnbfWYv2kIaYGV2ExS4n0MhkAig5tF6AvYIqKb2ajb/hWW4ktcSue9wbjl659LpsRbQRsm4Sqx6P78WV4FnL6E= ARC-Message-Signature: i=1; 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Tue, 27 Feb 2024 15:53:40 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 27 Feb 2024 07:53:38 -0800 From: Mukesh Ojha To: , CC: , , , , Mukesh Ojha , Elliot Berman Subject: [PATCH v12 4/9] firmware: qcom: scm: Rework dload mode availability check Date: Tue, 27 Feb 2024 21:23:03 +0530 Message-ID: <20240227155308.18395-5-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.43.0.254.ga26002b62827 In-Reply-To: <20240227155308.18395-1-quic_mojha@quicinc.com> References: <20240227155308.18395-1-quic_mojha@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: _uvA-hwPGXA3AiF7huwTShQtsp5GOOGL X-Proofpoint-GUID: _uvA-hwPGXA3AiF7huwTShQtsp5GOOGL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-27_01,2024-02-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 mlxscore=0 phishscore=0 adultscore=0 spamscore=0 impostorscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402270123 QCOM_SCM_BOOT_SET_DLOAD_MODE was only valid for very older target and firmware and for recent targets there is dload mode tcsr registers available to set the download mode. So, it is better to keep it as fallback check instead of checking its availability and failing it always. Signed-off-by: Mukesh Ojha Reviewed-by: Elliot Berman --- drivers/firmware/qcom/qcom_scm.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index bd6bfdf2d828..3fd89cddba3b 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -540,18 +540,16 @@ static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) static void qcom_scm_set_download_mode(bool enable) { u32 val = enable ? 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Tue, 27 Feb 2024 15:53:44 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41RFrhjS028712 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Feb 2024 15:53:43 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 27 Feb 2024 07:53:41 -0800 From: Mukesh Ojha To: , CC: , , , , Mukesh Ojha Subject: [PATCH v12 5/9] pinctrl: qcom: Use qcom_scm_io_rmw() function Date: Tue, 27 Feb 2024 21:23:04 +0530 Message-ID: <20240227155308.18395-6-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.43.0.254.ga26002b62827 In-Reply-To: <20240227155308.18395-1-quic_mojha@quicinc.com> References: <20240227155308.18395-1-quic_mojha@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: kBVG0DAQQiBnusn7Yhm6ROiLjrCfJjI4 X-Proofpoint-GUID: kBVG0DAQQiBnusn7Yhm6ROiLjrCfJjI4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-27_01,2024-02-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 mlxlogscore=719 clxscore=1015 suspectscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 spamscore=0 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402270123 Use qcom_scm_io_rmw() exported function in pinctrl-msm driver. Signed-off-by: Mukesh Ojha Acked-by: Linus Walleij --- @Linus.Walleij, I have removed your Ack on this patch after your comment on https://lore.kernel.org/lkml/CACRpkdbnj3W3k=snTx3iadHWU+RNv9GY4B3O4K0hu8TY+DrK=Q@mail.gmail.com/ If you agree on the current solution, please ack this again. drivers/pinctrl/qcom/pinctrl-msm.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index aeaf0d1958f5..1bd5c8c43fcd 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -1082,22 +1082,20 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) if (g->intr_target_width) intr_target_mask = GENMASK(g->intr_target_width - 1, 0); + intr_target_mask <<= g->intr_target_bit; if (pctrl->intr_target_use_scm) { u32 addr = pctrl->phys_base[0] + g->intr_target_reg; int ret; - qcom_scm_io_readl(addr, &val); - val &= ~(intr_target_mask << g->intr_target_bit); - val |= g->intr_target_kpss_val << g->intr_target_bit; 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WARNING: Possible unnecessary 'out of memory' message + if (!mdata_buf) { + dev_err(__scm->dev, "Allocation of metadata buffer failed.\n"); Signed-off-by: Mukesh Ojha Reviewed-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_scm.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 3fd89cddba3b..6c252cddd44e 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -598,10 +598,9 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size, */ mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys, GFP_KERNEL); - if (!mdata_buf) { - dev_err(__scm->dev, "Allocation of metadata buffer failed.\n"); + if (!mdata_buf) return -ENOMEM; - } + memcpy(mdata_buf, metadata, size); ret = qcom_scm_clk_enable(); From patchwork Tue Feb 27 15:53:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mukesh Ojha X-Patchwork-Id: 776320 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0E0314A4E0; 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Tue, 27 Feb 2024 15:53:49 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41RFrmRa000472 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Feb 2024 15:53:48 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 27 Feb 2024 07:53:46 -0800 From: Mukesh Ojha To: , CC: , , , , Mukesh Ojha Subject: [PATCH v12 7/9] firmware: qcom: scm: Fix __scm->dev assignement Date: Tue, 27 Feb 2024 21:23:06 +0530 Message-ID: <20240227155308.18395-8-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.43.0.254.ga26002b62827 In-Reply-To: <20240227155308.18395-1-quic_mojha@quicinc.com> References: <20240227155308.18395-1-quic_mojha@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: OxoyHR36EaGPMTU2SDlkdk8ZqNJP6E5g X-Proofpoint-GUID: OxoyHR36EaGPMTU2SDlkdk8ZqNJP6E5g X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-27_01,2024-02-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 clxscore=1015 impostorscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402270123 qcom_scm_is_available() gives wrong indication if __scm is initialized but __scm->dev is not. Fix this appropriately by making sure if __scm is initialized and then it is associated with its device. Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 6c252cddd44e..6f14254c0c10 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -1859,6 +1859,7 @@ static int qcom_scm_probe(struct platform_device *pdev) if (!scm) return -ENOMEM; + scm->dev = &pdev->dev; ret = qcom_scm_find_dload_address(&pdev->dev, &scm->dload_mode_addr); if (ret < 0) return ret; @@ -1895,7 +1896,6 @@ static int qcom_scm_probe(struct platform_device *pdev) return ret; __scm = scm; - __scm->dev = &pdev->dev; init_completion(&__scm->waitq_comp); From patchwork Tue Feb 27 15:53:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mukesh Ojha X-Patchwork-Id: 776599 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C81E314AD08; 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Tue, 27 Feb 2024 15:53:52 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41RFrpeH000509 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Feb 2024 15:53:51 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 27 Feb 2024 07:53:49 -0800 From: Mukesh Ojha To: , CC: , , , , Mukesh Ojha Subject: [PATCH v12 8/9] firmware: qcom: scm: Add check to prevent Null pointer dereference Date: Tue, 27 Feb 2024 21:23:07 +0530 Message-ID: <20240227155308.18395-9-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.43.0.254.ga26002b62827 In-Reply-To: <20240227155308.18395-1-quic_mojha@quicinc.com> References: <20240227155308.18395-1-quic_mojha@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: fyPuyRGHGIXIzs5iAnHf6unKLxvVSn0I X-Proofpoint-GUID: fyPuyRGHGIXIzs5iAnHf6unKLxvVSn0I X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-27_01,2024-02-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 bulkscore=0 suspectscore=0 phishscore=0 malwarescore=0 mlxscore=0 lowpriorityscore=0 adultscore=0 mlxlogscore=999 clxscore=1015 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402270122 There are multiple place in SCM driver __scm->dev is being accessed without checking if it is valid or not and all not all of function needs the device but it is needed for some cases when the number of argument passed is more and dma_map_single () api is used. Add a NULL check for the cases when it is fine even to pass device as NULL and add qcom_scm_is_available() check for cases when it is needed for DMA api's. Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 88 ++++++++++++++++++++++++-------- 1 file changed, 66 insertions(+), 22 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 6f14254c0c10..a1dce417e6ec 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -465,7 +465,7 @@ int qcom_scm_set_remote_state(u32 state, u32 id) struct qcom_scm_res res; int ret; - ret = qcom_scm_call(__scm->dev, &desc, &res); + ret = qcom_scm_call(__scm ? __scm->dev : NULL, &desc, &res); return ret ? : res.result[0]; } @@ -591,6 +591,9 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size, }; struct qcom_scm_res res; + if (!qcom_scm_is_available()) + return -EPROBE_DEFER; + /* * During the scm call memory protection will be enabled for the meta * data blob, so make sure it's physically contiguous, 4K aligned and @@ -637,6 +640,9 @@ EXPORT_SYMBOL_GPL(qcom_scm_pas_init_image); */ void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx) { + if (!qcom_scm_is_available()) + return -EPROBE_DEFER; + if (!ctx->ptr) return; @@ -671,6 +677,9 @@ int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size) }; struct qcom_scm_res res; + if (!qcom_scm_is_available()) + return -EPROBE_DEFER; + ret = qcom_scm_clk_enable(); if (ret) return ret; @@ -706,6 +715,9 @@ int qcom_scm_pas_auth_and_reset(u32 peripheral) }; struct qcom_scm_res res; + if (!qcom_scm_is_available()) + return -EPROBE_DEFER; + ret = qcom_scm_clk_enable(); if (ret) return ret; @@ -740,6 +752,9 @@ int qcom_scm_pas_shutdown(u32 peripheral) }; struct qcom_scm_res res; + if (!qcom_scm_is_available()) + return -EPROBE_DEFER; + ret = qcom_scm_clk_enable(); if (ret) return ret; @@ -776,11 +791,11 @@ bool qcom_scm_pas_supported(u32 peripheral) }; struct qcom_scm_res res; - if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, + if (!__qcom_scm_is_call_available(__scm ? __scm->dev : NULL, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_IS_SUPPORTED)) return false; - ret = qcom_scm_call(__scm->dev, &desc, &res); + ret = qcom_scm_call(__scm ? __scm->dev : NULL, &desc, &res); return ret ? false : !!res.result[0]; } @@ -840,7 +855,7 @@ int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) int ret; - ret = qcom_scm_call_atomic(__scm->dev, &desc, &res); + ret = qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, &res); if (ret >= 0) *val = res.result[0]; @@ -859,7 +874,7 @@ int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) .owner = ARM_SMCCC_OWNER_SIP, }; - return qcom_scm_call_atomic(__scm->dev, &desc, NULL); + return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL); } EXPORT_SYMBOL_GPL(qcom_scm_io_writel); @@ -871,7 +886,8 @@ EXPORT_SYMBOL_GPL(qcom_scm_io_writel); */ bool qcom_scm_restore_sec_cfg_available(void) { - return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP, + return __qcom_scm_is_call_available(__scm ? __scm->dev : NULL, + QCOM_SCM_SVC_MP, QCOM_SCM_MP_RESTORE_SEC_CFG); } EXPORT_SYMBOL_GPL(qcom_scm_restore_sec_cfg_available); @@ -889,7 +905,7 @@ int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) struct qcom_scm_res res; int ret; - ret = qcom_scm_call(__scm->dev, &desc, &res); + ret = qcom_scm_call(__scm ? __scm->dev : NULL, &desc, &res); return ret ? : res.result[0]; } @@ -907,7 +923,7 @@ int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) struct qcom_scm_res res; int ret; - ret = qcom_scm_call(__scm->dev, &desc, &res); + ret = qcom_scm_call(__scm ? __scm->dev : NULL, &desc, &res); if (size) *size = res.result[0]; @@ -930,7 +946,7 @@ int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) }; int ret; - ret = qcom_scm_call(__scm->dev, &desc, NULL); + ret = qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL); /* the pg table has been initialized already, ignore the error */ if (ret == -EPERM) @@ -951,7 +967,7 @@ int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size) .owner = ARM_SMCCC_OWNER_SIP, }; - return qcom_scm_call(__scm->dev, &desc, NULL); + return qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL); } EXPORT_SYMBOL_GPL(qcom_scm_iommu_set_cp_pool_size); @@ -973,7 +989,7 @@ int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size, }; struct qcom_scm_res res; - ret = qcom_scm_call(__scm->dev, &desc, &res); + ret = qcom_scm_call(__scm ? __scm->dev : NULL, &desc, &res); return ret ? : res.result[0]; } @@ -1038,6 +1054,9 @@ int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, int ret, i, b; u64 srcvm_bits = *srcvm; + if (!qcom_scm_is_available()) + return -EPROBE_DEFER; + src_sz = hweight64(srcvm_bits) * sizeof(*src); mem_to_map_sz = sizeof(*mem_to_map); dest_sz = dest_cnt * sizeof(*destvm); @@ -1093,7 +1112,8 @@ EXPORT_SYMBOL_GPL(qcom_scm_assign_mem); */ bool qcom_scm_ocmem_lock_available(void) { - return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_OCMEM, + return __qcom_scm_is_call_available(__scm ? __scm->dev : NULL, + QCOM_SCM_SVC_OCMEM, QCOM_SCM_OCMEM_LOCK_CMD); } EXPORT_SYMBOL_GPL(qcom_scm_ocmem_lock_available); @@ -1120,7 +1140,7 @@ int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size, .arginfo = QCOM_SCM_ARGS(4), }; - return qcom_scm_call(__scm->dev, &desc, NULL); + return qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL); } EXPORT_SYMBOL_GPL(qcom_scm_ocmem_lock); @@ -1143,7 +1163,7 @@ int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size) .arginfo = QCOM_SCM_ARGS(3), }; - return qcom_scm_call(__scm->dev, &desc, NULL); + return qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL); } EXPORT_SYMBOL_GPL(qcom_scm_ocmem_unlock); @@ -1155,9 +1175,11 @@ EXPORT_SYMBOL_GPL(qcom_scm_ocmem_unlock); */ bool qcom_scm_ice_available(void) { - return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES, + return __qcom_scm_is_call_available(__scm ? __scm->dev : NULL, + QCOM_SCM_SVC_ES, QCOM_SCM_ES_INVALIDATE_ICE_KEY) && - __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES, + __qcom_scm_is_call_available(__scm ?__scm->dev : NULL, + QCOM_SCM_SVC_ES, QCOM_SCM_ES_CONFIG_SET_ICE_KEY); } EXPORT_SYMBOL_GPL(qcom_scm_ice_available); @@ -1184,7 +1206,7 @@ int qcom_scm_ice_invalidate_key(u32 index) .owner = ARM_SMCCC_OWNER_SIP, }; - return qcom_scm_call(__scm->dev, &desc, NULL); + return qcom_scm_call(__scm ?__scm->dev : NULL, &desc, NULL); } EXPORT_SYMBOL_GPL(qcom_scm_ice_invalidate_key); @@ -1228,6 +1250,9 @@ int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size, dma_addr_t key_phys; int ret; + if (!qcom_scm_is_available()) + return -EPROBE_DEFER; + /* * 'key' may point to vmalloc()'ed memory, but we need to pass a * physical address that's been properly flushed. The sanctioned way to @@ -1262,7 +1287,12 @@ EXPORT_SYMBOL_GPL(qcom_scm_ice_set_key); bool qcom_scm_hdcp_available(void) { bool avail; - int ret = qcom_scm_clk_enable(); + int ret; + + if (!qcom_scm_is_available()) + return -EPROBE_DEFER; + + ret = qcom_scm_clk_enable(); if (ret) return ret; @@ -1307,6 +1337,9 @@ int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) }; struct qcom_scm_res res; + if (!qcom_scm_is_available()) + return -EPROBE_DEFER; + if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT) return -ERANGE; @@ -1335,7 +1368,7 @@ int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt) .owner = ARM_SMCCC_OWNER_SIP, }; - return qcom_scm_call(__scm->dev, &desc, NULL); + return qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL); } EXPORT_SYMBOL_GPL(qcom_scm_iommu_set_pt_format); @@ -1351,13 +1384,15 @@ int qcom_scm_qsmmu500_wait_safe_toggle(bool en) }; - return qcom_scm_call_atomic(__scm->dev, &desc, NULL); + return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL); } EXPORT_SYMBOL_GPL(qcom_scm_qsmmu500_wait_safe_toggle); bool qcom_scm_lmh_dcvsh_available(void) { - return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_LMH, QCOM_SCM_LMH_LIMIT_DCVSH); + return __qcom_scm_is_call_available(__scm ? __scm->dev : NULL, + QCOM_SCM_SVC_LMH, + QCOM_SCM_LMH_LIMIT_DCVSH); } EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh_available); @@ -1371,7 +1406,7 @@ int qcom_scm_lmh_profile_change(u32 profile_id) .owner = ARM_SMCCC_OWNER_SIP, }; - return qcom_scm_call(__scm->dev, &desc, NULL); + return qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL); } EXPORT_SYMBOL_GPL(qcom_scm_lmh_profile_change); @@ -1394,6 +1429,9 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, .owner = ARM_SMCCC_OWNER_SIP, }; + if (!qcom_scm_is_available()) + return -EPROBE_DEFER; + payload_buf = dma_alloc_coherent(__scm->dev, payload_size, &payload_phys, GFP_KERNEL); if (!payload_buf) return -ENOMEM; @@ -1568,6 +1606,9 @@ int qcom_scm_qseecom_app_get_id(const char *app_name, u32 *app_id) char *name_buf; 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Tue, 27 Feb 2024 15:53:55 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41RFrsDc011850 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Feb 2024 15:53:54 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 27 Feb 2024 07:53:52 -0800 From: Mukesh Ojha To: , CC: , , , , Mukesh Ojha Subject: [PATCH v12 9/9] firmware: scm: Remove redundant scm argument from qcom_scm_waitq_wakeup() Date: Tue, 27 Feb 2024 21:23:08 +0530 Message-ID: <20240227155308.18395-10-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.43.0.254.ga26002b62827 In-Reply-To: <20240227155308.18395-1-quic_mojha@quicinc.com> References: <20240227155308.18395-1-quic_mojha@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: C_3KrFfEdNVvreYXkud8SuXx7N98pwtA X-Proofpoint-ORIG-GUID: C_3KrFfEdNVvreYXkud8SuXx7N98pwtA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-27_01,2024-02-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 mlxlogscore=947 clxscore=1015 bulkscore=0 mlxscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 adultscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402270122 Remove unused scm argument from qcom_scm_waitq_wakeup(). Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index a1dce417e6ec..d91f5872e003 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -1853,7 +1853,7 @@ int qcom_scm_wait_for_wq_completion(u32 wq_ctx) return 0; } -static int qcom_scm_waitq_wakeup(struct qcom_scm *scm, unsigned int wq_ctx) +static int qcom_scm_waitq_wakeup(unsigned int wq_ctx) { int ret; @@ -1885,7 +1885,7 @@ static irqreturn_t qcom_scm_irq_handler(int irq, void *data) goto out; } - ret = qcom_scm_waitq_wakeup(scm, wq_ctx); + ret = qcom_scm_waitq_wakeup(wq_ctx); if (ret) goto out; } while (more_pending);