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[209.51.188.17]) by mx.google.com with ESMTPS id r126si1397125qkd.39.2019.09.25.11.52.22 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Sep 2019 11:52:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="fu9N3v/C"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56084 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCOj-0005yL-P6 for patch@linaro.org; Wed, 25 Sep 2019 14:52:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46915) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCIV-0001eg-0r for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:45:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDCIT-00049n-Th for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:45:54 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:44315) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iDCIT-00048s-NO for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:45:53 -0400 Received: by mail-pg1-x52d.google.com with SMTP id i14so142457pgt.11 for ; Wed, 25 Sep 2019 11:45:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q6zTCS3a7jbtaH9NaP7Qy7VX+G/mKKsgVF1UpUR0SU0=; b=fu9N3v/CyUj/AF1Jqou+Qwav1uyd1l+Fwy4D4qmEZmi33EKs4W3qnvY3yR9jLD0yU4 veUfrSnFBqm2TZBbmRnZZEm2MPz9c2Ue06agPoeXt2KiXbUAtu28fWtUzuDFBWZsX7Ma mJoOPnpKkM6h4ElbPC4fXcS9Kfe7AIXHmbjT5monn04u+UrEcqxodE0sLirLc2dZ0wt6 j9j6vAGEbVGrkiaqwooATKogVKGaGWMSPKpo3DEFqpzH9zqPL/FoXr9D7TK4ukzRo60h cRvESQKVXnq1PvNdtOO8Yw+FiQPZrlf3IrZXyhLKoPs/Q7gKrbGOKjmw5qEamT8AY/Gi jlOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q6zTCS3a7jbtaH9NaP7Qy7VX+G/mKKsgVF1UpUR0SU0=; b=XbFR4VjM2draCp9Fcx+ACTWZsm8CWMCn0gd+XnXDSgKj87OLyQokuqQJCOBjIrrn00 hwpcU2eLLGUsVFya3Hj973F9iZVFg6+sDGDbU7Kd219cltHEpob9jXNRqjwwMdFfnI8L gZwcaoYZjpNX5pNr37M6DdmzMEEP18SBR2OsW3v3J5A6yN4k69vzDarav+e3vmmKsb/f qId3RYxVxUBeICzw6X6e0zjDKav1nodAe8UeHZBQJNBhDS8nnGRGI2IK4dprL/0A8BcU rxBOTtbsX85AzRY9WW8z5y30pOF3nrMeeeZAoRBbmX1wnAbAzf8yeIIyUMs/teyDhVQQ LlvQ== X-Gm-Message-State: APjAAAVFGm3YTyeAiEB/p64oMbJ0801a7xHy/zZYJSszbe0jsegQBoLM FuvNNRapEvPFOEKzbqqrGLlCdn1ltJc= X-Received: by 2002:a62:2b51:: with SMTP id r78mr11146723pfr.149.1569437152312; Wed, 25 Sep 2019 11:45:52 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.61]) by smtp.gmail.com with ESMTPSA id l24sm6133229pff.151.2019.09.25.11.45.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 11:45:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 01/16] exec: Use TARGET_PAGE_BITS_MIN for TLB flags Date: Wed, 25 Sep 2019 11:45:33 -0700 Message-Id: <20190925184548.30673-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190925184548.30673-1-richard.henderson@linaro.org> References: <20190925184548.30673-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These bits do not need to vary with the actual page size used by the guest. Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand Reviewed-by: Paolo Bonzini Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index d2d443c4f9..e0c8dc540c 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -317,20 +317,24 @@ CPUArchState *cpu_copy(CPUArchState *env); #if !defined(CONFIG_USER_ONLY) -/* Flags stored in the low bits of the TLB virtual address. These are - * defined so that fast path ram access is all zeros. +/* + * Flags stored in the low bits of the TLB virtual address. + * These are defined so that fast path ram access is all zeros. * The flags all must be between TARGET_PAGE_BITS and * maximum address alignment bit. + * + * Use TARGET_PAGE_BITS_MIN so that these bits are constant + * when TARGET_PAGE_BITS_VARY is in effect. */ /* Zero if TLB entry is valid. */ -#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS - 1)) +#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) /* Set if TLB entry references a clean RAM page. The iotlb entry will contain the page physical address. */ -#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS - 2)) +#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) /* Set if TLB entry is an IO callback. */ -#define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3)) +#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) /* Set if TLB entry contains a watchpoint. */ -#define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS - 4)) +#define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) /* Use this mask to check interception with an alignment mask * in a TCG backend. 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X-Received-From: 2607:f8b0:4864:20::436 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This forced inlining can result in missing symbols, which makes a debugging build harder to follow. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: David Hildenbrand Reported-by: Peter Maydell Signed-off-by: Richard Henderson --- include/qemu/compiler.h | 11 +++++++++++ accel/tcg/cputlb.c | 4 ++-- 2 files changed, 13 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h index 09fc44cca4..20780e722d 100644 --- a/include/qemu/compiler.h +++ b/include/qemu/compiler.h @@ -170,6 +170,17 @@ # define QEMU_NONSTRING #endif +/* + * Forced inlining may be desired to encourage constant propagation + * of function parameters. However, it can also make debugging harder, + * so disable it for a non-optimizing build. + */ +#if defined(__OPTIMIZE__) +#define QEMU_ALWAYS_INLINE __attribute__((always_inline)) +#else +#define QEMU_ALWAYS_INLINE +#endif + /* Implement C11 _Generic via GCC builtins. Example: * * QEMU_GENERIC(x, (float, sinf), (long double, sinl), sin) (x) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index abae79650c..2222b87764 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1281,7 +1281,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, typedef uint64_t FullLoadHelper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); -static inline uint64_t __attribute__((always_inline)) +static inline uint64_t QEMU_ALWAYS_INLINE load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr, MemOp op, bool code_read, FullLoadHelper *full_load) @@ -1530,7 +1530,7 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, * Store Helpers */ -static inline void __attribute__((always_inline)) +static inline void QEMU_ALWAYS_INLINE store_helper(CPUArchState *env, target_ulong addr, uint64_t val, TCGMemOpIdx oi, uintptr_t retaddr, MemOp op) { From patchwork Wed Sep 25 18:45:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174403 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1017473ill; Wed, 25 Sep 2019 11:48:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqzIt4+q99GWhX23tMaY1HfKfUw9Eo1cGAcAfAkpnqQGnBFR3rpeOZFw5lhVzwJYlpYf/VzV X-Received: by 2002:a17:906:4b47:: with SMTP id j7mr654980ejv.63.1569437292805; Wed, 25 Sep 2019 11:48:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569437292; cv=none; d=google.com; s=arc-20160816; b=e03TsuZLkBjgjDBi4338G68wDbWn+ceOvkkWKIntEAfrFYq7IAwPoEr0/4HqOn0726 Lf7URo45QG85ojfljRi1iG8eeNcJkPJ1+CY1fKMc+VYhZVgMoTWegrG6Fcv+4hYhntf7 2LOS04W9dCNEh9s/T/PAumUryV8aRI6zXabLLzZWrEwPuuAHzTV1KwNiBuI6ncGSE3Gb efQbcTXKjQEzkyYIkh6UDpRPJEOB32tLZNvgb2GooznqoE6Oy7w18axJ68vf+/QNOZcr SI66sGCISW4esftYZjBgyjOelt9S3wc4YFsH5SO9CzUtiRvkNQF537Ye7oRC5yZfHeO9 mgIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Cgi8cwP/kPiakDiYJkRI89bBSyLkz6ovsWz2x/LD2wI=; b=fluwEidybGgMCSI8k2kR0HFFmZzO79ik9V23pZLkj0UVw8b28DFWD/hzULYdkwI+1u +KfPK1w0443ie1zudgNSCeJS4GAtn95hplK7y1gSky23zona0G8qTbqC1lqsxrM+P330 ueuUDcCYyxDq930AX+kOr2+evXZ99XIiH8WAObF5LFuWw5cwSxCxrM8K7AwzJZ3JXsan p/D75fYjWT8A6/ZpyhX0xRJ8lNHDA6LxpeUECrzzn1xZvJd6ZG7/Hd0qpU0kSvVLv/z7 CcPBfO+iCfeTTQ8HvK0nuKbTQEfF/GwD9I16Sm9P70wDteWJV5ZBl5U0kBkB8WcHyZre eWmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pEfhyXa3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v2si250455eju.3.2019.09.25.11.48.12 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Sep 2019 11:48:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pEfhyXa3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55974 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCKh-0001iS-1b for patch@linaro.org; Wed, 25 Sep 2019 14:48:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46972) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCIX-0001fl-Ey for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:45:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDCIW-0004DL-HY for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:45:57 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:45504) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iDCIW-0004CN-Bu for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:45:56 -0400 Received: by mail-pf1-x42f.google.com with SMTP id y72so4134536pfb.12 for ; Wed, 25 Sep 2019 11:45:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Cgi8cwP/kPiakDiYJkRI89bBSyLkz6ovsWz2x/LD2wI=; b=pEfhyXa3LMv/9lv5T4yuYVMwG0mRmtmPtjlMft6HTOfQ6SZaQQKmNcgDXBCGvpyRhY zR6DJxm27kK5KLsB5eEnkJD8js6yPO3Fc8W7PfqB/DGr6nTYf8L/w2kdrloIU8hhrLh9 9Kq8U1vjAUeIgmFWq979TJz3nnkjpxZ9o3fyw7n6Xv8dIJFFG1MGsHF+U4KVuQPWFPlZ kZ3hGKz4X9gR4Jf7fcwNcGXyahW1nLq92gpvRg7FSA91TN9RsBKJtci0/yT5SYqsTloL NYWuTEFNZ8AcgS3BxnnEf9GCdfevnrfGLiAyS3MYCUZ0Ng4WQyVFJDPglySWNL1CJaWb nPqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Cgi8cwP/kPiakDiYJkRI89bBSyLkz6ovsWz2x/LD2wI=; b=WLuR6pNu1LptV8y8PRxEMHcL+jPsymJ+sSSjhwHEWwDw36dxxauAgCfWHjpjcbpdKm SMLfdYpAV3lgtT6nSKoGZ7bjYKn9SJn4+xoKB93L4Z9ES3rqKQlqb/A48ctTWpdEuJa/ RA4r2XVci4djg3lQtQ7Oy8Uf6NRxPtvgQ3le5cqWr7vlgEtXqD3b2Ei5tl/JBzXGaiMH 1c3GheJGz218ipqBkS9gB38A5HTinx0WcS4NOilkeXHA9EFYkR2+fGZEU6UuqZI6p6Wk eXgV1xP12N08DLwEfXqeHm15FBAimqL1MR7udGCCb5STDYT0JOj5VCv+6gM1PKlm1C3d HvsQ== X-Gm-Message-State: APjAAAX6pCSZTV1zcgFy4m9n6ROcL1Oni4ry3cUEvLtoNDDOTiajq7xl VJhCNb1uUyt6gyk6L3j1RyZioJR2Feo= X-Received: by 2002:a62:db84:: with SMTP id f126mr11647089pfg.25.1569437154916; Wed, 25 Sep 2019 11:45:54 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.61]) by smtp.gmail.com with ESMTPSA id l24sm6133229pff.151.2019.09.25.11.45.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 11:45:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 03/16] qemu/compiler.h: Add qemu_build_not_reached Date: Wed, 25 Sep 2019 11:45:35 -0700 Message-Id: <20190925184548.30673-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190925184548.30673-1-richard.henderson@linaro.org> References: <20190925184548.30673-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42f X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use this as a compile-time assert that a particular code path is not reachable. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/qemu/compiler.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.17.1 diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h index 20780e722d..7b93c73340 100644 --- a/include/qemu/compiler.h +++ b/include/qemu/compiler.h @@ -221,4 +221,19 @@ #define QEMU_GENERIC9(x, a0, ...) QEMU_GENERIC_IF(x, a0, QEMU_GENERIC8(x, __VA_ARGS__)) #define QEMU_GENERIC10(x, a0, ...) QEMU_GENERIC_IF(x, a0, QEMU_GENERIC9(x, __VA_ARGS__)) +/** + * qemu_build_not_reached() + * + * The compiler, during optimization, is expected to prove that a call + * to this function cannot be reached and remove it. If the compiler + * supports QEMU_ERROR, this will be reported at compile time; otherwise + * this will be reported at link time due to the missing symbol. + */ +#ifdef __OPTIMIZE__ +extern void QEMU_NORETURN QEMU_ERROR("code path is reachable") + qemu_build_not_reached(void); +#else +#define qemu_build_not_reached() g_assert_not_reached() +#endif + #endif /* COMPILER_H */ From patchwork Wed Sep 25 18:45:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174407 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1021609ill; Wed, 25 Sep 2019 11:52:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqxqKq8tqPZHXjNoxjIqqqF16oyupIlypcdsrw+kWvU0ac+J1QdcOY0XXbtXRggO5FTYH28A X-Received: by 2002:ac8:5046:: with SMTP id h6mr871852qtm.13.1569437551480; Wed, 25 Sep 2019 11:52:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569437551; cv=none; d=google.com; s=arc-20160816; b=JI4L40ZlI6v1yM87+9hAl9y0mAO0HZEk/6sxry0x1O5pxjgVkVtDIJ4ky5apuKyNb2 dOnT8xknZxEw9HlqXhNNj1mAxUjNZ0X5B9qUaOBRKJ6S+B1IM9zViBt1QXyyamRlGMUc dJk0SxaKTovkcQQPrpuMfJ8Z/mNIdZdrUWiTr/owW6Ig0Fgyfj9MF7YZpMCJd9E+KHUt 3IzeuLcZ975OGD5AKbCCJ0hZ6mZKiTXDsu+VCvMgMEhW3vyiJobYpZbDTRtuVXnl8TgK jS6JR++cHiXrmsgpmu66PiyMhTsQKHMLUEhzBNzX/EznRDHaxY1pHI+eDSHgRVNnCnWX W8fA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tEvO5tw4/suCh+mwvodKHXWtN16PlVfrxqaiSrTER6g=; b=ha81hlf9JOFZV7R6JR7z5Ry9SL4MPvoTIl1eF7zLyf4ls7zAVyBIIWCOFLy4HGNJ8A V0/CdsmpsY/Bb8DwSxTpvF+EvZFklKmL4o++Hpk93UvLsQx4MYkIW32vY/rMExoexX1s 8rRThHNN3WzIsh3aKLGFbqyjFWKOmGt3Aclq2hr978Ylb2Fz5itSbjFJG1DJeEXKp94N SSDS21opRD9Ihc+Tcz5TOiSKOtZaH5q1amF2dhpfxTDdFDoXLcyX3KkG//X+dJcHtF+T yL62+MDsuKr/9Oqe2M1FNfKpPGmDACWU8efyyqAx827w28kFZqqg67vUQzciYU04rueJ PuNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bbVQHKnF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h9si4501471qkm.174.2019.09.25.11.52.31 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Sep 2019 11:52:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bbVQHKnF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56098 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCOs-0006Ef-R1 for patch@linaro.org; Wed, 25 Sep 2019 14:52:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46987) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCIZ-0001h1-2Y for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:45:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDCIY-0004EF-25 for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:45:58 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:37023) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iDCIX-0004Dr-TD for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:45:58 -0400 Received: by mail-pf1-x443.google.com with SMTP id y5so4160998pfo.4 for ; Wed, 25 Sep 2019 11:45:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tEvO5tw4/suCh+mwvodKHXWtN16PlVfrxqaiSrTER6g=; b=bbVQHKnFvAbHmLIb7cT7R+nAFllNJtICyzl/XE6Kih9SFhg6LmnrXZHdgDpICNJbHI TloWJcSxR4kNLINaxiblKd1IWStyQ6vI8fJgLp+SFlLzfDaBFlxR7BQlboBeT3JN5dgw TEe/sBHh6MvVT3ckgmtz+x0vtw6KwOqI3RpIqEvt4ZFQdlKLgkmnfRrVAyX44wbVzxDE sLMHT83TWCCkQxDhWBwLFlNEBH/yT0R7BX/tN8NePh90B1SqVe3kF5RlMetgvsFYmA40 aYQomumq1WLkPSd7VOt+5zo1UAQ6DKePMRkVX7uJatJXdlge+elD78gKjdJnxn7LoQ3u GHpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tEvO5tw4/suCh+mwvodKHXWtN16PlVfrxqaiSrTER6g=; b=hLLT+9I+4TtVuqGsNnyayjPBHX8zh87nC1MA9P5D64OzgBpnllDrzCkykDchUKOE/O YS9puqkTSfjs/jzBGf9b9S6GT81uDEOU5gzhgjakvHXDLTia77dkJLtWDOc5Hg/uwFRe TPaDi6vNTe8czFjcwDz8hE3irXsvuJswtO3w07x1RpkHijJKug1pkNI6Oz2zNAHNlW+i Fwfo7OP0DlLCTd533pYWon3oYVngB99UoMHmT0COcSPa8lF3CqXW2vYMqJGPEZysi+8U Eg7Iha1MLFDAbeAH+AkhumLF87kgkxcm7wrhOAmO9jrORWTCODmgwmgTY3/lNE5BXoS8 Pj+Q== X-Gm-Message-State: APjAAAXy3ZXXVXWXmCAdvC/uV+iHTUDYRB9JaK22YdP+sKWl330N6ZVW 0iax10qlN/OQDfMBu6rwQWGghJbHU9w= X-Received: by 2002:a62:7ece:: with SMTP id z197mr18817pfc.78.1569437156411; Wed, 25 Sep 2019 11:45:56 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.61]) by smtp.gmail.com with ESMTPSA id l24sm6133229pff.151.2019.09.25.11.45.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 11:45:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 04/16] cputlb: Use qemu_build_not_reached in load/store_helpers Date: Wed, 25 Sep 2019 11:45:36 -0700 Message-Id: <20190925184548.30673-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190925184548.30673-1-richard.henderson@linaro.org> References: <20190925184548.30673-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Increase the current runtime assert to a compile-time assert. Reviewed-by: David Hildenbrand Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 2222b87764..e31378bce3 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1396,7 +1396,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, res = ldq_le_p(haddr); break; default: - g_assert_not_reached(); + qemu_build_not_reached(); } return res; @@ -1680,8 +1680,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, stq_le_p(haddr, val); break; default: - g_assert_not_reached(); - break; + qemu_build_not_reached(); } } From patchwork Wed Sep 25 18:45:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174404 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1017521ill; Wed, 25 Sep 2019 11:48:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqyZPalJ08fWfJm5kO+UXEutKrApVCQHsHKpBF7lS3qobTjluiHAyLBIv565owch7eFHDWZQ X-Received: by 2002:a17:906:7e56:: with SMTP id z22mr626493ejr.294.1569437296507; Wed, 25 Sep 2019 11:48:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569437296; cv=none; d=google.com; s=arc-20160816; b=moFRvPPRjakR4EIovyRyON9MvKvBGdSyaW7eYFy+fIiYcx1mXIlCCYn50HaiJA/FTg BtbelvQUgXOiwzRaDMIPTXDZyQWpayLdlPRMcAfBQro2CsgSADsLqGyKGJFAyBIfJmbF dz8z9qbBJX6QwqUUMyDIv4qhpGN1p8je2SHBE0w4nr2ubuxKjKjNqhsyzspQcx9v7W0/ FT+ceOGLH0uF8j0Cbr8+/zGHbY2c4lVSDd8ucTXVz6X7AycbZ9BRUhSawmohBwlRBryC TUIHGFJHTbFSDC0tXmDMmjE+nSG4j6x07CbQCSDz6ob/tKyhyW+6d6MoK4POfr6+ADej jzWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dpjQdA7JkkGx46Rli+yrKoXDpXOevLhotnlmbVLP3mg=; b=MMs8TvQTTNDUVoWvi/UnCBX1bCLd3Q0V67RPzOWy+ybS1jZ7bN/yE1jHg8el8uSlj6 d9c1bm34zN69pKukZ1X5taqHvq8Oa+i5SYFbWjhHLayQTNNZDJNehLCg/jlVbo3N8Qml Ip7qY166lHDyTJTalVhPS6TCZ+6BlNS0RCz4UnP7xD3fL8/ppUzH3e7iXG7KBdwYiBi7 T5PBYBzWK0jiiWH/xQ++9byRJYc7EVik/PiklwEChpUXWBlX+JXUyN6CF/Zp4yLjBewx CS5ElVzRBucKTrDdV7NcKiaYTYqtXjSgoK1uoxnYMZ17d9XvGUUsUWB+TYpOWBPUOEM5 gbGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Qjp0JUK4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w54si4113479edd.427.2019.09.25.11.48.16 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Sep 2019 11:48:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Qjp0JUK4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55996 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCKk-0001nW-Ks for patch@linaro.org; Wed, 25 Sep 2019 14:48:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47001) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCIa-0001j1-N9 for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDCIZ-0004Ef-Go for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:00 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:43869) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iDCIZ-0004EV-BO for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:45:59 -0400 Received: by mail-pl1-x633.google.com with SMTP id f21so539425plj.10 for ; Wed, 25 Sep 2019 11:45:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dpjQdA7JkkGx46Rli+yrKoXDpXOevLhotnlmbVLP3mg=; b=Qjp0JUK4Dp2sjVrTeu15m/JGRzbnlZ6vOzaGsjOFpVbDafFjxvP/+VWwO4qCL6lMpN /f5LTA+VcRpqny0zfq4rV9x0+tOxnecAoVt3CtJjHnn5PAwCYHrn4jwLAmG3NRfgVXHY jr8ceFM59yM+QasTIOdgNkU2cquP2vwnnNIQSESr8l15nwn7T4xJ+IvxSMrnRJTUmYhE TQmr7aQXVHuKlYC2BWthrQkj1qgM2MFhxvMkxNsz5bNr8DWqmtQuGx3Xq4U+WPvPhHfy 1T/G1rDE15TR8RVnqRFc3Of4cEye/gVBUB7PHK0vz+IhMWk5IdKptEdlIQoq4WmxAMQZ 8HoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dpjQdA7JkkGx46Rli+yrKoXDpXOevLhotnlmbVLP3mg=; b=V7gkPVapJ/tft8/l0Za7tGo94bBmcrT4PWueDWmCnXkQkkZPux4hxQS5xBxIf0EAl9 jai16Iy8QwIwrSrrH9Qbs+f3AhLUDfLV3598jsdbLs6x1CZa/2Qr92TkOGtMQYR8bwNz t4MQsFUpp9YeZCOjqM8zphEF7NgkkQAoyaQfYI2RtRD2zrZM4qgb0kE5II1rJ54jHz1r qd1f8e00tClJ65jurES3i86LKLz83ByqXZ5hnbM7B2YaqK8k1pGvxmio1MBHK5LJqPNS zpbNoz+JiObC885eEneIKjX8eXn16XOUdM1FQ9MREWPzvsMIMzUoykQIn2S5heiDHAoc SpBw== X-Gm-Message-State: APjAAAWrrWfPFbyj38ZGIRf/YnrI+KcxWqmZOrjN/cKSqLJTltloHOGW YH/DXzvpDSldEjkTYYSXJHcISUhbzWY= X-Received: by 2002:a17:902:fe86:: with SMTP id x6mr10925297plm.28.1569437157768; Wed, 25 Sep 2019 11:45:57 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.61]) by smtp.gmail.com with ESMTPSA id l24sm6133229pff.151.2019.09.25.11.45.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 11:45:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 05/16] cputlb: Split out load/store_memop Date: Wed, 25 Sep 2019 11:45:37 -0700 Message-Id: <20190925184548.30673-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190925184548.30673-1-richard.henderson@linaro.org> References: <20190925184548.30673-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::633 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will shortly be using these more than once. Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 107 +++++++++++++++++++++++---------------------- 1 file changed, 55 insertions(+), 52 deletions(-) -- 2.17.1 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e31378bce3..eeba8c9847 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1281,6 +1281,29 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, typedef uint64_t FullLoadHelper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +static inline uint64_t QEMU_ALWAYS_INLINE +load_memop(const void *haddr, MemOp op) +{ + switch (op) { + case MO_UB: + return ldub_p(haddr); + case MO_BEUW: + return lduw_be_p(haddr); + case MO_LEUW: + return lduw_le_p(haddr); + case MO_BEUL: + return (uint32_t)ldl_be_p(haddr); + case MO_LEUL: + return (uint32_t)ldl_le_p(haddr); + case MO_BEQ: + return ldq_be_p(haddr); + case MO_LEQ: + return ldq_le_p(haddr); + default: + qemu_build_not_reached(); + } +} + static inline uint64_t QEMU_ALWAYS_INLINE load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr, MemOp op, bool code_read, @@ -1373,33 +1396,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, do_aligned_access: haddr = (void *)((uintptr_t)addr + entry->addend); - switch (op) { - case MO_UB: - res = ldub_p(haddr); - break; - case MO_BEUW: - res = lduw_be_p(haddr); - break; - case MO_LEUW: - res = lduw_le_p(haddr); - break; - case MO_BEUL: - res = (uint32_t)ldl_be_p(haddr); - break; - case MO_LEUL: - res = (uint32_t)ldl_le_p(haddr); - break; - case MO_BEQ: - res = ldq_be_p(haddr); - break; - case MO_LEQ: - res = ldq_le_p(haddr); - break; - default: - qemu_build_not_reached(); - } - - return res; + return load_memop(haddr, op); } /* @@ -1530,6 +1527,36 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, * Store Helpers */ +static inline void QEMU_ALWAYS_INLINE +store_memop(void *haddr, uint64_t val, MemOp op) +{ + switch (op) { + case MO_UB: + stb_p(haddr, val); + break; + case MO_BEUW: + stw_be_p(haddr, val); + break; + case MO_LEUW: + stw_le_p(haddr, val); + break; + case MO_BEUL: + stl_be_p(haddr, val); + break; + case MO_LEUL: + stl_le_p(haddr, val); + break; + case MO_BEQ: + stq_be_p(haddr, val); + break; + case MO_LEQ: + stq_le_p(haddr, val); + break; + default: + qemu_build_not_reached(); + } +} + static inline void QEMU_ALWAYS_INLINE store_helper(CPUArchState *env, target_ulong addr, uint64_t val, TCGMemOpIdx oi, uintptr_t retaddr, MemOp op) @@ -1657,31 +1684,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, do_aligned_access: haddr = (void *)((uintptr_t)addr + entry->addend); - switch (op) { - case MO_UB: - stb_p(haddr, val); - break; - case MO_BEUW: - stw_be_p(haddr, val); - break; - case MO_LEUW: - stw_le_p(haddr, val); - break; - case MO_BEUL: - stl_be_p(haddr, val); - break; - case MO_LEUL: - stl_le_p(haddr, val); - break; - case MO_BEQ: - stq_be_p(haddr, val); - break; - case MO_LEQ: - stq_le_p(haddr, val); - break; - default: - qemu_build_not_reached(); - } + store_memop(haddr, val, op); } void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, From patchwork Wed Sep 25 18:45:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174409 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1025560ill; Wed, 25 Sep 2019 11:56:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqy8ai6mzXDWkEFauNK5kQalA9PjhqnqGUM/mMeA9CCbpyWObN4Ot7v/5Pm9R6BEdJv4Hql+ X-Received: by 2002:ac8:184:: with SMTP id x4mr882858qtf.249.1569437791065; Wed, 25 Sep 2019 11:56:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569437791; cv=none; d=google.com; s=arc-20160816; b=LyeyXaR70pkmiN1Cj0NQpufOEwumS1dUwKr5/4/5bSwbWvQtda1tHBpyMifZLloPPu jsaNhI1efBLUGnWhnnCoCeh7vNIrB8ovSALJXCK3luS9TAqnbIFc3Ar0WX8bfipwcXAy /waSAXawepDZqprHcNZxjyqBCv5EbsMvhdshVBrAzgstzgFnF02Gjrpffubwqd6prZ5l Dr7X3VUJ4I53ODfSyscXLA4eVaRMbHTu30KeXUN7uO/bHmUcO4WR++B2Qd5qsBEsr/QT V86VeJDcRoEK5et2ruw7KRWULWmJMUfYCtmyS2tUFgdYkAwEYJFMcSL+/ClcpSoA3F+M 2WfQ== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id v8si421446qtb.125.2019.09.25.11.56.30 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Sep 2019 11:56:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yj84Hus4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56146 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCSk-0001jt-6i for patch@linaro.org; Wed, 25 Sep 2019 14:56:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47016) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCIc-0001ku-IO for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDCIb-0004FO-13 for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:02 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:33419) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iDCIa-0004F1-P7 for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:00 -0400 Received: by mail-pl1-x636.google.com with SMTP id d22so2945375pls.0 for ; Wed, 25 Sep 2019 11:46:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VU8gXJ0ha+BxU/auLcZl3iqhGwLSOAQ2I5JEO3/h8Yw=; b=yj84Hus4B03MBtSSLlSTLIPbiF7Wmw/YsBAFyO/HFgEdtQYr1YrIeSuJ45AXvu4oZq aEv7huRujb/U3ogGaliSZiU4X3Vh998j7z8VubAfWL+JU7I4SKUgzaqvnyLwNdbwhDWk GqGvnOgWQs20v9VgndldTWVJ4O58kQDrzOsV+z9u8qHpU7C/wn/C+WB3yEWxxYX/Howe bU3IAklyjegUqf7uFylZgAH0fheWQeHaBOTo7+5D30jT0jiAyOYaUqVe+/L2KD8plEdD gRTDdZ2/m1p4eGaB6l+FFwfPEMmpsiMnqJmdBO6YBk0yKQijgo5FNKdKBMr8eCexn8Pf kB5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VU8gXJ0ha+BxU/auLcZl3iqhGwLSOAQ2I5JEO3/h8Yw=; b=JFJqbMpp/hRYXE0yyJPt9jWwHEXoS9J7LXCHbP0WRXkj/dyItmsZpGcTsuBMQtTqP8 lvRB+wK8Fe6pKtgp3u7wXOvafgqSA/QkFFICXAJgJQqY/1CiJGyMEJQXQyMEsPjq1Ole aYYGF1bhSUsZCUzfUuzgDoFF2Rr8Zxijr+MiW3M3k7/rTaz+06QMVd6kNYDcFUFSdmmA el0qt0c5H8v6JcV0CBvPyDUZIOhXywXaaXCrnFbX02B3WaN3+kL0RXdlv+sb4NQudt85 R234boosdgLqUFEEJe/svCTc5yG9DwSTgBA4j0Xe3g3aNp+CK+AnvYqCWx6sgF5csRah dcXQ== X-Gm-Message-State: APjAAAUYVpTGhPCeGM8A7dMcR9FCk+W7yjsd9CEdLV0RHB3mZryKA4DM 0a8sAFzy5K9Xfk1tcnkseuUTZgzqSrA= X-Received: by 2002:a17:902:9a05:: with SMTP id v5mr10778603plp.237.1569437159291; Wed, 25 Sep 2019 11:45:59 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.61]) by smtp.gmail.com with ESMTPSA id l24sm6133229pff.151.2019.09.25.11.45.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 11:45:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 06/16] cputlb: Introduce TLB_BSWAP Date: Wed, 25 Sep 2019 11:45:38 -0700 Message-Id: <20190925184548.30673-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190925184548.30673-1-richard.henderson@linaro.org> References: <20190925184548.30673-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::636 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Handle bswap on ram directly in load/store_helper. This fixes a bug with the previous implementation in that one cannot use the I/O path for RAM. Fixes: a26fc6f5152b47f1 Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 4 ++- accel/tcg/cputlb.c | 72 +++++++++++++++++++++++++----------------- 2 files changed, 46 insertions(+), 30 deletions(-) -- 2.17.1 diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index e0c8dc540c..d148bded35 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -335,12 +335,14 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) /* Set if TLB entry contains a watchpoint. */ #define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) +/* Set if TLB entry requires byte swap. */ +#define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5)) /* Use this mask to check interception with an alignment mask * in a TCG backend. */ #define TLB_FLAGS_MASK \ - (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO | TLB_WATCHPOINT) + (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO | TLB_WATCHPOINT | TLB_BSWAP) /** * tlb_hit_page: return true if page aligned @addr is a hit against the diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index eeba8c9847..028eebcb44 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -737,8 +737,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, address |= TLB_INVALID_MASK; } if (attrs.byte_swap) { - /* Force the access through the I/O slow path. */ - address |= TLB_MMIO; + address |= TLB_BSWAP; } if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) { @@ -901,10 +900,6 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, bool locked = false; MemTxResult r; - if (iotlbentry->attrs.byte_swap) { - op ^= MO_BSWAP; - } - section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; @@ -947,10 +942,6 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, bool locked = false; MemTxResult r; - if (iotlbentry->attrs.byte_swap) { - op ^= MO_BSWAP; - } - section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; @@ -1133,8 +1124,8 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, wp_access, retaddr); } - if (tlb_addr & (TLB_NOTDIRTY | TLB_MMIO)) { - /* I/O access */ + /* Reject I/O access, or other required slow-path. */ + if (tlb_addr & (TLB_NOTDIRTY | TLB_MMIO | TLB_BSWAP)) { return NULL; } @@ -1344,6 +1335,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, /* Handle anything that isn't just a straight memory access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { CPUIOTLBEntry *iotlbentry; + bool need_swap; /* For anything that is unaligned, recurse through full_load. */ if ((addr & (size - 1)) != 0) { @@ -1357,17 +1349,27 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, /* On watchpoint hit, this will longjmp out. */ cpu_check_watchpoint(env_cpu(env), addr, size, iotlbentry->attrs, BP_MEM_READ, retaddr); - - /* The backing page may or may not require I/O. */ - tlb_addr &= ~TLB_WATCHPOINT; - if ((tlb_addr & ~TARGET_PAGE_MASK) == 0) { - goto do_aligned_access; - } } + need_swap = size > 1 && (tlb_addr & TLB_BSWAP); + /* Handle I/O access. */ - return io_readx(env, iotlbentry, mmu_idx, addr, - retaddr, access_type, op); + if (likely(tlb_addr & TLB_MMIO)) { + return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, + access_type, op ^ (need_swap * MO_BSWAP)); + } + + haddr = (void *)((uintptr_t)addr + entry->addend); + + /* + * Keep these two load_memop separate to ensure that the compiler + * is able to fold the entire function to a single instruction. + * There is a build-time assert inside to remind you of this. ;-) + */ + if (unlikely(need_swap)) { + return load_memop(haddr, op ^ MO_BSWAP); + } + return load_memop(haddr, op); } /* Handle slow unaligned access (it spans two pages or IO). */ @@ -1394,7 +1396,6 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, return res & MAKE_64BIT_MASK(0, size * 8); } - do_aligned_access: haddr = (void *)((uintptr_t)addr + entry->addend); return load_memop(haddr, op); } @@ -1591,6 +1592,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, /* Handle anything that isn't just a straight memory access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { CPUIOTLBEntry *iotlbentry; + bool need_swap; /* For anything that is unaligned, recurse through byte stores. */ if ((addr & (size - 1)) != 0) { @@ -1604,16 +1606,29 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, /* On watchpoint hit, this will longjmp out. */ cpu_check_watchpoint(env_cpu(env), addr, size, iotlbentry->attrs, BP_MEM_WRITE, retaddr); - - /* The backing page may or may not require I/O. */ - tlb_addr &= ~TLB_WATCHPOINT; - if ((tlb_addr & ~TARGET_PAGE_MASK) == 0) { - goto do_aligned_access; - } } + need_swap = size > 1 && (tlb_addr & TLB_BSWAP); + /* Handle I/O access. */ - io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, op); + if (likely(tlb_addr & (TLB_MMIO | TLB_NOTDIRTY))) { + io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, + op ^ (need_swap * MO_BSWAP)); + return; + } + + haddr = (void *)((uintptr_t)addr + entry->addend); + + /* + * Keep these two store_memop separate to ensure that the compiler + * is able to fold the entire function to a single instruction. + * There is a build-time assert inside to remind you of this. ;-) + */ + if (unlikely(need_swap)) { + store_memop(haddr, val, op ^ MO_BSWAP); + } else { + store_memop(haddr, val, op); + } return; } @@ -1682,7 +1697,6 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, return; } - do_aligned_access: haddr = (void *)((uintptr_t)addr + entry->addend); store_memop(haddr, val, op); } From patchwork Wed Sep 25 18:45:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174406 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1021572ill; Wed, 25 Sep 2019 11:52:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqySUZUuhZvhe/E7E27WS4Iu2Q4sNsIQeW9g+e6TYIi06xxz52hQ4WA+fJDO6ZttK6TwbkG5 X-Received: by 2002:ac8:4702:: with SMTP id f2mr901179qtp.134.1569437548334; Wed, 25 Sep 2019 11:52:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569437548; cv=none; d=google.com; s=arc-20160816; b=A1wTx0nqdSfsqXy0wpp3UF74XYdPlJaWtbWXAunT1OMfTTSRf0YFb7jNb8mhyPjv0R VMJVuN86ab1rhEwQLp8E1AbWzJPB7R8t1cgPJC1SvyCGg9Un0JhG8viJnxwxFYniLZUV KJ7pQrXz6NTTFsA4jhgPPCIAc2OLrLdxRqXT46AFXsk+KnPNRHUZwoszcbKs8ba0NN34 xlKYIWwvb71CPeJJ38jYmJ6TIm7ax7TZI8QbI+edGNHm6vEgc3lGzdjqPegWDVI/DMIp Nt6UcFTx6oyZdOvjmwlIjTEZCYMTzBivnvG89QiuR7DpmqMXEuk7as3vl50EFuGFuFeZ H0IA== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id 21si4675576qki.323.2019.09.25.11.52.28 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Sep 2019 11:52:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tPHRRPv3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56092 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCOp-00069x-7Z for patch@linaro.org; Wed, 25 Sep 2019 14:52:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47047) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCIe-0001mU-2u for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDCIc-0004Fu-GV for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:03 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:45205) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iDCIc-0004Fd-Aw for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:02 -0400 Received: by mail-pl1-x642.google.com with SMTP id u12so2904050pls.12 for ; Wed, 25 Sep 2019 11:46:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RKAV78KOhwa7cM2YUh+Cq3BXcX5AFdgHACRoOW8XrYE=; b=tPHRRPv3eAAti8D+Jn2FdazqpxaQ60EJLHJIBqVHuuCicY6JEsHrZKMLxfgQcG7toa lybbdUVwxXwAYsMc7yj9r4rIad9hOiyd9M0oR9yi0feXsNUKy+6s68yweLsAKfhTa0Hg 4UYivvZzHoyKOw1UDCg6FwwGKkCqBGhFUUD4K0fwRh7ir1p4MOa2HM38dYYpwCQVzFeL JTz1CjHGEspuaVNgJvr7SzrKPKjyCUa+BOjF7UjzKO4MH/XMvVlYUgp8qoYKqAZp2PEJ GeHVnlHMEdTWvPdoSvzICE6mT3cwdXgXRcRrZsq+Fuls6I3pQO0jFc/0bTa/4wd/c1Jc 2Kzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RKAV78KOhwa7cM2YUh+Cq3BXcX5AFdgHACRoOW8XrYE=; b=lufWKTyGJqjWa+0dEeq8/bFfbxZxdCylI/tt/H1B780348rkI/zxrZefZiaJvWpEsv 1NiUb2wORFHWhMS0zmOil4yKRGwbhOB8A9kUEPJgZ22fH71x52iaacXSt+82ESe+aSSi PeyC1Q+KbqM5nq4q3XAWfyx236EBU34+1/gbnZRn4RSDem5FB1LpHLTK60O0WZvJ2DQP HDrgdjOubhQafrlK0pJI8wQz/ixqToU11UVds4pGBPRphVivSSslpsk6JMz+340lsRs5 GzOwrUhAkbQyk9cuPBThCOSUi/Ci6UlSpMM9bziqXZF4cdPwgx+nnZAuwBpau8yLpOyo s8ZQ== X-Gm-Message-State: APjAAAVIGuH5ZKWEzi0qn8KBhNJx+mtEJ6sVeSBQA40sZ8eNWsw5FQ0K HmouFH2fU7l4ay5oq6RPiOrJrmbb3Dk= X-Received: by 2002:a17:902:850b:: with SMTP id bj11mr10890877plb.39.1569437160735; Wed, 25 Sep 2019 11:46:00 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.61]) by smtp.gmail.com with ESMTPSA id l24sm6133229pff.151.2019.09.25.11.45.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 11:45:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 07/16] exec: Adjust notdirty tracing Date: Wed, 25 Sep 2019 11:45:39 -0700 Message-Id: <20190925184548.30673-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190925184548.30673-1-richard.henderson@linaro.org> References: <20190925184548.30673-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The memory_region_tb_read tracepoint is unreachable, since notdirty is supposed to apply only to writes. The memory_region_tb_write tracepoint is mis-named, because notdirty is not only used for TB invalidation. It is also used for e.g. VGA RAM updates and migration. Replace memory_region_tb_write with memory_notdirty_write_access, and place it in memory_notdirty_write_prepare where it can catch all of the instances. Add memory_notdirty_set_dirty to log when we no longer intercept writes to a page. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- exec.c | 3 +++ memory.c | 4 ---- trace-events | 4 ++-- 3 files changed, 5 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/exec.c b/exec.c index 8b998974f8..5f2587b621 100644 --- a/exec.c +++ b/exec.c @@ -2755,6 +2755,8 @@ void memory_notdirty_write_prepare(NotDirtyInfo *ndi, ndi->size = size; ndi->pages = NULL; + trace_memory_notdirty_write_access(mem_vaddr, ram_addr, size); + assert(tcg_enabled()); if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { ndi->pages = page_collection_lock(ram_addr, ram_addr + size); @@ -2779,6 +2781,7 @@ void memory_notdirty_write_complete(NotDirtyInfo *ndi) /* we remove the notdirty callback only if the code has been flushed */ if (!cpu_physical_memory_is_clean(ndi->ram_addr)) { + trace_memory_notdirty_set_dirty(ndi->mem_vaddr); tlb_set_dirty(ndi->cpu, ndi->mem_vaddr); } } diff --git a/memory.c b/memory.c index b9dd6b94ca..57c44c97db 100644 --- a/memory.c +++ b/memory.c @@ -438,7 +438,6 @@ static MemTxResult memory_region_read_accessor(MemoryRegion *mr, /* Accesses to code which has previously been translated into a TB show * up in the MMIO path, as accesses to the io_mem_notdirty * MemoryRegion. */ - trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size); } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size); @@ -465,7 +464,6 @@ static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr, /* Accesses to code which has previously been translated into a TB show * up in the MMIO path, as accesses to the io_mem_notdirty * MemoryRegion. */ - trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size); } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size); @@ -490,7 +488,6 @@ static MemTxResult memory_region_write_accessor(MemoryRegion *mr, /* Accesses to code which has previously been translated into a TB show * up in the MMIO path, as accesses to the io_mem_notdirty * MemoryRegion. */ - trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size); } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size); @@ -515,7 +512,6 @@ static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr, /* Accesses to code which has previously been translated into a TB show * up in the MMIO path, as accesses to the io_mem_notdirty * MemoryRegion. */ - trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size); } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size); diff --git a/trace-events b/trace-events index 823a4ae64e..20821ba545 100644 --- a/trace-events +++ b/trace-events @@ -52,14 +52,14 @@ dma_map_wait(void *dbs) "dbs=%p" find_ram_offset(uint64_t size, uint64_t offset) "size: 0x%" PRIx64 " @ 0x%" PRIx64 find_ram_offset_loop(uint64_t size, uint64_t candidate, uint64_t offset, uint64_t next, uint64_t mingap) "trying size: 0x%" PRIx64 " @ 0x%" PRIx64 ", offset: 0x%" PRIx64" next: 0x%" PRIx64 " mingap: 0x%" PRIx64 ram_block_discard_range(const char *rbname, void *hva, size_t length, bool need_madvise, bool need_fallocate, int ret) "%s@%p + 0x%zx: madvise: %d fallocate: %d ret: %d" +memory_notdirty_write_access(uint64_t vaddr, uint64_t ram_addr, unsigned size) "0x%" PRIx64 " ram_addr 0x%" PRIx64 " size %u" +memory_notdirty_set_dirty(uint64_t vaddr) "0x%" PRIx64 # memory.c memory_region_ops_read(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64" size %u" memory_region_ops_write(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64" size %u" memory_region_subpage_read(int cpu_index, void *mr, uint64_t offset, uint64_t value, unsigned size) "cpu %d mr %p offset 0x%"PRIx64" value 0x%"PRIx64" size %u" memory_region_subpage_write(int cpu_index, void *mr, uint64_t offset, uint64_t value, unsigned size) "cpu %d mr %p offset 0x%"PRIx64" value 0x%"PRIx64" size %u" -memory_region_tb_read(int cpu_index, uint64_t addr, uint64_t value, unsigned size) "cpu %d addr 0x%"PRIx64" value 0x%"PRIx64" size %u" -memory_region_tb_write(int cpu_index, uint64_t addr, uint64_t value, unsigned size) "cpu %d addr 0x%"PRIx64" value 0x%"PRIx64" size %u" memory_region_ram_device_read(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64" size %u" memory_region_ram_device_write(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64" size %u" flatview_new(void *view, void *root) "%p (root %p)" From patchwork Wed Sep 25 18:45:40 2019 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id p19si385313qtk.274.2019.09.25.11.52.31 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Sep 2019 11:52:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Lyo7E/xo"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56102 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCOs-0006KJ-TR for patch@linaro.org; Wed, 25 Sep 2019 14:52:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47084) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCIf-0001oO-Oc for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDCId-0004He-Vd for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:05 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:33890) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iDCId-0004Gd-Na for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:03 -0400 Received: by mail-pl1-x644.google.com with SMTP id k7so2337321pll.1 for ; Wed, 25 Sep 2019 11:46:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+mSQUtExxffwFsuh/c6IBrL9OKLsUbH86Mr3RPL+odM=; b=Lyo7E/xo4ojw1cWW9330esFALB35CrtNQq/UIGkmVZuwWy5wR1ww4D5pKPcWiHq4A1 kb7UTIGF6Zr8ZyXFKR0ILXpCAKFBiflzLF2B3omXtWT2wD3q7mJsRcKbZG40i0GDNahN iVZ62aiOcckyA4e8EXg9C5GN/2yvFul8FXY8hS64giuQssbWycKhpTErXDF3nvM3NAaa feOzohU86ckJbrXCpO0XJfSb+/NoRJBrxqCbwgKjVwA8nyd1Jbf5+ajiLLsaU0JSobqk nmYaNLyaSpzn79kW/U59aWr8eUuZF8W5PbtuemIpXMcC2bIofhDnwgXdgxCuw4j+xeP0 gN9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+mSQUtExxffwFsuh/c6IBrL9OKLsUbH86Mr3RPL+odM=; b=aeiqbJR3QQGmXpCWeOCOGdrNzjt1LZ7vk6ivVFpY8LB8wkUT5huLz0N8VWx9np5Ywk ZIYJeYnUOhWXZwTPEQM6FSnBZUz6DhwMdya4Pybb46tAh0cAKbg/PTKYFQta2d58/zor MKtTJrdg6xxgG4aOv0mA+MmRxqLjMG9D6iZle/M0eUD+xnCa9GezBhkhMqZhf8D3hQ+A BmRFMZoQlm9G35i9FVVFPzUE3yHCxHtXCxQ96Z1D5BaAZgAJXnxS9f+2zZkuZyn4s2GE A5YYkA7QSMPVFpJdrWFbv+7GeY6t6gkFxYigcCDOoN7XzHhibihrwl6m4E6OshqwPiAy YbAA== X-Gm-Message-State: APjAAAU0fYdPAs3s1divx5kyEp1tIb+RWmp9c66DhwsSG66sKXBBmFPu SxaQpn/w5Fwpe3ofl6Z1h6tsKmGat4o= X-Received: by 2002:a17:902:7595:: with SMTP id j21mr10377950pll.162.1569437162197; Wed, 25 Sep 2019 11:46:02 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.61]) by smtp.gmail.com with ESMTPSA id l24sm6133229pff.151.2019.09.25.11.46.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 11:46:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 08/16] cputlb: Move ROM handling from I/O path to TLB path Date: Wed, 25 Sep 2019 11:45:40 -0700 Message-Id: <20190925184548.30673-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190925184548.30673-1-richard.henderson@linaro.org> References: <20190925184548.30673-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" It does not require going through the whole I/O path in order to discard a write. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 5 ++++- include/exec/cpu-common.h | 1 - accel/tcg/cputlb.c | 36 ++++++++++++++++++++-------------- exec.c | 41 +-------------------------------------- 4 files changed, 26 insertions(+), 57 deletions(-) -- 2.17.1 diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index d148bded35..ad9ab85eb3 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -337,12 +337,15 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) /* Set if TLB entry requires byte swap. */ #define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5)) +/* Set if TLB entry writes ignored. */ +#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6)) /* Use this mask to check interception with an alignment mask * in a TCG backend. */ #define TLB_FLAGS_MASK \ - (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO | TLB_WATCHPOINT | TLB_BSWAP) + (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ + | TLB_WATCHPOINT | TLB_BSWAP | TLB_DISCARD_WRITE) /** * tlb_hit_page: return true if page aligned @addr is a hit against the diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index f7dbe75fbc..1c0e03ddc2 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -100,7 +100,6 @@ void qemu_flush_coalesced_mmio_buffer(void); void cpu_flush_icache_range(hwaddr start, hwaddr len); -extern struct MemoryRegion io_mem_rom; extern struct MemoryRegion io_mem_notdirty; typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 028eebcb44..404ec57a4e 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -577,7 +577,8 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry, { uintptr_t addr = tlb_entry->addr_write; - if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_NOTDIRTY)) == 0) { + if ((addr & (TLB_INVALID_MASK | TLB_MMIO | + TLB_DISCARD_WRITE | TLB_NOTDIRTY)) == 0) { addr &= TARGET_PAGE_MASK; addr += tlb_entry->addend; if ((addr - start) < length) { @@ -745,7 +746,6 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, address |= TLB_MMIO; addend = 0; } else { - /* TLB_MMIO for rom/romd handled below */ addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat; } @@ -822,16 +822,17 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, tn.addr_write = -1; if (prot & PAGE_WRITE) { - if ((memory_region_is_ram(section->mr) && section->readonly) - || memory_region_is_romd(section->mr)) { - /* Write access calls the I/O callback. */ - tn.addr_write = address | TLB_MMIO; - } else if (memory_region_is_ram(section->mr) - && cpu_physical_memory_is_clean( - memory_region_get_ram_addr(section->mr) + xlat)) { - tn.addr_write = address | TLB_NOTDIRTY; - } else { - tn.addr_write = address; + tn.addr_write = address; + if (memory_region_is_romd(section->mr)) { + /* Use the MMIO path so that the device can switch states. */ + tn.addr_write |= TLB_MMIO; + } else if (memory_region_is_ram(section->mr)) { + if (section->readonly) { + tn.addr_write |= TLB_DISCARD_WRITE; + } else if (cpu_physical_memory_is_clean( + memory_region_get_ram_addr(section->mr) + xlat)) { + tn.addr_write |= TLB_NOTDIRTY; + } } if (prot & PAGE_WRITE_INV) { tn.addr_write |= TLB_INVALID_MASK; @@ -904,7 +905,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc = retaddr; - if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu->can_do_io) { + if (mr != &io_mem_notdirty && !cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); } @@ -945,7 +946,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; - if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu->can_do_io) { + if (mr != &io_mem_notdirty && !cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); } cpu->mem_io_vaddr = addr; @@ -1125,7 +1126,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, } /* Reject I/O access, or other required slow-path. */ - if (tlb_addr & (TLB_NOTDIRTY | TLB_MMIO | TLB_BSWAP)) { + if (tlb_addr & (TLB_NOTDIRTY | TLB_MMIO | TLB_BSWAP | TLB_DISCARD_WRITE)) { return NULL; } @@ -1617,6 +1618,11 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, return; } + /* Ignore writes to ROM. */ + if (unlikely(tlb_addr & TLB_DISCARD_WRITE)) { + return; + } + haddr = (void *)((uintptr_t)addr + entry->addend); /* diff --git a/exec.c b/exec.c index 5f2587b621..ea8c0b18ac 100644 --- a/exec.c +++ b/exec.c @@ -88,7 +88,7 @@ static MemoryRegion *system_io; AddressSpace address_space_io; AddressSpace address_space_memory; -MemoryRegion io_mem_rom, io_mem_notdirty; +MemoryRegion io_mem_notdirty; static MemoryRegion io_mem_unassigned; #endif @@ -192,7 +192,6 @@ typedef struct subpage_t { #define PHYS_SECTION_UNASSIGNED 0 #define PHYS_SECTION_NOTDIRTY 1 -#define PHYS_SECTION_ROM 2 static void io_mem_init(void); static void memory_map_init(void); @@ -1475,8 +1474,6 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu, iotlb = memory_region_get_ram_addr(section->mr) + xlat; if (!section->readonly) { iotlb |= PHYS_SECTION_NOTDIRTY; - } else { - iotlb |= PHYS_SECTION_ROM; } } else { AddressSpaceDispatch *d; @@ -3002,38 +2999,6 @@ static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr) return phys_section_add(map, §ion); } -static void readonly_mem_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - /* Ignore any write to ROM. */ -} - -static bool readonly_mem_accepts(void *opaque, hwaddr addr, - unsigned size, bool is_write, - MemTxAttrs attrs) -{ - return is_write; -} - -/* This will only be used for writes, because reads are special cased - * to directly access the underlying host ram. - */ -static const MemoryRegionOps readonly_mem_ops = { - .write = readonly_mem_write, - .valid.accepts = readonly_mem_accepts, - .endianness = DEVICE_NATIVE_ENDIAN, - .valid = { - .min_access_size = 1, - .max_access_size = 8, - .unaligned = false, - }, - .impl = { - .min_access_size = 1, - .max_access_size = 8, - .unaligned = false, - }, -}; - MemoryRegionSection *iotlb_to_section(CPUState *cpu, hwaddr index, MemTxAttrs attrs) { @@ -3047,8 +3012,6 @@ MemoryRegionSection *iotlb_to_section(CPUState *cpu, static void io_mem_init(void) { - memory_region_init_io(&io_mem_rom, NULL, &readonly_mem_ops, - NULL, NULL, UINT64_MAX); memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX); @@ -3069,8 +3032,6 @@ AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv) assert(n == PHYS_SECTION_UNASSIGNED); n = dummy_section(&d->map, fv, &io_mem_notdirty); assert(n == PHYS_SECTION_NOTDIRTY); - n = dummy_section(&d->map, fv, &io_mem_rom); - assert(n == PHYS_SECTION_ROM); d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 }; From patchwork Wed Sep 25 18:45:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174414 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1027663ill; Wed, 25 Sep 2019 11:58:48 -0700 (PDT) X-Google-Smtp-Source: APXvYqx+bmiUKhUDk2S0pquTEMTOf0xwTL3aKKY8T/yIO7An4ol5LPeq9qdjZW3tXzrVoWJXrolJ X-Received: by 2002:a17:906:5c49:: with SMTP id c9mr724946ejr.78.1569437928392; Wed, 25 Sep 2019 11:58:48 -0700 (PDT) ARC-Seal: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id e18si212846ejq.55.2019.09.25.11.58.48 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Sep 2019 11:58:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jtGcg8nw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56194 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCUx-0005eX-42 for patch@linaro.org; Wed, 25 Sep 2019 14:58:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47122) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCIh-0001qM-E7 for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDCIf-0004JT-GD for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:07 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:37307) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iDCIf-0004IR-7j for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:05 -0400 Received: by mail-pl1-x643.google.com with SMTP id u20so2927089plq.4 for ; Wed, 25 Sep 2019 11:46:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lX5+tQiTw7pbywR4o4yaxcCikFvv/gVg8TPYVx+VaVQ=; b=jtGcg8nw5dEC11J861lR2ghlPLoj+YU76dkTCAPsVXMqqsGU0EA6BMzVnTCCYIEb2f LXy4JOnJZYnT53MQgMyZrRJegokCmHWOKvFVTHSv2vFcUjV3xpr5vh3CQudBuhasSGLt wCQb/6fnFoR2N+b5nDuFOETb593/fCaEg+bcmUaGVXR1bPKRBJJzHXu/4REwtIqW9g8s +OHijnEYUv32L7mtOy8KVFoQ42XD2D112kUxYSPuiaYutvNZ67CoSxF2/8mJfl1ZnBd4 d/QFegVHHU2IQtoPLEpoONTXaxRgm7JUaZFnN3T0uzBGuSrwtJj1ckS3Mtmzvl2ahhR2 SSDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lX5+tQiTw7pbywR4o4yaxcCikFvv/gVg8TPYVx+VaVQ=; b=W4MsWK3ZxwWIJ2Hp4Na03rnQAuJsNsX2ShRg/4ZZS/W+/tyOjsrLU4mcvB5SDd1M9M 9z+zRpY7cacZlwr5txF1Pd7MNVk3KPb4NE8viqAVLVC7I6q7wai9uRfxZ32u/oq5zZHs akGvOzytRqGIc13tJ6s0AtIutsKSmscTR7kA6fo7qLtEJ/v2DPDvw1KKX47Xt5bQxGPP u3GfLqLdMrR/jEQFqm/E+1zesvvfsdBTV7oT8lnEqdB57cbyvPJvV08exTXdZC8KosW2 X5OHl3VDvv7pluFHhsBXLNfZYX2ipuTR4KAi/xj8UdyoSQ1X+eQEoeePVrGdbkVeKMfW 9jKg== X-Gm-Message-State: APjAAAWOLbNlv32QKOj6q+571GDm5HU6MbgVtPoEjbGfxMU4suMf74bX toeLIA+gRsgRdiXTT3E3/nZDHSDdMiQ= X-Received: by 2002:a17:902:a418:: with SMTP id p24mr10551070plq.312.1569437163709; Wed, 25 Sep 2019 11:46:03 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.61]) by smtp.gmail.com with ESMTPSA id l24sm6133229pff.151.2019.09.25.11.46.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 11:46:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 09/16] cputlb: Move NOTDIRTY handling from I/O path to TLB path Date: Wed, 25 Sep 2019 11:45:41 -0700 Message-Id: <20190925184548.30673-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190925184548.30673-1-richard.henderson@linaro.org> References: <20190925184548.30673-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Pages that we want to track for NOTDIRTY are RAM. We do not really need to go through the I/O path to handle them. Acked-by: David Hildenbrand Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/cpu-common.h | 2 -- accel/tcg/cputlb.c | 26 +++++++++++++++++--- exec.c | 50 --------------------------------------- memory.c | 16 ------------- 4 files changed, 23 insertions(+), 71 deletions(-) -- 2.17.1 diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 1c0e03ddc2..81753bbb34 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -100,8 +100,6 @@ void qemu_flush_coalesced_mmio_buffer(void); void cpu_flush_icache_range(hwaddr start, hwaddr len); -extern struct MemoryRegion io_mem_notdirty; - typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque); int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 404ec57a4e..7e9a0f7ac8 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -905,7 +905,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc = retaddr; - if (mr != &io_mem_notdirty && !cpu->can_do_io) { + if (!cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); } @@ -946,7 +946,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; - if (mr != &io_mem_notdirty && !cpu->can_do_io) { + if (!cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); } cpu->mem_io_vaddr = addr; @@ -1612,7 +1612,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, need_swap = size > 1 && (tlb_addr & TLB_BSWAP); /* Handle I/O access. */ - if (likely(tlb_addr & (TLB_MMIO | TLB_NOTDIRTY))) { + if (tlb_addr & TLB_MMIO) { io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, op ^ (need_swap * MO_BSWAP)); return; @@ -1625,6 +1625,26 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, haddr = (void *)((uintptr_t)addr + entry->addend); + /* Handle clean RAM pages. */ + if (tlb_addr & TLB_NOTDIRTY) { + NotDirtyInfo ndi; + + /* We require mem_io_pc in tb_invalidate_phys_page_range. */ + env_cpu(env)->mem_io_pc = retaddr; + + memory_notdirty_write_prepare(&ndi, env_cpu(env), addr, + addr + iotlbentry->addr, size); + + if (unlikely(need_swap)) { + store_memop(haddr, val, op ^ MO_BSWAP); + } else { + store_memop(haddr, val, op); + } + + memory_notdirty_write_complete(&ndi); + return; + } + /* * Keep these two store_memop separate to ensure that the compiler * is able to fold the entire function to a single instruction. diff --git a/exec.c b/exec.c index ea8c0b18ac..dc7001f115 100644 --- a/exec.c +++ b/exec.c @@ -88,7 +88,6 @@ static MemoryRegion *system_io; AddressSpace address_space_io; AddressSpace address_space_memory; -MemoryRegion io_mem_notdirty; static MemoryRegion io_mem_unassigned; #endif @@ -191,7 +190,6 @@ typedef struct subpage_t { } subpage_t; #define PHYS_SECTION_UNASSIGNED 0 -#define PHYS_SECTION_NOTDIRTY 1 static void io_mem_init(void); static void memory_map_init(void); @@ -1472,9 +1470,6 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu, if (memory_region_is_ram(section->mr)) { /* Normal RAM. */ iotlb = memory_region_get_ram_addr(section->mr) + xlat; - if (!section->readonly) { - iotlb |= PHYS_SECTION_NOTDIRTY; - } } else { AddressSpaceDispatch *d; @@ -2783,42 +2778,6 @@ void memory_notdirty_write_complete(NotDirtyInfo *ndi) } } -/* Called within RCU critical section. */ -static void notdirty_mem_write(void *opaque, hwaddr ram_addr, - uint64_t val, unsigned size) -{ - NotDirtyInfo ndi; - - memory_notdirty_write_prepare(&ndi, current_cpu, current_cpu->mem_io_vaddr, - ram_addr, size); - - stn_p(qemu_map_ram_ptr(NULL, ram_addr), size, val); - memory_notdirty_write_complete(&ndi); -} - -static bool notdirty_mem_accepts(void *opaque, hwaddr addr, - unsigned size, bool is_write, - MemTxAttrs attrs) -{ - return is_write; -} - -static const MemoryRegionOps notdirty_mem_ops = { - .write = notdirty_mem_write, - .valid.accepts = notdirty_mem_accepts, - .endianness = DEVICE_NATIVE_ENDIAN, - .valid = { - .min_access_size = 1, - .max_access_size = 8, - .unaligned = false, - }, - .impl = { - .min_access_size = 1, - .max_access_size = 8, - .unaligned = false, - }, -}; - /* Generate a debug exception if a watchpoint has been hit. */ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, MemTxAttrs attrs, int flags, uintptr_t ra) @@ -3014,13 +2973,6 @@ static void io_mem_init(void) { memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX); - - /* io_mem_notdirty calls tb_invalidate_phys_page_fast, - * which can be called without the iothread mutex. - */ - memory_region_init_io(&io_mem_notdirty, NULL, ¬dirty_mem_ops, NULL, - NULL, UINT64_MAX); - memory_region_clear_global_locking(&io_mem_notdirty); } AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv) @@ -3030,8 +2982,6 @@ AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv) n = dummy_section(&d->map, fv, &io_mem_unassigned); assert(n == PHYS_SECTION_UNASSIGNED); - n = dummy_section(&d->map, fv, &io_mem_notdirty); - assert(n == PHYS_SECTION_NOTDIRTY); d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 }; diff --git a/memory.c b/memory.c index 57c44c97db..a99b8c0767 100644 --- a/memory.c +++ b/memory.c @@ -434,10 +434,6 @@ static MemTxResult memory_region_read_accessor(MemoryRegion *mr, tmp = mr->ops->read(mr->opaque, addr, size); if (mr->subpage) { trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size); - } else if (mr == &io_mem_notdirty) { - /* Accesses to code which has previously been translated into a TB show - * up in the MMIO path, as accesses to the io_mem_notdirty - * MemoryRegion. */ } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size); @@ -460,10 +456,6 @@ static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr, r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs); if (mr->subpage) { trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size); - } else if (mr == &io_mem_notdirty) { - /* Accesses to code which has previously been translated into a TB show - * up in the MMIO path, as accesses to the io_mem_notdirty - * MemoryRegion. */ } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size); @@ -484,10 +476,6 @@ static MemTxResult memory_region_write_accessor(MemoryRegion *mr, if (mr->subpage) { trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size); - } else if (mr == &io_mem_notdirty) { - /* Accesses to code which has previously been translated into a TB show - * up in the MMIO path, as accesses to the io_mem_notdirty - * MemoryRegion. */ } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size); @@ -508,10 +496,6 @@ static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr, if (mr->subpage) { trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size); - } else if (mr == &io_mem_notdirty) { - /* Accesses to code which has previously been translated into a TB show - * up in the MMIO path, as accesses to the io_mem_notdirty - * MemoryRegion. */ } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size); From patchwork Wed Sep 25 18:45:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174411 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1025654ill; Wed, 25 Sep 2019 11:56:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqzh1qO6abW6XV56pgiBsqJwPU8jN7MRtQ1L8Y+vCxWRQNwat/tfhP+ufyOA/PV4JyQWmlVr X-Received: by 2002:a37:7403:: with SMTP id p3mr4958638qkc.366.1569437797065; Wed, 25 Sep 2019 11:56:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569437797; cv=none; d=google.com; s=arc-20160816; b=NQJVxo1P69/g0SoJH87/rahTc2vxtf/UmcsbW7cd8YUjyfTcUy9/0ACcFhME4FxuIP RNdaFhYLeNh9QOlp6sZKrEAE/cLaMDslx7QPvPXkO7q6q/c2BnMEpLQt7CRgBQ8vdFzD QHZ9U1KIRHzOY6rDsFH1C5c6/HygBV0AVU6aUcRDuHC00x1nrgukysj5aJITi5g0Vchr 7x1A2l/JukrGmcr5R1tV5nYEeUQw/FuRBfommcyQHj5hiAgF64J2o3Anrq6XbGr53RLe zAh06VoQk6d6nqbW5OKELJZ26xZPWn/UWJHtch8mVuQb6lTL9cNVVzVzSO6qYiBchnEY sh5g== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id w77si4682029qkb.241.2019.09.25.11.56.36 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Sep 2019 11:56:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=obzLGpmu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56150 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCSp-0001v7-V3 for patch@linaro.org; Wed, 25 Sep 2019 14:56:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47152) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCIi-0001s1-OH for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDCIg-0004L5-KO for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:08 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:43872) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iDCIg-0004K9-BU for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:06 -0400 Received: by mail-pl1-x636.google.com with SMTP id f21so539567plj.10 for ; Wed, 25 Sep 2019 11:46:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=thoGiFuad0+sCfOpAMLAT3aKZ6kfKYJYfdagLPNuTGE=; b=obzLGpmus8NXGajsJbBANMPP1Lr9oKl26c9ALC/g3ZVjwdIviv7vHovKTsUKsdr5GX 8UdKcDq2RgoDaJi5E2y8abFH2EtNZf+hGSz5aQOosle62tDMF4+U82BLZ6BlVa5i4r0f symZO6y5FgXpaecoKfYDxWzWdDftRr/NIOsRp9gQTklRBnShR244zyonBxxMv7MQ5cDd d0HczvjrDVGtojvpy9ZMHwd3EgjytwSA8HKUhltokzJOTNkHeWSFXiLzDkMhVIUjgzNE mDAkc7TfHwo+rqDLRwQE15z26wb/wdCqeR8zeEGy2DOPoX3kScAXid2FBmpV6ILNFpMy Pzag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=thoGiFuad0+sCfOpAMLAT3aKZ6kfKYJYfdagLPNuTGE=; b=QNXT1DEbvnS6qi0TjUr4GBNvTLc1E1/cQspOCK/q8bEsZuWPmPl8mf5trv53AUAJES DMqu7qjTfz9xm9CzaSDlleq+YpCgoTKhnLSEScpIN16RdyjIcA/fr0X6Dvr2UtZhFzwZ Cj7JERLIZGquDlAhRytzaWe8NvUNdj8t+mRIp/aWA8Gc437eDBZyWZjwBFKzCYaR2LmI qJOPeYfQLN3rc0rAepl0rsbwhaBdnoAkGsiyJgk1rA1qdQwAhbaHx6qJLsdOq+zswv2V fgJZxh7x5Odk62QX8o24aWit9Z9SKB3o/AdgCYv2CIBH9hiHUxd13GWpfA+nTV4OGFxg kuFQ== X-Gm-Message-State: APjAAAWy3zNX3cJdfWKQamWz0DrhEWWCwnVAd4KaD9FO/ewsMlYNnObN BNJAmgFzAOKC4YLjrlj+WFCfAT6+C+w= X-Received: by 2002:a17:902:7296:: with SMTP id d22mr10991369pll.41.1569437165034; Wed, 25 Sep 2019 11:46:05 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.61]) by smtp.gmail.com with ESMTPSA id l24sm6133229pff.151.2019.09.25.11.46.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 11:46:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 10/16] cputlb: Partially inline memory_region_section_get_iotlb Date: Wed, 25 Sep 2019 11:45:42 -0700 Message-Id: <20190925184548.30673-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190925184548.30673-1-richard.henderson@linaro.org> References: <20190925184548.30673-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::636 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is only one caller, tlb_set_page_with_attrs. We cannot inline the entire function because the AddressSpaceDispatch structure is private to exec.c, and cannot easily be moved to include/exec/memory-internal.h. Compute is_ram and is_romd once within tlb_set_page_with_attrs. Fold the number of tests against these predicates. Compute cpu_physical_memory_is_clean outside of the tlb lock region. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 6 +--- accel/tcg/cputlb.c | 68 ++++++++++++++++++++++++++--------------- exec.c | 22 ++----------- 3 files changed, 47 insertions(+), 49 deletions(-) -- 2.17.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 81b02eb2fe..49db07ba0b 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -509,11 +509,7 @@ address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, hwaddr *xlat, hwaddr *plen, MemTxAttrs attrs, int *prot); hwaddr memory_region_section_get_iotlb(CPUState *cpu, - MemoryRegionSection *section, - target_ulong vaddr, - hwaddr paddr, hwaddr xlat, - int prot, - target_ulong *address); + MemoryRegionSection *section); #endif /* vl.c */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 7e9a0f7ac8..4f118d2cc9 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -705,13 +705,14 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, MemoryRegionSection *section; unsigned int index; target_ulong address; - target_ulong code_address; + target_ulong write_address; uintptr_t addend; CPUTLBEntry *te, tn; hwaddr iotlb, xlat, sz, paddr_page; target_ulong vaddr_page; int asidx = cpu_asidx_from_attrs(cpu, attrs); int wp_flags; + bool is_ram, is_romd; assert_cpu_is_self(cpu); @@ -740,18 +741,46 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, if (attrs.byte_swap) { address |= TLB_BSWAP; } - if (!memory_region_is_ram(section->mr) && - !memory_region_is_romd(section->mr)) { - /* IO memory case */ - address |= TLB_MMIO; - addend = 0; - } else { + + is_ram = memory_region_is_ram(section->mr); + is_romd = memory_region_is_romd(section->mr); + + if (is_ram || is_romd) { + /* RAM and ROMD both have associated host memory. */ addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat; + } else { + /* I/O does not; force the host address to NULL. */ + addend = 0; + } + + write_address = address; + if (is_ram) { + iotlb = memory_region_get_ram_addr(section->mr) + xlat; + /* + * Computing is_clean is expensive; avoid all that unless + * the page is actually writable. + */ + if (prot & PAGE_WRITE) { + if (section->readonly) { + write_address |= TLB_DISCARD_WRITE; + } else if (cpu_physical_memory_is_clean(iotlb)) { + write_address |= TLB_NOTDIRTY; + } + } + } else { + /* I/O or ROMD */ + iotlb = memory_region_section_get_iotlb(cpu, section) + xlat; + /* + * Writes to romd devices must go through MMIO to enable write. + * Reads to romd devices go through the ram_ptr found above, + * but of course reads to I/O must go through MMIO. + */ + write_address |= TLB_MMIO; + if (!is_romd) { + address = write_address; + } } - code_address = address; - iotlb = memory_region_section_get_iotlb(cpu, section, vaddr_page, - paddr_page, xlat, prot, &address); wp_flags = cpu_watchpoint_address_matches(cpu, vaddr_page, TARGET_PAGE_SIZE); @@ -791,8 +820,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, /* * At this point iotlb contains a physical section number in the lower * TARGET_PAGE_BITS, and either - * + the ram_addr_t of the page base of the target RAM (if NOTDIRTY or ROM) - * + the offset within section->mr of the page base (otherwise) + * + the ram_addr_t of the page base of the target RAM (RAM) + * + the offset within section->mr of the page base (I/O, ROMD) * We subtract the vaddr_page (which is page aligned and thus won't * disturb the low bits) to give an offset which can be added to the * (non-page-aligned) vaddr of the eventual memory access to get @@ -815,25 +844,14 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, } if (prot & PAGE_EXEC) { - tn.addr_code = code_address; + tn.addr_code = address; } else { tn.addr_code = -1; } tn.addr_write = -1; if (prot & PAGE_WRITE) { - tn.addr_write = address; - if (memory_region_is_romd(section->mr)) { - /* Use the MMIO path so that the device can switch states. */ - tn.addr_write |= TLB_MMIO; - } else if (memory_region_is_ram(section->mr)) { - if (section->readonly) { - tn.addr_write |= TLB_DISCARD_WRITE; - } else if (cpu_physical_memory_is_clean( - memory_region_get_ram_addr(section->mr) + xlat)) { - tn.addr_write |= TLB_NOTDIRTY; - } - } + tn.addr_write = write_address; if (prot & PAGE_WRITE_INV) { tn.addr_write |= TLB_INVALID_MASK; } diff --git a/exec.c b/exec.c index dc7001f115..961d7d6497 100644 --- a/exec.c +++ b/exec.c @@ -1459,26 +1459,10 @@ bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap, /* Called from RCU critical section */ hwaddr memory_region_section_get_iotlb(CPUState *cpu, - MemoryRegionSection *section, - target_ulong vaddr, - hwaddr paddr, hwaddr xlat, - int prot, - target_ulong *address) + MemoryRegionSection *section) { - hwaddr iotlb; - - if (memory_region_is_ram(section->mr)) { - /* Normal RAM. */ - iotlb = memory_region_get_ram_addr(section->mr) + xlat; - } else { - AddressSpaceDispatch *d; - - d = flatview_to_dispatch(section->fv); - iotlb = section - d->map.sections; - iotlb += xlat; - } - - return iotlb; + AddressSpaceDispatch *d = flatview_to_dispatch(section->fv); + return section - d->map.sections; } #endif /* defined(CONFIG_USER_ONLY) */ From patchwork Wed Sep 25 18:45:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174410 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1025567ill; Wed, 25 Sep 2019 11:56:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqwZQbwu/hiafkF+Tax8Kf8AaDCV9JZiPNx+9Egq0uUKTJ1jc6dSs+v5kb1ONyjtRwEVHO1f X-Received: by 2002:ac8:2c86:: with SMTP id 6mr874330qtw.113.1569437791344; Wed, 25 Sep 2019 11:56:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569437791; 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[209.51.188.17]) by mx.google.com with ESMTPS id p90si390307qtd.327.2019.09.25.11.56.31 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Sep 2019 11:56:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TLp7pkjr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56142 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCSk-0001jM-Ak for patch@linaro.org; Wed, 25 Sep 2019 14:56:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47181) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCIj-0001tH-VZ for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDCIi-0004N4-3C for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:09 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:44313) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iDCIh-0004M7-RF for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:08 -0400 Received: by mail-pg1-x52a.google.com with SMTP id i14so142949pgt.11 for ; Wed, 25 Sep 2019 11:46:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SSIp61nlyQIjm5GOge2E7ScAyXdbAUa4X76UCYWm8z8=; b=TLp7pkjrgsvLed37Ucz8vhb8EZ1g3IaFtw4atqWaiIQsQ9A5N1WZHD1+m8yt+uaYjK YKIjZy3YveQEpDx56YTAcM4xDtH8nw8QDJ7HcnLGlFWcPtPL1+zzXOdNmP5Aiiaau5xV Jgmvw5lT7EoPNpuV7nBFze3ohmtHBfn4QH8bCSvs1p8pISp8e9/IPwswlLoye7DS86pO 7QBH1BQIDAif/sAsu0Z3FyeymemyUemHYJfYHMT7pDD4knlDSzyZcRz1VQ55aaptPCdP JE1higzFy0+RNrsoduik3YLcxfKfZ0i0mq2JzE08d1H7cb0Dduo8mD2EVjwpTEt6I1XQ G/OA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SSIp61nlyQIjm5GOge2E7ScAyXdbAUa4X76UCYWm8z8=; b=J5T7s4f3CmSArU/DOiuHL9DQbFJaRM2Kgzu0BTadeRvfvf8df3oO/pnpmpe8lHixLf OHq3t24SRvVTXKkOyFxrm7fPN70TNCHxuSrMhkZtrT6CpeFxaiSNcPhO9EQLht28+bue sDEuHvhkWwHXeu0RVmodFIal5NY9cYWm/CZV3fINOtsVloF/jE1NiEmGr37/z+/LAmPa KVs4KnpxjK24tdSqft6k+Aq4pphDaZGY2nBma3ncnqUU+qstxtRzCL7sRSSbiyhI90qb 1zFK8GUINWAMDollf2+n8mCtKmw/1TyJgUDyla+WuQgpe/bN1lchItJ7aHUz0LfwiY5R dcjw== X-Gm-Message-State: APjAAAXr92MUIEQcKMnpd6H6whRxM0O5+WvAPR0pUgSBJyGGRtiQdAlk 7XIplV6ynnvDkqbr+KAe0m+6rWkAQic= X-Received: by 2002:a62:7c4d:: with SMTP id x74mr11307843pfc.95.1569437166398; Wed, 25 Sep 2019 11:46:06 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.61]) by smtp.gmail.com with ESMTPSA id l24sm6133229pff.151.2019.09.25.11.46.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 11:46:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 11/16] cputlb: Merge and move memory_notdirty_write_{prepare, complete} Date: Wed, 25 Sep 2019 11:45:43 -0700 Message-Id: <20190925184548.30673-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190925184548.30673-1-richard.henderson@linaro.org> References: <20190925184548.30673-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52a X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since 9458a9a1df1a, all readers of the dirty bitmaps wait for the rcu lock, which means that they wait until the end of any executing TranslationBlock. As a consequence, there is no need for the actual access to happen in between the _prepare and _complete. Therefore, we can improve things by merging the two functions into notdirty_write and dropping the NotDirtyInfo structure. In addition, the only users of notdirty_write are in cputlb.c, so move the merged function there. Pass in the CPUIOTLBEntry from which the ram_addr_t may be computed. Reviewed-by: David Hildenbrand Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/exec/memory-internal.h | 65 ----------------------------- accel/tcg/cputlb.c | 76 +++++++++++++++++++--------------- exec.c | 44 -------------------- 3 files changed, 42 insertions(+), 143 deletions(-) -- 2.17.1 diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h index ef4fb92371..9fcc2af25c 100644 --- a/include/exec/memory-internal.h +++ b/include/exec/memory-internal.h @@ -49,70 +49,5 @@ void address_space_dispatch_free(AddressSpaceDispatch *d); void mtree_print_dispatch(struct AddressSpaceDispatch *d, MemoryRegion *root); - -struct page_collection; - -/* Opaque struct for passing info from memory_notdirty_write_prepare() - * to memory_notdirty_write_complete(). Callers should treat all fields - * as private, with the exception of @active. - * - * @active is a field which is not touched by either the prepare or - * complete functions, but which the caller can use if it wishes to - * track whether it has called prepare for this struct and so needs - * to later call the complete function. - */ -typedef struct { - CPUState *cpu; - struct page_collection *pages; - ram_addr_t ram_addr; - vaddr mem_vaddr; - unsigned size; - bool active; -} NotDirtyInfo; - -/** - * memory_notdirty_write_prepare: call before writing to non-dirty memory - * @ndi: pointer to opaque NotDirtyInfo struct - * @cpu: CPU doing the write - * @mem_vaddr: virtual address of write - * @ram_addr: the ram address of the write - * @size: size of write in bytes - * - * Any code which writes to the host memory corresponding to - * guest RAM which has been marked as NOTDIRTY must wrap those - * writes in calls to memory_notdirty_write_prepare() and - * memory_notdirty_write_complete(): - * - * NotDirtyInfo ndi; - * memory_notdirty_write_prepare(&ndi, ....); - * ... perform write here ... - * memory_notdirty_write_complete(&ndi); - * - * These calls will ensure that we flush any TCG translated code for - * the memory being written, update the dirty bits and (if possible) - * remove the slowpath callback for writing to the memory. - * - * This must only be called if we are using TCG; it will assert otherwise. - * - * We may take locks in the prepare call, so callers must ensure that - * they don't exit (via longjump or otherwise) without calling complete. - * - * This call must only be made inside an RCU critical section. - * (Note that while we're executing a TCG TB we're always in an - * RCU critical section, which is likely to be the case for callers - * of these functions.) - */ -void memory_notdirty_write_prepare(NotDirtyInfo *ndi, - CPUState *cpu, - vaddr mem_vaddr, - ram_addr_t ram_addr, - unsigned size); -/** - * memory_notdirty_write_complete: finish write to non-dirty memory - * @ndi: pointer to the opaque NotDirtyInfo struct which was initialized - * by memory_not_dirty_write_prepare(). - */ -void memory_notdirty_write_complete(NotDirtyInfo *ndi); - #endif #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 4f118d2cc9..3e91838519 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -33,6 +33,7 @@ #include "exec/helper-proto.h" #include "qemu/atomic.h" #include "qemu/atomic128.h" +#include "translate-all.h" /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ @@ -1085,6 +1086,37 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) return qemu_ram_addr_from_host_nofail(p); } +static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size, + CPUIOTLBEntry *iotlbentry, uintptr_t retaddr) +{ + ram_addr_t ram_addr = mem_vaddr + iotlbentry->addr; + + trace_memory_notdirty_write_access(mem_vaddr, ram_addr, size); + + if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { + struct page_collection *pages + = page_collection_lock(ram_addr, ram_addr + size); + + /* We require mem_io_pc in tb_invalidate_phys_page_range. */ + cpu->mem_io_pc = retaddr; + + tb_invalidate_phys_page_fast(pages, ram_addr, size); + page_collection_unlock(pages); + } + + /* + * Set both VGA and migration bits for simplicity and to remove + * the notdirty callback faster. + */ + cpu_physical_memory_set_dirty_range(ram_addr, size, DIRTY_CLIENTS_NOCODE); + + /* We remove the notdirty callback only if the code has been flushed. */ + if (!cpu_physical_memory_is_clean(ram_addr)) { + trace_memory_notdirty_set_dirty(mem_vaddr); + tlb_set_dirty(cpu, mem_vaddr); + } +} + /* * Probe for whether the specified guest access is permitted. If it is not * permitted then an exception will be taken in the same way as if this @@ -1204,8 +1236,7 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, /* Probe for a read-modify-write atomic operation. Do not allow unaligned * operations, or io operations to proceed. Return the host address. */ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr, - NotDirtyInfo *ndi) + TCGMemOpIdx oi, uintptr_t retaddr) { size_t mmu_idx = get_mmuidx(oi); uintptr_t index = tlb_index(env, mmu_idx, addr); @@ -1265,12 +1296,9 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, hostaddr = (void *)((uintptr_t)addr + tlbe->addend); - ndi->active = false; if (unlikely(tlb_addr & TLB_NOTDIRTY)) { - ndi->active = true; - memory_notdirty_write_prepare(ndi, env_cpu(env), addr, - qemu_ram_addr_from_host_nofail(hostaddr), - 1 << s_bits); + notdirty_write(env_cpu(env), addr, 1 << s_bits, + &env_tlb(env)->d[mmu_idx].iotlb[index], retaddr); } return hostaddr; @@ -1641,28 +1669,13 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, return; } - haddr = (void *)((uintptr_t)addr + entry->addend); - /* Handle clean RAM pages. */ if (tlb_addr & TLB_NOTDIRTY) { - NotDirtyInfo ndi; - - /* We require mem_io_pc in tb_invalidate_phys_page_range. */ - env_cpu(env)->mem_io_pc = retaddr; - - memory_notdirty_write_prepare(&ndi, env_cpu(env), addr, - addr + iotlbentry->addr, size); - - if (unlikely(need_swap)) { - store_memop(haddr, val, op ^ MO_BSWAP); - } else { - store_memop(haddr, val, op); - } - - memory_notdirty_write_complete(&ndi); - return; + notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr); } + haddr = (void *)((uintptr_t)addr + entry->addend); + /* * Keep these two store_memop separate to ensure that the compiler * is able to fold the entire function to a single instruction. @@ -1793,14 +1806,9 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, #define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr #define ATOMIC_NAME(X) \ HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu)) -#define ATOMIC_MMU_DECLS NotDirtyInfo ndi -#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, oi, retaddr, &ndi) -#define ATOMIC_MMU_CLEANUP \ - do { \ - if (unlikely(ndi.active)) { \ - memory_notdirty_write_complete(&ndi); \ - } \ - } while (0) +#define ATOMIC_MMU_DECLS +#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, oi, retaddr) +#define ATOMIC_MMU_CLEANUP #define DATA_SIZE 1 #include "atomic_template.h" @@ -1828,7 +1836,7 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, #undef ATOMIC_MMU_LOOKUP #define EXTRA_ARGS , TCGMemOpIdx oi #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) -#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, oi, GETPC(), &ndi) +#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, oi, GETPC()) #define DATA_SIZE 1 #include "atomic_template.h" diff --git a/exec.c b/exec.c index 961d7d6497..7d835b1a2b 100644 --- a/exec.c +++ b/exec.c @@ -2718,50 +2718,6 @@ ram_addr_t qemu_ram_addr_from_host(void *ptr) return block->offset + offset; } -/* Called within RCU critical section. */ -void memory_notdirty_write_prepare(NotDirtyInfo *ndi, - CPUState *cpu, - vaddr mem_vaddr, - ram_addr_t ram_addr, - unsigned size) -{ - ndi->cpu = cpu; - ndi->ram_addr = ram_addr; - ndi->mem_vaddr = mem_vaddr; - ndi->size = size; - ndi->pages = NULL; - - trace_memory_notdirty_write_access(mem_vaddr, ram_addr, size); - - assert(tcg_enabled()); - if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { - ndi->pages = page_collection_lock(ram_addr, ram_addr + size); - tb_invalidate_phys_page_fast(ndi->pages, ram_addr, size); - } -} - -/* Called within RCU critical section. */ -void memory_notdirty_write_complete(NotDirtyInfo *ndi) -{ - if (ndi->pages) { - assert(tcg_enabled()); - page_collection_unlock(ndi->pages); - ndi->pages = NULL; - } - - /* Set both VGA and migration bits for simplicity and to remove - * the notdirty callback faster. - */ - cpu_physical_memory_set_dirty_range(ndi->ram_addr, ndi->size, - DIRTY_CLIENTS_NOCODE); - /* we remove the notdirty callback only if the code has been - flushed */ - if (!cpu_physical_memory_is_clean(ndi->ram_addr)) { - trace_memory_notdirty_set_dirty(ndi->mem_vaddr); - tlb_set_dirty(ndi->cpu, ndi->mem_vaddr); - } -} - /* Generate a debug exception if a watchpoint has been hit. */ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, MemTxAttrs attrs, int flags, uintptr_t ra) From patchwork Wed Sep 25 18:45:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174416 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1031820ill; Wed, 25 Sep 2019 12:02:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqxcyGloCqDBrIT2hvzL+lJGSvyaG4IX5xweF0FzMWlcRpZay7NxRlapmkpWZEefHTzSlZX+ X-Received: by 2002:a5d:52c8:: with SMTP id r8mr11294422wrv.256.1569438132473; Wed, 25 Sep 2019 12:02:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569438132; cv=none; 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[209.51.188.17]) by mx.google.com with ESMTPS id g15si3747849edm.349.2019.09.25.12.02.12 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Sep 2019 12:02:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="j8sr21E/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCYE-0000zD-F9 for patch@linaro.org; Wed, 25 Sep 2019 15:02:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47196) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCIk-0001u2-LN for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDCIj-0004OP-F0 for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:10 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:44244) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iDCIj-0004NZ-5J for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:09 -0400 Received: by mail-pg1-x542.google.com with SMTP id i14so142992pgt.11 for ; Wed, 25 Sep 2019 11:46:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yAC6RG3wvhI3H3mXOjF1M8pzwn6maoZxTmCA0mspbiE=; b=j8sr21E/7b0HcIha4bK+txI5RcHSDB5hgO/mBCmw9C01jPpwe0EJhDMezWYD1nSHxN 45k4cZSLyb5qnB2D2+F4z/1u3LSe5S7AndiUdnxMEKrjyTdlG5tCp/Yrdhf77uk5jpxH brqBILK9azxYj9SPKlfbAuFlWRre3WYTw6usQ1/x8Wf2js9amISDTvgZUxXJznwq85mx 3/3X1VHHAKMoG0PQJ1WNotV2+YxUYqoxFGSbDBISLaqn9fWWb/QiWkJIiKIKQNwIZetf Gsv8xruh1O/yvbYo+zpLlG3FpD42CZsSVvHOasjKL7uNWe/T3G8G3yAmYgwG/zgaGhqG 4KXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yAC6RG3wvhI3H3mXOjF1M8pzwn6maoZxTmCA0mspbiE=; b=FPKYXiX8jjAWTEfVgpx86SA2s7obenYhsCuhV3YO6bhyKgT/sk8WDD1f5cVTLD8uzu PkXt+LKaStqKSre88DAq6ANoUbZexrEoJOmVGpeAG2ymIsYtf0CcJx4sz0OAjb9X994j btewq79a/N7DRooTw1yO7EJTy8KeLLdNeWmP2ZbWL+7qF9DRNpBJFXU+0mBCGsW9ZR/0 50VSHvJy6FXcFzidxX/29yx3Qa2lf67WuoNexnub5rCulGJl8nH+Y/tNgnnAKOaEYxWg YnGat2oVLBgKKXaEnKKH6cuYc4eHkgjPgl2nNw0Tx881+uf4C2VFhseSJVXqe54KeSbO TDow== X-Gm-Message-State: APjAAAXAo/iKgaBfRYYKx51koWpaq4EBD7YrMZkAPIRy4gSkv2oOFCpe NwMvkB578fQJo53dmPhEGqq5JUbUcII= X-Received: by 2002:a17:90a:b385:: with SMTP id e5mr8169741pjr.91.1569437167666; Wed, 25 Sep 2019 11:46:07 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.61]) by smtp.gmail.com with ESMTPSA id l24sm6133229pff.151.2019.09.25.11.46.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 11:46:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 12/16] cputlb: Handle TLB_NOTDIRTY in probe_access Date: Wed, 25 Sep 2019 11:45:44 -0700 Message-Id: <20190925184548.30673-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190925184548.30673-1-richard.henderson@linaro.org> References: <20190925184548.30673-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can use notdirty_write for the write and return a valid host pointer for this case. Reviewed-by: David Hildenbrand Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 3e91838519..b56e9ddf8c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1168,16 +1168,24 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return NULL; } - /* Handle watchpoints. */ - if (tlb_addr & TLB_WATCHPOINT) { - cpu_check_watchpoint(env_cpu(env), addr, size, - env_tlb(env)->d[mmu_idx].iotlb[index].attrs, - wp_access, retaddr); - } + if (unlikely(tlb_addr & TLB_FLAGS_MASK)) { + CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index]; - /* Reject I/O access, or other required slow-path. */ - if (tlb_addr & (TLB_NOTDIRTY | TLB_MMIO | TLB_BSWAP | TLB_DISCARD_WRITE)) { - return NULL; + /* Reject I/O access, or other required slow-path. */ + if (tlb_addr & (TLB_MMIO | TLB_BSWAP | TLB_DISCARD_WRITE)) { + return NULL; + } + + /* Handle watchpoints. */ + if (tlb_addr & TLB_WATCHPOINT) { + cpu_check_watchpoint(env_cpu(env), addr, size, + iotlbentry->attrs, wp_access, retaddr); + } + + /* Handle clean RAM pages. */ + if (tlb_addr & TLB_NOTDIRTY) { + notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr); + } } return (void *)((uintptr_t)addr + entry->addend); From patchwork Wed Sep 25 18:45:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174415 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1027768ill; Wed, 25 Sep 2019 11:58:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqyq4YT6XPoheL5zCikVAij+UrHmjKFlfVa82BSPHuNr+eZ4xxasrdiZ4qdhS4TgsCYMsXW7 X-Received: by 2002:a17:906:9703:: with SMTP id k3mr653665ejx.159.1569437935699; Wed, 25 Sep 2019 11:58:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569437935; cv=none; d=google.com; s=arc-20160816; b=P5JyrR8OaHkpG4EOKNgEzFtAD7eMiFnW1NgWR2agt31EtGkjzIl6eb6hH1Zq+AALpd JP0oRbX71Famuo5aROn75Qt/uhpZqSzG8qBUh/ESo3me5Z8CUcUTfgX4zCr94esgfBoD mh/yNBBPrlVq49WtyxoZOgqcpc06dbNOr1A+hlDchcVDwXJDGMPwmtfl54ZgdsMH1XUE MYpnid3THs0Q9TR9/vTMwlo6hGJfsa5ROr4SjCOxduAFupmBQH1uJzoREcrwu8gp59Uy br7cL4KA2B3S/uYekaJm8z8Jj+9f0BGRaCxYf8zlJZf7/imBjotXuLw/qmCFhP4enQum 0CXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fp+IhM5CQTB4UG88fPA7PY7U/XNGkntrALZi2zvKv3E=; b=ToVu3Ogm6ZnjjOgH0NOVlGBOUoshQesi/uFbRoAwbZHk41FsPiVYTwOEXs9nlu0X4h Iic/ST17F5PLBWfX0glzwUrUYFJBD4FJTG8U6q6bv4M8NvQbkM3ROMs5gKbANOlME0ot bsICptCsMRBHxBcXVvr8tMmrTHZ4RkaZXAzLl2UD6SEuO2GGxh3B0XiSagWh59y7bD5t URzNPVr1rGYZluB0Ys1RDQ+O3IZHMJa0O6wi1ZAmVd7RengfR+/eE7X7ZYDrt47nEw5L K8Ac0c6Y/XB69I5g9Wr3mEPP7roEJl4PgpFbGCFwvkAKeenK7aDmX87ohl/0DYtjSxki VQCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=faxW6FtG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b12si4328679edk.16.2019.09.25.11.58.55 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Sep 2019 11:58:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=faxW6FtG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56210 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCV4-000624-Dz for patch@linaro.org; Wed, 25 Sep 2019 14:58:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47244) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCIm-0001w9-Ci for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDCIl-0004QW-0q for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:12 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:42028) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iDCIk-0004Pf-RR for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:10 -0400 Received: by mail-pf1-x443.google.com with SMTP id q12so4145411pff.9 for ; Wed, 25 Sep 2019 11:46:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fp+IhM5CQTB4UG88fPA7PY7U/XNGkntrALZi2zvKv3E=; b=faxW6FtGYTuPX1Z9H1uXQIDVHyVZmJo4OpZK6UyixfJ6RjM1HW5/XzQfdNaPeKPIIy CfqjcD7e1eUpJyEeJPYv2PlXER9rzjbbzpiJX6tFkaB48fGhkLoxhLPp6JFW+57vzsfL SuWuJz8nIuvllc/qXQHX95B2mEfUmQxQvUijyL/ASzhZafMQxio7q9CqP5EfkgLPU8GE Ofp3K7H97Y9f4akCJcMiFeSeqhZTjyF6ZZz+IiNgj9VvxRZIIB5XkC9j5kG+h6IEjFne rkw6dgXdr6uPLcxRXg8oDEHTX0Ec2nHOnt3+zfA0QjRJxagY8vf36vHMyp73yn9CE93g +xHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fp+IhM5CQTB4UG88fPA7PY7U/XNGkntrALZi2zvKv3E=; b=RC/3bJ0j+Cxhd9idwl4gbUDpYNPpV+Tr2fRjPb/EX1NH4QpoTrJJwi9fHKEoVUegg+ MujKxVS/elUKO+eGouHAqz83c4Q9xMfmZPZ3aTO5ntcvRmhLHcHxfR8fpVNkFDavMviv KCtfZMDOS7/XRI28Q9e8mjL7b39k5ZPv/P1NnJc7ijXfVYDCv4xHcQO4ZLhF6clOu2yb i6/Hee3su80rnd+Uz1fBBIkznjBZwZ+s1GFhXb2THtcxJBJW9NLhyewqHA5GXqEOIvG9 42gjQWnlMHyct/a2LwZy7dzF4ql10kM66r7cecgeRNpWDuGrVzpKkhVU+JTiqCmIg5Xx uCtQ== X-Gm-Message-State: APjAAAV4LC+dYGH3FbgVB84y5L3rJDCHtL9HbXaKLeqPWv2IBXUWIWgY bDMYkvBPnJ0/O+YJip0f3uk4uRB+Z/Q= X-Received: by 2002:a17:90a:9ca:: with SMTP id 68mr7989502pjo.66.1569437169030; Wed, 25 Sep 2019 11:46:09 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.61]) by smtp.gmail.com with ESMTPSA id l24sm6133229pff.151.2019.09.25.11.46.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 11:46:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 13/16] cputlb: Remove cpu->mem_io_vaddr Date: Wed, 25 Sep 2019 11:45:45 -0700 Message-Id: <20190925184548.30673-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190925184548.30673-1-richard.henderson@linaro.org> References: <20190925184548.30673-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With the merge of notdirty handling into store_helper, the last user of cpu->mem_io_vaddr was removed. Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 2 -- accel/tcg/cputlb.c | 2 -- hw/core/cpu.c | 1 - 3 files changed, 5 deletions(-) -- 2.17.1 diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c7cda65c66..031f587e51 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -338,7 +338,6 @@ struct qemu_work_item; * @next_cpu: Next CPU sharing TB cache. * @opaque: User data. * @mem_io_pc: Host Program Counter at which the memory was accessed. - * @mem_io_vaddr: Target virtual address at which the memory was accessed. * @kvm_fd: vCPU file descriptor for KVM. * @work_mutex: Lock to prevent multiple access to queued_work_*. * @queued_work_first: First asynchronous work pending. @@ -413,7 +412,6 @@ struct CPUState { * we store some rarely used information in the CPU context. */ uintptr_t mem_io_pc; - vaddr mem_io_vaddr; /* * This is only needed for the legacy cpu_unassigned_access() hook; * when all targets using it have been converted to use diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b56e9ddf8c..4b24811ce7 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -928,7 +928,6 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, cpu_io_recompile(cpu, retaddr); } - cpu->mem_io_vaddr = addr; cpu->mem_io_access_type = access_type; if (mr->global_locking && !qemu_mutex_iothread_locked()) { @@ -968,7 +967,6 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, if (!cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); } - cpu->mem_io_vaddr = addr; cpu->mem_io_pc = retaddr; if (mr->global_locking && !qemu_mutex_iothread_locked()) { diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 0035845511..73b1ee34d0 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -261,7 +261,6 @@ static void cpu_common_reset(CPUState *cpu) cpu->interrupt_request = 0; cpu->halted = 0; cpu->mem_io_pc = 0; - cpu->mem_io_vaddr = 0; cpu->icount_extra = 0; atomic_set(&cpu->icount_decr_ptr->u32, 0); cpu->can_do_io = 1; From patchwork Wed Sep 25 18:45:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174417 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1033120ill; Wed, 25 Sep 2019 12:03:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqxMvB1Dpj+NSr0DI3FNAGb9K7QVxC2RCHo6WET8t+cNb/rhJXRhibeNB9A+B1RbIgi3OkbH X-Received: by 2002:ac8:5245:: with SMTP id y5mr944623qtn.33.1569438187769; Wed, 25 Sep 2019 12:03:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569438187; cv=none; d=google.com; s=arc-20160816; b=WCvIlTRZO4Bu6DQHUO0vlJNDkSmVmk3pDIBMDujROcduV6Zv8CGzoPwGQ4C+rNorWQ oQn0Ow3t701GspwPNnEGbOYOffZRTpWGeejYWyNVYB3AfBBrAZ+lHQaa4zkjaGF5Tyef 4BqsXrNHRak2hB9bTX5OuAppQNCM5KfIAQhcH2xYnYJR0BaSUpJfne44W0AM0d5235L+ Pp9mPyO03qOf4gwNR714ij+VEYa8VJBAi52UIJ8+8nu6BNcfMn6CLffpqjpx8b+lPQp3 iHj9kjB8isvQ2+EHSIqMcEUXkmNjY6C6VncmicK48o0hP4x8JYJwtzVivws8WZRB7WVf HSCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=60zIbLUAmUNSEgAQIKyqCRl8+f6RWn+eou5eyJkQXA8=; b=uv5KIbLO8xC5ASTxuKy6Te0ejdjVmcZIIslKGngJYqwn1Jcjsqp8ZwjGEgdOhtuMLq Ynex1RWP5wlPi62xQHCtQNrx7hJXew2xgm257LdDAruzhWR6o03vpag+OAgHQn/Czuf9 ScypPWRbu3hw97n8fELMdV4gpzlvclzecD1oEytELZOKR5giPRog2dQ7ChIXXFEMfF5c /ycpmDoxYcGTq/vDTF9s0K2yPDUkGk75QMW4atiC2WfXwsi2K8tuA4QOnGx1uaf96GQ7 YLpklZe21zw7XzDBC8kLRnMtv9mpgino5Di/ecwIYtHxjpvb2BLBcPHAkoQWKSrqr4d/ NI3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xrCPvpri; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 14si430604qvs.26.2019.09.25.12.03.07 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Sep 2019 12:03:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xrCPvpri; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56252 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCZ8-00015u-VE for patch@linaro.org; Wed, 25 Sep 2019 15:03:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47276) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCIq-00020L-0u for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDCIm-0004Sl-F9 for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:13 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:45561) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iDCIm-0004Rc-98 for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:12 -0400 Received: by mail-pg1-x542.google.com with SMTP id 4so360227pgm.12 for ; Wed, 25 Sep 2019 11:46:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=60zIbLUAmUNSEgAQIKyqCRl8+f6RWn+eou5eyJkQXA8=; b=xrCPvprifaONXZagZ/fLiCRF0Tp5WX4YVEhS72UkFdTUxPK+uVjcB9kbg934woTf8+ x1dUu7KyBEpkmeOuRycTGdgTIbKZg9ASP3so9ouWNqcb+NU5xCucBbnMqYTbqmo4rWQ5 GuVB5vc4VeXsHaI/kLo5pKRnvfIOblOVZ/rtGxbPVZUrOvI9WGlCL2J0mtBhQcVtwo0J QRSPHhGbFO62lcBncVwXgnkBWQR3L2lfvKU0GMJtOg6X9mbeF5N8uo6xlTcUVSxFUKMS lrKeHsQSSR0akGKVKq2IW4sPcW9bXor6306M8bzd0IfIpfEQ2hGv2IqKn/nrfBLCoonr MqDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=60zIbLUAmUNSEgAQIKyqCRl8+f6RWn+eou5eyJkQXA8=; b=LFd6ho3whf8NYlIoBy/Uh3D/x/6vZ7rKx1iGNe8EVnuVG6qYzAcOUg1bxfHqRGmhrD J42AJnhTLE2/6OyC5MtGoEQQETNzbb6XM4tk+xsSiPnUWtcnWD7XRzokQmNorrx3uBrh d6lLThbO33i/531dDUjc3htl8YPSBtSbF6fFmMVKHoBZP0TnvVWV7q2bpcPQSvVvap6W WHqYcNylOMtsr9BK1D/fe0u9/eETMik6y3gDydrwXMWQBshTwFiVxXXvcHd2Nln4EsIo LbNLOcZkz4rYzMENrDSYrp4QFRhLGjK5VzcFdJyVDKT+axgi+G95euSfjz14PW29SEXF 2BQA== X-Gm-Message-State: APjAAAUUUI1t6NmngSvTAGx+TsiKFIrlPyTEaLxWUrfuGdhcI7wDUYOj IwHg8SBRHAnwWNlkKYo3qr14cwbcxLk= X-Received: by 2002:a17:90b:946:: with SMTP id dw6mr8133586pjb.48.1569437170739; Wed, 25 Sep 2019 11:46:10 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.61]) by smtp.gmail.com with ESMTPSA id l24sm6133229pff.151.2019.09.25.11.46.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 11:46:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 14/16] cputlb: Remove tb_invalidate_phys_page_range is_cpu_write_access Date: Wed, 25 Sep 2019 11:45:46 -0700 Message-Id: <20190925184548.30673-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190925184548.30673-1-richard.henderson@linaro.org> References: <20190925184548.30673-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" All callers pass false to this argument. Remove it and pass the constant on to tb_invalidate_phys_page_range__locked. Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- accel/tcg/translate-all.h | 3 +-- accel/tcg/translate-all.c | 6 ++---- exec.c | 4 ++-- 3 files changed, 5 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/accel/tcg/translate-all.h b/accel/tcg/translate-all.h index 64f5fd9a05..31f2117188 100644 --- a/accel/tcg/translate-all.h +++ b/accel/tcg/translate-all.h @@ -28,8 +28,7 @@ struct page_collection *page_collection_lock(tb_page_addr_t start, void page_collection_unlock(struct page_collection *set); void tb_invalidate_phys_page_fast(struct page_collection *pages, tb_page_addr_t start, int len); -void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, - int is_cpu_write_access); +void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end); void tb_check_watchpoint(CPUState *cpu); #ifdef CONFIG_USER_ONLY diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 5d1e08b169..de4b697163 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1983,8 +1983,7 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages, * * Called with mmap_lock held for user-mode emulation */ -void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, - int is_cpu_write_access) +void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end) { struct page_collection *pages; PageDesc *p; @@ -1996,8 +1995,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, return; } pages = page_collection_lock(start, end); - tb_invalidate_phys_page_range__locked(pages, p, start, end, - is_cpu_write_access); + tb_invalidate_phys_page_range__locked(pages, p, start, end, 0); page_collection_unlock(pages); } diff --git a/exec.c b/exec.c index 7d835b1a2b..b3df826039 100644 --- a/exec.c +++ b/exec.c @@ -1012,7 +1012,7 @@ const char *parse_cpu_option(const char *cpu_option) void tb_invalidate_phys_addr(target_ulong addr) { mmap_lock(); - tb_invalidate_phys_page_range(addr, addr + 1, 0); + tb_invalidate_phys_page_range(addr, addr + 1); mmap_unlock(); } @@ -1039,7 +1039,7 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs) return; } ram_addr = memory_region_get_ram_addr(mr) + addr; - tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); + tb_invalidate_phys_page_range(ram_addr, ram_addr + 1); rcu_read_unlock(); } From patchwork Wed Sep 25 18:45:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174418 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1035227ill; Wed, 25 Sep 2019 12:04:49 -0700 (PDT) X-Google-Smtp-Source: APXvYqzJ4i7ECR7o6xOSOx0cfUhKFt0t/JCZlINNrxDIy2jc91pY3Tb713NQx7VxX3jSmfCCGgHh X-Received: by 2002:ac8:554a:: with SMTP id o10mr1028793qtr.0.1569438289367; Wed, 25 Sep 2019 12:04:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569438289; cv=none; d=google.com; s=arc-20160816; b=Y/TnuK81ZSMclt23OiVmnebJ0vacUvyknmP6vzbK0IQi4XG/AvopsbgQrckx1cGWVr Ds6y3HsrXaq1gkiqNzvjzLyREYXbX2KoX7kfN/MMEVb/6q8g/D3WTBU8kYN3NmfvXkK1 1MQynObcpi4DaxkyJgNPcbdJOZEO881CkhWxQSEevFmkCC5x5uq8Q9eDgZgDMRj8bl1u nzEG2aXDDEbBSFC29Tm/XOKhoM3FrsgQ+qAHHmLmEJnkrRDEh1mxq7NhNuJSL+9mbIYd uXbKBD1aZXZsZOCkyYAgQouck1V8l06HYs/eAGHPDyzAvAa2j9v9ZjBj5Ksc3sgs+2NO OLQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MGym46ItcVgrFEop1vv6vOBmHP52BveKepQrEUSeRf8=; b=SEZK03Zjz/p3KyYGxp3ZGJ6qct029adQ3A6lo+uOZlSwLVioKv4u579PTQ8jrgKVvm q9YbM7fNOwBs2Df94gNpJkY8hfizFN23j8EDUefb2oaI3CAmAlk9Neg4ZLbT1GsCRfjr TrYu7gVaQ6tAGIYlg8XxJvyz01MkdpYhGjLl26MTa+H99OoMeyJwFEDmWMpPLJm12DmF cKBNov82vG9Lykvfv3sh1Gbmh9XVW7KXwuVH/Jw9fjSdHke8Ct9Ui6o0y9uFePc5UHhs +tHsoiknwQ/dlTtcC7wgpeLf5P4YZIWq+/gtzxjuAhM6ZJ/+2JiTZFwd5rZohWLIG9ZH iy7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="F69/UaKN"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o17si4288774qkm.364.2019.09.25.12.04.49 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Sep 2019 12:04:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="F69/UaKN"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56284 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCam-0004EI-K0 for patch@linaro.org; Wed, 25 Sep 2019 15:04:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47309) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCIs-00020u-6y for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDCIq-0004WW-Qv for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:18 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:33710) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iDCIo-0004T7-Sb for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:16 -0400 Received: by mail-pf1-x442.google.com with SMTP id q10so4173653pfl.0 for ; Wed, 25 Sep 2019 11:46:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MGym46ItcVgrFEop1vv6vOBmHP52BveKepQrEUSeRf8=; b=F69/UaKN4W2rsE5fVmNSn9hPI1nAh1iHfCIvkiuPnoI6UPuG01lZsNOGl6Ss7X/nEX yul8FhTqwAiztkTzCfmc5J72iK/1kLahPqUnS97vFFFalgfzdAAzxGrRra5gdGR6i5t9 9VyZr+mcKb8bLFfuO85oYXazdC4r1TA0/DMqx9JfaV9NLdl2TiZRJ3FAmyEcQqfesC6O QAOcK63SNaQwWMfKDx4tzgaPt1wX5qgb1yKa20N2KNLcCDynYJOD8V++CozRNSa6erxN XWHqRBXgF/yitzcMq+2urThLkeqdZ3ICM4cEKPzNzLtLDJQ0II4RtD8qB0lCXAe5i0vK y5pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MGym46ItcVgrFEop1vv6vOBmHP52BveKepQrEUSeRf8=; b=iKhEiJIj1HxGDBSYywvuLgRsmI/PCk6Q8yOUM0azHhsXyZk6slqCODoisUMT81poj9 2J0zW8hB3ldY+MZJm13OkRKzPBf4rl1sCpNUFRXU+ptLwaBuOj9F2lPVONi7RYnTROeQ ahuYwfgKn15+dQd3ygQx7hBGlsH8kb4xltLBTj7RLneMwkl0h4jy8SwEermp7uzu8bxH AEN9WWTDUZRLBQKy05r6C5l1f20P8CIl+IRxlMBJP3TFvFuCcAcr+X4UrgriFWh/5xWn QPZdtvatlEpZkyRu/KCzmw/V49Hv4vx5aXFIDW6vGxnYXX0qXnfVuxlqFpWoQH1kWqHR 6dCQ== X-Gm-Message-State: APjAAAWglx0n0sfes5c/JKkWl8vGsNDREFRq5SaYXUMava9MHGSqMazq m3K23HpPm/kmV/HohJGmFiqODtzb8aI= X-Received: by 2002:a17:90a:264a:: with SMTP id l68mr8280471pje.74.1569437172186; Wed, 25 Sep 2019 11:46:12 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.61]) by smtp.gmail.com with ESMTPSA id l24sm6133229pff.151.2019.09.25.11.46.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 11:46:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 15/16] cputlb: Pass retaddr to tb_invalidate_phys_page_fast Date: Wed, 25 Sep 2019 11:45:47 -0700 Message-Id: <20190925184548.30673-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190925184548.30673-1-richard.henderson@linaro.org> References: <20190925184548.30673-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rather than rely on cpu->mem_io_pc, pass retaddr down directly. Within tb_invalidate_phys_page_range__locked, the is_cpu_write_access parameter is non-zero exactly when retaddr would be non-zero, so that is a simple replacement. Recognize that current_tb_not_found is true only when mem_io_pc (and now retaddr) are also non-zero, so remove a redundant test. Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- accel/tcg/translate-all.h | 3 ++- accel/tcg/cputlb.c | 6 +----- accel/tcg/translate-all.c | 39 +++++++++++++++++++-------------------- 3 files changed, 22 insertions(+), 26 deletions(-) -- 2.17.1 diff --git a/accel/tcg/translate-all.h b/accel/tcg/translate-all.h index 31f2117188..135c1ea96a 100644 --- a/accel/tcg/translate-all.h +++ b/accel/tcg/translate-all.h @@ -27,7 +27,8 @@ struct page_collection *page_collection_lock(tb_page_addr_t start, tb_page_addr_t end); void page_collection_unlock(struct page_collection *set); void tb_invalidate_phys_page_fast(struct page_collection *pages, - tb_page_addr_t start, int len); + tb_page_addr_t start, int len, + uintptr_t retaddr); void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end); void tb_check_watchpoint(CPUState *cpu); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 4b24811ce7..defc8d5929 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1094,11 +1094,7 @@ static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size, if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { struct page_collection *pages = page_collection_lock(ram_addr, ram_addr + size); - - /* We require mem_io_pc in tb_invalidate_phys_page_range. */ - cpu->mem_io_pc = retaddr; - - tb_invalidate_phys_page_fast(pages, ram_addr, size); + tb_invalidate_phys_page_fast(pages, ram_addr, size, retaddr); page_collection_unlock(pages); } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index de4b697163..db77fb221b 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1889,7 +1889,7 @@ static void tb_invalidate_phys_page_range__locked(struct page_collection *pages, PageDesc *p, tb_page_addr_t start, tb_page_addr_t end, - int is_cpu_write_access) + uintptr_t retaddr) { TranslationBlock *tb; tb_page_addr_t tb_start, tb_end; @@ -1897,9 +1897,9 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages, #ifdef TARGET_HAS_PRECISE_SMC CPUState *cpu = current_cpu; CPUArchState *env = NULL; - int current_tb_not_found = is_cpu_write_access; + bool current_tb_not_found = retaddr != 0; + bool current_tb_modified = false; TranslationBlock *current_tb = NULL; - int current_tb_modified = 0; target_ulong current_pc = 0; target_ulong current_cs_base = 0; uint32_t current_flags = 0; @@ -1931,24 +1931,21 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages, if (!(tb_end <= start || tb_start >= end)) { #ifdef TARGET_HAS_PRECISE_SMC if (current_tb_not_found) { - current_tb_not_found = 0; - current_tb = NULL; - if (cpu->mem_io_pc) { - /* now we have a real cpu fault */ - current_tb = tcg_tb_lookup(cpu->mem_io_pc); - } + current_tb_not_found = false; + /* now we have a real cpu fault */ + current_tb = tcg_tb_lookup(retaddr); } if (current_tb == tb && (tb_cflags(current_tb) & CF_COUNT_MASK) != 1) { - /* If we are modifying the current TB, we must stop - its execution. We could be more precise by checking - that the modification is after the current PC, but it - would require a specialized function to partially - restore the CPU state */ - - current_tb_modified = 1; - cpu_restore_state_from_tb(cpu, current_tb, - cpu->mem_io_pc, true); + /* + * If we are modifying the current TB, we must stop + * its execution. We could be more precise by checking + * that the modification is after the current PC, but it + * would require a specialized function to partially + * restore the CPU state. + */ + current_tb_modified = true; + cpu_restore_state_from_tb(cpu, current_tb, retaddr, true); cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, ¤t_flags); } @@ -2042,7 +2039,8 @@ void tb_invalidate_phys_range(target_ulong start, target_ulong end) * Call with all @pages in the range [@start, @start + len[ locked. */ void tb_invalidate_phys_page_fast(struct page_collection *pages, - tb_page_addr_t start, int len) + tb_page_addr_t start, int len, + uintptr_t retaddr) { PageDesc *p; @@ -2069,7 +2067,8 @@ void tb_invalidate_phys_page_fast(struct page_collection *pages, } } else { do_invalidate: - tb_invalidate_phys_page_range__locked(pages, p, start, start + len, 1); + tb_invalidate_phys_page_range__locked(pages, p, start, start + len, + retaddr); } } #else From patchwork Wed Sep 25 18:45:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174419 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1040481ill; Wed, 25 Sep 2019 12:09:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqxeolDw24kY2SF5MQNmwXyPTTmdOpgGggN+wjuThd3nsGOcBRW2xAX+Jhm2EWjZBhJI72x+ X-Received: by 2002:a0c:b596:: with SMTP id g22mr926429qve.231.1569438545346; Wed, 25 Sep 2019 12:09:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569438545; cv=none; d=google.com; s=arc-20160816; b=n0uKR4lp2JZcxrOpXHztjcc6u2tMhutVNWLR0hfNW4VkVKukd6DyVEVNx3ogDNtPj8 m7MWnUbV0Y8yWty2H71SMxrdl0xdHX/g9G8zPjEoKiXS69ikfTOIifTkHCgcY4DClD3U IK4yERJSBkOx4Zw2ObloPdU1N3HB5AJaOx3kj12Vt7bXo5d+d8rf1JDVGqVhLsnqxnyx kkggVYO9gSlpbJmPaciwFDQy0sPFhrNYVzY+WHcXFLWFtJk7iWJQLkjE01Ls47uVX9c4 4/UW7ou7/0iTlYqGFEMkA6kgNemwVFkWp05zzDjDpEG3HJT+xAJX3VhLVXrtCAycS8Hm 25vA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Eck7z4xU6rWZDIf+jUdftaZDf15l360hvN4eD+K3cX0=; b=f7V4Vh9C8FWsPbJ4DDJ0bxm+tf/UgZ60Br2nIo/zjYVzqvkedHDtEZZ5FBfX1jMC8q +jexhcxDAn3PqEx8ULd8VBtJIleS3I0bjTs2BZVGilf4FDCzkYFK/yhXDL/5CEdZaBKy Ox78g2NqLfG2Snx+a0o1S7IejbHFOOMOLvRCc1EBDZqCS/yEsTSOmB5Wq1ZqFJq8s3Hk Gy2DQwVoijhV6LCZoRTrFV/2OXJ5afOo0IthVwNTy7s0yvygIcRZAe+K1hmg/Fe8bEzM fs4EO8G9qMOu2At2/iaaYYooiYbogh6tGDrU6wWJkgfmdifXQYvzaCBazzc/TvG0xn5o WKjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S0QUhfur; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b7si445162qvh.10.2019.09.25.12.09.05 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Sep 2019 12:09:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S0QUhfur; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCeu-0007Uv-IA for patch@linaro.org; Wed, 25 Sep 2019 15:09:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47322) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDCIu-00021d-WC for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDCIs-0004X3-4l for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:20 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:34827) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iDCIq-0004VA-3D for qemu-devel@nongnu.org; Wed, 25 Sep 2019 14:46:16 -0400 Received: by mail-pl1-x630.google.com with SMTP id y10so2936307plp.2 for ; Wed, 25 Sep 2019 11:46:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Eck7z4xU6rWZDIf+jUdftaZDf15l360hvN4eD+K3cX0=; b=S0QUhfurjE0ohyg7NT/RKXb3JlbA3RVowbnV81ytUzRzUMh+Jxu4ilASjWByY9HigY HPySyI2KtyBf9V8sCG0xP3OXjt5qWsNYO69pZ5pM9yUbbd5VSsaBxHHRDZUprFk7Kgfj cqA/GoYK0RAzynx5LlV38k74W4hJ8g5u5Q1M+dsKx8Bri2LtWhkPvb7jg/OaNr0+AHFz 0z1JBZHQ+TzRCJ9oxqxBXQ8kmkdU18lmv1612iqwnejBlMGV4ZmbuA8tMWweJEvVlrZl pBqHtojT2n5dAcSwfBJbFQn8BsSBo+sUk1jxyRv92pKSV2Hb0IwwXqulP+T9HPAHNzuq 9v7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Eck7z4xU6rWZDIf+jUdftaZDf15l360hvN4eD+K3cX0=; b=FY+gjpLmRL5yRMQY0yKicXU6HGMjIeF4U2KNOryOE+OahOR428Orv2t241oc/fiDOo t5kAAgnBVVzeA2ND/TMyFGO73sOtovkV4OMQkDlM+UfmkNoH+0hixMiAFNu0AYcikZaF VSdDjWCNeCVaIcAnfbVR7j9JMQjyc7GcYXstYW9Pj+zVDNlqrbtnBc18+NS860THr+JH ItRa84qA5e7thyU0YxzqdAxEyprov/XLkOZRnHdJVmpms+5Ny0ixor+XacInQLUJneJo c5RkOfX5Xn7gk7eXGzniTasqxzjh2UHueow7mI+VxNvmGbROV/QvVXRjPRPae/BMesCU p/cA== X-Gm-Message-State: APjAAAUjwKuq9MCs5znhXxI815gPrlPBroFYIfqhUMqDv13FxXsBh8Ww nQv5K7dXhYJizfbRDuy/mxUFY0OXRAs= X-Received: by 2002:a17:902:654a:: with SMTP id d10mr10653303pln.199.1569437173816; Wed, 25 Sep 2019 11:46:13 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.61]) by smtp.gmail.com with ESMTPSA id l24sm6133229pff.151.2019.09.25.11.46.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 11:46:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 16/16] cputlb: Pass retaddr to tb_check_watchpoint Date: Wed, 25 Sep 2019 11:45:48 -0700 Message-Id: <20190925184548.30673-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190925184548.30673-1-richard.henderson@linaro.org> References: <20190925184548.30673-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::630 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Fixes the previous TLB_WATCHPOINT patches because we are currently failing to set cpu->mem_io_pc with the call to cpu_check_watchpoint. Pass down the retaddr directly because it's readily available. Fixes: 50b107c5d61 Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- accel/tcg/translate-all.h | 2 +- accel/tcg/translate-all.c | 6 +++--- exec.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/accel/tcg/translate-all.h b/accel/tcg/translate-all.h index 135c1ea96a..a557b4e2bb 100644 --- a/accel/tcg/translate-all.h +++ b/accel/tcg/translate-all.h @@ -30,7 +30,7 @@ void tb_invalidate_phys_page_fast(struct page_collection *pages, tb_page_addr_t start, int len, uintptr_t retaddr); void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end); -void tb_check_watchpoint(CPUState *cpu); +void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); #ifdef CONFIG_USER_ONLY int page_unprotect(target_ulong address, uintptr_t pc); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index db77fb221b..66d4bc4341 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -2142,16 +2142,16 @@ static bool tb_invalidate_phys_page(tb_page_addr_t addr, uintptr_t pc) #endif /* user-mode: call with mmap_lock held */ -void tb_check_watchpoint(CPUState *cpu) +void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr) { TranslationBlock *tb; assert_memory_lock(); - tb = tcg_tb_lookup(cpu->mem_io_pc); + tb = tcg_tb_lookup(retaddr); if (tb) { /* We can use retranslation to find the PC. */ - cpu_restore_state_from_tb(cpu, tb, cpu->mem_io_pc, true); + cpu_restore_state_from_tb(cpu, tb, retaddr, true); tb_phys_invalidate(tb, -1); } else { /* The exception probably happened in a helper. The CPU state should diff --git a/exec.c b/exec.c index b3df826039..8a0a6613b1 100644 --- a/exec.c +++ b/exec.c @@ -2758,7 +2758,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, cpu->watchpoint_hit = wp; mmap_lock(); - tb_check_watchpoint(cpu); + tb_check_watchpoint(cpu, ra); if (wp->flags & BP_STOP_BEFORE_ACCESS) { cpu->exception_index = EXCP_DEBUG; mmap_unlock();