From patchwork Mon Sep 23 22:59:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174225 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp3396603ill; Mon, 23 Sep 2019 16:00:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqxKAzGDI7d9Ca89JyPFlasitgxU6hc2tFyY31KVI5OTRu8llq/1rfTulvt5XCgF9VmcI85K X-Received: by 2002:a37:82c1:: with SMTP id e184mr398193qkd.206.1569279657265; Mon, 23 Sep 2019 16:00:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569279657; cv=none; d=google.com; s=arc-20160816; b=h0O8XuqNnR54fb1f3bOovX9IZcA83qe77vH2iKqd6c5cTQTRwmB9/mhQBPfeueVpQ8 aNt6AZyiN7Q64TRvaGs8QT372/l1tgfVQOlCcJtYnSHgk8YPW+C/AFU139SHK98W/+6T pXZVNlxPYDmDDMZEw2M1bkJDUbC4o7zHGWRr9Omvd4WfalzOK2A/fIUMAn4motiGenTJ sPAiCRbsZnxyBg5sGlkrxsMEjx9mGYkGi4U12BSbfPhh8mvPeMSqLkdDYwQlYr6lJ3NS qyJ5QovYR0QnVpLy0kyu0zL+yW/1o/Uy2rfoxC9N0qDI6seOLVtfy1wCjNFmuKcuYjbT AtsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=q+p5QzYNQKTvFHxw7w5r06HbHDvLV91pgGFYaSNj9io=; b=vXpntecGJUdYXf2glnoFa2I6e1B97BGh+Nxa5zwPEFs8TYYbdKlSlJZVe8mbBVpOyG JBf/5NeF2H6VC2iZCdSaOknAWL/Khr68SMGEd8N5aLd5xLjV3svQLlKVlJowXzpFvR7y qQEkBCj/RKegvM+CmlUNaOf77TmT4QdE0UTsQoXwL2fluv8TFtbIvDkUU+eCDuYDViRB UNL4fA3SRvDmSO/k0TeyDRhTJUnCyqmMGC6cEx8pbcHIPMy91MR6cIjhGALfhXVtqcuL s76RylqUdXnkNDJOlsj8dgHI2xsQIDJ19LP4jYX67mAEPR7SzKG6pAtd4/D1zvmtN6Ta +2ig== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jiklDqjN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f50si9663405qte.342.2019.09.23.16.00.57 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Sep 2019 16:00:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jiklDqjN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36924 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXKB-0005QT-PX for patch@linaro.org; Mon, 23 Sep 2019 19:00:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35681) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXJT-0005Q7-UV for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCXJS-0007w1-NA for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:11 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:33713) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iCXJS-0007ur-HM for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:10 -0400 Received: by mail-pg1-x543.google.com with SMTP id i30so4421pgl.0 for ; Mon, 23 Sep 2019 16:00:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=q+p5QzYNQKTvFHxw7w5r06HbHDvLV91pgGFYaSNj9io=; b=jiklDqjNjvOwyGkMWVnwjr0pGn76PejnXREOb3AMWwgrRNKqBmAn7hv08hKIfiRDb5 Cv7Pt24gCTv5gcQ2yt3ao5qQkLTHhY5QXniNV4lHBp6uG3hMze+AW2A6YXHrcNxckN2n a8vScAzUUA/AMuDrfLBQ8ndris44KrlyMUYeTIWNDZUVQYv6cQd/UytSTc6oCciSFi5p t6obh3ET2aarXXiuPR8Fkl/O5NvwhNdoC1a5wWxPt63M9KdNc5AeblBYhdgFIl+gT8ua z8PQHBvb1U5SDE1voTqS7W1R08sbd5Gtbhmhq/dvToQTYLVbYbw4+ziYICCIDf3Q+Avx jTww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q+p5QzYNQKTvFHxw7w5r06HbHDvLV91pgGFYaSNj9io=; b=a3zAUtKieWuXoFQpLS/yjjNE2ioyEmMb4EdubbY+fQneaqV5uQAkOVPOB8Zs1EHt1Q xI4p9J8uHrlvUNNZgGWVAPz98PwZehc0mo7ijbL+92bpKWmz1b5tbOVIRncY+FoHHUco AZOInchoZfnXedZccedMa012/bbGaI536mbKWv9fIpSkjVPT3bJRE0fj9TdDeQg/uRyp LCJV9FdHhG0mYJYzZE7skuJjsB9f5N4qQudN/wGeV4IsFyYQkR3KsUOaWTckaw/gFeqF hg0T0JKbXq8N5bicJ9xZAAtB9BRI02DQhlZsBvtBydMGq6s19VeEwNwg1/GTKQ9qyg7E +t4g== X-Gm-Message-State: APjAAAU4158HjnynyR9d/OgEUgNAvGN/7by4yL4FXUfrV04TAmDzptTJ A3xxnXZhYZrKwur/qlKp2Adt2Zmq8e0= X-Received: by 2002:a63:e1a:: with SMTP id d26mr153193pgl.73.1569279609108; Mon, 23 Sep 2019 16:00:09 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.59]) by smtp.gmail.com with ESMTPSA id 74sm11674810pfy.78.2019.09.23.16.00.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Sep 2019 16:00:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/16] exec: Use TARGET_PAGE_BITS_MIN for TLB flags Date: Mon, 23 Sep 2019 15:59:49 -0700 Message-Id: <20190923230004.9231-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190923230004.9231-1-richard.henderson@linaro.org> References: <20190923230004.9231-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, alex.bennee@linaro.org, stefanha@redhat.com, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These bits do not need to vary with the actual page size used by the guest. Reviewed-by: David Hildenbrand Reviewed-by: Paolo Bonzini Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index d2d443c4f9..e0c8dc540c 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -317,20 +317,24 @@ CPUArchState *cpu_copy(CPUArchState *env); #if !defined(CONFIG_USER_ONLY) -/* Flags stored in the low bits of the TLB virtual address. These are - * defined so that fast path ram access is all zeros. +/* + * Flags stored in the low bits of the TLB virtual address. + * These are defined so that fast path ram access is all zeros. * The flags all must be between TARGET_PAGE_BITS and * maximum address alignment bit. + * + * Use TARGET_PAGE_BITS_MIN so that these bits are constant + * when TARGET_PAGE_BITS_VARY is in effect. */ /* Zero if TLB entry is valid. */ -#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS - 1)) +#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) /* Set if TLB entry references a clean RAM page. The iotlb entry will contain the page physical address. */ -#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS - 2)) +#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) /* Set if TLB entry is an IO callback. */ -#define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3)) +#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) /* Set if TLB entry contains a watchpoint. */ -#define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS - 4)) +#define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) /* Use this mask to check interception with an alignment mask * in a TCG backend. From patchwork Mon Sep 23 22:59:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174228 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp3401474ill; Mon, 23 Sep 2019 16:05:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqwJUseBU222pXjWhAY0rXOpF0VW+JhncSg66/IZx5CisZ6R55mSpf9LBHp2+tkc0TJ5gjj7 X-Received: by 2002:a50:ab84:: with SMTP id u4mr2640585edc.13.1569279922043; Mon, 23 Sep 2019 16:05:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569279922; cv=none; d=google.com; s=arc-20160816; b=mUvEzxcp3Cwp9E2o+rAHwJbi0FwuZM5k/oKt2E7kxyeR3+DmpJHw6FVzS4FYlsyBMA eAPHhopZTgbW9HI5Jdu0OV8WKnLfT/FBzeVszc4KrJM/2EzMbvVj9FNNyCKTsu42DUcp r/hYtCpvqSpQ7wwDiZKLWg5vIHa9WfHOdcplF9g5Ok+bR10OOJ2Bnpt2IkUmETwN9CIX ulblMYKzCJZPTfWzMWYeYoJR70TGZjzEtLmfjNH8Lk1nLUQRryVk0Z0OiffuOuAFhk2j FWlflW+dD8M2yAxkpUuOT5Y1c/prqvmkOgkoMGi90A6zIMCsSXsxGP7adH3rW4vLdXqU OLAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DLSBL7HpLmLBUzIEzjw9q9aafzQEGfd8fwlel43TucU=; b=MycbN2BIAj+SgnRltPfICfGO+9BAo7zysgjvpV2IAXtumVBDWUMF2f/hJ3KjVSvG9+ B3h3wSctp2wWPSUHED3TKEvrmoaWNDnlDioWVGAZSjZaXuOlxWs2hHRqBhVL013gm//p SxBExc27RG3wUwkNW1LI9A5vPtJDm02JGQTdqx5l3tYBy27x348YNHUj7h8rsyP+r3oq npZYswsmKgTMx5WKPT2U9U7ayXF+yHvHf04MWrLuqKL0jCCHPA2m6PB38WFv1I9N74mo abyvifmABzvjDsLFKNd1LJY2q+6VTrNyi0KKYimvMi92BrCT1ysAVg6ovSs88ToWEuO7 WYHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cjawjnek; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k16si5952481ejc.134.2019.09.23.16.05.21 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Sep 2019 16:05:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cjawjnek; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37074 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXOS-0000QT-CY for patch@linaro.org; Mon, 23 Sep 2019 19:05:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35709) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXJW-0005Qy-CG for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCXJV-00080O-55 for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:14 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:41685) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iCXJU-0007zh-VH for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:13 -0400 Received: by mail-pg1-x541.google.com with SMTP id s1so7779579pgv.8 for ; Mon, 23 Sep 2019 16:00:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DLSBL7HpLmLBUzIEzjw9q9aafzQEGfd8fwlel43TucU=; b=cjawjnekOI9pYfGesh2bquow7IgGYQHFqQGvA0o3qE+iyx8ON9ptVksJ3HXoaBcHwT d9ESK6K9bmxN8Tind2EJse+zTuDNNeJJ/pVGN4/5rm/yxOFYeLhMwU2RwtvHIE/V662y zNOGgC78fGhVMLc25ZqeXiLPcUgEtIHlRaH5ORq5vly/tT/+LlXLFr6nDCX+UImvuPPX iV0Nij+vKZjPlpDlV6qsiftInLcVZRF6Flsrv3bYUqSm9jA8jl5cWXnuX+fJicNuCQU+ ACDQoraNALA6vI7O9DO4s0DkPK1vMOBZB998a7biQNVhPOE8T3//6yJFuYRJjiIAE8uG p/5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DLSBL7HpLmLBUzIEzjw9q9aafzQEGfd8fwlel43TucU=; b=ltHzcvd1VsmcMpFp8MW39g14gmpc2j5p6TjFwSZ0llRGNNPTemH9a5Lt2X7togx+eL Y2lO8Ks1sS1Cd850vR57ye8H3WD0v8Y88j83mjEwwgAD/R5PobBLkv0gh76EaCDhTIxm uHhBeN3uTMonW90S3ZDiu4lLm6D/m6/ppRkRVanUBVJNYUr61Sq1AWJz3ThdNxTt8qQj qJicXlE6fA6mpTVzqJtkk2oGOgA4jjeUW5jXnyg8LigtAK5mskA31/0uwgwAtuRVZrYk xdzlOWsENgsFqayRa3qYa0peQzRiJ2unUYpeDrPVA0+DGKkXzyNKLyDYsDzYS7DzSDih dlmw== X-Gm-Message-State: APjAAAWCuNpMlFVjf1VkEg3VCkb1axXWRXKm3NYif3NKiaZDJfQCZ70Q fQ52DUSONH7gM9leqe6A/Y+CPn8GKeg= X-Received: by 2002:a63:c050:: with SMTP id z16mr2314463pgi.250.1569279611464; Mon, 23 Sep 2019 16:00:11 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.59]) by smtp.gmail.com with ESMTPSA id 74sm11674810pfy.78.2019.09.23.16.00.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Sep 2019 16:00:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 02/16] cputlb: Disable __always_inline__ without optimization Date: Mon, 23 Sep 2019 15:59:50 -0700 Message-Id: <20190923230004.9231-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190923230004.9231-1-richard.henderson@linaro.org> References: <20190923230004.9231-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, alex.bennee@linaro.org, stefanha@redhat.com, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This forced inlining can result in missing symbols, which makes a debugging build harder to follow. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: David Hildenbrand Reported-by: Peter Maydell Signed-off-by: Richard Henderson --- include/qemu/compiler.h | 11 +++++++++++ accel/tcg/cputlb.c | 4 ++-- 2 files changed, 13 insertions(+), 2 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h index 09fc44cca4..20780e722d 100644 --- a/include/qemu/compiler.h +++ b/include/qemu/compiler.h @@ -170,6 +170,17 @@ # define QEMU_NONSTRING #endif +/* + * Forced inlining may be desired to encourage constant propagation + * of function parameters. However, it can also make debugging harder, + * so disable it for a non-optimizing build. + */ +#if defined(__OPTIMIZE__) +#define QEMU_ALWAYS_INLINE __attribute__((always_inline)) +#else +#define QEMU_ALWAYS_INLINE +#endif + /* Implement C11 _Generic via GCC builtins. Example: * * QEMU_GENERIC(x, (float, sinf), (long double, sinl), sin) (x) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index abae79650c..2222b87764 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1281,7 +1281,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, typedef uint64_t FullLoadHelper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); -static inline uint64_t __attribute__((always_inline)) +static inline uint64_t QEMU_ALWAYS_INLINE load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr, MemOp op, bool code_read, FullLoadHelper *full_load) @@ -1530,7 +1530,7 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, * Store Helpers */ -static inline void __attribute__((always_inline)) +static inline void QEMU_ALWAYS_INLINE store_helper(CPUArchState *env, target_ulong addr, uint64_t val, TCGMemOpIdx oi, uintptr_t retaddr, MemOp op) { From patchwork Mon Sep 23 22:59:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174227 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp3398349ill; Mon, 23 Sep 2019 16:02:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqz6FEE8AeBcxU5uOHMUIb1d+ZPOySiFM0P/e3k8qxW//LQy8/aQR5syDAcYt5tVWinq7Ume X-Received: by 2002:a05:6214:1463:: with SMTP id c3mr27270qvy.48.1569279738923; Mon, 23 Sep 2019 16:02:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569279738; cv=none; d=google.com; s=arc-20160816; b=KPJAAWVBf9Dpmf0gJLf9lZycoor6ApVrw6A+j0oxqZqOnK2AKd1ZHFSrHxmG1y/zyI PYJXSLgHnWFpLacgY2pKJiLH1SsctOwOxY64W8UHNSTBtwKAxE7spHeJ2EgaqANAsij/ mGthQWPq78TW4+iGXSqgWgBUFywGMu1/ja9VGGV9OULIcEI0c5q6zGQxuvpZI9nCyZKI R4DMpq6KPfJzIcm2AkMLOcZ5fCmHrEhhkBk9scur6ZA814Uce9Or2MCRysQmpPuBt67v BP8EMitHQs8BH9G9KSpK3XBR30Fm+XdHn7JOdVYCzFis1sf52jrmtw++LfMDB/Zk5hYB f57Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=5Kl11ZmsMIccTxhXV5md4kUi848D5Wwz0Vh+1GCVY20=; b=ZJzI5s2e1+xD8hGuRf0F7cKkNGhYFQT1R4JjtQJUhAXdjCHp0YrYc8yE4fmy6huE6D N2SoTGrrGZLLlqoDOueKTfn7pb4jEqyzM7u6qPbgfaP+kf7VorDl0rtRn3iXSRmsEIjv iVY0hfHxO4MsfMbsBjp96YMf5M+2y+NV7Y6g5Xq2REfHInLoUeZ1UD2uHRP2koxJzoXa AMjPU45dRSdGmtdSFgIox+R+dllWHA+BnR4g49l/sXI9FDcAaIB6ePU/M28XYh3hw5gH lIFzGZrm1zjZGyaHL1Zsv/eMl+NR1UvdWRmZ9XQPXXMrOB+cxM3WXpkoyrh70TWLh+oC 2irw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NY+RhAnU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a186si9345028qke.250.2019.09.23.16.02.18 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Sep 2019 16:02:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NY+RhAnU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36960 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXLV-0005Yi-N0 for patch@linaro.org; Mon, 23 Sep 2019 19:02:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35724) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXJX-0005Rx-BL for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCXJW-000815-8H for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:15 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:33714) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iCXJW-00080h-2I for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:14 -0400 Received: by mail-pg1-x544.google.com with SMTP id i30so4573pgl.0 for ; Mon, 23 Sep 2019 16:00:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5Kl11ZmsMIccTxhXV5md4kUi848D5Wwz0Vh+1GCVY20=; b=NY+RhAnUVegbSZ++M38hCn07AAmF9N20PcXLqREfICQIWIkg0+4VRaKv9aYF37Hb3r 2WObegdpu5p1sNo4kso5lrgGD9LNwh4wZ8plzDixSyfOVtrzDyOM+PgWW8XscZ5VJP/B OM0ZbEQUS5YB0PXUvb7mK+Wes4ZjINW2dx0FSyYUYXdetHk1tx3UiizySGXXaNuSCFrl IhU8wR2/t/SnZCo2f3fE0H9hJG8NZ7Q5CfNsK2wRVzFpU6qNyr4oFXaHmS9I5S2s5zlH vFY4M25VX22Ruyk1yBmumklzcRqK8ttJ5wzNp96HNsUejCgW87dwq7p0iQeKDok2WSck 2kjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5Kl11ZmsMIccTxhXV5md4kUi848D5Wwz0Vh+1GCVY20=; b=lXHxtJ0IVX0mnz0K0M/KV+WwOUXGSDxRKRtcVYATGQUD1DO4IAICYGgLNjZegxwh/+ aZ8oXUhJ/8Lul1Ntk3kju6P3jLdmeOGEEbRtgXaB3lUKGZxmQRn7wKJ6YefxlH8MK/Wn RKLIs1x0GvETMaO4NU7Z+WbMcLjbR32yUaKmcyABgspOPtgJK+u4eXav/qbbmULxA83t y44e1FExqO337gPElbgWeSNkmbkiHOWVld+SLv6j+N7tZH+NC72reo9uaD6etXRRC7H7 v4/MYwBShh9kLvNNJBOpjoTUqdeBp8de8so7EU+K04JEJC9j7RHxt3E+x9PWbIGyM8uN ZwPw== X-Gm-Message-State: APjAAAVbQGsAPua8e7s4Ydt8L+rOF5EO8R8htAu3RUKq8BNBp9HkAtSy 1D3luY2WPgq0ws0sm+v+K+SyXmew5zs= X-Received: by 2002:a63:505:: with SMTP id 5mr2189265pgf.297.1569279612724; Mon, 23 Sep 2019 16:00:12 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.59]) by smtp.gmail.com with ESMTPSA id 74sm11674810pfy.78.2019.09.23.16.00.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Sep 2019 16:00:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 03/16] qemu/compiler.h: Add optimize_away Date: Mon, 23 Sep 2019 15:59:51 -0700 Message-Id: <20190923230004.9231-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190923230004.9231-1-richard.henderson@linaro.org> References: <20190923230004.9231-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, alex.bennee@linaro.org, stefanha@redhat.com, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use this as a compile-time assert that a particular code path is not reachable. Signed-off-by: Richard Henderson --- include/qemu/compiler.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h index 20780e722d..6604ccea92 100644 --- a/include/qemu/compiler.h +++ b/include/qemu/compiler.h @@ -221,4 +221,19 @@ #define QEMU_GENERIC9(x, a0, ...) QEMU_GENERIC_IF(x, a0, QEMU_GENERIC8(x, __VA_ARGS__)) #define QEMU_GENERIC10(x, a0, ...) QEMU_GENERIC_IF(x, a0, QEMU_GENERIC9(x, __VA_ARGS__)) +/** + * optimize_away() + * + * The compiler, during optimization, is expected to prove that a call + * to this function cannot be reached and remove it. If the compiler + * supports QEMU_ERROR, this will be reported at compile time; otherwise + * this will be reported at link time, due to the missing symbol. + */ +#ifdef __OPTIMIZE__ +extern void QEMU_NORETURN QEMU_ERROR("code path is reachable") + optimize_away(void); +#else +#define optimize_away() g_assert_not_reached() +#endif + #endif /* COMPILER_H */ From patchwork Mon Sep 23 22:59:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174229 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp3401582ill; Mon, 23 Sep 2019 16:05:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqxR9atvukkIDkB7FI2l9yMiniCt00eehYmzFVaf4xrfYLT/6CtyPml4uBF8s8OeCZ9HETAw X-Received: by 2002:aa7:cd5a:: with SMTP id v26mr2625917edw.256.1569279928894; Mon, 23 Sep 2019 16:05:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569279928; cv=none; d=google.com; s=arc-20160816; b=QY4jS/K1fgm8kzRhtEhADOce5BZcanTocNFqEH5XG9lElpwdEub+J/ex1pSBh1mwOi pUUXNj5bwpL8wz18IKnPaYUbsyCAUu/B4IySMt4QxWLLL3E1RLVY/YoRg50IzRxr3Fn7 awO819ykqmND3nc4YB6wjEmEamkPj14klyivo93oolqFBVtAlcZegC2Sw/VlvA3fSKJs 2/2gV1Wc68P/gth/GsoDnCStX7qKmQWLiTil43jPi1A+NrBUUCwA0duJK/Q72IA015iN NetqutPTV9FChn7T0tDAvqA6O6JFp2LSXEM1ov1VB/P0GLETr5qpd5/lPchn0/d8fuWN +TiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=QCKS3yxfLQ4jE5yT+JsFmTOrmseheZBe+jPLNTKKzwI=; b=M3GRw4AK7UfwUwv8u2T5rdAuNEaz5Rn9zB8cLcw2+S0NMbQ6WgZrTyheRtDKU6gIZH Cbe7feKE28LfLrwcpzGZWm8TSzZi7SV6e4yh9YKrBSbGkPoIZT7KAqH0Ruzpri+lvECj Qt9IImHXWLa6W8hUeIhGuBJIUd/JWTH38KtJaejFV/ur1hZzN/C6GINUWcmQFmW5/wfl Jt8EuQTdWgsdQ+ghSLG6NC+63cJ4ArAcJL3DsCqqJqJ1x+TwvwIMgEZBqFPHzhF2JFIf +nKvw7/WHHXgLtFBNfgEN2kfX87iqTxDqEZbyMY099iMdC/vp2AyctNrJY7aRbp9J+WR q6Uw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=tQZ9bhlZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id nj7si5783232ejb.262.2019.09.23.16.05.28 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Sep 2019 16:05:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=tQZ9bhlZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37084 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXOZ-0000VM-EJ for patch@linaro.org; Mon, 23 Sep 2019 19:05:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35769) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXJb-0005Y1-2S for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCXJY-00082F-3a for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:18 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:39790) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iCXJX-00081W-Qm for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:15 -0400 Received: by mail-pl1-x644.google.com with SMTP id s17so5724938plp.6 for ; Mon, 23 Sep 2019 16:00:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QCKS3yxfLQ4jE5yT+JsFmTOrmseheZBe+jPLNTKKzwI=; b=tQZ9bhlZ78sLR0JmELQxY75Ky/qNTx8OOgpz52R5Uw8qOCjxeKwQWqX2aKHXYGKMsd 2oWixByLYfif6P7v505svSGt1w2akl0C+1u8K/iWFQ9yN9Odb2MsI8ZIEfgd1LUwV18b hKwGPwukX+/AZtWCThzPvy8RNy19/h9KStpRoTFqJa/EYsdvfa0II9TFjeqDRirgBmrD ALuRtmrMV6/sdCIbZKK2vjIebEUpJeDE7StIABJjmyN7aWjhhV9AV9oN3t5AHY73Muaf iTBjiNPh6FFxmbSiRVTk7LHo3dvztMOdKPW4AjWI5/l8lBP/RGVI8TBeK2wh7S3lZY7P QHOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QCKS3yxfLQ4jE5yT+JsFmTOrmseheZBe+jPLNTKKzwI=; b=tRkSY02VQCJlLIaNOxDfwIAf7B8+I2IlDdHyGN/n3dyDghZtAaV2QfU7aNMEkcRadQ afPUHlFMRdmKIBPaHeoHblqrN9x/UZTpCkIwe9Eip+64DntIDD+0gYSTGb2IQsUJamb+ zwuJwUroUFRWm2vuTizRq6glplb1iU7QUzT81piZXS1U48HOTzMCcJfq2N1si42ctzwS Gz80RdZEB98gHtoTB7iccOOdXBarR+hfRIyHHxzhlc8qgwuF0HVVACfXpclYHvMtZ57r qFM74Rd2oNq7VWjyPBFbGoC8HLbQ9L+SUQj6AsEWAXo40AhqIpFyA/4tovhBhIv7TmRU gu/w== X-Gm-Message-State: APjAAAXzM0FuwK+EbrSs34ctXi+eAX5Bhta9P/Gb+waZLhu5oTsKZ9LS aR/3Ue2c5+uSWaOx6CQPA5AYfNaTzro= X-Received: by 2002:a17:902:fe12:: with SMTP id g18mr2107665plj.97.1569279614328; Mon, 23 Sep 2019 16:00:14 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.59]) by smtp.gmail.com with ESMTPSA id 74sm11674810pfy.78.2019.09.23.16.00.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Sep 2019 16:00:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 04/16] cputlb: Use optimize_away in load/store_helpers Date: Mon, 23 Sep 2019 15:59:52 -0700 Message-Id: <20190923230004.9231-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190923230004.9231-1-richard.henderson@linaro.org> References: <20190923230004.9231-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, alex.bennee@linaro.org, stefanha@redhat.com, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Increase the current runtime assert to a compile-time assert. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) -- 2.17.1 Reviewed-by: David Hildenbrand Reviewed-by: Alex Bennée diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 2222b87764..e529af6d09 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1396,7 +1396,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, res = ldq_le_p(haddr); break; default: - g_assert_not_reached(); + optimize_away(); } return res; @@ -1680,8 +1680,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, stq_le_p(haddr, val); break; default: - g_assert_not_reached(); - break; + optimize_away(); } } From patchwork Mon Sep 23 22:59:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174236 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp3409959ill; Mon, 23 Sep 2019 16:14:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqwcZS6Qs/8o7fWA3/Q8vtxjfBZHOy6mwVZvDlRh/9GLa3BaLhBvNXlMepGGjYcCqsjlw9fl X-Received: by 2002:a50:f703:: with SMTP id g3mr2668385edn.43.1569280467042; Mon, 23 Sep 2019 16:14:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569280467; cv=none; d=google.com; s=arc-20160816; b=MtVTzpQCoPq7CCfRQgiYspalBqVRIpwqUhN78ch5/q+TBJ7qbMacml6ZIf1Ur2uBwk rHnCExU4CitU3TISoAFoSHsL++amRziUXKBpOHVlDcxhHsP6OkuFpdfmMqHD9kXsQa/m 6umPEswfxcBPfoEd7XE8hJIa7pvDTGA+0hN1mH1QPqg5I/1y6EQNU1zmFwEtHyA6GPEb S0bMFTLf6kziFYweznZYUiaWXWMgLsiNknDDpueVJbAiX387KDOcD888V9rsifDQ/Z11 FTn+aOeLNQPZ6Hb1WAZjPhKsScwxEnFfJKGfOlyXcAIdC3SqPaf96LuqKiFYYfBes15q /a0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=dvpk1u15QL1a//tCscA4fTR0Q7V0VdpD0cml5SNVwXw=; b=aNll5rkDMF4pIde5VCI/tdhzrTAkaRrGwRiEK0xr+hgKqgL+DWWHJMedQ2tQKXj79m MoWuxzbz6P/njYLPOb82KxgDPM+/Mas87RlDGzDPK1vSlsYxX0WrTZq3Yp4F0ZrBnlTt prt2eiLHoNxktQa5pvFCaLyR9zIQvU4kA1NyMfa8dvmexteGdOuWX2TpVe8ZHF/n/HeO yvD4AKh6IzPQIuFmGLnFEpiVCWDWz49Sa8rdSUvHQ56gOrYlM4dA4Pp74Bac0zPxasJ7 swo+vwiyGeaLZowoyNqJrbvbY/qa75YnM7OveSqYeMjwQQLRTXWhe8w23w8RGo+ugabl w0kA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jPY2q1BU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, alex.bennee@linaro.org, stefanha@redhat.com, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will shortly be using these more than once. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 110 +++++++++++++++++++++++---------------------- 1 file changed, 57 insertions(+), 53 deletions(-) -- 2.17.1 Reviewed-by: David Hildenbrand Reviewed-by: Alex Bennée diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e529af6d09..430ba4a69d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1281,6 +1281,29 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, typedef uint64_t FullLoadHelper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr); +static inline uint64_t QEMU_ALWAYS_INLINE +load_memop(const void *haddr, MemOp op) +{ + switch (op) { + case MO_UB: + return ldub_p(haddr); + case MO_BEUW: + return lduw_be_p(haddr); + case MO_LEUW: + return lduw_le_p(haddr); + case MO_BEUL: + return (uint32_t)ldl_be_p(haddr); + case MO_LEUL: + return (uint32_t)ldl_le_p(haddr); + case MO_BEQ: + return ldq_be_p(haddr); + case MO_LEQ: + return ldq_le_p(haddr); + default: + optimize_away(); + } +} + static inline uint64_t QEMU_ALWAYS_INLINE load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr, MemOp op, bool code_read, @@ -1373,33 +1396,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, do_aligned_access: haddr = (void *)((uintptr_t)addr + entry->addend); - switch (op) { - case MO_UB: - res = ldub_p(haddr); - break; - case MO_BEUW: - res = lduw_be_p(haddr); - break; - case MO_LEUW: - res = lduw_le_p(haddr); - break; - case MO_BEUL: - res = (uint32_t)ldl_be_p(haddr); - break; - case MO_LEUL: - res = (uint32_t)ldl_le_p(haddr); - break; - case MO_BEQ: - res = ldq_be_p(haddr); - break; - case MO_LEQ: - res = ldq_le_p(haddr); - break; - default: - optimize_away(); - } - - return res; + return load_memop(haddr, op); } /* @@ -1415,7 +1412,8 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, MO_UB, false, full_ldub_mmu); + return load_helper(env, addr, oi, retaddr, MO_UB, false, + full_ldub_mmu); } tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, @@ -1530,6 +1528,36 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, * Store Helpers */ +static inline void QEMU_ALWAYS_INLINE +store_memop(void *haddr, uint64_t val, MemOp op) +{ + switch (op) { + case MO_UB: + stb_p(haddr, val); + break; + case MO_BEUW: + stw_be_p(haddr, val); + break; + case MO_LEUW: + stw_le_p(haddr, val); + break; + case MO_BEUL: + stl_be_p(haddr, val); + break; + case MO_LEUL: + stl_le_p(haddr, val); + break; + case MO_BEQ: + stq_be_p(haddr, val); + break; + case MO_LEQ: + stq_le_p(haddr, val); + break; + default: + optimize_away(); + } +} + static inline void QEMU_ALWAYS_INLINE store_helper(CPUArchState *env, target_ulong addr, uint64_t val, TCGMemOpIdx oi, uintptr_t retaddr, MemOp op) @@ -1657,31 +1685,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, do_aligned_access: haddr = (void *)((uintptr_t)addr + entry->addend); - switch (op) { - case MO_UB: - stb_p(haddr, val); - break; - case MO_BEUW: - stw_be_p(haddr, val); - break; - case MO_LEUW: - stw_le_p(haddr, val); - break; - case MO_BEUL: - stl_be_p(haddr, val); - break; - case MO_LEUL: - stl_le_p(haddr, val); - break; - case MO_BEQ: - stq_be_p(haddr, val); - break; - case MO_LEQ: - stq_le_p(haddr, val); - break; - default: - optimize_away(); - } + store_memop(haddr, val, op); } void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, From patchwork Mon Sep 23 22:59:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174231 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp3404423ill; Mon, 23 Sep 2019 16:08:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqw/ot+//eHRds9FfKgV//+MlwUOjpmJe94ou32+DXpmhDYFDb6ZMmA+mU9Wcu6MPXQfnUVW X-Received: by 2002:a50:8a9d:: with SMTP id j29mr2668187edj.283.1569280101632; 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X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, alex.bennee@linaro.org, stefanha@redhat.com, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Handle bswap on ram directly in load/store_helper. This fixes a bug with the previous implementation in that one cannot use the I/O path for RAM. Fixes: a26fc6f5152b47f1 Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 4 ++- accel/tcg/cputlb.c | 62 ++++++++++++++++++++++-------------------- 2 files changed, 36 insertions(+), 30 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index e0c8dc540c..d148bded35 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -335,12 +335,14 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) /* Set if TLB entry contains a watchpoint. */ #define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) +/* Set if TLB entry requires byte swap. */ +#define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5)) /* Use this mask to check interception with an alignment mask * in a TCG backend. */ #define TLB_FLAGS_MASK \ - (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO | TLB_WATCHPOINT) + (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO | TLB_WATCHPOINT | TLB_BSWAP) /** * tlb_hit_page: return true if page aligned @addr is a hit against the diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 430ba4a69d..f634edb4f4 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -737,8 +737,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, address |= TLB_INVALID_MASK; } if (attrs.byte_swap) { - /* Force the access through the I/O slow path. */ - address |= TLB_MMIO; + address |= TLB_BSWAP; } if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) { @@ -901,10 +900,6 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, bool locked = false; MemTxResult r; - if (iotlbentry->attrs.byte_swap) { - op ^= MO_BSWAP; - } - section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; @@ -947,10 +942,6 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, bool locked = false; MemTxResult r; - if (iotlbentry->attrs.byte_swap) { - op ^= MO_BSWAP; - } - section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; @@ -1133,8 +1124,8 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, wp_access, retaddr); } - if (tlb_addr & (TLB_NOTDIRTY | TLB_MMIO)) { - /* I/O access */ + /* Reject I/O access, or other required slow-path. */ + if (tlb_addr & (TLB_NOTDIRTY | TLB_MMIO | TLB_BSWAP)) { return NULL; } @@ -1344,6 +1335,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, /* Handle anything that isn't just a straight memory access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { CPUIOTLBEntry *iotlbentry; + bool need_swap; /* For anything that is unaligned, recurse through full_load. */ if ((addr & (size - 1)) != 0) { @@ -1357,17 +1349,22 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, /* On watchpoint hit, this will longjmp out. */ cpu_check_watchpoint(env_cpu(env), addr, size, iotlbentry->attrs, BP_MEM_READ, retaddr); - - /* The backing page may or may not require I/O. */ - tlb_addr &= ~TLB_WATCHPOINT; - if ((tlb_addr & ~TARGET_PAGE_MASK) == 0) { - goto do_aligned_access; - } } + need_swap = size > 1 && (tlb_addr & TLB_BSWAP); + /* Handle I/O access. */ - return io_readx(env, iotlbentry, mmu_idx, addr, - retaddr, access_type, op); + if (likely(tlb_addr & TLB_MMIO)) { + return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, + access_type, op ^ (need_swap * MO_BSWAP)); + } + + haddr = (void *)((uintptr_t)addr + entry->addend); + + if (unlikely(need_swap)) { + return load_memop(haddr, op ^ MO_BSWAP); + } + return load_memop(haddr, op); } /* Handle slow unaligned access (it spans two pages or IO). */ @@ -1394,7 +1391,6 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, return res & MAKE_64BIT_MASK(0, size * 8); } - do_aligned_access: haddr = (void *)((uintptr_t)addr + entry->addend); return load_memop(haddr, op); } @@ -1592,6 +1588,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, /* Handle anything that isn't just a straight memory access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { CPUIOTLBEntry *iotlbentry; + bool need_swap; /* For anything that is unaligned, recurse through byte stores. */ if ((addr & (size - 1)) != 0) { @@ -1605,16 +1602,24 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, /* On watchpoint hit, this will longjmp out. */ cpu_check_watchpoint(env_cpu(env), addr, size, iotlbentry->attrs, BP_MEM_WRITE, retaddr); - - /* The backing page may or may not require I/O. */ - tlb_addr &= ~TLB_WATCHPOINT; - if ((tlb_addr & ~TARGET_PAGE_MASK) == 0) { - goto do_aligned_access; - } } + need_swap = size > 1 && (tlb_addr & TLB_BSWAP); + /* Handle I/O access. */ - io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, op); + if (likely(tlb_addr & (TLB_MMIO | TLB_NOTDIRTY))) { + io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, + op ^ (need_swap * MO_BSWAP)); + return; + } + + haddr = (void *)((uintptr_t)addr + entry->addend); + + if (unlikely(need_swap)) { + store_memop(haddr, val, op ^ MO_BSWAP); + } else { + store_memop(haddr, val, op); + } return; } @@ -1683,7 +1688,6 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, return; } - do_aligned_access: haddr = (void *)((uintptr_t)addr + entry->addend); store_memop(haddr, val, op); } From patchwork Mon Sep 23 22:59:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174234 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp3407864ill; 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[209.51.188.17]) by mx.google.com with ESMTPS id p39si7298036eda.416.2019.09.23.16.11.56 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Sep 2019 16:11:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="eQS98y/x"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37158 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXUp-0006GT-Qu for patch@linaro.org; Mon, 23 Sep 2019 19:11:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35800) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXJe-0005aP-Rg for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCXJc-00084a-WF for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:22 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:46080) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iCXJc-00083S-NV for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:20 -0400 Received: by mail-pg1-x542.google.com with SMTP id a3so8866196pgm.13 for ; Mon, 23 Sep 2019 16:00:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z4fsQyjcOSp3U9YW2COSXHromnUnZCH6RDomXXmObRw=; b=eQS98y/xBy3Oc/KtVKeGFQ7UGXjjt/Ek8TMuDTKXa5zNYbpSjDCn6BHefK9x5U+lVd h4qGAm02aS+vATpeck6e3Sk3JwpYlpshtidTSdjDcPix/Vg+UrhoRIH8D79zF24UHSM/ jeOllPlk3FOjoqoac70erAXhpkcRKfk2dk0WSPpAnlTFoytf8raBHM/kgy0R94GScnIO yBR62STPIdQpHSR2xEJ0ARHs9Q09NIVAYZpVdgAQHdKy74gHSqNLm/XvfS1KECNOE448 LRYY04+vxqjpt1PCHI4nEv5DQKc+1rK4NHIMJCi3jpNTpfJ2i5/tYtSpckkRfibbKnz4 VL9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z4fsQyjcOSp3U9YW2COSXHromnUnZCH6RDomXXmObRw=; b=afkFQdpBb3aSsN5JWcRiKRAU35Cay5wdsPzmGWsFoakOBK0uDy4MZWhTaOqy2VAD1S hkJBD8MwF/7YaXit4q/+/sxc3FFjqsG/xYUPneGXINPRtKA9q+MU406R6P/ufFOO6nYt cGVF+ERtIpA8a8BzxI1O1puvIq2jcQ01ZMgz/60v4/Rz2ebqvmb3wsapeuBpE3RvouNU 4kDicdduKhQpoA7PDxOO6T4kOB6EEJlX+lyBznyOMcJEJpLUndaBsGgrEPUcXWO5ELku MewjrJU3jK5t5roDJZrWLLq3UcnlTZ38BQxqQNKB1AImp9wrVGXTN6G0HfO4O4Jk/TmW 7A1A== X-Gm-Message-State: APjAAAXxisJ4QegyCwih6aIoVVpnhAwPtHX4KhhyeIqs6HFewo9lmsso 3GsT874taQ2Wbe5WckW+KtBNXmj59TQ= X-Received: by 2002:a62:7684:: with SMTP id r126mr2170607pfc.26.1569279618689; Mon, 23 Sep 2019 16:00:18 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.59]) by smtp.gmail.com with ESMTPSA id 74sm11674810pfy.78.2019.09.23.16.00.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Sep 2019 16:00:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/16] exec: Adjust notdirty tracing Date: Mon, 23 Sep 2019 15:59:55 -0700 Message-Id: <20190923230004.9231-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190923230004.9231-1-richard.henderson@linaro.org> References: <20190923230004.9231-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, alex.bennee@linaro.org, stefanha@redhat.com, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The memory_region_tb_read tracepoint is unreachable, since notdirty is supposed to apply only to writes. The memory_region_tb_write tracepoint is mis-named, because notdirty is not only used for TB invalidation. It is also used for e.g. VGA RAM updates and migration. Replace memory_region_tb_write with memory_notdirty_write_access, and place it in memory_notdirty_write_prepare where it can catch all of the instances. Add memory_notdirty_set_dirty to log when we no longer intercept writes to a page. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- exec.c | 3 +++ memory.c | 4 ---- trace-events | 4 ++-- 3 files changed, 5 insertions(+), 6 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/exec.c b/exec.c index 8b998974f8..5f2587b621 100644 --- a/exec.c +++ b/exec.c @@ -2755,6 +2755,8 @@ void memory_notdirty_write_prepare(NotDirtyInfo *ndi, ndi->size = size; ndi->pages = NULL; + trace_memory_notdirty_write_access(mem_vaddr, ram_addr, size); + assert(tcg_enabled()); if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { ndi->pages = page_collection_lock(ram_addr, ram_addr + size); @@ -2779,6 +2781,7 @@ void memory_notdirty_write_complete(NotDirtyInfo *ndi) /* we remove the notdirty callback only if the code has been flushed */ if (!cpu_physical_memory_is_clean(ndi->ram_addr)) { + trace_memory_notdirty_set_dirty(ndi->mem_vaddr); tlb_set_dirty(ndi->cpu, ndi->mem_vaddr); } } diff --git a/memory.c b/memory.c index b9dd6b94ca..57c44c97db 100644 --- a/memory.c +++ b/memory.c @@ -438,7 +438,6 @@ static MemTxResult memory_region_read_accessor(MemoryRegion *mr, /* Accesses to code which has previously been translated into a TB show * up in the MMIO path, as accesses to the io_mem_notdirty * MemoryRegion. */ - trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size); } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size); @@ -465,7 +464,6 @@ static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr, /* Accesses to code which has previously been translated into a TB show * up in the MMIO path, as accesses to the io_mem_notdirty * MemoryRegion. */ - trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size); } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size); @@ -490,7 +488,6 @@ static MemTxResult memory_region_write_accessor(MemoryRegion *mr, /* Accesses to code which has previously been translated into a TB show * up in the MMIO path, as accesses to the io_mem_notdirty * MemoryRegion. */ - trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size); } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size); @@ -515,7 +512,6 @@ static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr, /* Accesses to code which has previously been translated into a TB show * up in the MMIO path, as accesses to the io_mem_notdirty * MemoryRegion. */ - trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size); } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size); diff --git a/trace-events b/trace-events index 823a4ae64e..20821ba545 100644 --- a/trace-events +++ b/trace-events @@ -52,14 +52,14 @@ dma_map_wait(void *dbs) "dbs=%p" find_ram_offset(uint64_t size, uint64_t offset) "size: 0x%" PRIx64 " @ 0x%" PRIx64 find_ram_offset_loop(uint64_t size, uint64_t candidate, uint64_t offset, uint64_t next, uint64_t mingap) "trying size: 0x%" PRIx64 " @ 0x%" PRIx64 ", offset: 0x%" PRIx64" next: 0x%" PRIx64 " mingap: 0x%" PRIx64 ram_block_discard_range(const char *rbname, void *hva, size_t length, bool need_madvise, bool need_fallocate, int ret) "%s@%p + 0x%zx: madvise: %d fallocate: %d ret: %d" +memory_notdirty_write_access(uint64_t vaddr, uint64_t ram_addr, unsigned size) "0x%" PRIx64 " ram_addr 0x%" PRIx64 " size %u" +memory_notdirty_set_dirty(uint64_t vaddr) "0x%" PRIx64 # memory.c memory_region_ops_read(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64" size %u" memory_region_ops_write(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64" size %u" memory_region_subpage_read(int cpu_index, void *mr, uint64_t offset, uint64_t value, unsigned size) "cpu %d mr %p offset 0x%"PRIx64" value 0x%"PRIx64" size %u" memory_region_subpage_write(int cpu_index, void *mr, uint64_t offset, uint64_t value, unsigned size) "cpu %d mr %p offset 0x%"PRIx64" value 0x%"PRIx64" size %u" -memory_region_tb_read(int cpu_index, uint64_t addr, uint64_t value, unsigned size) "cpu %d addr 0x%"PRIx64" value 0x%"PRIx64" size %u" -memory_region_tb_write(int cpu_index, uint64_t addr, uint64_t value, unsigned size) "cpu %d addr 0x%"PRIx64" value 0x%"PRIx64" size %u" memory_region_ram_device_read(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64" size %u" memory_region_ram_device_write(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64" size %u" flatview_new(void *view, void *root) "%p (root %p)" From patchwork Mon Sep 23 22:59:56 2019 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, alex.bennee@linaro.org, stefanha@redhat.com, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" It does not require going through the whole I/O path in order to discard a write. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 5 ++++- include/exec/cpu-common.h | 1 - accel/tcg/cputlb.c | 35 +++++++++++++++++++-------------- exec.c | 41 +-------------------------------------- 4 files changed, 25 insertions(+), 57 deletions(-) -- 2.17.1 diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index d148bded35..26547cd6dd 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -337,12 +337,15 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) /* Set if TLB entry requires byte swap. */ #define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5)) +/* Set if TLB entry writes ignored. */ +#define TLB_ROM (1 << (TARGET_PAGE_BITS_MIN - 6)) /* Use this mask to check interception with an alignment mask * in a TCG backend. */ #define TLB_FLAGS_MASK \ - (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO | TLB_WATCHPOINT | TLB_BSWAP) + (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ + | TLB_WATCHPOINT | TLB_BSWAP | TLB_ROM) /** * tlb_hit_page: return true if page aligned @addr is a hit against the diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index f7dbe75fbc..1c0e03ddc2 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -100,7 +100,6 @@ void qemu_flush_coalesced_mmio_buffer(void); void cpu_flush_icache_range(hwaddr start, hwaddr len); -extern struct MemoryRegion io_mem_rom; extern struct MemoryRegion io_mem_notdirty; typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f634edb4f4..af9a44a847 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -577,7 +577,7 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry, { uintptr_t addr = tlb_entry->addr_write; - if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_NOTDIRTY)) == 0) { + if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_ROM | TLB_NOTDIRTY)) == 0) { addr &= TARGET_PAGE_MASK; addr += tlb_entry->addend; if ((addr - start) < length) { @@ -745,7 +745,6 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, address |= TLB_MMIO; addend = 0; } else { - /* TLB_MMIO for rom/romd handled below */ addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat; } @@ -822,16 +821,17 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, tn.addr_write = -1; if (prot & PAGE_WRITE) { - if ((memory_region_is_ram(section->mr) && section->readonly) - || memory_region_is_romd(section->mr)) { - /* Write access calls the I/O callback. */ - tn.addr_write = address | TLB_MMIO; - } else if (memory_region_is_ram(section->mr) - && cpu_physical_memory_is_clean( - memory_region_get_ram_addr(section->mr) + xlat)) { - tn.addr_write = address | TLB_NOTDIRTY; - } else { - tn.addr_write = address; + tn.addr_write = address; + if (memory_region_is_romd(section->mr)) { + /* Use the MMIO path so that the device can switch states. */ + tn.addr_write |= TLB_MMIO; + } else if (memory_region_is_ram(section->mr)) { + if (section->readonly) { + tn.addr_write |= TLB_ROM; + } else if (cpu_physical_memory_is_clean( + memory_region_get_ram_addr(section->mr) + xlat)) { + tn.addr_write |= TLB_NOTDIRTY; + } } if (prot & PAGE_WRITE_INV) { tn.addr_write |= TLB_INVALID_MASK; @@ -904,7 +904,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc = retaddr; - if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu->can_do_io) { + if (mr != &io_mem_notdirty && !cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); } @@ -945,7 +945,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; - if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu->can_do_io) { + if (mr != &io_mem_notdirty && !cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); } cpu->mem_io_vaddr = addr; @@ -1125,7 +1125,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, } /* Reject I/O access, or other required slow-path. */ - if (tlb_addr & (TLB_NOTDIRTY | TLB_MMIO | TLB_BSWAP)) { + if (tlb_addr & (TLB_NOTDIRTY | TLB_MMIO | TLB_BSWAP | TLB_ROM)) { return NULL; } @@ -1613,6 +1613,11 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, return; } + /* Ignore writes to ROM. */ + if (unlikely(tlb_addr & TLB_ROM)) { + return; + } + haddr = (void *)((uintptr_t)addr + entry->addend); if (unlikely(need_swap)) { diff --git a/exec.c b/exec.c index 5f2587b621..ea8c0b18ac 100644 --- a/exec.c +++ b/exec.c @@ -88,7 +88,7 @@ static MemoryRegion *system_io; AddressSpace address_space_io; AddressSpace address_space_memory; -MemoryRegion io_mem_rom, io_mem_notdirty; +MemoryRegion io_mem_notdirty; static MemoryRegion io_mem_unassigned; #endif @@ -192,7 +192,6 @@ typedef struct subpage_t { #define PHYS_SECTION_UNASSIGNED 0 #define PHYS_SECTION_NOTDIRTY 1 -#define PHYS_SECTION_ROM 2 static void io_mem_init(void); static void memory_map_init(void); @@ -1475,8 +1474,6 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu, iotlb = memory_region_get_ram_addr(section->mr) + xlat; if (!section->readonly) { iotlb |= PHYS_SECTION_NOTDIRTY; - } else { - iotlb |= PHYS_SECTION_ROM; } } else { AddressSpaceDispatch *d; @@ -3002,38 +2999,6 @@ static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr) return phys_section_add(map, §ion); } -static void readonly_mem_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - /* Ignore any write to ROM. */ -} - -static bool readonly_mem_accepts(void *opaque, hwaddr addr, - unsigned size, bool is_write, - MemTxAttrs attrs) -{ - return is_write; -} - -/* This will only be used for writes, because reads are special cased - * to directly access the underlying host ram. - */ -static const MemoryRegionOps readonly_mem_ops = { - .write = readonly_mem_write, - .valid.accepts = readonly_mem_accepts, - .endianness = DEVICE_NATIVE_ENDIAN, - .valid = { - .min_access_size = 1, - .max_access_size = 8, - .unaligned = false, - }, - .impl = { - .min_access_size = 1, - .max_access_size = 8, - .unaligned = false, - }, -}; - MemoryRegionSection *iotlb_to_section(CPUState *cpu, hwaddr index, MemTxAttrs attrs) { @@ -3047,8 +3012,6 @@ MemoryRegionSection *iotlb_to_section(CPUState *cpu, static void io_mem_init(void) { - memory_region_init_io(&io_mem_rom, NULL, &readonly_mem_ops, - NULL, NULL, UINT64_MAX); memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX); @@ -3069,8 +3032,6 @@ AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv) assert(n == PHYS_SECTION_UNASSIGNED); n = dummy_section(&d->map, fv, &io_mem_notdirty); assert(n == PHYS_SECTION_NOTDIRTY); - n = dummy_section(&d->map, fv, &io_mem_rom); - assert(n == PHYS_SECTION_ROM); d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 }; From patchwork Mon Sep 23 22:59:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174233 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp3407813ill; Mon, 23 Sep 2019 16:11:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqwdVJXnkLovgp/TGcM1ueFuYvBF6u9++0HIRVgllJdmOMAl/OvJDO7ONrnFC3hkSa4sZKsV X-Received: by 2002:a17:906:c5b:: with SMTP id t27mr1915673ejf.180.1569280313111; Mon, 23 Sep 2019 16:11:53 -0700 (PDT) ARC-Seal: i=1; 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X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, alex.bennee@linaro.org, stefanha@redhat.com, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Pages that we want to track for NOTDIRTY are RAM. We do not really need to go through the I/O path to handle them. Acked-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/cpu-common.h | 2 -- accel/tcg/cputlb.c | 26 +++++++++++++++++--- exec.c | 50 --------------------------------------- memory.c | 16 ------------- 4 files changed, 23 insertions(+), 71 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 1c0e03ddc2..81753bbb34 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -100,8 +100,6 @@ void qemu_flush_coalesced_mmio_buffer(void); void cpu_flush_icache_range(hwaddr start, hwaddr len); -extern struct MemoryRegion io_mem_notdirty; - typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque); int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index af9a44a847..05212ff244 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -904,7 +904,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc = retaddr; - if (mr != &io_mem_notdirty && !cpu->can_do_io) { + if (!cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); } @@ -945,7 +945,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; - if (mr != &io_mem_notdirty && !cpu->can_do_io) { + if (!cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); } cpu->mem_io_vaddr = addr; @@ -1607,7 +1607,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, need_swap = size > 1 && (tlb_addr & TLB_BSWAP); /* Handle I/O access. */ - if (likely(tlb_addr & (TLB_MMIO | TLB_NOTDIRTY))) { + if (tlb_addr & TLB_MMIO) { io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, op ^ (need_swap * MO_BSWAP)); return; @@ -1620,6 +1620,26 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, haddr = (void *)((uintptr_t)addr + entry->addend); + /* Handle clean RAM pages. */ + if (tlb_addr & TLB_NOTDIRTY) { + NotDirtyInfo ndi; + + /* We require mem_io_pc in tb_invalidate_phys_page_range. */ + env_cpu(env)->mem_io_pc = retaddr; + + memory_notdirty_write_prepare(&ndi, env_cpu(env), addr, + addr + iotlbentry->addr, size); + + if (unlikely(need_swap)) { + store_memop(haddr, val, op ^ MO_BSWAP); + } else { + store_memop(haddr, val, op); + } + + memory_notdirty_write_complete(&ndi); + return; + } + if (unlikely(need_swap)) { store_memop(haddr, val, op ^ MO_BSWAP); } else { diff --git a/exec.c b/exec.c index ea8c0b18ac..dc7001f115 100644 --- a/exec.c +++ b/exec.c @@ -88,7 +88,6 @@ static MemoryRegion *system_io; AddressSpace address_space_io; AddressSpace address_space_memory; -MemoryRegion io_mem_notdirty; static MemoryRegion io_mem_unassigned; #endif @@ -191,7 +190,6 @@ typedef struct subpage_t { } subpage_t; #define PHYS_SECTION_UNASSIGNED 0 -#define PHYS_SECTION_NOTDIRTY 1 static void io_mem_init(void); static void memory_map_init(void); @@ -1472,9 +1470,6 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu, if (memory_region_is_ram(section->mr)) { /* Normal RAM. */ iotlb = memory_region_get_ram_addr(section->mr) + xlat; - if (!section->readonly) { - iotlb |= PHYS_SECTION_NOTDIRTY; - } } else { AddressSpaceDispatch *d; @@ -2783,42 +2778,6 @@ void memory_notdirty_write_complete(NotDirtyInfo *ndi) } } -/* Called within RCU critical section. */ -static void notdirty_mem_write(void *opaque, hwaddr ram_addr, - uint64_t val, unsigned size) -{ - NotDirtyInfo ndi; - - memory_notdirty_write_prepare(&ndi, current_cpu, current_cpu->mem_io_vaddr, - ram_addr, size); - - stn_p(qemu_map_ram_ptr(NULL, ram_addr), size, val); - memory_notdirty_write_complete(&ndi); -} - -static bool notdirty_mem_accepts(void *opaque, hwaddr addr, - unsigned size, bool is_write, - MemTxAttrs attrs) -{ - return is_write; -} - -static const MemoryRegionOps notdirty_mem_ops = { - .write = notdirty_mem_write, - .valid.accepts = notdirty_mem_accepts, - .endianness = DEVICE_NATIVE_ENDIAN, - .valid = { - .min_access_size = 1, - .max_access_size = 8, - .unaligned = false, - }, - .impl = { - .min_access_size = 1, - .max_access_size = 8, - .unaligned = false, - }, -}; - /* Generate a debug exception if a watchpoint has been hit. */ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, MemTxAttrs attrs, int flags, uintptr_t ra) @@ -3014,13 +2973,6 @@ static void io_mem_init(void) { memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX); - - /* io_mem_notdirty calls tb_invalidate_phys_page_fast, - * which can be called without the iothread mutex. - */ - memory_region_init_io(&io_mem_notdirty, NULL, ¬dirty_mem_ops, NULL, - NULL, UINT64_MAX); - memory_region_clear_global_locking(&io_mem_notdirty); } AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv) @@ -3030,8 +2982,6 @@ AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv) n = dummy_section(&d->map, fv, &io_mem_unassigned); assert(n == PHYS_SECTION_UNASSIGNED); - n = dummy_section(&d->map, fv, &io_mem_notdirty); - assert(n == PHYS_SECTION_NOTDIRTY); d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 }; diff --git a/memory.c b/memory.c index 57c44c97db..a99b8c0767 100644 --- a/memory.c +++ b/memory.c @@ -434,10 +434,6 @@ static MemTxResult memory_region_read_accessor(MemoryRegion *mr, tmp = mr->ops->read(mr->opaque, addr, size); if (mr->subpage) { trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size); - } else if (mr == &io_mem_notdirty) { - /* Accesses to code which has previously been translated into a TB show - * up in the MMIO path, as accesses to the io_mem_notdirty - * MemoryRegion. */ } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size); @@ -460,10 +456,6 @@ static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr, r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs); if (mr->subpage) { trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size); - } else if (mr == &io_mem_notdirty) { - /* Accesses to code which has previously been translated into a TB show - * up in the MMIO path, as accesses to the io_mem_notdirty - * MemoryRegion. */ } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size); @@ -484,10 +476,6 @@ static MemTxResult memory_region_write_accessor(MemoryRegion *mr, if (mr->subpage) { trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size); - } else if (mr == &io_mem_notdirty) { - /* Accesses to code which has previously been translated into a TB show - * up in the MMIO path, as accesses to the io_mem_notdirty - * MemoryRegion. */ } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size); @@ -508,10 +496,6 @@ static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr, if (mr->subpage) { trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size); - } else if (mr == &io_mem_notdirty) { - /* Accesses to code which has previously been translated into a TB show - * up in the MMIO path, as accesses to the io_mem_notdirty - * MemoryRegion. */ } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size); From patchwork Mon Sep 23 22:59:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174237 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp3410280ill; Mon, 23 Sep 2019 16:14:49 -0700 (PDT) X-Google-Smtp-Source: APXvYqxRJD4bB/7inid0SbjC9ucyBzVJrC2uBfqNcqd/el3+Y1MquPv8fG3BoW8wybk/qN7n1h3F X-Received: by 2002:a50:ac0a:: with SMTP id v10mr2672862edc.83.1569280489760; Mon, 23 Sep 2019 16:14:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569280489; cv=none; d=google.com; s=arc-20160816; b=Cx7ia4mDU1is/WwMGU5R6/CTLx49N3oHxzA0u0r0GbvQYH2Og4lmPHJTHmAybVfqxe 4tYmf1V5fOQtWIX3hzRhbqWX9WDVFerV60UvRHLxjq3WqEK4SY+83hY57R4Vqhjy8Dw1 rcfempSYZ3nUAK3sMJV57C7fVfYEfkXJdRa2uZXYT14hx08OQDXYPoFdAhmP9XF1OtU5 JoRj8ODhJMaZJRcl4a6uUCZzvRIDeeCt0eCggfsZATrLK9v37LiN34ScI1d327Gap1qk 4YhpOMrvuZa83ZsIJIAhtYLtmbN5sFWGtfcTJ+RCwRwuCB41UyDdH3ABznI0ubAxcMIR Iq3g== ARC-Message-Signature: i=1; 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X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, alex.bennee@linaro.org, stefanha@redhat.com, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is only one caller, tlb_set_page_with_attrs. We cannot inline the entire function because the AddressSpaceDispatch structure is private to exec.c, and cannot easily be moved to include/exec/memory-internal.h. Compute is_ram and is_romd once within tlb_set_page_with_attrs. Fold the number of tests against these predicates. Compute cpu_physical_memory_is_clean outside of the tlb lock region. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 6 +--- accel/tcg/cputlb.c | 68 ++++++++++++++++++++++++++--------------- exec.c | 22 ++----------- 3 files changed, 47 insertions(+), 49 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 81b02eb2fe..49db07ba0b 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -509,11 +509,7 @@ address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, hwaddr *xlat, hwaddr *plen, MemTxAttrs attrs, int *prot); hwaddr memory_region_section_get_iotlb(CPUState *cpu, - MemoryRegionSection *section, - target_ulong vaddr, - hwaddr paddr, hwaddr xlat, - int prot, - target_ulong *address); + MemoryRegionSection *section); #endif /* vl.c */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 05212ff244..05530a8b0c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -704,13 +704,14 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, MemoryRegionSection *section; unsigned int index; target_ulong address; - target_ulong code_address; + target_ulong write_address; uintptr_t addend; CPUTLBEntry *te, tn; hwaddr iotlb, xlat, sz, paddr_page; target_ulong vaddr_page; int asidx = cpu_asidx_from_attrs(cpu, attrs); int wp_flags; + bool is_ram, is_romd; assert_cpu_is_self(cpu); @@ -739,18 +740,46 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, if (attrs.byte_swap) { address |= TLB_BSWAP; } - if (!memory_region_is_ram(section->mr) && - !memory_region_is_romd(section->mr)) { - /* IO memory case */ - address |= TLB_MMIO; - addend = 0; - } else { + + is_ram = memory_region_is_ram(section->mr); + is_romd = memory_region_is_romd(section->mr); + + if (is_ram || is_romd) { + /* RAM and ROMD both have associated host memory. */ addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat; + } else { + /* I/O does not; force the host address to NULL. */ + addend = 0; + } + + write_address = address; + if (is_ram) { + iotlb = memory_region_get_ram_addr(section->mr) + xlat; + /* + * Computing is_clean is expensive; avoid all that unless + * the page is actually writable. + */ + if (prot & PAGE_WRITE) { + if (section->readonly) { + write_address |= TLB_ROM; + } else if (cpu_physical_memory_is_clean(iotlb)) { + write_address |= TLB_NOTDIRTY; + } + } + } else { + /* I/O or ROMD */ + iotlb = memory_region_section_get_iotlb(cpu, section) + xlat; + /* + * Writes to romd devices must go through MMIO to enable write. + * Reads to romd devices go through the ram_ptr found above, + * but of course reads to I/O must go through MMIO. + */ + write_address |= TLB_MMIO; + if (!is_romd) { + address = write_address; + } } - code_address = address; - iotlb = memory_region_section_get_iotlb(cpu, section, vaddr_page, - paddr_page, xlat, prot, &address); wp_flags = cpu_watchpoint_address_matches(cpu, vaddr_page, TARGET_PAGE_SIZE); @@ -790,8 +819,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, /* * At this point iotlb contains a physical section number in the lower * TARGET_PAGE_BITS, and either - * + the ram_addr_t of the page base of the target RAM (if NOTDIRTY or ROM) - * + the offset within section->mr of the page base (otherwise) + * + the ram_addr_t of the page base of the target RAM (RAM) + * + the offset within section->mr of the page base (I/O, ROMD) * We subtract the vaddr_page (which is page aligned and thus won't * disturb the low bits) to give an offset which can be added to the * (non-page-aligned) vaddr of the eventual memory access to get @@ -814,25 +843,14 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, } if (prot & PAGE_EXEC) { - tn.addr_code = code_address; + tn.addr_code = address; } else { tn.addr_code = -1; } tn.addr_write = -1; if (prot & PAGE_WRITE) { - tn.addr_write = address; - if (memory_region_is_romd(section->mr)) { - /* Use the MMIO path so that the device can switch states. */ - tn.addr_write |= TLB_MMIO; - } else if (memory_region_is_ram(section->mr)) { - if (section->readonly) { - tn.addr_write |= TLB_ROM; - } else if (cpu_physical_memory_is_clean( - memory_region_get_ram_addr(section->mr) + xlat)) { - tn.addr_write |= TLB_NOTDIRTY; - } - } + tn.addr_write = write_address; if (prot & PAGE_WRITE_INV) { tn.addr_write |= TLB_INVALID_MASK; } diff --git a/exec.c b/exec.c index dc7001f115..961d7d6497 100644 --- a/exec.c +++ b/exec.c @@ -1459,26 +1459,10 @@ bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap, /* Called from RCU critical section */ hwaddr memory_region_section_get_iotlb(CPUState *cpu, - MemoryRegionSection *section, - target_ulong vaddr, - hwaddr paddr, hwaddr xlat, - int prot, - target_ulong *address) + MemoryRegionSection *section) { - hwaddr iotlb; - - if (memory_region_is_ram(section->mr)) { - /* Normal RAM. */ - iotlb = memory_region_get_ram_addr(section->mr) + xlat; - } else { - AddressSpaceDispatch *d; - - d = flatview_to_dispatch(section->fv); - iotlb = section - d->map.sections; - iotlb += xlat; - } - - return iotlb; + AddressSpaceDispatch *d = flatview_to_dispatch(section->fv); + return section - d->map.sections; } #endif /* defined(CONFIG_USER_ONLY) */ From patchwork Mon Sep 23 22:59:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174239 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp3411948ill; Mon, 23 Sep 2019 16:16:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqyq01edZpVhlAqyyTRKmiPN++9DS4zHERjc6UeVBQCLQD+eYqjU7G5CiWFFpM4+KgKv0D3j X-Received: by 2002:a50:fa09:: with SMTP id b9mr2681455edq.165.1569280604665; Mon, 23 Sep 2019 16:16:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569280604; 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[209.51.188.17]) by mx.google.com with ESMTPS id ns21si5748824ejb.167.2019.09.23.16.16.44 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Sep 2019 16:16:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bsR5m4lj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37254 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXZT-000312-Ez for patch@linaro.org; Mon, 23 Sep 2019 19:16:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35922) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXJn-0005iq-0b for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCXJj-00088V-Nt for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:30 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:46080) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iCXJi-00086m-UC for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:27 -0400 Received: by mail-pg1-x541.google.com with SMTP id a3so8866384pgm.13 for ; Mon, 23 Sep 2019 16:00:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OntWFX85hgZhSLmNUdSTCPcWAPx7mPPaNsQ4yuD/3bw=; b=bsR5m4ljGfr99qwAJOK9mrC3tDOewgwbV5UB3xgGA0Eq3eb0P6HkmYVAD3H6UVkc64 Kx3DoGHEIRMUJrST+1xH1ieoqP87A9C2wNrtui7MsbHs5mW1P7A+FCAu2YsN5F11tNye FIKXh+U7aZYqliMy+sM5g9nUfjc9EycFTiiOliBMe2i88d/qXlSM17DyFWcMzVTuhU+X RxVqZp156du3UPopk1rIJ5D+kAlnSxD0wpEWfTEtb4V9gUjAvEms5YuRTaBZfFFS5yB3 p5fAoGqpfvhWl94TyFR/WliT32bO4IWHaQiTQJnurxtfZLax3hfivcNlP78aZcwG0lOF 2GLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OntWFX85hgZhSLmNUdSTCPcWAPx7mPPaNsQ4yuD/3bw=; b=q53I3cJ9nefI8tsy/6jm1J2aTKU+kthF5aio9fQnWVdCL6MW+IyR+akQk4zBJYs/X7 UVWGcwzRZhxyujsPNNs8CgUgPUfIFIsl+a4osvtwx0pAgGS0297Hwo6LNuLK4B+ywL9V cleYDI1x5VA3YY57TRLVBrgxyHuGhRB0gIK1/sd93EsHuOZUQRdNNwGsk+iZQmjj8zir NM5M3Zmy1kZ8Z0JmAa3Tg2+Mq06o9UWLLZcG11FZLNO1Kj8W+0ADWvBlAIW/Esu3Oq2y FcJEKjGQoiICzQzFcc/ozorbQ7XfeA2wCvOnQkDAUfdRdTg0yOHl+ar0EdBuUnIW0Nzb WopA== X-Gm-Message-State: APjAAAXhmIJMdGjhJFcVFH2gqAP6AhbhOWxjm/FYbK7QmydAzsezGn7+ dSEMHbkanIKmX6hNLlzwoqBHzCvQqfI= X-Received: by 2002:a17:90a:e64a:: with SMTP id ep10mr2015038pjb.59.1569279623843; Mon, 23 Sep 2019 16:00:23 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.59]) by smtp.gmail.com with ESMTPSA id 74sm11674810pfy.78.2019.09.23.16.00.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Sep 2019 16:00:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 11/16] cputlb: Merge and move memory_notdirty_write_{prepare, complete} Date: Mon, 23 Sep 2019 15:59:59 -0700 Message-Id: <20190923230004.9231-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190923230004.9231-1-richard.henderson@linaro.org> References: <20190923230004.9231-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, alex.bennee@linaro.org, stefanha@redhat.com, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since 9458a9a1df1a, all readers of the dirty bitmaps wait for the rcu lock, which means that they wait until the end of any executing TranslationBlock. As a consequence, there is no need for the actual access to happen in between the _prepare and _complete. Therefore, we can improve things by merging the two functions into notdirty_write and dropping the NotDirtyInfo structure. In addition, the only users of notdirty_write are in cputlb.c, so move the merged function there. Pass in the CPUIOTLBEntry from which the ram_addr_t may be computed. Signed-off-by: Richard Henderson --- include/exec/memory-internal.h | 65 ----------------------------- accel/tcg/cputlb.c | 76 +++++++++++++++++++--------------- exec.c | 44 -------------------- 3 files changed, 42 insertions(+), 143 deletions(-) -- 2.17.1 Reviewed-by: David Hildenbrand Reviewed-by: Alex Bennée diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h index ef4fb92371..9fcc2af25c 100644 --- a/include/exec/memory-internal.h +++ b/include/exec/memory-internal.h @@ -49,70 +49,5 @@ void address_space_dispatch_free(AddressSpaceDispatch *d); void mtree_print_dispatch(struct AddressSpaceDispatch *d, MemoryRegion *root); - -struct page_collection; - -/* Opaque struct for passing info from memory_notdirty_write_prepare() - * to memory_notdirty_write_complete(). Callers should treat all fields - * as private, with the exception of @active. - * - * @active is a field which is not touched by either the prepare or - * complete functions, but which the caller can use if it wishes to - * track whether it has called prepare for this struct and so needs - * to later call the complete function. - */ -typedef struct { - CPUState *cpu; - struct page_collection *pages; - ram_addr_t ram_addr; - vaddr mem_vaddr; - unsigned size; - bool active; -} NotDirtyInfo; - -/** - * memory_notdirty_write_prepare: call before writing to non-dirty memory - * @ndi: pointer to opaque NotDirtyInfo struct - * @cpu: CPU doing the write - * @mem_vaddr: virtual address of write - * @ram_addr: the ram address of the write - * @size: size of write in bytes - * - * Any code which writes to the host memory corresponding to - * guest RAM which has been marked as NOTDIRTY must wrap those - * writes in calls to memory_notdirty_write_prepare() and - * memory_notdirty_write_complete(): - * - * NotDirtyInfo ndi; - * memory_notdirty_write_prepare(&ndi, ....); - * ... perform write here ... - * memory_notdirty_write_complete(&ndi); - * - * These calls will ensure that we flush any TCG translated code for - * the memory being written, update the dirty bits and (if possible) - * remove the slowpath callback for writing to the memory. - * - * This must only be called if we are using TCG; it will assert otherwise. - * - * We may take locks in the prepare call, so callers must ensure that - * they don't exit (via longjump or otherwise) without calling complete. - * - * This call must only be made inside an RCU critical section. - * (Note that while we're executing a TCG TB we're always in an - * RCU critical section, which is likely to be the case for callers - * of these functions.) - */ -void memory_notdirty_write_prepare(NotDirtyInfo *ndi, - CPUState *cpu, - vaddr mem_vaddr, - ram_addr_t ram_addr, - unsigned size); -/** - * memory_notdirty_write_complete: finish write to non-dirty memory - * @ndi: pointer to the opaque NotDirtyInfo struct which was initialized - * by memory_not_dirty_write_prepare(). - */ -void memory_notdirty_write_complete(NotDirtyInfo *ndi); - #endif #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 05530a8b0c..09b0df87c6 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -33,6 +33,7 @@ #include "exec/helper-proto.h" #include "qemu/atomic.h" #include "qemu/atomic128.h" +#include "translate-all.h" /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ @@ -1084,6 +1085,37 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) return qemu_ram_addr_from_host_nofail(p); } +static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size, + CPUIOTLBEntry *iotlbentry, uintptr_t retaddr) +{ + ram_addr_t ram_addr = mem_vaddr + iotlbentry->addr; + + trace_memory_notdirty_write_access(mem_vaddr, ram_addr, size); + + if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { + struct page_collection *pages + = page_collection_lock(ram_addr, ram_addr + size); + + /* We require mem_io_pc in tb_invalidate_phys_page_range. */ + cpu->mem_io_pc = retaddr; + + tb_invalidate_phys_page_fast(pages, ram_addr, size); + page_collection_unlock(pages); + } + + /* + * Set both VGA and migration bits for simplicity and to remove + * the notdirty callback faster. + */ + cpu_physical_memory_set_dirty_range(ram_addr, size, DIRTY_CLIENTS_NOCODE); + + /* We remove the notdirty callback only if the code has been flushed. */ + if (!cpu_physical_memory_is_clean(ram_addr)) { + trace_memory_notdirty_set_dirty(mem_vaddr); + tlb_set_dirty(cpu, mem_vaddr); + } +} + /* * Probe for whether the specified guest access is permitted. If it is not * permitted then an exception will be taken in the same way as if this @@ -1203,8 +1235,7 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, /* Probe for a read-modify-write atomic operation. Do not allow unaligned * operations, or io operations to proceed. Return the host address. */ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr, - NotDirtyInfo *ndi) + TCGMemOpIdx oi, uintptr_t retaddr) { size_t mmu_idx = get_mmuidx(oi); uintptr_t index = tlb_index(env, mmu_idx, addr); @@ -1264,12 +1295,9 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, hostaddr = (void *)((uintptr_t)addr + tlbe->addend); - ndi->active = false; if (unlikely(tlb_addr & TLB_NOTDIRTY)) { - ndi->active = true; - memory_notdirty_write_prepare(ndi, env_cpu(env), addr, - qemu_ram_addr_from_host_nofail(hostaddr), - 1 << s_bits); + notdirty_write(env_cpu(env), addr, 1 << s_bits, + &env_tlb(env)->d[mmu_idx].iotlb[index], retaddr); } return hostaddr; @@ -1636,28 +1664,13 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, return; } - haddr = (void *)((uintptr_t)addr + entry->addend); - /* Handle clean RAM pages. */ if (tlb_addr & TLB_NOTDIRTY) { - NotDirtyInfo ndi; - - /* We require mem_io_pc in tb_invalidate_phys_page_range. */ - env_cpu(env)->mem_io_pc = retaddr; - - memory_notdirty_write_prepare(&ndi, env_cpu(env), addr, - addr + iotlbentry->addr, size); - - if (unlikely(need_swap)) { - store_memop(haddr, val, op ^ MO_BSWAP); - } else { - store_memop(haddr, val, op); - } - - memory_notdirty_write_complete(&ndi); - return; + notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr); } + haddr = (void *)((uintptr_t)addr + entry->addend); + if (unlikely(need_swap)) { store_memop(haddr, val, op ^ MO_BSWAP); } else { @@ -1783,14 +1796,9 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, #define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr #define ATOMIC_NAME(X) \ HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu)) -#define ATOMIC_MMU_DECLS NotDirtyInfo ndi -#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, oi, retaddr, &ndi) -#define ATOMIC_MMU_CLEANUP \ - do { \ - if (unlikely(ndi.active)) { \ - memory_notdirty_write_complete(&ndi); \ - } \ - } while (0) +#define ATOMIC_MMU_DECLS +#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, oi, retaddr) +#define ATOMIC_MMU_CLEANUP #define DATA_SIZE 1 #include "atomic_template.h" @@ -1818,7 +1826,7 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, #undef ATOMIC_MMU_LOOKUP #define EXTRA_ARGS , TCGMemOpIdx oi #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) -#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, oi, GETPC(), &ndi) +#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, oi, GETPC()) #define DATA_SIZE 1 #include "atomic_template.h" diff --git a/exec.c b/exec.c index 961d7d6497..7d835b1a2b 100644 --- a/exec.c +++ b/exec.c @@ -2718,50 +2718,6 @@ ram_addr_t qemu_ram_addr_from_host(void *ptr) return block->offset + offset; } -/* Called within RCU critical section. */ -void memory_notdirty_write_prepare(NotDirtyInfo *ndi, - CPUState *cpu, - vaddr mem_vaddr, - ram_addr_t ram_addr, - unsigned size) -{ - ndi->cpu = cpu; - ndi->ram_addr = ram_addr; - ndi->mem_vaddr = mem_vaddr; - ndi->size = size; - ndi->pages = NULL; - - trace_memory_notdirty_write_access(mem_vaddr, ram_addr, size); - - assert(tcg_enabled()); - if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { - ndi->pages = page_collection_lock(ram_addr, ram_addr + size); - tb_invalidate_phys_page_fast(ndi->pages, ram_addr, size); - } -} - -/* Called within RCU critical section. */ -void memory_notdirty_write_complete(NotDirtyInfo *ndi) -{ - if (ndi->pages) { - assert(tcg_enabled()); - page_collection_unlock(ndi->pages); - ndi->pages = NULL; - } - - /* Set both VGA and migration bits for simplicity and to remove - * the notdirty callback faster. - */ - cpu_physical_memory_set_dirty_range(ndi->ram_addr, ndi->size, - DIRTY_CLIENTS_NOCODE); - /* we remove the notdirty callback only if the code has been - flushed */ - if (!cpu_physical_memory_is_clean(ndi->ram_addr)) { - trace_memory_notdirty_set_dirty(ndi->mem_vaddr); - tlb_set_dirty(ndi->cpu, ndi->mem_vaddr); - } -} - /* Generate a debug exception if a watchpoint has been hit. */ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, MemTxAttrs attrs, int flags, uintptr_t ra) From patchwork Mon Sep 23 23:00:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174232 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp3405294ill; Mon, 23 Sep 2019 16:09:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqwM995Tq5BI6tN0r8F/QS6ecm25uJZGA0zyW8Fjee5QuMjJj9jtHVkyjvdE7wNnH14lMTEP X-Received: by 2002:a50:b6c8:: with SMTP id f8mr2688016ede.33.1569280157311; Mon, 23 Sep 2019 16:09:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569280157; cv=none; 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[209.51.188.17]) by mx.google.com with ESMTPS id m10si5652898ejx.96.2019.09.23.16.09.17 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Sep 2019 16:09:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=oNk8NQ93; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37130 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXSF-0003iz-Q8 for patch@linaro.org; Mon, 23 Sep 2019 19:09:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35883) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXJl-0005hS-Eq for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCXJj-00088E-Gt for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:29 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:43647) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iCXJi-00087E-Ue for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:27 -0400 Received: by mail-pg1-x544.google.com with SMTP id v27so2796262pgk.10 for ; Mon, 23 Sep 2019 16:00:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=C7NIKJXdUrtrKzRhohggBciUBf2QS9tq3iex/j818EA=; b=oNk8NQ93dRplDNU8a9jkYUOIIxsXsPUMhFGjWWuc407ONzGPNoNTodmO2DzLhQicbN v5CJHj5fPDGfvkmJz9U4UfjQfJ32OfJQwTZ8IKErbXE2ktI6xAKdy+eEvEk86jOfUFBH pDTPqHiCdErH2f3cJc7GtLZCYtpB4VzzTHgMXK4xpJeluNOOR7Av14DgS/WsSQKHa66/ rESxYrhs+T9dFoz29/0buSMwgVM5MlZbv8HWCj62/xMx392zlD7y9P/mr7iyeCYqeaqz yGjvWAnsF36htFkXov4pujX78aU650ps4l1I30zylj9rUxGinRs2qf+0dq5Lxi3Hqb5D Nr1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=C7NIKJXdUrtrKzRhohggBciUBf2QS9tq3iex/j818EA=; b=YfQugzycTsdkc9TrNC1xIjZKAzV/GtfPhWFNuyMrR3z3xkIxn/DRljo5eP/sfu531Q mkg1ZiXKcl2aQzdc+hnJgdODbGBUhqBPWIL/qrmtTRKkf2F5NCx6dIOke/K1oTjwkCJE HuQXcAzM/M2AKtbUlMNOIKxCanfFw6gyoqgS9dNKp/iQzxgrjydByX4I+gwIjYvJXkN9 ueyktJ1kqrQ3fLybgoLmco/Qc58U1gEHwVTWEnnqyYyY21A/jcg/NgwmDXAeQhMPhTTP DCGmytyYcn7acim5hwRULgdFtYF7F/P30a512yaygmVzLad5Zlhp1ZQJlPtTZbaYqrl5 w25Q== X-Gm-Message-State: APjAAAXsqtFvJfACtmzVZuZBl94MpxeHPSLJeQkpKI8FbTXBi6nzgZEw Lirg93KoLOe1MS4mU6/25Em1kqZQowc= X-Received: by 2002:a62:3147:: with SMTP id x68mr2125356pfx.129.1569279625122; Mon, 23 Sep 2019 16:00:25 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.59]) by smtp.gmail.com with ESMTPSA id 74sm11674810pfy.78.2019.09.23.16.00.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Sep 2019 16:00:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 12/16] cputlb: Handle TLB_NOTDIRTY in probe_access Date: Mon, 23 Sep 2019 16:00:00 -0700 Message-Id: <20190923230004.9231-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190923230004.9231-1-richard.henderson@linaro.org> References: <20190923230004.9231-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, alex.bennee@linaro.org, stefanha@redhat.com, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can use notdirty_write for the write and return a valid host pointer for this case. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) -- 2.17.1 Reviewed-by: David Hildenbrand Reviewed-by: Alex Bennée diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 09b0df87c6..d0bdef1eb3 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1167,16 +1167,24 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return NULL; } - /* Handle watchpoints. */ - if (tlb_addr & TLB_WATCHPOINT) { - cpu_check_watchpoint(env_cpu(env), addr, size, - env_tlb(env)->d[mmu_idx].iotlb[index].attrs, - wp_access, retaddr); - } + if (unlikely(tlb_addr & TLB_FLAGS_MASK)) { + CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index]; - /* Reject I/O access, or other required slow-path. */ - if (tlb_addr & (TLB_NOTDIRTY | TLB_MMIO | TLB_BSWAP | TLB_ROM)) { - return NULL; + /* Reject I/O access, or other required slow-path. */ + if (tlb_addr & (TLB_MMIO | TLB_BSWAP | TLB_ROM)) { + return NULL; + } + + /* Handle watchpoints. */ + if (tlb_addr & TLB_WATCHPOINT) { + cpu_check_watchpoint(env_cpu(env), addr, size, + iotlbentry->attrs, wp_access, retaddr); + } + + /* Handle clean RAM pages. */ + if (tlb_addr & TLB_NOTDIRTY) { + notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr); + } } return (void *)((uintptr_t)addr + entry->addend); From patchwork Mon Sep 23 23:00:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174238 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp3411521ill; Mon, 23 Sep 2019 16:16:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqzuL1HDue/LJer24C3b5I8UkssRk1Gkg0fvLgdElFbi4VCh8IW1vLwaK+9FHzpPJJAHhJbF X-Received: by 2002:a50:baab:: with SMTP id x40mr2774214ede.60.1569280572485; Mon, 23 Sep 2019 16:16:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569280572; cv=none; d=google.com; s=arc-20160816; b=Iqq5Zt8WrjuTBoEyZ+2q416NRdcU9BRgpPYltsyOaDbmQe/rMJW11uNaEgcLoC/MkT ipEasJnxi3zQQzlVKe5csNlG5h2ZhMF8nM0kB9heqKOzhSUdExT/rnJZ3ceR91huLa6P 7FPIDv21lINBq00IfzTxC4GH3rWeNHeljST8Gpp0iowN/2lG+zZos7CWLD1c85xSNXdZ VCxmPpF+dpF8tOpIpxkmNyxYy/HmWTNNEFNMkcU6XQv1Z9VfuQ/Yx1uGZaNhHqz2s20n 1/FD0iZvRt0rinRrv8aGNq/B5mC8Z4NE+7pyb9ojpI6i5bIbRx7mXOsqdY9WvNB89STK KkBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=QdsEwoYPo2VsUnkZYt75w7M34lLlPDJP4qSt8k4C0rI=; b=Kj5ZaV38K49K9CI3X3iYK6UTZscqunrlsNL13A3KBPGf1YZj+vNlxhp25HuDChgRFA HqFdB2h9/wp7EcT3Ty3dmc/6vk8AjgfogNmUhMIK/jhD4BtoMR5kvWyZd3CszidlEHHc Gc5MuPdKVSmeRy5PihsK/64XoZLhxnGWhJaYhZ4tiuc5DMy9VDaVb0AphbRuaKB+OJY2 cBgR6E+4niBq++EYpIPVcF/XSiqkCplsnpxUyV9s3nqGM1ZZ8VnbtjgIc+L2PKSEbiIH SH/qbaG3GUsCzwPnk9H3bI13PUBrllLKAhDm5a8BN7Nx4DcUoSDM9uxbM84Zp1XKC0+T cb/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yRgEbll8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, alex.bennee@linaro.org, stefanha@redhat.com, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With the merge of notdirty handling into store_helper, the last user of cpu->mem_io_vaddr was removed. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 2 -- accel/tcg/cputlb.c | 2 -- hw/core/cpu.c | 1 - 3 files changed, 5 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c7cda65c66..031f587e51 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -338,7 +338,6 @@ struct qemu_work_item; * @next_cpu: Next CPU sharing TB cache. * @opaque: User data. * @mem_io_pc: Host Program Counter at which the memory was accessed. - * @mem_io_vaddr: Target virtual address at which the memory was accessed. * @kvm_fd: vCPU file descriptor for KVM. * @work_mutex: Lock to prevent multiple access to queued_work_*. * @queued_work_first: First asynchronous work pending. @@ -413,7 +412,6 @@ struct CPUState { * we store some rarely used information in the CPU context. */ uintptr_t mem_io_pc; - vaddr mem_io_vaddr; /* * This is only needed for the legacy cpu_unassigned_access() hook; * when all targets using it have been converted to use diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d0bdef1eb3..0ca6ee60b3 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -927,7 +927,6 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, cpu_io_recompile(cpu, retaddr); } - cpu->mem_io_vaddr = addr; cpu->mem_io_access_type = access_type; if (mr->global_locking && !qemu_mutex_iothread_locked()) { @@ -967,7 +966,6 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, if (!cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); } - cpu->mem_io_vaddr = addr; cpu->mem_io_pc = retaddr; if (mr->global_locking && !qemu_mutex_iothread_locked()) { diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 0035845511..73b1ee34d0 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -261,7 +261,6 @@ static void cpu_common_reset(CPUState *cpu) cpu->interrupt_request = 0; cpu->halted = 0; cpu->mem_io_pc = 0; - cpu->mem_io_vaddr = 0; cpu->icount_extra = 0; atomic_set(&cpu->icount_decr_ptr->u32, 0); cpu->can_do_io = 1; From patchwork Mon Sep 23 23:00:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174240 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp3413447ill; Mon, 23 Sep 2019 16:18:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqwsgPZgJC5A+9co5OUuKYb7as/bB4p/6kPfMM8nMNepnb5eP7el9VAlKWupzbjXozgDStie X-Received: by 2002:a17:906:fad6:: with SMTP id lu22mr6994ejb.98.1569280710376; Mon, 23 Sep 2019 16:18:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569280710; cv=none; d=google.com; s=arc-20160816; b=nV1QsY80/OV/qtoGEUv+Wf9TK8rAEexng/L06Z5hf5ESPOtYom9mbsw80gVtWUjJBH 91JNNr5JlCd4f1ZEN/R1K0dzaacE1Hm5D92CZmf30i7I2pnCSthAkm0cyVXzBVfc8kWB lj51OOA+A8xMB8it7EEmorbrRSZkHxrGy/2fkcUwRJm6BnbAUOCu0E9f7ZgHGHLsrdAg jO3J5sTQbBARIKW5wBeGiDnE4KnutdWKk7KUhLKDyJiU9ZEnX9+hpw3rvxsa441mD1pH uW1UzYCSsR/SMDAhLcJXMxu/ey7oDITXEopFPSsWmznnRrAESfeJp4bADKJGgqdYsW25 IBLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=h1WBZAofTlP3LEJIOv9bQuQl53SA63G846KraTbrjlQ=; b=bu9v3tfvjQiTzXFvoW7WIAmlHQ0McWFFW0JC52FUCOpYW0hAq0NC6dCz7eNYiiGMCF ZFYbdLZVXbpLXRwexX9GajTXEekdkn7phQLJFpHeFAzVgWMbI4Feim83c5WbRQdEuGiG r5hObEc8AlgOuFs16gfK/dkss+qKHAkmdyY5VnQeXTtRjBzKiuPwTwGcX3a0Fa7d60cj +7KhLCDdHwrPNOyUoRaGdR4iy5IR8UaRtnS9nv+ykolBwDwJJeaHiWoQ20B1v+XS3o0/ RYUPHLufg0c4D8K4ztj3I7P8XVKxWIpotMKJwGnjHGMFAy8Nyjqzn76GynnMvPzWUsyQ 1Nhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="bF/gJ9lI"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id oy5si5578157ejb.170.2019.09.23.16.18.30 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Sep 2019 16:18:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="bF/gJ9lI"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37296 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXbB-0004ug-9Y for patch@linaro.org; Mon, 23 Sep 2019 19:18:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35934) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXJn-0005jL-M9 for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCXJl-00089p-HG for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:31 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:44992) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iCXJl-000892-3t for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:29 -0400 Received: by mail-pg1-x543.google.com with SMTP id g3so7313849pgs.11 for ; Mon, 23 Sep 2019 16:00:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=h1WBZAofTlP3LEJIOv9bQuQl53SA63G846KraTbrjlQ=; b=bF/gJ9lIziCS5Hb36tIc7A97PEWu07s9w0ytz3BKRobAvWf/L97VDS0IChUCo2jPPU 6l0Y2pf9kFUgW0u/4xgfY1b9a4ELaZS4xq4ZBOn2k0QZO1qiYPCFsUNCRMXtkyWCPeV4 F21Rq2QZSBlp0TM+eMraBd7tIojUaInyzcx+31UjyL53lNQczIpyw0ERVlZyIfgbUssT wP0MkQTI7trFFdoSGerQ/GWeJ769Y2T9phfdwYEuwAE5xuT82lg8sQ58kwcUv3T1DIbW j5zwyCmCeoD8GRbJ/WefPGDjWFPC01vxbQSPxMwfdi4UT7VTZxP5EvDyQ7n/3MXI7sUp Adng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=h1WBZAofTlP3LEJIOv9bQuQl53SA63G846KraTbrjlQ=; b=IOrzXUdRjC+JRNwHnY41Fjq5W2BcowMsmCPKeiC/NacoEPbHiZB1j2hzLRizhf9vcG 0fEEQnH9CcDAfeT6Afi3eRwd0d+w60oF2BC/nYKCCpiqYbUGgGERd/szVwE79qSoBBV5 4SlV3LAqSZeiozTh0XsbSD7KTpcKHSeDSUzHxdBFgTbgnAfQltksfJG+wD9GMatcaFVM fQmM6/BOAF9WMtgWi23QR+NW6+WvqT6bmqoI1GeGibqkiJfhHePM/X90f1PbsHVuD5X8 PypI4C7zfomYi9lHqMKgMxu+8YSll8aarRVsPveb+lowIWmi2cSLT4FSvRYwYr2HlJ5I nqDQ== X-Gm-Message-State: APjAAAVzStf6lTZ9s3cK7Z1YdRoxi9zXSbibxptN8W+Cnn+Dc3Sj+Y3n XPmkwgHl3jj93V7JxU9arTU+ng9OkOk= X-Received: by 2002:a17:90a:8087:: with SMTP id c7mr2020948pjn.56.1569279627596; Mon, 23 Sep 2019 16:00:27 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.59]) by smtp.gmail.com with ESMTPSA id 74sm11674810pfy.78.2019.09.23.16.00.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Sep 2019 16:00:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 14/16] cputlb: Remove tb_invalidate_phys_page_range is_cpu_write_access Date: Mon, 23 Sep 2019 16:00:02 -0700 Message-Id: <20190923230004.9231-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190923230004.9231-1-richard.henderson@linaro.org> References: <20190923230004.9231-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, alex.bennee@linaro.org, stefanha@redhat.com, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" All callers pass false to this argument. Remove it and pass the constant on to tb_invalidate_phys_page_range__locked. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- accel/tcg/translate-all.h | 3 +-- accel/tcg/translate-all.c | 6 ++---- exec.c | 4 ++-- 3 files changed, 5 insertions(+), 8 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/accel/tcg/translate-all.h b/accel/tcg/translate-all.h index 64f5fd9a05..31f2117188 100644 --- a/accel/tcg/translate-all.h +++ b/accel/tcg/translate-all.h @@ -28,8 +28,7 @@ struct page_collection *page_collection_lock(tb_page_addr_t start, void page_collection_unlock(struct page_collection *set); void tb_invalidate_phys_page_fast(struct page_collection *pages, tb_page_addr_t start, int len); -void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, - int is_cpu_write_access); +void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end); void tb_check_watchpoint(CPUState *cpu); #ifdef CONFIG_USER_ONLY diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 5d1e08b169..de4b697163 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1983,8 +1983,7 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages, * * Called with mmap_lock held for user-mode emulation */ -void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, - int is_cpu_write_access) +void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end) { struct page_collection *pages; PageDesc *p; @@ -1996,8 +1995,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, return; } pages = page_collection_lock(start, end); - tb_invalidate_phys_page_range__locked(pages, p, start, end, - is_cpu_write_access); + tb_invalidate_phys_page_range__locked(pages, p, start, end, 0); page_collection_unlock(pages); } diff --git a/exec.c b/exec.c index 7d835b1a2b..b3df826039 100644 --- a/exec.c +++ b/exec.c @@ -1012,7 +1012,7 @@ const char *parse_cpu_option(const char *cpu_option) void tb_invalidate_phys_addr(target_ulong addr) { mmap_lock(); - tb_invalidate_phys_page_range(addr, addr + 1, 0); + tb_invalidate_phys_page_range(addr, addr + 1); mmap_unlock(); } @@ -1039,7 +1039,7 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs) return; } ram_addr = memory_region_get_ram_addr(mr) + addr; - tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); + tb_invalidate_phys_page_range(ram_addr, ram_addr + 1); rcu_read_unlock(); } From patchwork Mon Sep 23 23:00:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174235 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp3407967ill; Mon, 23 Sep 2019 16:12:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqwjo1a30c79tM0mGNLh6Fb6+cUOTsJwFevd8+gOddNma5UHhl/ogoWOMCLNi0IBvGVj+va6 X-Received: by 2002:a17:906:7cc7:: with SMTP id h7mr1965363ejp.204.1569280323495; Mon, 23 Sep 2019 16:12:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569280323; cv=none; d=google.com; s=arc-20160816; b=Vy+yDd2OMu7iWLqqLHyW1aP7SoZLoKtPIXd7yT1NeeM3ZbtILQJtYnkB7dWP5rB6kK ytZvhSXbt0InMKIticdP9HfEkgMwm5u48lXLxhKBmaPcUJTFheGjK9UjYiyXbIC4eYxx hrPVjAuWUB3ANzaC5UGyW/b3mDOYQ0ZrijfoVjvX34y09NOV2pJWOZ2roCPj8H8PK/Ly uAfoG0gfccT7iNYT4y4NTvN8/H+R13naYYak1inMbN1zhzZN8V5Mh0s2UF8KovulKtbU uOTWPujPCEAOCe4Knt014QkoJmf3/9coJA917VJtUl/ioresUK9PY1iwJtN0Eii2bI9h mRFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=Fy8yqGvXJfEtemqcYdzYU9XShb4v7XS8MjArgMABc6w=; b=q8HHsY0Er4iwzHHllRotRvLWmDDnSSGgF+j019CyWE1wLUy3mdI7T6MLafaOSeEl+F EJiFEBZjy5hy8+14zc9ZB271GyFaRM9dQGpEMaTwp4ndd18OLAsLh4bV0xy12rgw30xC O31lj9tXMXXev/kxSGpyL1FsB8zMS9YdS34ln02TJ1AuN/kw2Iwx9e4iwc5HU5qFzdmE pjeqhRIxCf8MXaSrZJl516yo7ooWtdPM3xncPOlqHJmWS3PLK3jOROOd9TwkuQtao4rt pmXl4iNLRXgARQs1ycKagXoOCNlJQLZO/Ajl5UeGDOGXDgLYXnOTeJhS/LKCJ1KWQyt3 JmOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Uh7DC6M4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w6si7280301eda.336.2019.09.23.16.12.03 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Sep 2019 16:12:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Uh7DC6M4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37166 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXUw-0006TH-3L for patch@linaro.org; Mon, 23 Sep 2019 19:12:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35951) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXJo-0005kB-HU for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCXJm-0008AQ-M6 for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:32 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:36260) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iCXJm-00089y-A1 for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:30 -0400 Received: by mail-pf1-x443.google.com with SMTP id y22so10153179pfr.3 for ; Mon, 23 Sep 2019 16:00:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Fy8yqGvXJfEtemqcYdzYU9XShb4v7XS8MjArgMABc6w=; b=Uh7DC6M4fZGv0z+2vD70cpe39Z/CcwRdC5TWSZMpLxDgRH3zdsH/nTiIQKQowcqoRs So9Sh/D+dKzaLJxlP4ESNzSa+R97yG44+I6ynK41HU6bklBucFWfTWII/vq9ZKmUHdze BDxl3/O6ddErC5kbccJ0IeZttVhg+G5C15XSwaM2HpRgVc6b0+bSm9u63qqL/1tY+gNn kxZDyUDnJH47GksZKxejMA4Y75iROr+PgOPI/sRsuvICMMKCpnEbFkcyDXBc73FWGlxJ luvY2gwEv7XkRk7PBW4euFoP5ornrj0LiL6nk+MCEXTBw9KjnMp/NZw3eaGX1o3dP8Ly Vieg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Fy8yqGvXJfEtemqcYdzYU9XShb4v7XS8MjArgMABc6w=; b=FKXKgFTC+/tJOmhqYimtVgoq8V+nu6n62QSiUR1S0RQ4iobHjPYxvnJONaKvZ0JXj1 mTeO5DzV/41Unz11IwOrrt4xd8zQGFQik9vEzq+iuLQpKUHftr78US0CafYKOSy0Scaq kmDKxN1XtowVGPPvieNAg7tFkOlkw0WvEPlBTSIgZOMMd3+vgYNsef4FSmOJhQPVqYVM MIIlst34i8BqNbR1iK38S0kQkifV2pH45sD1uWRgaJmjZOVSQ6bWcJJ8JR/vkMJOMOEX 5+JzdP79WzOPoM8MQ60FIN8PxQQeTnXNJSr9pxj4m/yWOdiaR1At4SjN0eyiDdzTov4h nAFg== X-Gm-Message-State: APjAAAWobTAi+kXCOVnUljYZPOOoLZVyPjYdcMNEvE0u5RuyPIjA0rzI MTT5iuOynGo8rr5EUoOIpJztmUIQTrU= X-Received: by 2002:a62:2f84:: with SMTP id v126mr2173907pfv.167.1569279628832; Mon, 23 Sep 2019 16:00:28 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.59]) by smtp.gmail.com with ESMTPSA id 74sm11674810pfy.78.2019.09.23.16.00.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Sep 2019 16:00:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 15/16] cputlb: Pass retaddr to tb_invalidate_phys_page_fast Date: Mon, 23 Sep 2019 16:00:03 -0700 Message-Id: <20190923230004.9231-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190923230004.9231-1-richard.henderson@linaro.org> References: <20190923230004.9231-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, alex.bennee@linaro.org, stefanha@redhat.com, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rather than rely on cpu->mem_io_pc, pass retaddr down directly. Within tb_invalidate_phys_page_range__locked, the is_cpu_write_access parameter is non-zero exactly when retaddr would be non-zero, so that is a simple replacement. Recognize that current_tb_not_found is true only when mem_io_pc (and now retaddr) are also non-zero, so remove a redundant test. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- accel/tcg/translate-all.h | 3 ++- accel/tcg/cputlb.c | 6 +----- accel/tcg/translate-all.c | 39 +++++++++++++++++++-------------------- 3 files changed, 22 insertions(+), 26 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/accel/tcg/translate-all.h b/accel/tcg/translate-all.h index 31f2117188..135c1ea96a 100644 --- a/accel/tcg/translate-all.h +++ b/accel/tcg/translate-all.h @@ -27,7 +27,8 @@ struct page_collection *page_collection_lock(tb_page_addr_t start, tb_page_addr_t end); void page_collection_unlock(struct page_collection *set); void tb_invalidate_phys_page_fast(struct page_collection *pages, - tb_page_addr_t start, int len); + tb_page_addr_t start, int len, + uintptr_t retaddr); void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end); void tb_check_watchpoint(CPUState *cpu); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 0ca6ee60b3..ea5d12c59d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1093,11 +1093,7 @@ static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size, if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { struct page_collection *pages = page_collection_lock(ram_addr, ram_addr + size); - - /* We require mem_io_pc in tb_invalidate_phys_page_range. */ - cpu->mem_io_pc = retaddr; - - tb_invalidate_phys_page_fast(pages, ram_addr, size); + tb_invalidate_phys_page_fast(pages, ram_addr, size, retaddr); page_collection_unlock(pages); } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index de4b697163..db77fb221b 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1889,7 +1889,7 @@ static void tb_invalidate_phys_page_range__locked(struct page_collection *pages, PageDesc *p, tb_page_addr_t start, tb_page_addr_t end, - int is_cpu_write_access) + uintptr_t retaddr) { TranslationBlock *tb; tb_page_addr_t tb_start, tb_end; @@ -1897,9 +1897,9 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages, #ifdef TARGET_HAS_PRECISE_SMC CPUState *cpu = current_cpu; CPUArchState *env = NULL; - int current_tb_not_found = is_cpu_write_access; + bool current_tb_not_found = retaddr != 0; + bool current_tb_modified = false; TranslationBlock *current_tb = NULL; - int current_tb_modified = 0; target_ulong current_pc = 0; target_ulong current_cs_base = 0; uint32_t current_flags = 0; @@ -1931,24 +1931,21 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages, if (!(tb_end <= start || tb_start >= end)) { #ifdef TARGET_HAS_PRECISE_SMC if (current_tb_not_found) { - current_tb_not_found = 0; - current_tb = NULL; - if (cpu->mem_io_pc) { - /* now we have a real cpu fault */ - current_tb = tcg_tb_lookup(cpu->mem_io_pc); - } + current_tb_not_found = false; + /* now we have a real cpu fault */ + current_tb = tcg_tb_lookup(retaddr); } if (current_tb == tb && (tb_cflags(current_tb) & CF_COUNT_MASK) != 1) { - /* If we are modifying the current TB, we must stop - its execution. We could be more precise by checking - that the modification is after the current PC, but it - would require a specialized function to partially - restore the CPU state */ - - current_tb_modified = 1; - cpu_restore_state_from_tb(cpu, current_tb, - cpu->mem_io_pc, true); + /* + * If we are modifying the current TB, we must stop + * its execution. We could be more precise by checking + * that the modification is after the current PC, but it + * would require a specialized function to partially + * restore the CPU state. + */ + current_tb_modified = true; + cpu_restore_state_from_tb(cpu, current_tb, retaddr, true); cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, ¤t_flags); } @@ -2042,7 +2039,8 @@ void tb_invalidate_phys_range(target_ulong start, target_ulong end) * Call with all @pages in the range [@start, @start + len[ locked. */ void tb_invalidate_phys_page_fast(struct page_collection *pages, - tb_page_addr_t start, int len) + tb_page_addr_t start, int len, + uintptr_t retaddr) { PageDesc *p; @@ -2069,7 +2067,8 @@ void tb_invalidate_phys_page_fast(struct page_collection *pages, } } else { do_invalidate: - tb_invalidate_phys_page_range__locked(pages, p, start, start + len, 1); + tb_invalidate_phys_page_range__locked(pages, p, start, start + len, + retaddr); } } #else From patchwork Mon Sep 23 23:00:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 174241 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp3415286ill; Mon, 23 Sep 2019 16:20:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqwnJbbCpJiOmdT5sN0uD/BgESNHsr4BmhWdFkPoLVI+OqMIEzeuYSXIECGNuF0Ao2mufRIz X-Received: by 2002:a05:6214:1189:: with SMTP id t9mr49474qvv.89.1569280852913; Mon, 23 Sep 2019 16:20:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569280852; cv=none; d=google.com; s=arc-20160816; b=kgLR00wIU5/VQF6o5YQwtj5i8PzIj6RdeYPtO0Uw1F7Mwhk3YOwr8EOwWtwZdjoSeV 6JCODIwn1YSpvy6gFu+a1oZQQy9xW7pLQRyJIfYmkyi+wMRmcOB7imHbkcBsh9KXZdeA +6uNlSk5GovbNlf0drxID7nahB9W9wJMxhFbAqR6ya89AQmJhZEncRjx2Bk5lTDDIjdI L50RW83/it3h/JoMXqncX3fi2L7t8RIWf08CZYafsj+9gS+1TWh9uolswUQA9wGaTrfv AR/PrwdW+RVnZgBIRztyIRqmoqbRkrukgxLW5XTSEpGBQ69AkDPz2mG6ve+4vsWDHUhM s87w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=jECBewfqaW7UcxXyZuLJYCCjFkwJDy6OJzmhsg374E4=; b=rnD8AbepQV/26m7i+iFw40tF/zQ/EBr0K2SqfAcMFjQTA7HZWEoAqVWiSHuivazAZZ iWqwbmfsM4Lwu3c5YSATisTPw0VXUXXQK0IYw6OjiFQZZVGOTnZlB3f5XFZJ1SSl3Z3y 6naCqLRA01OATrNHa1RBSY+TTrsvdnyzdTb8D79NwhFnChYyZXqA5U1R0rArmz3tc+0E usofupsbW4HL3V1cbGtbF2cWcplTEAfd6ikjLCAuxObj5zdwd3hqsYMcN+Hh7ckzaYA+ iHSZJ3vp45eWArTefWRHRzbR4aiw5A9o1rgFu/pNC1rV7l3ZT8SfzSwjPZk1S2n1N9iy y/tQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=uSa8OYsa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n16si1583381qkg.368.2019.09.23.16.20.52 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Sep 2019 16:20:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=uSa8OYsa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37316 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXdU-0006zP-7I for patch@linaro.org; Mon, 23 Sep 2019 19:20:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35971) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCXJp-0005kw-OF for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCXJn-0008BI-NQ for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:33 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:41688) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iCXJn-0008Ah-EH for qemu-devel@nongnu.org; Mon, 23 Sep 2019 19:00:31 -0400 Received: by mail-pg1-x543.google.com with SMTP id s1so7780240pgv.8 for ; Mon, 23 Sep 2019 16:00:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jECBewfqaW7UcxXyZuLJYCCjFkwJDy6OJzmhsg374E4=; b=uSa8OYsaAPdBlDySx3jpe8K4Lkk2zDZHOBVdRRmmuqtJmm6HwFTPJ6tUw9BHce3iiO eU/0TGg2XhC2D1rt8vO0foHpZdr2BIhydY6/LXJTQEWnPBiHLE+bcZPrXHMUY1uxVfnT r7dKPv+ejn/MdbzmOpsZbQcEG3jaHbzLqYtT/SkW+72xOGr6SI46JQJLho7ay9s1CNyU e+1DgbodXNZMWFyLtQpXW5FBjVjTFL0mCNz477RbWtVKConOWPk0mQFlTJlO9zTuFrEb qIpDnSnMOAblgWeXUfFbUFO2VulBfWnxr46GczkGcnJbLrZZr8b0BAzCms5VmsIqqidd X65g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jECBewfqaW7UcxXyZuLJYCCjFkwJDy6OJzmhsg374E4=; b=WgnfUPM0kIGu84vOL3BH6a+stS9cPyROlYO2vngujglV815B/kCqDAfG+qhpWuQSwb kywU4B+GWpjczrHNhj/f1LyAGZ9yLYqXqbyuk1pG01gseoOVOMpem/C1rpJWgoSws6gh xuOQiXeMmxFDBxrYJdDIHJ/dFpv0eOGYtz++gXh3ZuQ4Ui/tzWoc+vLYnOyQN+aOtViL vAIJ+yqClWkN23ucDGfGlEqjhL/enr1/aH04ntevfGbSByghb2ymzLPL72qngPlsmKwX cC4ZWQ0ePU2BxUbza0fyVqPdWAjcOhE8AwJQfsO2yUXiqIrjs7eU/vrp9CciMXV0yA3N rDhQ== X-Gm-Message-State: APjAAAU+a70G9tD4Dhfw/QBZqwP2ykKn5gH1B8R4Sd25+dGueZc7OJZ6 72Kfrk5gK8ZaSRWe38o3K/yHH3+qgQs= X-Received: by 2002:a65:420d:: with SMTP id c13mr2247741pgq.293.1569279630041; Mon, 23 Sep 2019 16:00:30 -0700 (PDT) Received: from localhost.localdomain ([12.206.46.59]) by smtp.gmail.com with ESMTPSA id 74sm11674810pfy.78.2019.09.23.16.00.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Sep 2019 16:00:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 16/16] cputlb: Pass retaddr to tb_check_watchpoint Date: Mon, 23 Sep 2019 16:00:04 -0700 Message-Id: <20190923230004.9231-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190923230004.9231-1-richard.henderson@linaro.org> References: <20190923230004.9231-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, alex.bennee@linaro.org, stefanha@redhat.com, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Fixes the previous TLB_WATCHPOINT patches because we are currently failing to set cpu->mem_io_pc with the call to cpu_check_watchpoint. Pass down the retaddr directly because it's readily available. Fixes: 50b107c5d61 Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- accel/tcg/translate-all.h | 2 +- accel/tcg/translate-all.c | 6 +++--- exec.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/accel/tcg/translate-all.h b/accel/tcg/translate-all.h index 135c1ea96a..a557b4e2bb 100644 --- a/accel/tcg/translate-all.h +++ b/accel/tcg/translate-all.h @@ -30,7 +30,7 @@ void tb_invalidate_phys_page_fast(struct page_collection *pages, tb_page_addr_t start, int len, uintptr_t retaddr); void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end); -void tb_check_watchpoint(CPUState *cpu); +void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); #ifdef CONFIG_USER_ONLY int page_unprotect(target_ulong address, uintptr_t pc); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index db77fb221b..66d4bc4341 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -2142,16 +2142,16 @@ static bool tb_invalidate_phys_page(tb_page_addr_t addr, uintptr_t pc) #endif /* user-mode: call with mmap_lock held */ -void tb_check_watchpoint(CPUState *cpu) +void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr) { TranslationBlock *tb; assert_memory_lock(); - tb = tcg_tb_lookup(cpu->mem_io_pc); + tb = tcg_tb_lookup(retaddr); if (tb) { /* We can use retranslation to find the PC. */ - cpu_restore_state_from_tb(cpu, tb, cpu->mem_io_pc, true); + cpu_restore_state_from_tb(cpu, tb, retaddr, true); tb_phys_invalidate(tb, -1); } else { /* The exception probably happened in a helper. The CPU state should diff --git a/exec.c b/exec.c index b3df826039..8a0a6613b1 100644 --- a/exec.c +++ b/exec.c @@ -2758,7 +2758,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, cpu->watchpoint_hit = wp; mmap_lock(); - tb_check_watchpoint(cpu); + tb_check_watchpoint(cpu, ra); if (wp->flags & BP_STOP_BEFORE_ACCESS) { cpu->exception_index = EXCP_DEBUG; mmap_unlock();