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[2001:14ba:a00e:a300::8a5]) by smtp.gmail.com with ESMTPSA id b8-20020ac25628000000b00512c8d9c8a0sm240802lff.113.2024.02.20.09.12.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 09:12:16 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 20 Feb 2024 19:12:10 +0200 Subject: [PATCH] drm/msm/a6xx: specify UBWC config for sc7180 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240220-fd-sc7180-explicit-ubwc-v1-1-611a58091724@linaro.org> X-B4-Tracking: v=1; b=H4sIAGrd1GUC/x3MSQqAMAxA0atI1gZibXG4irjQmmpAVFonEO9uc fkW/z8Q2AsHqJMHPJ8SZF0isjQBO3XLyChDNChSmpQidAMGW2QlId/bLFZ2PPrLoqbK5K4zptI FxHrz7OT+z037vh92pKZiaQAAAA== To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten Cc: David Airlie , Daniel Vetter , Connor Abbott , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Leonard Lausen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1745; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=BnIHUEr8mYm7RtcY6EIoREgODeHWv+l5ytTt0UKBG8g=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBl1N1wx/mMxixCVwdRRTD/ucyIwKcwBbXBvC30g rD2Iyw2+UWJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZdTdcAAKCRCLPIo+Aiko 1T8iB/4w9oI2xjlbk3C6OJx+Kq76dR5a36rY2818UsGabyH8zrIrLvQ1reO94havjNuL5TOlL9k Rh0xKkeO8Vy/cgIVyYC9pKJ6CU0d7SXKzXfPFHsrwbBKyolMMLm99NXX6ex+FtU+ZtFcLArMikx XcqrbDFKFhSBGFg1KIQjIq8ydqS6XByYClfWwKkbAPcvxe+kAdjM2eXWj+IF0APg+FQSPMHoZhp 2luSTFnVRuoOAH94mr9JC8svyYMjlDEGPX2x4kT/jvcZx/b6f2j8f4e9ytgCVVdV9/yM78Ja3Dd QZiKQZqgP2vFyRjC9uKtqFF2Cv7oqev6Fbh6jJodA9JRdkhK X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Historically the Adreno driver has not been updating memory configuration registers on a618 (SC7180 platform) implying that the default configuration is fine. After the rework performed in the commit 8814455a0e54 ("drm/msm: Refactor UBWC config setting") the function a6xx_calc_ubwc_config() still contained this shortcut and did not calculate UBWC configuration. However the function which now actually updates hardware registers, a6xx_set_ubwc_config(), doesn't contain such check. Rather than adding the check to a6xx_set_ubwc_config(), fill in the UBWC config for a618 (based on readings from SC7180). Reported-by: Leonard Lausen Link: https://gitlab.freedesktop.org/drm/msm/-/issues/49 Fixes: 8814455a0e54 ("drm/msm: Refactor UBWC config setting") Cc: Connor Abbott Signed-off-by: Dmitry Baryshkov Reviewed-by: Connor Abbott --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) --- base-commit: 41c177cf354126a22443b5c80cec9fdd313e67e1 change-id: 20240220-fd-sc7180-explicit-ubwc-40953fa55947 Best regards, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c9c55e2ea584..dc80e5940f51 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1292,9 +1292,8 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) gpu->ubwc_config.ubwc_mode = 1; } - /* a618 is using the hw default values */ if (adreno_is_a618(gpu)) - return; + gpu->ubwc_config.highest_bank_bit = 14; if (adreno_is_a619_holi(gpu)) gpu->ubwc_config.highest_bank_bit = 13;