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[176.184.23.7]) by smtp.gmail.com with ESMTPSA id cc3-20020a5d5c03000000b0033d5e3c6835sm5702004wrb.5.2024.02.20.11.26.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 20 Feb 2024 11:26:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Alex_Benn=C3=A9e?= , Mark Cave-Ayland , Bernhard Beschow , Richard Henderson , Markus Armbruster , Alexander Graf , Anton Johansson , Paolo Bonzini , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 1/2] target/alpha: Expose TMR and SMP IRQ lines via QDev Date: Tue, 20 Feb 2024 20:26:24 +0100 Message-ID: <20240220192625.17944-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240220192625.17944-1-philmd@linaro.org> References: <20240220192625.17944-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In order to remove calls to cpu_interrupt() from hw/ code, expose the TMR and SMP interrupts via QDev as named GPIOs. Signed-off-by: Philippe Mathieu-Daudé --- target/alpha/cpu.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index bf70173a25..619cd54593 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -25,6 +25,31 @@ #include "cpu.h" #include "exec/exec-all.h" +#ifndef CONFIG_USER_ONLY +static void alpha_cpu_tmr_irq(void *opaque, int irq, int level) +{ + DeviceState *dev = opaque; + CPUState *cs = CPU(dev); + + if (level) { + cs->interrupt_request |= CPU_INTERRUPT_TIMER; + } else { + cs->interrupt_request &= ~CPU_INTERRUPT_TIMER; + } +} + +static void alpha_cpu_smp_irq(void *opaque, int irq, int level) +{ + DeviceState *dev = opaque; + CPUState *cs = CPU(dev); + + if (level) { + cs->interrupt_request |= CPU_INTERRUPT_SMP; + } else { + cs->interrupt_request &= ~CPU_INTERRUPT_SMP; + } +} +#endif static void alpha_cpu_set_pc(CPUState *cs, vaddr value) { @@ -89,6 +114,11 @@ static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) qemu_init_vcpu(cs); +#ifndef CONFIG_USER_ONLY + qdev_init_gpio_in_named(dev, alpha_cpu_tmr_irq, "TMR", 1); + qdev_init_gpio_in_named(dev, alpha_cpu_smp_irq, "SMP", 1); +#endif + acc->parent_realize(dev, errp); } From patchwork Tue Feb 20 19:26:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 774288 Delivered-To: patch@linaro.org Received: by 2002:a5d:4943:0:b0:33b:4db1:f5b3 with SMTP id r3csp1820384wrs; Tue, 20 Feb 2024 11:27:37 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWfVBElJJ4DPfuYYIh137l4wO2aPqntq7rd+XnFsEkZzCydCv5VjVzje7oH6i/20TWgouF/v28GTHbJmvZb+1r5 X-Google-Smtp-Source: AGHT+IGDrM0fUyr/XIQZL0GpAlOiBOiU2yn7fovVyMdOV3Tr2FMtS3yKpjT1pZHJ2B2FW6+F54Tv X-Received: by 2002:ac8:5314:0:b0:42c:6e6b:2d75 with SMTP id t20-20020ac85314000000b0042c6e6b2d75mr18741330qtn.44.1708457257210; Tue, 20 Feb 2024 11:27:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1708457257; cv=none; d=google.com; s=arc-20160816; b=Oin8U2Dc5Vzdv6iIfI7XFEdCSXwXnDZQ9J6EifxADN8+fpkBU+zKx4YtM1MW9ZiEuv RJbGOhHvjI9EiIg93cakLWQmc/HQ2vF6c7juLfAtPJEGkCfSKLgGTYY9q9YgbqHgGDaP MqPLDp+qlRjDO7iu0cA/lvOce0VVJwFNia5hUbzSONRPh021jd0QwGWXjP53ngxq8WhG wThaFw0obx7otwIex4EEfZvH8X0NWYWm58bRg5L+nbmK3dY2AUaJhCj8Gas5rVqj0+XK ODTyHOLVOQnjJ7WDWCdzwXwGOPl7BmKhOh6sRif2c2hHLJtKpJRL4oTwy4GjpkGh86Ye 7pFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2hUt/YzOZmeP2AC1y1qRNyEeuFDCyV/aUnZ8Viy/DjY=; fh=gWdwvapFCBy64EEWQ3+1o3ppMDrs/UbMYMOdTfatJbY=; b=HLjjivEif2/bfc+rWMUd42XtvfSRjDonjZXT7ngU//axMHWUw8cUYjK979ymRvyTlT oJGESLjEielcYfvtFUvKOrNPoP2exWxPU2xH8Gl89pBsWEWic5KAhByosnrEjB0iplYN l3XDpgjhLC9S6eIYz9PioVTzq1H3DwY/HzV1iHGoN/DkYNTgxlIiw6Ye6q4s9W74Llzt XVVHpLhSuuLjkGVRJmNxx472Ham+uZc8YiIWU3dv+glMk6uzzjALUuAqXdrf34We77VB U4lgLEWwrU1oWCMQ2ZddFgXq0kDi8/CTOrjL+IExIUkrENaHqiuHBznp9aCZ/fUn6odf oSUw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OTkJS3+M; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.23.7]) by smtp.gmail.com with ESMTPSA id m8-20020a05600c4f4800b00411fb769583sm15737715wmq.27.2024.02.20.11.26.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 20 Feb 2024 11:26:40 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Alex_Benn=C3=A9e?= , Mark Cave-Ayland , Bernhard Beschow , Richard Henderson , Markus Armbruster , Alexander Graf , Anton Johansson , Paolo Bonzini , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 2/2] hw/alpha/typhoon: Set CPU IRQs using QDev API Date: Tue, 20 Feb 2024 20:26:25 +0100 Message-ID: <20240220192625.17944-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240220192625.17944-1-philmd@linaro.org> References: <20240220192625.17944-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=philmd@linaro.org; helo=mail-lj1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Keep a reference of CPU IRQs in the TyphoonCchip state. Resolve them once in typhoon_init(), and access them with the qemu_irq API. Signed-off-by: Philippe Mathieu-Daudé --- hw/alpha/typhoon.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index e8711ae16a..f038b6f000 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -26,6 +26,8 @@ typedef struct TyphoonCchip { uint64_t dim[4]; uint32_t iic[4]; AlphaCPU *cpu[4]; + qemu_irq cpu_tmr[4]; + qemu_irq cpu_smp[4]; } TyphoonCchip; typedef struct TyphoonWindow { @@ -343,17 +345,16 @@ static MemTxResult cchip_write(void *opaque, hwaddr addr, for (i = 0; i < 4; ++i) { AlphaCPU *cpu = s->cchip.cpu[i]; if (cpu != NULL) { - CPUState *cs = CPU(cpu); /* IPI can be either cleared or set by the write. */ if (newval & (1 << (i + 8))) { - cpu_interrupt(cs, CPU_INTERRUPT_SMP); + qemu_irq_raise(s->cchip.cpu_smp[i]); } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_SMP); + qemu_irq_lower(s->cchip.cpu_smp[i]); } /* ITI can only be cleared by the write. */ if ((newval & (1 << (i + 4))) == 0) { - cpu_reset_interrupt(cs, CPU_INTERRUPT_TIMER); + qemu_irq_lower(s->cchip.cpu_tmr[i]); } } } @@ -802,7 +803,7 @@ static void typhoon_set_timer_irq(void *opaque, int irq, int level) /* Set the ITI bit for this cpu. */ s->cchip.misc |= 1 << (i + 4); /* And signal the interrupt. */ - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_TIMER); + qemu_irq_raise(s->cchip.cpu_tmr[i]); } } } @@ -815,7 +816,7 @@ static void typhoon_alarm_timer(void *opaque) /* Set the ITI bit for this cpu. */ s->cchip.misc |= 1 << (cpu + 4); - cpu_interrupt(CPU(s->cchip.cpu[cpu]), CPU_INTERRUPT_TIMER); + qemu_irq_raise(s->cchip.cpu_tmr[cpu]); } PCIBus *typhoon_init(MemoryRegion *ram, qemu_irq *p_isa_irq, @@ -845,6 +846,8 @@ PCIBus *typhoon_init(MemoryRegion *ram, qemu_irq *p_isa_irq, cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, typhoon_alarm_timer, (void *)((uintptr_t)s + i)); + s->cchip.cpu_tmr[i] = qdev_get_gpio_in_named(DEVICE(cpu), "TMR", 0); + s->cchip.cpu_smp[i] = qdev_get_gpio_in_named(DEVICE(cpu), "SMP", 0); } }