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[176.184.23.7]) by smtp.gmail.com with ESMTPSA id s10-20020a05600c044a00b004122fbf9253sm14710257wmb.39.2024.02.20.07.08.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 20 Feb 2024 07:08:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Markus Armbruster , qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Christian Borntraeger , =?utf-8?q?Philippe_Mathi?= =?utf-8?q?eu-Daud=C3=A9?= Subject: [PATCH 1/4] hw/nmi: Use object_child_foreach_recursive() in nmi_children() Date: Tue, 20 Feb 2024 16:08:30 +0100 Message-ID: <20240220150833.13674-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240220150833.13674-1-philmd@linaro.org> References: <20240220150833.13674-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace object_child_foreach() and recursion by a single object_child_foreach_recursive() call. Propagate the returned value so callers can check it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/core/nmi.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/hw/core/nmi.c b/hw/core/nmi.c index a7bce8a04a..f5220111c1 100644 --- a/hw/core/nmi.c +++ b/hw/core/nmi.c @@ -31,8 +31,6 @@ struct do_nmi_s { bool handled; }; -static void nmi_children(Object *o, struct do_nmi_s *ns); - static int do_nmi(Object *o, void *opaque) { struct do_nmi_s *ns = opaque; @@ -47,14 +45,13 @@ static int do_nmi(Object *o, void *opaque) return -1; } } - nmi_children(o, ns); return 0; } -static void nmi_children(Object *o, struct do_nmi_s *ns) +static int nmi_children(Object *o, struct do_nmi_s *ns) { - object_child_foreach(o, do_nmi, ns); + return object_child_foreach_recursive(o, do_nmi, ns); } void nmi_monitor_handle(int cpu_index, Error **errp) @@ -65,10 +62,9 @@ void nmi_monitor_handle(int cpu_index, Error **errp) .handled = false }; - nmi_children(object_get_root(), &ns); - if (ns.handled) { + if (nmi_children(object_get_root(), &ns)) { error_propagate(errp, ns.err); - } else { + } else if (!ns.handled) { error_setg(errp, "machine does not provide NMIs"); } } From patchwork Tue Feb 20 15:08:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 774267 Delivered-To: patch@linaro.org Received: by 2002:a5d:4943:0:b0:33b:4db1:f5b3 with SMTP id r3csp1699787wrs; Tue, 20 Feb 2024 07:09:39 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWJ7iziIMbx1qpBX5XqCbEKkPIwWYP5pgCd/5SoTA0nNn7n4oakKnqOnmzXBV3y3wl4O0PdeP5GRa81ZVlHohgU X-Google-Smtp-Source: AGHT+IH1SxT8QPjUy5XA4IGKlh0Q+LosNFktj0dvDctss0fwOzROlioPEQhY+j+HRB2gJxnqavoA X-Received: by 2002:a05:622a:1196:b0:42e:1f86:3910 with SMTP id m22-20020a05622a119600b0042e1f863910mr4618785qtk.62.1708441778824; Tue, 20 Feb 2024 07:09:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1708441778; cv=none; d=google.com; s=arc-20160816; b=v+hpP8O1oJ/RczBMnP+243hhkZLdcl2hiRSuelA/ASP3a+RouzFm2YhAl/LW5xoBpO HchZamsTwO8PzEH1Ho05hp34I5cS6UkUnGWPj58gSW+YMU17h34i70VFpq9AlrkkJc7p BsOtr0ReUKT4ZSZX+6zbcUjDV5l8zXQQrISpeu7a+mTKx9xGsfe20C4JEs8Z1txxnrsW QX8WvCEEW3liglhORNog26oSYN6tsGZl+HqQarQwRBGXi0HnMTClr9KSRnN1Hr0ffV6Y ces5lvuOi2SoNhzaB3b5f2lNN67qUc55lKqDy/iYYZT5CTl0zXpCFuDLFpe8VjIqeGSv u1mQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9BjoHKgBAqJhVWzvihYewG3Mo1EyFTHucbJxjZyHAzY=; fh=mb86JNre3oQjGuH95DPd3qgDTY1GRs15m6ZKblGCJhs=; b=MmeVPaHnOkTdOA6T+RzB1dACU0zuQ1vjTMBoomkyrVDPNj7jg8ovvmk2L+kNyTbcdp W+buET5ET5rTXWl2B5IDGO2TIaD2HduAIowbkTY09xK26+NNgVyX10CHnHnscwYV6RC9 NKpND3pt21sHbdugMJ/5GYfM+QxEJS8tZBzZNU6ieitzTHKM2dvBJ29oB8NTpy8BHOfS ujDGD6GoqdTwaRfRHbRG2EwddB+MXCWcCc76NRbUN5BUrN3ivbmtnn76j0GTMAi4axKB Z55L8YscGT6CezpOwWyR1CVsP8Nx9mnVTnhdCwmwddNCCRezjA6TkLs5EGTNtV926DVu rHDA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AF+XmJU8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.23.7]) by smtp.gmail.com with ESMTPSA id 14-20020a056000154e00b0033d10bd6612sm14090980wry.81.2024.02.20.07.08.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 20 Feb 2024 07:08:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Markus Armbruster , qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Christian Borntraeger , =?utf-8?q?Philippe_Mathi?= =?utf-8?q?eu-Daud=C3=A9?= , "Dr. David Alan Gilbert" , Richard Henderson , David Hildenbrand , Ilya Leoshkevich , Halil Pasic , Eric Farman , Eric Blake , Paolo Bonzini Subject: [PATCH 2/4] hw/s390x/virtio-ccw: Always deliver NMI to first CPU Date: Tue, 20 Feb 2024 16:08:31 +0100 Message-ID: <20240220150833.13674-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240220150833.13674-1-philmd@linaro.org> References: <20240220150833.13674-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We can trigger NMI from HMP or QMP. QEMU maps the NMI to the s390x per-CPU 'RESTART' interrupt. Linux guests usually setup this interrupt to trigger kdump or crash. Such crashdump can be triggered in QEMU by HMP "nmi" or QMP "inject-nmi" commands. Using QMP, since we can not select a particular CPU, the first CPU is used (CPU#0). See the documentation from commit 795dc6e4 ("watchdog: Add new Virtual Watchdog action INJECT-NMI"): @inject-nmi: a non-maskable interrupt is injected into the first VCPU (all VCPUS on x86) (since 2.4) While we can select a particular CPU on HMP, the guest behavior is expected to be the same if using CPU #N or CPU #0. Since always using CPU#0 simplifies API maintainance, update s390_nmi() to deliver NMI to the first CPU. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: David Hildenbrand --- qapi/run-state.json | 5 +++-- hw/s390x/s390-virtio-ccw.c | 4 +--- hmp-commands.hx | 2 +- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/qapi/run-state.json b/qapi/run-state.json index 08bc99cb85..a2542f1a50 100644 --- a/qapi/run-state.json +++ b/qapi/run-state.json @@ -320,8 +320,9 @@ # # @none: nothing is done # -# @inject-nmi: a non-maskable interrupt is injected into the first -# VCPU (all VCPUS on x86) (since 2.4) +# @inject-nmi: a non-maskable interrupt is injected (architecture +# specific: on s390x only the first vCPU receive the NMI, on +# other architectures all vCPUs receive it). (since 2.4) # # Since: 2.1 ## diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 62804cc228..ba1fa6472f 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -605,9 +605,7 @@ static HotplugHandler *s390_get_hotplug_handler(MachineState *machine, static void s390_nmi(NMIState *n, int cpu_index, Error **errp) { - CPUState *cs = qemu_get_cpu(cpu_index); - - s390_cpu_restart(S390_CPU(cs)); + s390_cpu_restart(S390_CPU(first_cpu)); } static ram_addr_t s390_fixup_ram_size(ram_addr_t sz) diff --git a/hmp-commands.hx b/hmp-commands.hx index 17b5ea839d..2b01bb5926 100644 --- a/hmp-commands.hx +++ b/hmp-commands.hx @@ -851,7 +851,7 @@ ERST }, SRST ``nmi`` *cpu* - Inject an NMI on the default CPU (x86/s390) or all CPUs (ppc64). + Inject an NMI. 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[176.184.23.7]) by smtp.gmail.com with ESMTPSA id ay5-20020a5d6f05000000b0033d1ef15821sm13635990wrb.25.2024.02.20.07.08.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 20 Feb 2024 07:08:55 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Markus Armbruster , qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Christian Borntraeger , =?utf-8?q?Philippe_Mathi?= =?utf-8?q?eu-Daud=C3=A9?= , Richard Henderson , Helge Deller , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?C=C3=A9dric_Le_?= =?utf-8?q?Goater?= , Nicholas Piggin , =?utf-8?b?RnLDqWTDqXJpYyBCYXJyYXQ=?= , Daniel Henrique Barboza , David Gibson , Harsh Prateek Bora , Halil Pasic , Eric Farman , David Hildenbrand , Ilya Leoshkevich Subject: [PATCH 3/4] hw/nmi: Remove @cpu_index argument from NMIClass::nmi_handler() Date: Tue, 20 Feb 2024 16:08:32 +0100 Message-ID: <20240220150833.13674-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240220150833.13674-1-philmd@linaro.org> References: <20240220150833.13674-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::232; envelope-from=philmd@linaro.org; helo=mail-lj1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Only s390x was using the 'cpu_index' argument, but since the previous commit it isn't anymore (it use the first cpu). Since this argument is now completely unused, remove it. Have the callback return a boolean indicating failure. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/nmi.h | 11 ++++++++++- hw/core/nmi.c | 3 +-- hw/hppa/machine.c | 8 +++++--- hw/i386/x86.c | 7 ++++--- hw/intc/m68k_irqc.c | 6 ++++-- hw/m68k/q800-glue.c | 6 ++++-- hw/misc/macio/gpio.c | 6 ++++-- hw/ppc/pnv.c | 6 ++++-- hw/ppc/spapr.c | 6 ++++-- hw/s390x/s390-virtio-ccw.c | 6 ++++-- 10 files changed, 44 insertions(+), 21 deletions(-) diff --git a/include/hw/nmi.h b/include/hw/nmi.h index fff41bebc6..c70db941c9 100644 --- a/include/hw/nmi.h +++ b/include/hw/nmi.h @@ -37,7 +37,16 @@ typedef struct NMIState NMIState; struct NMIClass { InterfaceClass parent_class; - void (*nmi_monitor_handler)(NMIState *n, int cpu_index, Error **errp); + /** + * nmi_handler: Callback to handle NMI notifications. + * + * @n: Class #NMIState state + * @errp: pointer to error object + * + * On success, return %true. + * On failure, store an error through @errp and return %false. + */ + bool (*nmi_handler)(NMIState *n, Error **errp); }; void nmi_monitor_handle(int cpu_index, Error **errp); diff --git a/hw/core/nmi.c b/hw/core/nmi.c index f5220111c1..409164d445 100644 --- a/hw/core/nmi.c +++ b/hw/core/nmi.c @@ -40,8 +40,7 @@ static int do_nmi(Object *o, void *opaque) NMIClass *nc = NMI_GET_CLASS(n); ns->handled = true; - nc->nmi_monitor_handler(n, ns->cpu_index, &ns->err); - if (ns->err) { + if (!nc->nmi_handler(n, &ns->err)) { return -1; } } diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 5fcaf5884b..75b61a0683 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -673,13 +673,15 @@ static void hppa_machine_reset(MachineState *ms, ShutdownCause reason) cpu[0]->env.gr[19] = FW_CFG_IO_BASE; } -static void hppa_nmi(NMIState *n, int cpu_index, Error **errp) +static bool hppa_nmi(NMIState *n, Error **errp) { CPUState *cs; CPU_FOREACH(cs) { cpu_interrupt(cs, CPU_INTERRUPT_NMI); } + + return true; } static void HP_B160L_machine_init_class_init(ObjectClass *oc, void *data) @@ -705,7 +707,7 @@ static void HP_B160L_machine_init_class_init(ObjectClass *oc, void *data) mc->default_ram_id = "ram"; mc->default_nic = "tulip"; - nc->nmi_monitor_handler = hppa_nmi; + nc->nmi_handler = hppa_nmi; } static const TypeInfo HP_B160L_machine_init_typeinfo = { @@ -741,7 +743,7 @@ static void HP_C3700_machine_init_class_init(ObjectClass *oc, void *data) mc->default_ram_id = "ram"; mc->default_nic = "tulip"; - nc->nmi_monitor_handler = hppa_nmi; + nc->nmi_handler = hppa_nmi; } static const TypeInfo HP_C3700_machine_init_typeinfo = { diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 684dce90e9..0d756c4857 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -512,9 +512,8 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms) return ms->possible_cpus; } -static void x86_nmi(NMIState *n, int cpu_index, Error **errp) +static bool x86_nmi(NMIState *n, Error **errp) { - /* cpu index isn't used */ CPUState *cs; CPU_FOREACH(cs) { @@ -526,6 +525,8 @@ static void x86_nmi(NMIState *n, int cpu_index, Error **errp) cpu_interrupt(cs, CPU_INTERRUPT_NMI); } } + + return true; } static long get_file_size(FILE *f) @@ -1416,7 +1417,7 @@ static void x86_machine_class_init(ObjectClass *oc, void *data) mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; x86mc->save_tsc_khz = true; x86mc->fwcfg_dma_enabled = true; - nc->nmi_monitor_handler = x86_nmi; + nc->nmi_handler = x86_nmi; object_class_property_add(oc, X86_MACHINE_SMM, "OnOffAuto", x86_machine_get_smm, x86_machine_set_smm, diff --git a/hw/intc/m68k_irqc.c b/hw/intc/m68k_irqc.c index 4b11fb9f72..acc9348218 100644 --- a/hw/intc/m68k_irqc.c +++ b/hw/intc/m68k_irqc.c @@ -71,9 +71,11 @@ static void m68k_irqc_instance_init(Object *obj) qdev_init_gpio_in(DEVICE(obj), m68k_set_irq, M68K_IRQC_LEVEL_NUM); } -static void m68k_nmi(NMIState *n, int cpu_index, Error **errp) +static bool m68k_nmi(NMIState *n, Error **errp) { m68k_set_irq(n, M68K_IRQC_LEVEL_7, 1); + + return true; } static const VMStateDescription vmstate_m68k_irqc = { @@ -99,7 +101,7 @@ static void m68k_irqc_class_init(ObjectClass *oc, void *data) InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(oc); device_class_set_props(dc, m68k_irqc_properties); - nc->nmi_monitor_handler = m68k_nmi; + nc->nmi_handler = m68k_nmi; dc->reset = m68k_irqc_reset; dc->vmsd = &vmstate_m68k_irqc; ic->get_statistics = m68k_irqc_get_statistics; diff --git a/hw/m68k/q800-glue.c b/hw/m68k/q800-glue.c index b5a7713863..f92bd5064a 100644 --- a/hw/m68k/q800-glue.c +++ b/hw/m68k/q800-glue.c @@ -159,13 +159,15 @@ static void glue_auxmode_set_irq(void *opaque, int irq, int level) s->auxmode = level; } -static void glue_nmi(NMIState *n, int cpu_index, Error **errp) +static bool glue_nmi(NMIState *n, Error **errp) { GLUEState *s = GLUE(n); /* Hold NMI active for 100ms */ GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 1); timer_mod(s->nmi_release, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100); + + return true; } static void glue_nmi_release(void *opaque) @@ -238,7 +240,7 @@ static void glue_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_glue; device_class_set_props(dc, glue_properties); rc->phases.hold = glue_reset_hold; - nc->nmi_monitor_handler = glue_nmi; + nc->nmi_handler = glue_nmi; } static const TypeInfo glue_info_types[] = { diff --git a/hw/misc/macio/gpio.c b/hw/misc/macio/gpio.c index 549563747d..9ac93d9ed5 100644 --- a/hw/misc/macio/gpio.c +++ b/hw/misc/macio/gpio.c @@ -183,10 +183,12 @@ static void macio_gpio_reset(DeviceState *dev) macio_set_gpio(s, 1, true); } -static void macio_gpio_nmi(NMIState *n, int cpu_index, Error **errp) +static bool macio_gpio_nmi(NMIState *n, Error **errp) { macio_set_gpio(MACIO_GPIO(n), 9, true); macio_set_gpio(MACIO_GPIO(n), 9, false); + + return true; } static void macio_gpio_class_init(ObjectClass *oc, void *data) @@ -196,7 +198,7 @@ static void macio_gpio_class_init(ObjectClass *oc, void *data) dc->reset = macio_gpio_reset; dc->vmsd = &vmstate_macio_gpio; - nc->nmi_monitor_handler = macio_gpio_nmi; + nc->nmi_handler = macio_gpio_nmi; } static const TypeInfo macio_gpio_init_info = { diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0297871bdd..f572f8d0ce 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -2321,13 +2321,15 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) } } -static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) +static bool pnv_nmi(NMIState *n, Error **errp) { CPUState *cs; CPU_FOREACH(cs) { async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); } + + return true; } static void pnv_machine_class_init(ObjectClass *oc, void *data) @@ -2351,7 +2353,7 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data) mc->default_ram_size = 1 * GiB; mc->default_ram_id = "pnv.ram"; ispc->print_info = pnv_pic_print_info; - nc->nmi_monitor_handler = pnv_nmi; + nc->nmi_handler = pnv_nmi; object_class_property_add_bool(oc, "hb-mode", pnv_machine_get_hb, pnv_machine_set_hb); diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 0d72d286d8..7327bf3429 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3505,13 +3505,15 @@ void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) } } -static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) +static bool spapr_nmi(NMIState *n, Error **errp) { CPUState *cs; CPU_FOREACH(cs) { async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); } + + return true; } int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, @@ -4672,7 +4674,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) mc->nvdimm_supported = true; smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; fwc->get_dev_path = spapr_get_fw_dev_path; - nc->nmi_monitor_handler = spapr_nmi; + nc->nmi_handler = spapr_nmi; smc->phb_placement = spapr_phb_placement; vhc->cpu_in_nested = spapr_cpu_in_nested; vhc->deliver_hv_excp = spapr_exit_nested; diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index ba1fa6472f..817f414767 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -603,9 +603,11 @@ static HotplugHandler *s390_get_hotplug_handler(MachineState *machine, return NULL; } -static void s390_nmi(NMIState *n, int cpu_index, Error **errp) +static bool s390_nmi(NMIState *n, Error **errp) { s390_cpu_restart(S390_CPU(first_cpu)); + + return true; } static ram_addr_t s390_fixup_ram_size(ram_addr_t sz) @@ -774,7 +776,7 @@ static void ccw_machine_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = S390_CPU_TYPE_NAME("qemu"); hc->plug = s390_machine_device_plug; hc->unplug_request = s390_machine_device_unplug_request; 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[176.184.23.7]) by smtp.gmail.com with ESMTPSA id r13-20020a05600c35cd00b00410c7912c6esm15202117wmq.14.2024.02.20.07.09.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 20 Feb 2024 07:09:01 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Markus Armbruster , qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Christian Borntraeger , =?utf-8?q?Philippe_Mathi?= =?utf-8?q?eu-Daud=C3=A9?= , Corey Minyard , Paolo Bonzini , Richard Henderson Subject: [PATCH 4/4] hw/nmi: Remove @cpu_index argument from nmi_trigger() Date: Tue, 20 Feb 2024 16:08:33 +0100 Message-ID: <20240220150833.13674-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240220150833.13674-1-philmd@linaro.org> References: <20240220150833.13674-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org nmi_monitor_handle() is not related to the monitor, rename it as nmi_trigger(). Return boolean value indicating success / failure. The 'cpu_index' argument is not used, remove it. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/nmi.h | 13 ++++++++++++- hw/core/nmi.c | 9 ++++----- hw/ipmi/ipmi.c | 3 +-- hw/watchdog/watchdog.c | 2 +- system/cpus.c | 2 +- 5 files changed, 19 insertions(+), 10 deletions(-) diff --git a/include/hw/nmi.h b/include/hw/nmi.h index c70db941c9..32b27067f2 100644 --- a/include/hw/nmi.h +++ b/include/hw/nmi.h @@ -49,6 +49,17 @@ struct NMIClass { bool (*nmi_handler)(NMIState *n, Error **errp); }; -void nmi_monitor_handle(int cpu_index, Error **errp); +/** + * nmi_trigger: Trigger a NMI. + * + * @errp: pointer to error object + * + * Iterate over all objects implementing the TYPE_NMI interface + * and deliver NMI to them. + * + * On success, return %true. + * On failure, store an error through @errp and return %false. + */ +bool nmi_trigger(Error **errp); #endif /* NMI_H */ diff --git a/hw/core/nmi.c b/hw/core/nmi.c index 409164d445..a740f39c98 100644 --- a/hw/core/nmi.c +++ b/hw/core/nmi.c @@ -22,11 +22,8 @@ #include "qemu/osdep.h" #include "hw/nmi.h" #include "qapi/error.h" -#include "qemu/module.h" -#include "monitor/monitor.h" struct do_nmi_s { - int cpu_index; Error *err; bool handled; }; @@ -53,19 +50,21 @@ static int nmi_children(Object *o, struct do_nmi_s *ns) return object_child_foreach_recursive(o, do_nmi, ns); } -void nmi_monitor_handle(int cpu_index, Error **errp) +bool nmi_trigger(Error **errp) { struct do_nmi_s ns = { - .cpu_index = cpu_index, .err = NULL, .handled = false }; if (nmi_children(object_get_root(), &ns)) { error_propagate(errp, ns.err); + return false; } else if (!ns.handled) { error_setg(errp, "machine does not provide NMIs"); + return false; } + return true; } static const TypeInfo nmi_info = { diff --git a/hw/ipmi/ipmi.c b/hw/ipmi/ipmi.c index bbb07b151e..45e36a7492 100644 --- a/hw/ipmi/ipmi.c +++ b/hw/ipmi/ipmi.c @@ -59,8 +59,7 @@ static int ipmi_do_hw_op(IPMIInterface *s, enum ipmi_op op, int checkonly) if (checkonly) { return 0; } - /* We don't care what CPU we use. */ - nmi_monitor_handle(0, NULL); + nmi_trigger(NULL); return 0; case IPMI_SHUTDOWN_VIA_ACPI_OVERTEMP: diff --git a/hw/watchdog/watchdog.c b/hw/watchdog/watchdog.c index 955046161b..d324c761aa 100644 --- a/hw/watchdog/watchdog.c +++ b/hw/watchdog/watchdog.c @@ -81,7 +81,7 @@ void watchdog_perform_action(void) case WATCHDOG_ACTION_INJECT_NMI: qapi_event_send_watchdog(WATCHDOG_ACTION_INJECT_NMI); - nmi_monitor_handle(0, NULL); + nmi_trigger(NULL); break; default: diff --git a/system/cpus.c b/system/cpus.c index 68d161d96b..f11ee3d404 100644 --- a/system/cpus.c +++ b/system/cpus.c @@ -856,6 +856,6 @@ exit: void qmp_inject_nmi(Error **errp) { - nmi_monitor_handle(monitor_get_cpu_index(monitor_cur()), errp); + nmi_trigger(errp); }