From patchwork Mon Feb 19 16:38:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 774091 Delivered-To: patch@linaro.org Received: by 2002:a5d:4943:0:b0:33b:4db1:f5b3 with SMTP id r3csp1252466wrs; Mon, 19 Feb 2024 08:39:42 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU/wm2mnPcMJlpoDboFTcU3a8Xi58AYnMeYUbpBUSr0KcbxeduV53Dj2wjcELwB9NZ2Dc06F5nJzvSbtX5AuM4W X-Google-Smtp-Source: AGHT+IE8aR+oR4ehDp6XQFDkKqO0LxJFQwA5AubCegyPvd2VsA8SdWAnYKcZghsQxI92x+KilFDi X-Received: by 2002:a05:6830:1096:b0:6e2:daea:1b35 with SMTP id y22-20020a056830109600b006e2daea1b35mr12795669oto.35.1708360782132; Mon, 19 Feb 2024 08:39:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1708360782; cv=none; d=google.com; s=arc-20160816; b=e0YkcfGaLyNuwx78QaNacHqR3hFgpBmn/V6GWO3gVEY184XxSu8InyGL1w1ULsmEcF MZtnBJsv9zNORnLONZ0lAavrqxFOxBwTH7IpT66UPutweWQikiXbfpxNtGnBUyoNHKum iQ/JWv4NG/LZi7zQyunZir6PcoAxlCHFXcDYUDRyVkW+320d5hTybp2z96zUOF3dT/4p ZXGRnyx/rkn9tHnEE4IsZuPbzH55cx+JebDCQ+L8k32m3DXs30gU3tjeYzmNQLIkhLnn c5nFOnVzSQSTJGGdDgqk48LpGleqFYBYadN5u0t3FWYty0drbaiSClCB/OAEX/5OHt5q CJBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7g5vOQ8eZi29yIHTGoT9HD5BPvRL3ou+PdzCGqII3v4=; fh=GFH0+Nfz+rN0IvTHf71Tn8mJWCh907g2jnPgVcMG7yo=; b=MydgHCLvVWkhSN4WZJhNv3stSEW0je4hxy/ouYuyVWEVcglSD/+jeRCjQ9kzDbWKvw 6ZSvhDC/DZwNOH0IHHf4BIjYR6qNENzDNX2sCOgQJ1YoFidanTULvsh+c27fORgNtqUL rNu5tfGTcp8lnp9jsnw+86hLAWBdZoV2iGn65GM0uuECki/YXaI3Yh14aM/0KiV7YrCm mzcWJduN4wNH0ImiWR801eDk9dfw43It5wIeABPT2rDr4ZkNkLKDNb1dOyXy8k1YbC+r 2tPSwpOXbB8kJaJ77v1Kl7laGHnevQEu8JLePCVxIcTbQh+bpE6shiwv/eEOZIFc1Psd gISw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hsZFgLCo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o7-20020ac86987000000b0042dfc34b70esi5104345qtq.528.2024.02.19.08.39.41 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2024 08:39:42 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hsZFgLCo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rc6ff-0001Hw-QO; Mon, 19 Feb 2024 11:39:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rc6fe-0001Hb-CW for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:10 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rc6fc-0002v4-PK for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:10 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-41261233e61so8603045e9.0 for ; Mon, 19 Feb 2024 08:39:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708360747; x=1708965547; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7g5vOQ8eZi29yIHTGoT9HD5BPvRL3ou+PdzCGqII3v4=; b=hsZFgLCoKCha+7NLdqzfzboAIKu1uU3YjkXWtKEKoW3f6NtLi4vT+318mEqcQoxdsH RihQlZXdYwmrQi1+rPrEjVHGpS2YocHcGF/IBo1N/bIZ5k0Voa60EJG43kctXMCuNvyG f1Y0u2D9nGbmNTWRekWTwEgOtbZIwbAZaVoMx9bva3XQJuuVR5Zw5KhvIYLokTZ1+9DA EVIJBVnjCB1bozfgD+Tu68oDIAWnvBttvUkVXq+TbxHSxFU1x7kva4Rcs3xgvfMx7YBZ aKWDjCPgi3v5x6b89IxRiP77IWofVpxliJo8ZgfzmA1388bZAFdLUpMpfEFG7JMrcZiv WZsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708360747; x=1708965547; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7g5vOQ8eZi29yIHTGoT9HD5BPvRL3ou+PdzCGqII3v4=; b=j7V1hHCTJLtNbzNkK7oI4rOvdxo10PmFKkHvmBqcI27wt07YXfDRH2I3bU3fPLTTZ5 I287YdpURCG5PZ5BPAadK0grGI4kNlUCkc13C+8Y9VN0uAdipkJL7vWS9I+2ynVHRdNw PmI+voYF325CDiEh4LzU6I/LwMbwSbTFp5GnMPuazqqFmZTEYHNa93hj4R3HzzXfcRWZ VyiiK1wLCGUbs+YULdf9wXq8gD2IrOMMC/Fh5uI2JVmor+rCvtDW2WGgKy3cVumy5VpX /oomGbPleXG0VpBJY6Ais93wDev8n9EK9CXEyuEQhEMaxsxdPAzX7ytsM3DfIQXZ9WH3 u6dA== X-Gm-Message-State: AOJu0YzWuTwDZyE2dRHVGvkJz20G0zrg/t9QFsK7Olt6moOrp3q1dsq7 WH2bgvoMQDF37AsnjJPzxGz8Bt7CXJjmIvao5tbqFQrVCl3qSHHv8chOsKxm97UlMf2EUVUBa5d D X-Received: by 2002:a05:600c:19c7:b0:412:5296:9737 with SMTP id u7-20020a05600c19c700b0041252969737mr8340793wmq.12.1708360746815; Mon, 19 Feb 2024 08:39:06 -0800 (PST) Received: from m1x-phil.lan ([176.176.181.220]) by smtp.gmail.com with ESMTPSA id s6-20020a05600c45c600b00412696bd7d9sm1956339wmo.41.2024.02.19.08.39.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 19 Feb 2024 08:39:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 01/14] MAINTAINERS: Add 'ICH9 South Bridge' section Date: Mon, 19 Feb 2024 17:38:41 +0100 Message-ID: <20240219163855.87326-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Extract 'ICH9 South Bridge' from the 'PC' section. Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 7d61fb9319..1b210c5cc1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1808,12 +1808,7 @@ F: include/hw/pci-host/i440fx.h F: include/hw/pci-host/q35.h F: include/hw/pci-host/pam.h F: hw/isa/piix.c -F: hw/isa/lpc_ich9.c -F: hw/i2c/smbus_ich9.c F: hw/acpi/piix4.c -F: hw/acpi/ich9*.c -F: include/hw/acpi/ich9*.h -F: include/hw/southbridge/ich9.h F: include/hw/southbridge/piix.h F: hw/isa/apm.c F: include/hw/isa/apm.h @@ -2606,6 +2601,16 @@ F: hw/display/edid* F: include/hw/display/edid.h F: qemu-edid.c +ICH9 South Bridge (82801i) +M: Michael S. Tsirkin +M: Marcel Apfelbaum +S: Supported +F: hw/acpi/ich9*.c +F: hw/i2c/smbus_ich9.c +F: hw/isa/lpc_ich9.c +F: include/hw/acpi/ich9*.h +F: include/hw/southbridge/ich9.h + PIIX4 South Bridge (i82371AB) M: Hervé Poussineau M: Philippe Mathieu-Daudé From patchwork Mon Feb 19 16:38:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 774104 Delivered-To: patch@linaro.org Received: by 2002:a5d:4943:0:b0:33b:4db1:f5b3 with SMTP id r3csp1253536wrs; Mon, 19 Feb 2024 08:42:00 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWkI0deMY76btTwW37SyK4jcgsimBexRuqhThW/r19bKxETtmzgveQyLJrZI3L1FzclLvmUEi9DEIGhKAul5bQn X-Google-Smtp-Source: AGHT+IGBxgL1uWOvzBNIBr6xIiXn8Art+3bTu1uhgmWnD6hdFf40GdxA7TBnreJmQFrqBhDNdDbh X-Received: by 2002:a37:c44b:0:b0:785:a111:bbe2 with SMTP id h11-20020a37c44b000000b00785a111bbe2mr14889129qkm.41.1708360784741; Mon, 19 Feb 2024 08:39:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1708360784; cv=none; d=google.com; s=arc-20160816; b=Ob/EGfzIMQGeRUJf10+xgzfwtADHszR5dOSo67i/lpTq6BTPmFXOXpTLV3z4bR2peu GQ0hXajuTikfmYeZLhSQ5mqctans7NO3byUfcBJjhjksnN7vVJvjsTPjBt1jeC6ei2E3 A7ArnXlg4oYDCsYlK/xE1lDQqD7CJMSotmIqUtiLpUWO607Vp2SSzhaZzkXpjjitxHGq qRGFr7YF3Y0E9pxYI7yoblMJcNrNTEZ8e8BUnooJ3vFnGtCYWv5vuKLDFU41c9arAhgs tYDkdLXtk49nvj6IUde4V7c1AeZykz+DCvUGaYtxSS1YhMjCyCepglyVfM/V17yMhpTo Or6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=g4FCzhBMxBMDZoobHoXe86blnQI4iLx/WEkq5NXhKrY=; fh=GFH0+Nfz+rN0IvTHf71Tn8mJWCh907g2jnPgVcMG7yo=; b=q4LbANB+XDvCLIscwoMXsqnZsJE1Xlwrkt38gtbBETtriI3bJN7kwIp+eHZK2s3W5E 4vHPd4KJaBWG0y4mS8CXiv7jRaIb2fLsj26kFyzAruYg2x+3tiTFdup+r8oNQFi/YtHL AS4NeC/cpaRs19lnbdRAOQphLTGYPYa/pa48kXNuxfromU+JV5QhZO5Wx4AnzYL9ifuJ g7CWZFABv4/f8yxN1RzK//mLEPoZ1ppK/jOxVrHULiGhtvEgZnZX+OSNFdKHtHJv+b3V txj9IezBH+LEqHDeY5mTHX5lBNs/2GEjlvUJ0ZMpUXTStY9/mFYbcRaa4zjCJFW6oxx5 KUNw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JnyXsnuI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id vu16-20020a05620a561000b00785da73ab98si6527317qkn.241.2024.02.19.08.39.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2024 08:39:44 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JnyXsnuI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rc6fv-0001SN-18; Mon, 19 Feb 2024 11:39:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rc6fs-0001RB-BK for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:24 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rc6fl-0002vv-Ve for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:23 -0500 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-33d38c9ca5bso898234f8f.2 for ; Mon, 19 Feb 2024 08:39:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708360754; x=1708965554; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g4FCzhBMxBMDZoobHoXe86blnQI4iLx/WEkq5NXhKrY=; b=JnyXsnuICmP5Jg8a/zmDVDVxQazwzX3Tv6u/RZpiIfm7eok2hFnOo5Q1kWJW0y6hxI TtjCSNJmnvfPNPTQqIk4UZvEkj6DqFoBM3AtIH+4e1rr2YUqbmJa5pO3HSsVEmwz107K oZZOuES1zVdRn2Gg5i9g7lHnY/GRy9i3b8Y8TFR0VDIHjbTNAAGLXydEkSqXUB2fuCUA jyAhuBskbiks4mOWPFmUA4W/8Ui/XAjhDem2eIo2YN0XZcSit0OWQT5OWcdAw8t4O6GL 30r9lZaOVSgoxicf+guv6jEOUg5Zsn0h79WzcKLjOVhZtMDuk1nTZnrIDqAQg1EsCQ+l ET/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708360754; x=1708965554; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g4FCzhBMxBMDZoobHoXe86blnQI4iLx/WEkq5NXhKrY=; b=rfM8Z7Har5IB2BG3hgKwzjH6JiMgt/SEJHumyRtT3c6fwbPIuj6YhfjVk4huVtsc1v x+cVwWtH9wnD8U4BdZkfHPr0qJm2sKDItGu0kwwhq9vwsOG5pYOqaKXNvYg0gbhrdt8d gOyThxvUp9r3YMSYQmpS1prQcxwsbvdPCODxP6uo2J1lf2OebXd2ZQwtk/AhhOBrZZuN dZp7NbCPyjjXVx94GrAvYP2Q45QLINeG+xp1rXh2RoXfttDXLZTpOAOkodP2DjtXaQaL pw87ZEhMScNUo3QcnrUYAe0DoQghcUjgxapUonrN1bptRF49+vLu2T9JzJOYFT1cdsMl bCCg== X-Gm-Message-State: AOJu0YzSTU5wJ7I0mZwLWT/mCqvHxH0jgivpQS+3tCRvSsPowXFv21Pi bTLDterpUmCFIIRNIPDZtNxqoa8sT0EcD1+O1Xka98ksmy4fLM1xW6QXJHYtvjQ+vhZz2p2R5X/ M X-Received: by 2002:a5d:5248:0:b0:33d:36e0:b9eb with SMTP id k8-20020a5d5248000000b0033d36e0b9ebmr3278810wrc.50.1708360754075; Mon, 19 Feb 2024 08:39:14 -0800 (PST) Received: from m1x-phil.lan ([176.176.181.220]) by smtp.gmail.com with ESMTPSA id i13-20020a5d55cd000000b0033b198efbedsm10733258wrw.15.2024.02.19.08.39.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 19 Feb 2024 08:39:13 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 02/14] hw/i386/q35: Add local 'lpc_obj' variable Date: Mon, 19 Feb 2024 17:38:42 +0100 Message-ID: <20240219163855.87326-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instead of casting OBJECT(lpc) multiple times, do it once in the new 'lpc_obj' variable. Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc_q35.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index a91f414922..621661a738 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -126,6 +126,7 @@ static void pc_q35_init(MachineState *machine) Object *phb; PCIBus *host_bus; PCIDevice *lpc; + Object *lpc_obj; DeviceState *lpc_dev; BusState *idebus[MAX_SATA_PORTS]; ISADevice *rtc_state; @@ -238,6 +239,7 @@ static void pc_q35_init(MachineState *machine) /* create ISA bus */ lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), TYPE_ICH9_LPC_DEVICE); + lpc_obj = OBJECT(lpc); lpc_dev = DEVICE(lpc); qdev_prop_set_bit(lpc_dev, "smm-enabled", x86_machine_is_smm_enabled(x86ms)); @@ -246,7 +248,7 @@ static void pc_q35_init(MachineState *machine) qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); } - rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc")); + rtc_state = ISA_DEVICE(object_resolve_path_component(lpc_obj, "rtc")); object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, TYPE_HOTPLUG_HANDLER, @@ -254,13 +256,13 @@ static void pc_q35_init(MachineState *machine) object_property_allow_set_link, OBJ_PROP_LINK_STRONG); object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, - OBJECT(lpc), &error_abort); + lpc_obj, &error_abort); - acpi_pcihp = object_property_get_bool(OBJECT(lpc), + acpi_pcihp = object_property_get_bool(lpc_obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, NULL); - keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc), + keep_pci_slot_hpc = object_property_get_bool(lpc_obj, "x-keep-pci-slot-hpc", NULL); From patchwork Mon Feb 19 16:38:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 774099 Delivered-To: patch@linaro.org Received: by 2002:a5d:4943:0:b0:33b:4db1:f5b3 with SMTP id r3csp1253044wrs; Mon, 19 Feb 2024 08:40:54 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUagKLRTvcUbzlERLPSuBLGFBhGAttMD8I1SOl7aJDvHfSJ3AkOnCQCXcKK0Hh3fJetTcxRi+j7CRpQhRR3fORe X-Google-Smtp-Source: AGHT+IHDFLnU4QkhY7R5F2SjKVVyNtT9iugKcLPjOXZgbK7aPZ23rpGMkLL01CSHZoCnedlFvsm7 X-Received: by 2002:a05:620a:91d:b0:787:3503:8aa3 with SMTP id v29-20020a05620a091d00b0078735038aa3mr15184194qkv.4.1708360854358; Mon, 19 Feb 2024 08:40:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1708360854; cv=none; d=google.com; s=arc-20160816; b=GBx3GSc65KEqbohA/ETBtWKniCfOzCZp0Nh8hwyyAuAqfhYdVqmtDg03+/rUZ6Q3w+ iKNPko6bAFmIx53px2mdNSaBdocCBo2tdSpE1fcOj4scnXwVhsObHIbunJ6+gRtbOTcC pIIUeOqnIdTv/+SSs9hPd9SFo8TtwTuNz+N3mkgoVZSKUaZAJeKmBq2YszRdzLmTSdCf M6SexZsBoYxMp1bOIFrGch1ER63gSsu6SLszkK37o3Nt1IQPoa1oECM6FhcYthCbfQBI 1mLllxVG01+gyZjXSU0ZZOqiY4vevUhl6OVNWN5uQjpec6Nm8gIw96lVGPemYXl4qe5M wZsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=CzsFl96TqsANx0Bu/9mPtcZl7XwvdqWDGq2/cLicoFE=; fh=GFH0+Nfz+rN0IvTHf71Tn8mJWCh907g2jnPgVcMG7yo=; b=ty/JkuR5LAoPiWegzyqMRKSf2V4kY7+mgvcUHsOEOZKuQA2JaO5nYTRaL2fVpbJC5t ATQB8+SWr9det7DiozJ8sEYq24dHxrmycWOG0p/G+eGsnUpRYZx5mQnnhG9kYnm90u1i 7vmchWStDpFyHh3F5XZwxO0ROgOvQtQq+QR0e3NmxLvWygDokRpN1K/FWueJfHeRqzOx h3gm3c/vW98F8e8GcI4A4w2NovNuIP0A6jBMa2NwJHa/otvitDrATlrO0YGMTmbeTwZ7 QWIeClV5aeuqY31B53NZyu82jW5TocoxvU8j3x1+/EgC5+m4CdRzAcba+egIfBuqcw+T IPaw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="vFS4/IPX"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b16-20020a05620a0cd000b00785d42ba348si6194408qkj.155.2024.02.19.08.40.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2024 08:40:54 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="vFS4/IPX"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rc6fu-0001Si-Io; Mon, 19 Feb 2024 11:39:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rc6ft-0001Rt-US for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:25 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rc6fs-0002wJ-8x for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:25 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-4125eabb8f4so16788645e9.3 for ; Mon, 19 Feb 2024 08:39:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708360761; x=1708965561; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CzsFl96TqsANx0Bu/9mPtcZl7XwvdqWDGq2/cLicoFE=; b=vFS4/IPXvaSfFTS+xWdLBrfxLQlwE8h4CaELCeC2+j/j2WmBkrZqY5V15fQt1fCeZ3 kLKaJas1OXmMbSVPZ7F3klZTvF90QLSFf4T1ZTJumWq3sYKx6SqYxr1gt5eQrzbDdROm /C60DouBYD4m0QkRCrEE52aSPJ0SO6qVvKoY7TLWApaMM529xHj7MZUuG9E6UNHZJBsC 6k1BthiGYdFXyj/EUASUWsG9vJnXEW8gy4saMlJf/B3Yy6QZ7tcWhFv18W0fJyKY98K4 4apan46gc26vo6rOfCBty8jRYsxVLyDgTOyw65AwNULQu8sMY4O1KYoqWlADHT+JmwHj Sl/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708360761; x=1708965561; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CzsFl96TqsANx0Bu/9mPtcZl7XwvdqWDGq2/cLicoFE=; b=xTGXwaaULvCzRZ6dlTt9PB/uvEtm8wIccD7ylZdkoDNH3DGazAGYp4SuVzaw2VDrja pltb/ecvgz9J+N9L2eYbykUJd9BznABcjC0iHoJilN3Ze7cg3hipWUDukh3y+dj0/59u AwBdjcNYdBBtts2WO6khWsUnlIb+m9EmQQ9c5HTm+3C1CU0H+N2gs/WK8eSsxdJlXnj/ odSSHA6l59XqnVttFCfMpH3hoBz6IS8LFFICLChiO2PeaHbDn/yWi0hCbolmciQBEgC3 qcC3q3CDFjoeYCCr05z+Lsy4EQFuDze2BwMda5oR2vxzXwp+FdvtbnzjQZK/B07nmkhE WTHw== X-Gm-Message-State: AOJu0YxiAq+S9kb//2GStXC8vTLwoOrhZoCyXco0FJMLgHKxY+LKrLo1 R6Pphh1wlACikQbHdBGa7n8qGOw/2oNK63aI724H4lH93AeDos37Dxoxi3sv/7ea/gRkh2zKngj e X-Received: by 2002:a05:600c:34c4:b0:412:6cb2:e1db with SMTP id d4-20020a05600c34c400b004126cb2e1dbmr132672wmq.0.1708360760860; Mon, 19 Feb 2024 08:39:20 -0800 (PST) Received: from m1x-phil.lan ([176.176.181.220]) by smtp.gmail.com with ESMTPSA id d2-20020adfef82000000b0033b75b39aebsm10845231wro.11.2024.02.19.08.39.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 19 Feb 2024 08:39:20 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 03/14] hw/acpi/ich9: Restrict definitions from 'hw/southbridge/ich9.h' Date: Mon, 19 Feb 2024 17:38:43 +0100 Message-ID: <20240219163855.87326-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Restrict ACPI definitions from "hw/southbridge/ich9.h" to the ACPI files where they are used. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/acpi/ich9.h | 15 +++++++++++++++ include/hw/southbridge/ich9.h | 18 ------------------ hw/acpi/ich9.c | 4 ++++ 3 files changed, 19 insertions(+), 18 deletions(-) diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h index 215de3c91f..3587a35c9f 100644 --- a/include/hw/acpi/ich9.h +++ b/include/hw/acpi/ich9.h @@ -91,4 +91,19 @@ void ich9_pm_device_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, bool ich9_pm_is_hotpluggable_bus(HotplugHandler *hotplug_dev, BusState *bus); void ich9_pm_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list); + +#define ICH9_PMIO_PM1_STS 0x00 +#define ICH9_PMIO_PM1_EN 0x02 +#define ICH9_PMIO_PM1_CNT 0x04 +#define ICH9_PMIO_PM1_TMR 0x08 +#define ICH9_PMIO_GPE0_STS 0x20 +#define ICH9_PMIO_GPE0_EN 0x28 +#define ICH9_PMIO_GPE0_LEN 16 +#define ICH9_PMIO_SMI_EN 0x30 +#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5) +#define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13) +#define ICH9_PMIO_SMI_STS 0x34 +#define ICH9_PMIO_TCO_RLD 0x60 +#define ICH9_PMIO_TCO_LEN 32 + #endif /* HW_ACPI_ICH9_H */ diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index fd01649d04..1ac4238f7e 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -183,24 +183,6 @@ struct ICH9LPCState { /* D31:F0 power management I/O registers offset from the address ICH9_LPC_PMBASE */ -/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */ -#define ICH9_PMIO_SIZE 128 -#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1) - -#define ICH9_PMIO_PM1_STS 0x00 -#define ICH9_PMIO_PM1_EN 0x02 -#define ICH9_PMIO_PM1_CNT 0x04 -#define ICH9_PMIO_PM1_TMR 0x08 -#define ICH9_PMIO_GPE0_STS 0x20 -#define ICH9_PMIO_GPE0_EN 0x28 -#define ICH9_PMIO_GPE0_LEN 16 -#define ICH9_PMIO_SMI_EN 0x30 -#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5) -#define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13) -#define ICH9_PMIO_SMI_STS 0x34 -#define ICH9_PMIO_TCO_RLD 0x60 -#define ICH9_PMIO_TCO_LEN 32 - /* FADT ACPI_ENABLE/ACPI_DISABLE */ #define ICH9_APM_ACPI_ENABLE 0x2 #define ICH9_APM_ACPI_DISABLE 0x3 diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index be375a8b9d..228ebc9a1e 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -49,6 +49,10 @@ do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0) #define ICH9_DEBUG(fmt, ...) do { } while (0) #endif +/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */ +#define ICH9_PMIO_SIZE 128 +#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1) + static void ich9_pm_update_sci_fn(ACPIREGS *regs) { ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs); From patchwork Mon Feb 19 16:38:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 774092 Delivered-To: patch@linaro.org Received: by 2002:a5d:4943:0:b0:33b:4db1:f5b3 with SMTP id r3csp1252637wrs; Mon, 19 Feb 2024 08:40:06 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUYydCQIoo0pISnW4oaIzyCPQNmJoGYD0x0lGSRKIg9qxfkZmzt0TyjlSCyK3a+HFFUab4oHwaLqD2jylKnOlgz X-Google-Smtp-Source: AGHT+IEq2gpEX/JEBRyXZg7q7V/omAyKB4TLSwpp50OhVu43/Yf+ADdK7C3n2+mJgJ4nmrQT22Sg X-Received: by 2002:a05:6102:1286:b0:470:4729:dbbb with SMTP id jc6-20020a056102128600b004704729dbbbmr3555692vsb.0.1708360806251; Mon, 19 Feb 2024 08:40:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1708360806; cv=none; d=google.com; s=arc-20160816; b=fOJ2cZQZiv0o1Rs397I0uLUt+uxdHRMCYeRnT+ShBpgOWv9LkHKnO4vsid59uHAXby Htoc6bkPfK6MLEhrsAsAx9UZfavRU0BrAruwXvpQvV+UjMAp6LeJmAKeuhsTGLu7ZRxH fW3KcpCo7+G/4NKwBELsH6k2JoV0X3sU03fL6SBDE0q+zrqdlFqvKHVqzryfJHQO9eI+ iApp8a95IVbiSUWZ3p9ARzAESHjs9030o39ViTod816vJ3Q9NZU8kCmc54xwCOn9E+Wn M4IuejvOHfhT7UH80vV1W3gJqwbGugk/rqygEtw3LUPnjvJvbYWDxelEJXZJv7GIfMWE zgsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MHN0WwPF0EH6RoLWLYyydVS2IwI6/kKCgvu+Hk831E8=; fh=GFH0+Nfz+rN0IvTHf71Tn8mJWCh907g2jnPgVcMG7yo=; b=r7OuJZLvE39v3Uzpo04FHHW8U0YGiLrPpH9Mlm9xB2bTl32oD/t2+BlM7y1MjX3Z6T pXh/8AE0PWqMgGhNfquGuNg7JbyGi/ZGhFJmQVO3+R7qnSwdK7fdbUaNI1Cn5+AASRsR Klm2rcjJ8ts6d2DPhxhjyePa85fw0UBY6DezyS15aIUUygBP6V3weNFEJHai2a5dNlU0 88L0qMoc+VsYupHklTegE0HtO1eEYSL0E3Lplb3ppnxLMGFm441jUCjSRPEaIkfmQJVV qSJSqdBM0UhQmOQdoEndmKPh7UsmdaPw2RalrFHYio2VxoE+/PaTlQBQgSblnTap5yhA 4o2g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lwz6hbkW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o16-20020ac84290000000b0042dc8c49ff3si6333772qtl.360.2024.02.19.08.40.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2024 08:40:06 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lwz6hbkW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rc6g1-0001Tv-G2; Mon, 19 Feb 2024 11:39:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rc6fz-0001TV-JU for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:31 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rc6fx-0002xF-O3 for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:31 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-412698cdd77so4570605e9.1 for ; Mon, 19 Feb 2024 08:39:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708360768; x=1708965568; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MHN0WwPF0EH6RoLWLYyydVS2IwI6/kKCgvu+Hk831E8=; b=Lwz6hbkWFbh8LMKWvjqaqdYZBj64xMBkroarhToBzNh7jTVIyZ5+MrCfFfdWFCbWdG CjairSSNxN0Ps9QJDLIyPXKlE8WOW2Gs1FFDtkKIGpbJlGqu0o0HbsyWDp2J1xlihmLh SRDg5H9oPZbw3XpPAal1lRHcn+S1PQwsXXy8bQ8TvrLNiP8lMprXQbvb8KnoJPQYW313 CgQSqxYLuJXBf6clPyXtbPJKGC/InrQDrFYwVPjx9OqtcsY0kKjJ3Vdk1D1VrYMlTMdY mE4LuZKs3EWIMTH9B9LxSIBOnqtA18Apy7ZRRsk+eHaBSJ0BYCbx8YK04p1s31eFZbTV jR8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708360768; x=1708965568; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MHN0WwPF0EH6RoLWLYyydVS2IwI6/kKCgvu+Hk831E8=; b=gsnk5sn3HcuXrkaxpOhjzTJaYEU/WXF+MwNq6e/qhBkYWckmQA9rrbEA14zkONGURX u7csgOxFabRS5rKK5Gg0JUgRs7FHB/lbQWibDP95p0zn4tjncmaen3xyztyiud8aY0wl 06oXOvRVmtMv54e466UyCLAwy3LB9MKqaG6W0nMWlImkVMGY5cEhxAIsoCXhn+gwxFOi KJHisTECtTbyLFnZlpHbOUvi0o/wHB5RzHYna6Ix610NdBMn111CS1zSo+70cFXp0iDM 7k4a+gJ8bK9y3agZWS7EUctWE94phhsf8sJ7uMQ8+Ud8u4CHhYiV+uvL1yJcsFFIquUe jtGw== X-Gm-Message-State: AOJu0YxI0p9Lfe2nghDZEb+0UyL0gVUNHakbPaA6IXEjQzHgia/qLdwd l6BNnVveFiCZuyjP8kfbBxpoq2IaXA0jYaUQ5JsF4U8cXVKe1BOPEaeySTKDGHcmJD7QpWaP1SO J X-Received: by 2002:a05:600c:154f:b0:411:de5c:8023 with SMTP id f15-20020a05600c154f00b00411de5c8023mr11101835wmg.4.1708360767825; Mon, 19 Feb 2024 08:39:27 -0800 (PST) Received: from m1x-phil.lan ([176.176.181.220]) by smtp.gmail.com with ESMTPSA id o1-20020a05600c378100b004125f34fd7csm7131030wmr.31.2024.02.19.08.39.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 19 Feb 2024 08:39:27 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 04/14] hw/acpi/ich9_tco: Include 'ich9' in names Date: Mon, 19 Feb 2024 17:38:44 +0100 Message-ID: <20240219163855.87326-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Make it explicit the following are ICH9 specific: acpi_pm_tco_init() -> ich9_acpi_pm_tco_init() vmstate_tco_io_sts -> vmstate_ich9_sm_tco. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/acpi/ich9_tco.h | 5 ++--- hw/acpi/ich9.c | 4 ++-- hw/acpi/ich9_tco.c | 4 ++-- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/include/hw/acpi/ich9_tco.h b/include/hw/acpi/ich9_tco.h index 2562a7cf39..1c99781a79 100644 --- a/include/hw/acpi/ich9_tco.h +++ b/include/hw/acpi/ich9_tco.h @@ -75,9 +75,8 @@ typedef struct TCOIORegs { MemoryRegion io; } TCOIORegs; -/* tco.c */ -void acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent); +void ich9_acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent); -extern const VMStateDescription vmstate_tco_io_sts; +extern const VMStateDescription vmstate_ich9_sm_tco; #endif /* HW_ACPI_TCO_H */ diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 228ebc9a1e..660fa6a082 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -186,7 +186,7 @@ static const VMStateDescription vmstate_tco_io_state = { .minimum_version_id = 1, .needed = vmstate_test_use_tco, .fields = (const VMStateField[]) { - VMSTATE_STRUCT(tco_regs, ICH9LPCPMRegs, 1, vmstate_tco_io_sts, + VMSTATE_STRUCT(tco_regs, ICH9LPCPMRegs, 1, vmstate_ich9_sm_tco, TCOIORegs), VMSTATE_END_OF_LIST() } @@ -317,7 +317,7 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, qemu_irq sci_irq) memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi); if (pm->enable_tco) { - acpi_pm_tco_init(&pm->tco_regs, &pm->io); + ich9_acpi_pm_tco_init(&pm->tco_regs, &pm->io); } if (pm->acpi_pci_hotplug.use_acpi_hotplug_bridge) { diff --git a/hw/acpi/ich9_tco.c b/hw/acpi/ich9_tco.c index 81606219f7..dd4aff82e0 100644 --- a/hw/acpi/ich9_tco.c +++ b/hw/acpi/ich9_tco.c @@ -224,7 +224,7 @@ static const MemoryRegionOps tco_io_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -void acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent) +void ich9_acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent) { *tr = (TCOIORegs) { .tco = { @@ -250,7 +250,7 @@ void acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent) memory_region_add_subregion(parent, ICH9_PMIO_TCO_RLD, &tr->io); } -const VMStateDescription vmstate_tco_io_sts = { +const VMStateDescription vmstate_ich9_sm_tco = { .name = "tco io device status", .version_id = 1, .minimum_version_id = 1, From patchwork Mon Feb 19 16:38:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 774095 Delivered-To: patch@linaro.org Received: by 2002:a5d:4943:0:b0:33b:4db1:f5b3 with SMTP id r3csp1252784wrs; Mon, 19 Feb 2024 08:40:24 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWJ0l0M8RQR0UwOa9yaxb3yJ32u1887pRangVw4iflDEAQYykCjZPlA6W+As2tVPQbsJyBBbQ7lVmqNsyGwoGFY X-Google-Smtp-Source: AGHT+IG9FbEvi8fubf10lGdZw6vv1GAzD2bBAmCzTdIZImDBWodAvU5pL2czoAllQwcRz8zBtE81 X-Received: by 2002:a0c:f114:0:b0:68f:5c66:a935 with SMTP id i20-20020a0cf114000000b0068f5c66a935mr5747993qvl.49.1708360824173; Mon, 19 Feb 2024 08:40:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1708360824; cv=none; d=google.com; s=arc-20160816; b=MSuYjmWTUJvlDCBK7Jl4w8DNoIJcrQwhy9JWH4yZ59syOZ4ILt/hd57Xd5hRrbXj+5 E3WJS7XvNE2AtTPKQIy13GNM4bauW6k0VROCsL0Q1mUG2JbBRyZqqJ/b0/T4dGe6SA/B Cd3Kq7PELf4d+9ZOT0s0z2HBM65trS+P/41Aa32zoe3Ift0tu143tyR01zIzkfWPHK6x II+Vt6GL9rD/kyEXCSG468A3UkmoFHEj1oy+k0ByFoY2g+yEbGoaauuxGY2wx5oFgAth fiQPG6+dIoCPI2oRAMkq6GowGWcQYQ85O34XrOwTN/BZ4TBmD2swUULj6kiQnFbNH0JR 0liA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=teclhIdRp9DBtUYfsv1Nj0vfraIqiRBxDKPN1DGCTw4=; fh=GFH0+Nfz+rN0IvTHf71Tn8mJWCh907g2jnPgVcMG7yo=; b=GwLp5+y7J+Ygxzw8BMF/Ow0I80QHVvGLwvOOTJo7N15Iubw+H/sUl6Ry9Ks3LY6qw9 woQyT6HIkpxIiccL/xj1WwzsR+EeinQNXjk3RqQq6HBkE7BD3gjAXVjfyTUyGozcrcmT +kzRYlSH6cYc5pRQekGRjeRoun8ulim3yV78392Mk3pwL6qSjyRx2fs0Zd9JTbylNInQ Ns52nKc228x3znGPyuDvZkCjPBPmthHYsi7aTDNUFoNFyS5Kldn2QmhAv2gNbeScZHgY OhfIOGRx172MxU4fRGPEX3IFib1CHrrTHSwpS97nMKOYHrDNHr3rKbHQzvw8Oz0wle+p ZvBg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z0946+W8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q14-20020a056214194e00b0068cb0e2e9aesi6307616qvk.580.2024.02.19.08.40.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2024 08:40:24 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z0946+W8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rc6g6-0001YJ-PI; Mon, 19 Feb 2024 11:39:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rc6g6-0001Vm-0N for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:38 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rc6g4-0002y5-Dg for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:37 -0500 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-33aeb088324so2384253f8f.2 for ; Mon, 19 Feb 2024 08:39:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708360774; x=1708965574; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=teclhIdRp9DBtUYfsv1Nj0vfraIqiRBxDKPN1DGCTw4=; b=Z0946+W8T0GVl3pUl/1DR4QtwMAFKiJxmmUHrvs9pZOaBsj8N9T4lteRrjvrU94xm/ Y81slROxwNxkET+6eL6lb/1uVzapRxs3ddfACSeg+ai6MA496VddafzhAWmgwJU8/Sfs /4fwaQuvpxaWFEMLytevb3ig+u2JPN0exV1ak0eVs1dUuAxMPs4wN0DKc/U4HW+r2YZX 73hH0j3fja51or7svAXp/7weqNon83+kfMvF06tZRAaBVlHV4OPkafL1Gx+ykIl7Wik1 fJyeIhfJ0dz6Qoe13dvrOXm6LxpBRZ+OcCrGPuEHopx08jVL4txM5RQTBIctc4UbN8sY mm3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708360774; x=1708965574; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=teclhIdRp9DBtUYfsv1Nj0vfraIqiRBxDKPN1DGCTw4=; b=RPe7fUm9D7kOf2KyTZPDzpkgPMfY+4ew01A8ZNwsJ6hhzZ1jVG4UZtFdYK2C7Uz1Pq 19Is+8we2WieqX5tq1W5xSkqLPpMaIsjrIPFizvdBD9C0HSH++gy0tA/a7g4EYDbcs5K PlMWxqx0FxKaQtyVe0tqFNWml526UKew15woAyRnAOCJmcCM2gEcPAmFafZM/YPZLo58 HAoEK7JXgB3ZWbbEMLEwHn26n0W7On0TpKn2pUmsnTrIGj1DG4Yo5A2QVWgr6m+CvgKJ D0q3TuqxBjywwe4xt/bhU0ulVy0345uMt1g6DeCqgd06IEDmh4heX2feFyxp+sx6WmFW vFQw== X-Gm-Message-State: AOJu0YyLWNwLGJGK+4rxyr8EAdmubt3PtckPhY4YVToMYALdg1CkhVAV tn0On+rrBgMRI+J5kqDYsldxgArkg5nK33DHeD0Spbo+Ef/kOh7fK4NDDbybjfPnyVPQS1CJpXj 3 X-Received: by 2002:a05:6000:1864:b0:33d:6334:e14 with SMTP id d4-20020a056000186400b0033d63340e14mr373508wri.11.1708360774545; Mon, 19 Feb 2024 08:39:34 -0800 (PST) Received: from m1x-phil.lan ([176.176.181.220]) by smtp.gmail.com with ESMTPSA id ay3-20020a5d6f03000000b0033d1b760125sm11129469wrb.92.2024.02.19.08.39.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 19 Feb 2024 08:39:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 05/14] hw/acpi/ich9_tco: Restrict ich9_generate_smi() declaration Date: Mon, 19 Feb 2024 17:38:45 +0100 Message-ID: <20240219163855.87326-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Only files including "hw/acpi/ich9_tco.h" require the ich9_generate_smi() declaration. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/acpi/ich9_tco.h | 1 + include/hw/southbridge/ich9.h | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/include/hw/acpi/ich9_tco.h b/include/hw/acpi/ich9_tco.h index 1c99781a79..68ee64942f 100644 --- a/include/hw/acpi/ich9_tco.h +++ b/include/hw/acpi/ich9_tco.h @@ -76,6 +76,7 @@ typedef struct TCOIORegs { } TCOIORegs; void ich9_acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent); +void ich9_generate_smi(void); extern const VMStateDescription vmstate_ich9_sm_tco; diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index 1ac4238f7e..bee522a4cf 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -11,8 +11,6 @@ #include "qemu/notify.h" #include "qom/object.h" -void ich9_generate_smi(void); - #define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */ #define TYPE_ICH9_LPC_DEVICE "ICH9-LPC" From patchwork Mon Feb 19 16:38:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 774093 Delivered-To: patch@linaro.org Received: by 2002:a5d:4943:0:b0:33b:4db1:f5b3 with SMTP id r3csp1252700wrs; Mon, 19 Feb 2024 08:40:13 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVw/oAOIxlm9ZgnVANgF+jxBJkPVpDK7qEXAX+/rz9KmCubAa5WjcY0fmQp8AKayFyYReQVBLyV5LHcFMpukOvB X-Google-Smtp-Source: AGHT+IGMC8QkhzdlPtgvBnKzShBo7khn9xzUP8kZmfDeq2ETpSj6WqZnXeoqpTC+g/ws/0H0GrMR X-Received: by 2002:a05:6214:4103:b0:68c:4e3c:10b1 with SMTP id kc3-20020a056214410300b0068c4e3c10b1mr15528391qvb.52.1708360813682; Mon, 19 Feb 2024 08:40:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1708360813; cv=none; d=google.com; s=arc-20160816; b=POqxEEQ8dR5QVGfu2tsCkKTE7cYaWhw7sRWkbuRqkdDe2MHFNwpCTZYheq0cmcN92I hCI8aKt+eQ/DLP/tTssufIqamf3hrt75BkxzXMnBsQahqnGpXiuQAZNa/xSfSPyfU9jI HnsCxyVbMxOKNDix/4Hn7tUYFiFAQsWWiDEjZIaQX/51TpFd7rloDtW2Smqp7xgAk2eJ qObsIOxvXWtNHSz6frJZrBt0P9fIUS2u5PY5ntxbu2CH4qKmM5CIniiszvhLLq7IULuJ 0LoqP1ZmVHAokG92fqcEx6dIMiAimfZA2HQ8sHolFjl3xktTr/8p9cgTjtdrELbVa/7L wxAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=eHqLJIf48lUklPD2bsMO5k3sbW9zd3TEK1XtTCythow=; fh=GFH0+Nfz+rN0IvTHf71Tn8mJWCh907g2jnPgVcMG7yo=; b=Y8YRHkTpNvf7hXBcnIbTiRGJdIfn6CtFll9JrRLEmQfjpkFwtg/KpffCY9Jzb7B5fX kS3SovRPpfmBS5MYFe4EURzMHbeBpqtSxtnkcxmZUd4gOTTpSzFv07OupNZf73MVSsrY ytMiueJP/DEXleiPUYG9nm4wigTgUTj2ecKtpKJ47aZRojdzqLqog/jglNTL/nNN8fU2 fkjw0bFLXvgvkSQfwXzmk/CdFU1owV3Bwp3C0cvoXKHRMnmOVaWUEih3sLOMokOiLITB wyMK0wOBiqN8O+0O/nhsZElg6mgbpwHJ7z//QgkMvcG+c3reD5trBvuC/AgeB3WU+lPs fxDA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vbwXM9va; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e7-20020a0562141d0700b0068ef89a53bfsi6954529qvd.321.2024.02.19.08.40.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2024 08:40:13 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vbwXM9va; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rc6gF-00020n-77; Mon, 19 Feb 2024 11:39:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rc6gD-0001vH-2f for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:45 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rc6gB-0002yn-8I for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:44 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-41261233e61so8607315e9.0 for ; Mon, 19 Feb 2024 08:39:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708360781; x=1708965581; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eHqLJIf48lUklPD2bsMO5k3sbW9zd3TEK1XtTCythow=; b=vbwXM9vaKtADKSqj1B4rhNH9Qtpu+Wc2qlY/gRERD7lATZ0+aR8VQLO8CYVh6+HCzI VWo07vohP2vbRpqJTrSoEviaGxHKgFHq1exot130ANqNuUAAdb4qsQS8wd09mrgL2AeX Z+t3cYGg43izAg2VBfpEBiOLqQYxORNLWxL0r7XPKfAV6FjfaUhTrXhbQYIlb5e6sW4k +k/lbodmq26Ug/ksEg9rdFT0A2r7YgFLnuYrCuWbZ5+NIfrsmBaxF48R88X5MPhLX5lh F87WGRQBRVRvQmlLoW2KuOKSqa25FtjlKUluCS4iWolVYr4htreRJo2ywDhFT1DkMqd0 1LkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708360781; x=1708965581; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eHqLJIf48lUklPD2bsMO5k3sbW9zd3TEK1XtTCythow=; b=xSwkQify3752lJlU0hJYzZlqIGU1bvEds0fqbfvH3jKouVhZ51iOeOvmaQAmkyXtdN OZo603RuBUeLYadIiwxBMF+lw7CKurNLWids57M7RU6et7+P6kCn9bRagzeSM7TdUgCL 0TZDgNARgujIwJrnbSEOZGPUhoEBiadRgpjdkDxfD1d5V2HleV0u016orUdwiiDV2PSL nQfYzQW84b/wC6/1aQkhQGZAG93rppQThenT8IEtZ77cC+3m8cdezGAHMzgPA9nV0XSg 9L+keM56XgcLEW5JFYyIf/iDK2Ze+KS3owePiGR5fy//4BwyLFytNjLpJVDr2HipFp4L b6qQ== X-Gm-Message-State: AOJu0YyysRPbXP2PWs427iL4628m4zEHjddFj49YFKz58dbE9y7j2Fvb SaiUK2viqFTWAbS+gfgC+aiQsNXJWMbHlqiLJYclAh1vFRXUaCli7NFx4OR531v11lrsUCsK5Mq Y X-Received: by 2002:a05:600c:518e:b0:412:6c73:a63e with SMTP id fa14-20020a05600c518e00b004126c73a63emr484118wmb.0.1708360781284; Mon, 19 Feb 2024 08:39:41 -0800 (PST) Received: from m1x-phil.lan ([176.176.181.220]) by smtp.gmail.com with ESMTPSA id 21-20020a05600c229500b0041228b2e179sm11715550wmf.39.2024.02.19.08.39.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 19 Feb 2024 08:39:40 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 06/14] hw/pci-bridge: Extract QOM ICH definitions to 'ich_dmi_pci.h' Date: Mon, 19 Feb 2024 17:38:46 +0100 Message-ID: <20240219163855.87326-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Expose TYPE_ICH_DMI_PCI_BRIDGE to the new "hw/pci-bridge/ich_dmi_pci.h" header. Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + include/hw/pci-bridge/ich_dmi_pci.h | 20 ++++++++++++++++++++ include/hw/southbridge/ich9.h | 2 -- hw/pci-bridge/i82801b11.c | 11 ++++------- 4 files changed, 25 insertions(+), 9 deletions(-) create mode 100644 include/hw/pci-bridge/ich_dmi_pci.h diff --git a/MAINTAINERS b/MAINTAINERS index 1b210c5cc1..50507c3dd6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2609,6 +2609,7 @@ F: hw/acpi/ich9*.c F: hw/i2c/smbus_ich9.c F: hw/isa/lpc_ich9.c F: include/hw/acpi/ich9*.h +F: include/hw/pci-bridge/ich_dmi_pci.h F: include/hw/southbridge/ich9.h PIIX4 South Bridge (i82371AB) diff --git a/include/hw/pci-bridge/ich_dmi_pci.h b/include/hw/pci-bridge/ich_dmi_pci.h new file mode 100644 index 0000000000..7623b32b8e --- /dev/null +++ b/include/hw/pci-bridge/ich_dmi_pci.h @@ -0,0 +1,20 @@ +/* + * QEMU ICH4 i82801b11 dmi-to-pci Bridge Emulation + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_PCI_BRIDGE_ICH_D2P_H +#define HW_PCI_BRIDGE_ICH_D2P_H + +#include "qom/object.h" +#include "hw/pci/pci_bridge.h" + +#define TYPE_ICH_DMI_PCI_BRIDGE "i82801b11-bridge" +OBJECT_DECLARE_SIMPLE_TYPE(I82801b11Bridge, ICH_DMI_PCI_BRIDGE) + +struct I82801b11Bridge { + PCIBridge parent_obj; +}; + +#endif diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index bee522a4cf..b2abf483e0 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -114,8 +114,6 @@ struct ICH9LPCState { #define ICH9_D2P_SECONDARY_DEFAULT (256 - 8) -#define ICH9_D2P_A2_REVISION 0x92 - /* D31:F0 LPC Processor Interface */ #define ICH9_RST_CNT_IOPORT 0xCF9 diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c index c140919cbc..dd17e35b0a 100644 --- a/hw/pci-bridge/i82801b11.c +++ b/hw/pci-bridge/i82801b11.c @@ -45,7 +45,7 @@ #include "hw/pci/pci_bridge.h" #include "migration/vmstate.h" #include "qemu/module.h" -#include "hw/southbridge/ich9.h" +#include "hw/pci-bridge/ich_dmi_pci.h" /*****************************************************************************/ /* ICH9 DMI-to-PCI bridge */ @@ -53,11 +53,8 @@ #define I82801ba_SSVID_SVID 0 #define I82801ba_SSVID_SSID 0 -typedef struct I82801b11Bridge { - /*< private >*/ - PCIBridge parent_obj; - /*< public >*/ -} I82801b11Bridge; + +#define ICH9_D2P_A2_REVISION 0x92 static void i82801b11_bridge_realize(PCIDevice *d, Error **errp) { @@ -103,7 +100,7 @@ static void i82801b11_bridge_class_init(ObjectClass *klass, void *data) } static const TypeInfo i82801b11_bridge_info = { - .name = "i82801b11-bridge", + .name = TYPE_ICH_DMI_PCI_BRIDGE, .parent = TYPE_PCI_BRIDGE, .instance_size = sizeof(I82801b11Bridge), .class_init = i82801b11_bridge_class_init, From patchwork Mon Feb 19 16:38:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 774100 Delivered-To: patch@linaro.org Received: by 2002:a5d:4943:0:b0:33b:4db1:f5b3 with SMTP id r3csp1253139wrs; Mon, 19 Feb 2024 08:41:07 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCX5Liwv6ierVSUsZZYIrdoI6IAPLq/TB3JT7sTac36ypkmMOZ58H9hprwZ/H+WqaIXP/P4Am27tVSMu3wj/KMsF X-Google-Smtp-Source: AGHT+IFuXeG1/gnc2aGZ2ojvbrd9DZEHPjH/Qo4BRG0Bwl2iekjmy8zpWwAEVOaSoXfzemHXHCcD X-Received: by 2002:a05:620a:1aa6:b0:787:7298:78d2 with SMTP id bl38-20020a05620a1aa600b00787729878d2mr1409169qkb.38.1708360867312; Mon, 19 Feb 2024 08:41:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1708360867; cv=none; d=google.com; s=arc-20160816; b=XTK35oamPVNZYqOPj/81gDQ++1/9B1l7Lp6ARV7AlE3dSmxcdt4Bl3P17Bs7Dk4IaA vMXUlXF0h30lCNGKmm9G8Nk5m1Bn3BvU9KWGO4RIKzpQae0GguEUqHvyrGwaHD+xp1y4 9vLctvZBVZtgJMR0o1BDI7YqRNAuL4o8hV9hrVaa7GGnSXr4xcIGZ0ERyL4hEQqnQ7Fe Yx424ctTMu67atpt7yPHu8l3WDFEDmnXJ8ECM+oAAz0tD51AhCj+SKrVzeTtMuocnFw5 hGpXGri/HZR5kiCMe52FaYXb3lJZz9L2lMm9L++SSaKOZfUKrxZAsw1cY720/WvSshZm BpqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2OxqDvZ9j6jb6Om+1GR1gkKRNsMb1bOnUzZDExNDKOw=; fh=GFH0+Nfz+rN0IvTHf71Tn8mJWCh907g2jnPgVcMG7yo=; b=O4N2OmsGohiuTy05PO0RSUIRAOqOaVqOqZP0q3WNZpVuA1DH+Qker1+fV3WpT49FLX 9RwS1Fa6+N/7IIPm+l+YMyr/7bow2LxUailhqrTm6cwFTstrjhKmIIYXvlV3j1cowC6o JCZ8056stujA1lKI1gSCtkXfbqueeCaZTb/OtK63mKWTnIxsrpLyktBEYGrov8eL21U/ 5hyiJSCl4Yj2sd3+b/IYc/ov3cG/LRv/5BYnbu9zjU1KAjsqTiy9RllWf0BIYrr6fXkp YSPhqY5ojxY5eaJkuXQUYwey1VM+ii2vb5qFGwIc4OSYYZlSjX8AgV6U44yzYNEC+M7N cAIA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yXeVvcUf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id sq3-20020a05620a4ac300b007871791228fsi6573593qkn.669.2024.02.19.08.41.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2024 08:41:07 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yXeVvcUf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rc6gL-0002Eo-6F; Mon, 19 Feb 2024 11:39:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rc6gJ-00029x-UT for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:51 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rc6gI-00031s-2C for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:51 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-33d4c0b198aso631402f8f.2 for ; Mon, 19 Feb 2024 08:39:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708360788; x=1708965588; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2OxqDvZ9j6jb6Om+1GR1gkKRNsMb1bOnUzZDExNDKOw=; b=yXeVvcUfy3yR8ERObWsaLGERWC2SRwv7YC/oLlKDA+3ZwQbkNCUBbwl6nrY5G5fPpL YucuW3knGL9FziUdVvNisfcgy7Yg6aeM0p9FXbLLKFgPTf+ZT4eMVrUFdIrja7Fo67Vx 7IrZJ/sxHDpZ8XSWbocJYufyGlq7hC7kJGq8q2aZOfZPLMRAHqwVoEx6ciUbQnwjei1H 04zohsebj41kKTWiAVENpd1LGJCI3p3eS8LJvGQAr5HAg9p2zaSEyzbKaHr3XrNJklNR FglYyYYNSYzueAqajyM5JDWtVgk56v9Ht9Fi0GK/SDPu+IbFpBn/25ykZU8KwxEAUbbQ 52JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708360788; x=1708965588; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2OxqDvZ9j6jb6Om+1GR1gkKRNsMb1bOnUzZDExNDKOw=; b=m2WJ9XyJ7p6UyM5lJihSbrg7jrBrLGBPM6ERVbgRLelPO72plsXOe2c0eYqHuSgLyp JGqnrsUAYjmRRXIcV8sHJppNI35saCQg1gfrnwiI4/dWyqOr/G4ShCCERNKsZg5X8D8e USNBIqwaEWAkUHi98f1epbNzCc629lCIPlKolEYROSC9HOezbgXAym+oeY3keOgoC3ma PEErThHUJMO+Y314TygrvrmU79yyM1UJ2eH5VHyNOLirlvE2Xs/dAOumD05fRveF5h/q M//ZIygP5LKLfCmOpOSWL7fc3rtOpt1y5DoCWZfsfOz1/A89T2qNDINitk7pz1mzpJQq 5L+A== X-Gm-Message-State: AOJu0YxPcFL55lHLTnitVuVYMtuf2pSu5XfpG3Xp6JMxz8ZRz7NoM7+I rmKxKWOPLB+6JWKouF/XSU5acLZjsZpmItZ4zgoqD9V1OLzXi7b8esatsMV2KThYBRJ3ENDgfAc c X-Received: by 2002:a05:6000:1787:b0:33d:56a0:88e7 with SMTP id e7-20020a056000178700b0033d56a088e7mr2147299wrg.46.1708360788074; Mon, 19 Feb 2024 08:39:48 -0800 (PST) Received: from m1x-phil.lan ([176.176.181.220]) by smtp.gmail.com with ESMTPSA id co22-20020a0560000a1600b0033d2848046asm8501988wrb.95.2024.02.19.08.39.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 19 Feb 2024 08:39:47 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 07/14] hw/southbridge/ich9: Introduce TYPE_ICH9_SOUTHBRIDGE stub Date: Mon, 19 Feb 2024 17:38:47 +0100 Message-ID: <20240219163855.87326-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Start the TYPE_ICH9_SOUTHBRIDGE stub, a kind of QOM container which will contain all the ICH9 parts. Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + include/hw/southbridge/ich9.h | 3 ++ hw/i386/pc_q35.c | 7 ++++ hw/southbridge/ich9.c | 61 +++++++++++++++++++++++++++++++++++ hw/Kconfig | 1 + hw/i386/Kconfig | 1 + hw/meson.build | 1 + hw/southbridge/Kconfig | 5 +++ hw/southbridge/meson.build | 3 ++ 9 files changed, 83 insertions(+) create mode 100644 hw/southbridge/ich9.c create mode 100644 hw/southbridge/Kconfig create mode 100644 hw/southbridge/meson.build diff --git a/MAINTAINERS b/MAINTAINERS index 50507c3dd6..d1a2eddd4c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2608,6 +2608,7 @@ S: Supported F: hw/acpi/ich9*.c F: hw/i2c/smbus_ich9.c F: hw/isa/lpc_ich9.c +F: hw/southbridge/ich9.c F: include/hw/acpi/ich9*.h F: include/hw/pci-bridge/ich_dmi_pci.h F: include/hw/southbridge/ich9.h diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index b2abf483e0..162ae3baa1 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -11,6 +11,9 @@ #include "qemu/notify.h" #include "qom/object.h" +#define TYPE_ICH9_SOUTHBRIDGE "ICH9-southbridge" +OBJECT_DECLARE_SIMPLE_TYPE(ICH9State, ICH9_SOUTHBRIDGE) + #define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */ #define TYPE_ICH9_LPC_DEVICE "ICH9-LPC" diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 621661a738..311ac2be6f 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -125,6 +125,7 @@ static void pc_q35_init(MachineState *machine) X86MachineState *x86ms = X86_MACHINE(machine); Object *phb; PCIBus *host_bus; + DeviceState *ich9; PCIDevice *lpc; Object *lpc_obj; DeviceState *lpc_dev; @@ -233,6 +234,12 @@ static void pc_q35_init(MachineState *machine) host_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0")); pcms->bus = host_bus; + ich9 = qdev_new(TYPE_ICH9_SOUTHBRIDGE); + object_property_add_child(OBJECT(machine), "ich9", OBJECT(ich9)); + object_property_set_link(OBJECT(ich9), "mch-pcie-bus", + OBJECT(host_bus), &error_abort); + qdev_realize_and_unref(ich9, NULL, &error_fatal); + /* irq lines */ gsi_state = pc_gsi_create(&x86ms->gsi, true); diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c new file mode 100644 index 0000000000..f3a9b932ab --- /dev/null +++ b/hw/southbridge/ich9.c @@ -0,0 +1,61 @@ +/* + * QEMU Intel ICH9 south bridge emulation + * + * SPDX-FileCopyrightText: 2024 Linaro Ltd + * SPDX-FileContributor: Philippe Mathieu-Daudé + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/qdev-properties.h" +#include "hw/southbridge/ich9.h" +#include "hw/pci/pci.h" + +struct ICH9State { + DeviceState parent_obj; + + PCIBus *pci_bus; +}; + +static Property ich9_props[] = { + DEFINE_PROP_LINK("mch-pcie-bus", ICH9State, pci_bus, + TYPE_PCIE_BUS, PCIBus *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ich9_init(Object *obj) +{ +} + +static void ich9_realize(DeviceState *dev, Error **errp) +{ + ICH9State *s = ICH9_SOUTHBRIDGE(dev); + + if (!s->pci_bus) { + error_setg(errp, "'pcie-bus' property must be set"); + return; + } +} + +static void ich9_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = ich9_realize; + device_class_set_props(dc, ich9_props); + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); +} + +static const TypeInfo ich9_types[] = { + { + .name = TYPE_ICH9_SOUTHBRIDGE, + .parent = TYPE_DEVICE, + .instance_size = sizeof(ICH9State), + .instance_init = ich9_init, + .class_init = ich9_class_init, + } +}; + +DEFINE_TYPES(ich9_types) diff --git a/hw/Kconfig b/hw/Kconfig index 2c00936c28..6584f2f72a 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -36,6 +36,7 @@ source scsi/Kconfig source sd/Kconfig source sensor/Kconfig source smbios/Kconfig +source southbridge/Kconfig source ssi/Kconfig source timer/Kconfig source tpm/Kconfig diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index a1846be6f7..d21638f4f9 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -99,6 +99,7 @@ config Q35 select PC_PCI select PC_ACPI select PCI_EXPRESS_Q35 + select ICH9 select LPC_ICH9 select AHCI_ICH9 select DIMM diff --git a/hw/meson.build b/hw/meson.build index 463d702683..7f9ae8659a 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -33,6 +33,7 @@ subdir('rtc') subdir('scsi') subdir('sd') subdir('sensor') +subdir('southbridge') subdir('smbios') subdir('ssi') subdir('timer') diff --git a/hw/southbridge/Kconfig b/hw/southbridge/Kconfig new file mode 100644 index 0000000000..852b7f346f --- /dev/null +++ b/hw/southbridge/Kconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config ICH9 + bool + depends on PCI_EXPRESS diff --git a/hw/southbridge/meson.build b/hw/southbridge/meson.build new file mode 100644 index 0000000000..70c1fa3cb2 --- /dev/null +++ b/hw/southbridge/meson.build @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +system_ss.add(when: 'CONFIG_ICH9', if_true: files('ich9.c')) From patchwork Mon Feb 19 16:38:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 774097 Delivered-To: patch@linaro.org Received: by 2002:a5d:4943:0:b0:33b:4db1:f5b3 with SMTP id r3csp1253003wrs; Mon, 19 Feb 2024 08:40:50 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWsJ5vo43v1BV9o+YD+KQkTyHBqI1FckVgzz10Bb2/vXgRPBxam+AGJYlyBh/VvpWv03ZenAHW9ugz23WpX1sx8 X-Google-Smtp-Source: AGHT+IEdLuv08Jp/ggpiU2V3hJPTDa3RbOMcFZt3Rsn+Cc8/J8N+l9jNKYgzO0j2hAWpheN0aXPG X-Received: by 2002:a05:620a:e83:b0:785:d80e:491b with SMTP id w3-20020a05620a0e8300b00785d80e491bmr11107475qkm.43.1708360849730; Mon, 19 Feb 2024 08:40:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1708360849; cv=none; d=google.com; s=arc-20160816; b=iKMar79rJbhw5C2FJSisw+SR0zp1/fTD7C1ATsjQsi4MMXp9mGdfY49O0jketNMZ5q +t6g9sfhWJWdJWKxbyRgfQQJHWyMn45VMXr9kH7ZECEwSQLhrhSXDbO+PgPKiHtEU011 Xo1a6AWzz2deocl7/afUCA+4+VtTNoH6cgbkUymkSORLrScXOQclp5vTbAraLvEucVsg VCkfku+zTeJNmJCaBpHi0qUU+Iflutt+8SsxwzMufJZwPUGgD5iLXLhfAOIVEuTfHCz3 7M/rDfflnuDg0LA0neSIRKNIYJxplYHwudcIWfuTj9ZQF4QILFKumBMiyvNadMyo7qG9 7dhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=y/Jebg64AQMhqQ0a3cA7lmqym47W2wyRtw41CtoK9cY=; fh=GFH0+Nfz+rN0IvTHf71Tn8mJWCh907g2jnPgVcMG7yo=; b=vBWXt872Y02wNH997TDgeO5RNZornOZhy4WJxlxZUTFJVFSlR/Yu/8wIu+G0umK2YT foynyhT6bYeRdfu6f5KpONRH+hmnnWg1jonCy9A9ceJB40yZc2RXnZBiRHS4hzqVDwZu K0yQxkPd4L6c1nME21Lkwqzl4HBP/kHUrdnctJdnfPpCk7zbytHbBPd6rDgtIw6u0bxb I41dqJ4arq0LNfa6+uRi7YwaCMNfCixq1BEstcIjCJZUPHBWd8NUFPhCRotAOC85j8PV ZjYxIOO5gUe1sdIgRbDjHHbZ5gtQe7+EmNhIlOErMyTUmDGmaiDs9bD7TtdNZA67OyvE ARWg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZJdVPb58; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a7-20020a05620a438700b007873adcd28esi7194701qkp.231.2024.02.19.08.40.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2024 08:40:49 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZJdVPb58; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rc6gS-0002jn-Ob; Mon, 19 Feb 2024 11:40:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rc6gR-0002hS-8E for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:59 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rc6gP-00034I-D2 for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:39:58 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-3394bec856fso3191098f8f.0 for ; Mon, 19 Feb 2024 08:39:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708360795; x=1708965595; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y/Jebg64AQMhqQ0a3cA7lmqym47W2wyRtw41CtoK9cY=; b=ZJdVPb5868fUZs3gNwdcl4s8Vn6ovsALkFOwDuBwIdjwEofaGJ6xKc4XqOHFZVtHY8 m+L3HtXBka/AsqgS9ft/HhSjptxMKYYmhcsNWghYeiYxPSk05Mjxey3XZpJPwvZR7DBZ +F1n0Djt4fj8BNuWgg2wbWzu2Minediwi7OLf3ajCt1QUZuZdipEQNiAyls9Ajkq8YgT S4yQ87hCwE106fz7HoZuc/qw5saCYQ+A5JbXNpQiBgKbeCbNhnB6iX3A8NR7RJGsKmCi dML6KUP7JmSChUdO+zlXX/Dp73sNqI3mj62jUCX/wulYD03+1alS9dpCNvApFjOv4fZ+ vgXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708360795; x=1708965595; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y/Jebg64AQMhqQ0a3cA7lmqym47W2wyRtw41CtoK9cY=; b=ICVci7S53gS0JjngP9G16hSF/XOit9te1aau1N5zmvljIi54qi/gqdIXElSxasvVJ/ 1j36rqei7rFNDyzK7Oe3/goU1N85C1K+QsuBy4xJc1ACINPS9iWbF+6no7/ZRzfFz862 XLB1umssEDSNwV9XlamBogRahG1GO9S0qi5YlE/93YWgsJ8Bl4IWfFyTnWta2JuMGNhP FiP0mwBT2j69VzNolMkGPCM4eQXpVxmXho0zC1HWDdJCHjbQj9YNAFa13aHp49FDheT5 GvEW2eZYWSzaXZlQ7Zi6L5MFe9kHZs/j0FqHHZ1fvPgBZplEV4b6TtMb6MbAuT3XjnfP qYag== X-Gm-Message-State: AOJu0YyS/bK/qBRuKe+sXr5OCgj+rCzzNEo9T0gbjebnf03pHvcZrzAT 3/rbrPei5QRZQivV9sPJhFqtpBEam+nc4XLE27eKzel/lxYFFZQ45p4hx+cKmLJ4D7KlYoWHRAM 2 X-Received: by 2002:a5d:658f:0:b0:33d:513a:9248 with SMTP id q15-20020a5d658f000000b0033d513a9248mr2317433wru.15.1708360795575; Mon, 19 Feb 2024 08:39:55 -0800 (PST) Received: from m1x-phil.lan ([176.176.181.220]) by smtp.gmail.com with ESMTPSA id t23-20020a1c7717000000b00412680b270csm2471766wmi.5.2024.02.19.08.39.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 19 Feb 2024 08:39:55 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 08/14] hw/southbridge/ich9: Add the DMI-to-PCI bridge Date: Mon, 19 Feb 2024 17:38:48 +0100 Message-ID: <20240219163855.87326-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instantiate TYPE_ICH_DMI_PCI_BRIDGE in TYPE_ICH9_SOUTHBRIDGE. Since the Q35 machine doesn't use it, add the 'd2p-enabled' property to disable it. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/southbridge/ich9.h | 9 --------- hw/i386/pc_q35.c | 1 + hw/southbridge/ich9.c | 27 +++++++++++++++++++++++++++ hw/southbridge/Kconfig | 1 + 4 files changed, 29 insertions(+), 9 deletions(-) diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index 162ae3baa1..b9122d299d 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -108,15 +108,6 @@ struct ICH9LPCState { #define ICH9_USB_UHCI1_DEV 29 #define ICH9_USB_UHCI1_FUNC 0 -/* D30:F0 DMI-to-PCI bridge */ -#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE" -#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0 - -#define ICH9_D2P_BRIDGE_DEV 30 -#define ICH9_D2P_BRIDGE_FUNC 0 - -#define ICH9_D2P_SECONDARY_DEFAULT (256 - 8) - /* D31:F0 LPC Processor Interface */ #define ICH9_RST_CNT_IOPORT 0xCF9 diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 311ac2be6f..2f15af540f 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -238,6 +238,7 @@ static void pc_q35_init(MachineState *machine) object_property_add_child(OBJECT(machine), "ich9", OBJECT(ich9)); object_property_set_link(OBJECT(ich9), "mch-pcie-bus", OBJECT(host_bus), &error_abort); + qdev_prop_set_bit(ich9, "d2p-enabled", false); qdev_realize_and_unref(ich9, NULL, &error_fatal); /* irq lines */ diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c index f3a9b932ab..6df47e81fb 100644 --- a/hw/southbridge/ich9.c +++ b/hw/southbridge/ich9.c @@ -12,19 +12,42 @@ #include "hw/qdev-properties.h" #include "hw/southbridge/ich9.h" #include "hw/pci/pci.h" +#include "hw/pci-bridge/ich_dmi_pci.h" + +#define ICH9_D2P_DEVFN PCI_DEVFN(30, 0) struct ICH9State { DeviceState parent_obj; + I82801b11Bridge d2p; + PCIBus *pci_bus; + bool d2p_enabled; }; static Property ich9_props[] = { DEFINE_PROP_LINK("mch-pcie-bus", ICH9State, pci_bus, TYPE_PCIE_BUS, PCIBus *), + DEFINE_PROP_BOOL("d2p-enabled", ICH9State, d2p_enabled, true), DEFINE_PROP_END_OF_LIST(), }; +static bool ich9_realize_d2p(ICH9State *s, Error **errp) +{ + if (!module_object_class_by_name(TYPE_ICH_DMI_PCI_BRIDGE)) { + error_setg(errp, "DMI-to-PCI function not available in this build"); + return false; + } + object_initialize_child(OBJECT(s), "d2p", &s->d2p, TYPE_ICH_DMI_PCI_BRIDGE); + qdev_prop_set_int32(DEVICE(&s->d2p), "addr", ICH9_D2P_DEVFN); + if (!qdev_realize(DEVICE(&s->d2p), BUS(s->pci_bus), errp)) { + return false; + } + object_property_add_alias(OBJECT(s), "pci.0", OBJECT(&s->d2p), "pci.0"); + + return true; +} + static void ich9_init(Object *obj) { } @@ -37,6 +60,10 @@ static void ich9_realize(DeviceState *dev, Error **errp) error_setg(errp, "'pcie-bus' property must be set"); return; } + + if (s->d2p_enabled && !ich9_realize_d2p(s, errp)) { + return; + } } static void ich9_class_init(ObjectClass *klass, void *data) diff --git a/hw/southbridge/Kconfig b/hw/southbridge/Kconfig index 852b7f346f..db7259bf6f 100644 --- a/hw/southbridge/Kconfig +++ b/hw/southbridge/Kconfig @@ -3,3 +3,4 @@ config ICH9 bool depends on PCI_EXPRESS + imply I82801B11 From patchwork Mon Feb 19 16:38:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 774094 Delivered-To: patch@linaro.org Received: by 2002:a5d:4943:0:b0:33b:4db1:f5b3 with SMTP id r3csp1252755wrs; Mon, 19 Feb 2024 08:40:21 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWGowzBIfJKqvSv/Bq7BqbwKh6XMjY97IObneo2AO8ki4NIZvmhuvKMENaFASZVrDAukvaYq/75j0wateuzKnOB X-Google-Smtp-Source: AGHT+IEOTcw0UUIXtPwattqnPMksEOsHkrvaNryB8uMKJAnI1zsxu7JS6H6pcWYTpXGsiSnDCQrx X-Received: by 2002:a9d:7c82:0:b0:6e2:eb7f:1c3 with SMTP id q2-20020a9d7c82000000b006e2eb7f01c3mr13520306otn.16.1708360821511; Mon, 19 Feb 2024 08:40:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1708360821; cv=none; d=google.com; s=arc-20160816; b=nPuLMK6F2LRyGoESTD0HOZ3lD18hi7a7kpFmFVYGoJCIPbKEIVQYESQaiMYdmEhrVg asBinFX7OqPro37QHPsTDVc5b5YQ41kxIT92j7Zv9unkgn5mecnD/WqXPFbKp9JUArVZ SmEhZH5knsqX6ACFl4eNL8eXCNTEtECM6dfdORGlOpm7xT72Ppx3/W4O6fs2sCps0TTZ vX+QFx+yHg5NcIpYlVtFLtqHqnVgFyB4vACzYbz6CmMDs8Mf7biLHdztjYVffZrWKuFR 1guEyMLmpSe1Xs9F/PqygkLohZ5KFxTIewYgOYcrTL+jzgaNMz14XZ32rd+l0n0GCqhp x0Wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nXC/SCl82I2A4enONxI0zckdczUX4ZiZLg6vkrEkXzQ=; fh=GFH0+Nfz+rN0IvTHf71Tn8mJWCh907g2jnPgVcMG7yo=; b=lYsKrPJzPu1bl60pjgF96c6fH6gb1yFRVaBhmcUVIUAvJOLBXyhBPaFGK55vaGizJY aymWdAm3G4bUbCNMeBVPI0W5CxuczqYtjOKW0K2fUxxkTUWvTHPSMVSGYbaS9SsjSCwy BDLntmHZQam6lyBaO4iX4YffJVgoiuFHZFwmB8O5+D0lMSZC4YjKm4EXqjblU6ERNmrB ihUhxbZ8jVpq7lllzmGEPbIprqjljOyouPvcXtgTCKCx0dzyYqC7yRnSyuXCVNH2p0fK 6v6mFddoV3u87ycCmQ1d8CVuwm4vRjtgi7x/yBz414UqdM1X71XyJ6gPF7LSPK2QmXiK UumQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tKrdOL0u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s18-20020ac85cd2000000b0042c7504cd5dsi7308808qta.666.2024.02.19.08.40.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2024 08:40:21 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tKrdOL0u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rc6gg-0003HM-Ty; Mon, 19 Feb 2024 11:40:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rc6gZ-000301-Hx for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:40:10 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rc6gW-00036O-Cd for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:40:07 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-33d622f5568so155736f8f.0 for ; Mon, 19 Feb 2024 08:40:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708360802; x=1708965602; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nXC/SCl82I2A4enONxI0zckdczUX4ZiZLg6vkrEkXzQ=; b=tKrdOL0uai2r5geQlT8T4CCEDhqlUTfgVc3wrB+qE80ixDT+F8lT5zqsKiEZ0keHmU BX5J/Yizv72DfEVnZpudJ0/eb5trFTL+/ljTVNlH2VgjoCifdk/1ccQes3AbXkxQwcFp veHOPfGAx2djcGTfeqP1kJ5cXfM/F6bw86gmNR/sYbwJGznLDumsH8JRS7DQrv/R+1H5 3GLqLmecf5GhKq42PBAEfUJDe7pI0ip2Y4dGPEttg0qB5DPskigtMuYQ2gqgiLeEDdDC lA9jV2Fkm77Ljd9rLwLgLpDa/p9TXQpiCQ6+/tSsRJeTgfizIeWLxe1yk4Gx2bCpCTkG 2VSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708360802; x=1708965602; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nXC/SCl82I2A4enONxI0zckdczUX4ZiZLg6vkrEkXzQ=; b=FfXQYfty0ztvpceY5bKXf8bFeFN9Ig0bVwALsUbmfi5srutKcRL9Pxht7hx1UkjRck h0uLxWviJ1SgzydMXj0IOsSZ5R5pDnLA4nucmXSL6G0garQg3UsQuv86CKS4rEniP/LM 5ldCNajojrZMVuWqlKf/Twmu7rcMX7w++pY33500ZQoIPlxkhhAegO3rh+9eu0nSikuo lvPC6YK0PMd5cjMTau2U9WX787ctIBoQjD26ioDugXqOvTFzhKUH/YtPt5/QAgEMlv/V 4yUMicq8RBtldd6zW2GnO/AA2pUvHUCJcTp/h+YDts/FUPLlZB8DGRfvCnMBz3UVgNa3 OyTw== X-Gm-Message-State: AOJu0YzA9Y2AzEj7ubhTFAASF8jfTmGtaXNV3t6WBTELgDa7mciUOei+ CJX1dYAHqFatE9zfqO9F68YZe6HmloCNGIT4kK7P1g1tRdhGWLcA4sMX/HFgFCknrHZF4MOCHig Z X-Received: by 2002:a5d:5887:0:b0:33d:649c:8c2 with SMTP id n7-20020a5d5887000000b0033d649c08c2mr50195wrf.0.1708360802209; Mon, 19 Feb 2024 08:40:02 -0800 (PST) Received: from m1x-phil.lan ([176.176.181.220]) by smtp.gmail.com with ESMTPSA id w14-20020adfcd0e000000b0033d14c96ec1sm10702355wrm.45.2024.02.19.08.40.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 19 Feb 2024 08:40:01 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 09/14] hw/southbridge/ich9: Add a AHCI function Date: Mon, 19 Feb 2024 17:38:49 +0100 Message-ID: <20240219163855.87326-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instantiate TYPE_ICH9_AHCI in TYPE_ICH9_SOUTHBRIDGE. Since the PC machines can disable SATA (see the PC_MACHINE_SATA dynamic property), add the 'sata-enabled' property to disable it. Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 2 ++ include/hw/southbridge/ich9.h | 4 ---- hw/i386/pc_q35.c | 25 ++++--------------------- hw/southbridge/ich9.c | 35 +++++++++++++++++++++++++++++++++++ hw/i386/Kconfig | 1 - hw/southbridge/Kconfig | 1 + 6 files changed, 42 insertions(+), 26 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index d1a2eddd4c..937ebb5c96 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2607,9 +2607,11 @@ M: Marcel Apfelbaum S: Supported F: hw/acpi/ich9*.c F: hw/i2c/smbus_ich9.c +F: hw/ide/ich.c F: hw/isa/lpc_ich9.c F: hw/southbridge/ich9.c F: include/hw/acpi/ich9*.h +F: include/hw/ide/ahci-pci.h F: include/hw/pci-bridge/ich_dmi_pci.h F: include/hw/southbridge/ich9.h diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index b9122d299d..ac7f9f4ff5 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -166,10 +166,6 @@ struct ICH9LPCState { #define ICH9_GPIO_GSI "gsi" -/* D31:F2 SATA Controller #1 */ -#define ICH9_SATA1_DEV 31 -#define ICH9_SATA1_FUNC 2 - /* D31:F0 power management I/O registers offset from the address ICH9_LPC_PMBASE */ diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 2f15af540f..060358d449 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -61,9 +61,6 @@ #include "hw/acpi/acpi.h" #include "target/i386/cpu.h" -/* ICH9 AHCI has 6 ports */ -#define MAX_SATA_PORTS 6 - struct ehci_companions { const char *name; int func; @@ -129,7 +126,7 @@ static void pc_q35_init(MachineState *machine) PCIDevice *lpc; Object *lpc_obj; DeviceState *lpc_dev; - BusState *idebus[MAX_SATA_PORTS]; + BusState *idebus[2] = { }; ISADevice *rtc_state; MemoryRegion *system_memory = get_system_memory(); MemoryRegion *system_io = get_system_io(); @@ -138,7 +135,6 @@ static void pc_q35_init(MachineState *machine) ISABus *isa_bus; int i; ram_addr_t lowmem; - DriveInfo *hd[MAX_SATA_PORTS]; MachineClass *mc = MACHINE_GET_CLASS(machine); bool acpi_pcihp; bool keep_pci_slot_hpc; @@ -239,6 +235,7 @@ static void pc_q35_init(MachineState *machine) object_property_set_link(OBJECT(ich9), "mch-pcie-bus", OBJECT(host_bus), &error_abort); qdev_prop_set_bit(ich9, "d2p-enabled", false); + qdev_prop_set_bit(ich9, "sata-enabled", pcms->sata_enabled); qdev_realize_and_unref(ich9, NULL, &error_fatal); /* irq lines */ @@ -302,22 +299,8 @@ static void pc_q35_init(MachineState *machine) 0xff0104); if (pcms->sata_enabled) { - PCIDevice *pdev; - AHCIPCIState *ich9; - - /* ahci and SATA device, for q35 1 ahci controller is built-in */ - pdev = pci_create_simple_multifunction(host_bus, - PCI_DEVFN(ICH9_SATA1_DEV, - ICH9_SATA1_FUNC), - "ich9-ahci"); - ich9 = ICH9_AHCI(pdev); - idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0"); - idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); - g_assert(MAX_SATA_PORTS == ich9->ahci.ports); - ide_drive_get(hd, ich9->ahci.ports); - ahci_ide_create_devs(&ich9->ahci, hd); - } else { - idebus[0] = idebus[1] = NULL; + idebus[0] = qdev_get_child_bus(ich9, "ide.0"); + idebus[1] = qdev_get_child_bus(ich9, "ide.1"); } if (machine_usb(machine)) { diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c index 6df47e81fb..233dc1c5d7 100644 --- a/hw/southbridge/ich9.c +++ b/hw/southbridge/ich9.c @@ -13,22 +13,30 @@ #include "hw/southbridge/ich9.h" #include "hw/pci/pci.h" #include "hw/pci-bridge/ich_dmi_pci.h" +#include "hw/ide/ahci-pci.h" +#include "hw/ide.h" #define ICH9_D2P_DEVFN PCI_DEVFN(30, 0) +#define ICH9_SATA1_DEVFN PCI_DEVFN(31, 2) + +#define SATA_PORTS 6 struct ICH9State { DeviceState parent_obj; I82801b11Bridge d2p; + AHCIPCIState sata0; PCIBus *pci_bus; bool d2p_enabled; + bool sata_enabled; }; static Property ich9_props[] = { DEFINE_PROP_LINK("mch-pcie-bus", ICH9State, pci_bus, TYPE_PCIE_BUS, PCIBus *), DEFINE_PROP_BOOL("d2p-enabled", ICH9State, d2p_enabled, true), + DEFINE_PROP_BOOL("sata-enabled", ICH9State, sata_enabled, true), DEFINE_PROP_END_OF_LIST(), }; @@ -48,6 +56,29 @@ static bool ich9_realize_d2p(ICH9State *s, Error **errp) return true; } +static bool ich9_realize_sata(ICH9State *s, Error **errp) +{ + DriveInfo *hd[SATA_PORTS]; + + object_initialize_child(OBJECT(s), "sata[0]", &s->sata0, TYPE_ICH9_AHCI); + qdev_prop_set_int32(DEVICE(&s->sata0), "addr", ICH9_SATA1_DEVFN); + if (!qdev_realize(DEVICE(&s->sata0), BUS(s->pci_bus), errp)) { + return false; + } + for (unsigned i = 0; i < SATA_PORTS; i++) { + g_autofree char *portname = g_strdup_printf("ide.%u", i); + + object_property_add_alias(OBJECT(s), portname, + OBJECT(&s->sata0), portname); + } + + g_assert(SATA_PORTS == s->sata0.ahci.ports); + ide_drive_get(hd, s->sata0.ahci.ports); + ahci_ide_create_devs(&s->sata0.ahci, hd); + + return true; +} + static void ich9_init(Object *obj) { } @@ -64,6 +95,10 @@ static void ich9_realize(DeviceState *dev, Error **errp) if (s->d2p_enabled && !ich9_realize_d2p(s, errp)) { return; } + + if (s->sata_enabled && !ich9_realize_sata(s, errp)) { + return; + } } static void ich9_class_init(ObjectClass *klass, void *data) diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index d21638f4f9..226d7f6916 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -101,7 +101,6 @@ config Q35 select PCI_EXPRESS_Q35 select ICH9 select LPC_ICH9 - select AHCI_ICH9 select DIMM select SMBIOS select FW_CFG_DMA diff --git a/hw/southbridge/Kconfig b/hw/southbridge/Kconfig index db7259bf6f..f806033d48 100644 --- a/hw/southbridge/Kconfig +++ b/hw/southbridge/Kconfig @@ -4,3 +4,4 @@ config ICH9 bool depends on PCI_EXPRESS imply I82801B11 + select AHCI_ICH9 From patchwork Mon Feb 19 16:38:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 774101 Delivered-To: patch@linaro.org Received: by 2002:a5d:4943:0:b0:33b:4db1:f5b3 with SMTP id r3csp1253155wrs; Mon, 19 Feb 2024 08:41:09 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCX4i3mqLfbSSRpQlLjOcyi/skwT+sRLpqSjmpGaXFgpEQEwn0E0JpVjowegXcDwFqKt+uersZcZjb7VyY0fA/OV X-Google-Smtp-Source: AGHT+IHODfTP8nVnRZe6bNNxeTiiMOZGq58FmQmdPqjudfyHZBttcjaSdn8pjWukE5AzDzzAITDA X-Received: by 2002:a05:620a:190f:b0:787:6a5b:25ae with SMTP id bj15-20020a05620a190f00b007876a5b25aemr4681511qkb.28.1708360869010; Mon, 19 Feb 2024 08:41:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1708360868; cv=none; d=google.com; s=arc-20160816; b=vUgemcHqmIMO/++aiAauTdkVIlpWe7YzfGUnlOU72EHBDV6l8uFZGAklcLg4FEYAgh W9NTwhth7s7psJo9T8KdO8WLmIRA2gOThm3aMYztzm+TfGLBnROu75Y+uX67oNjoj0o8 6tqrDnNt7/jYTul14p/4qPXr/WSa3v9VoFNZRd3k6NjIHXDwnYP47m/3wlWb3ktTWJR/ fCqWAUEv6PezaSkgGTb77cGvHbG9IhplNPJURhc0tH1YkiJQF4rdp/cU8GiD5oOZ+m9p TpexqKSKjKmyySDEyZFMYbxnsswmy3eu5oTlgxfGUyEzMiQseaQRVg2uRIHuB9OXcYjL VZ3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=G3uRtm+UhgX23rdC9bJKVvQF8N8ZLI8dwwAO65r+PJ0=; fh=GFH0+Nfz+rN0IvTHf71Tn8mJWCh907g2jnPgVcMG7yo=; b=X1b8svy7NiJb63oCweeHrwCm0yoeNa8p6ExVjTdgW73RAztWWZlJagb7i2aNVDvLb2 JW1QCbnyDxp125rLosR0T9kK/HmSYERpkQqkB4WVZuScM+BISGkZ/fqgqnEYavFzKOv1 g0a7KcegFw4V5UcTiRmMymFxyatrQ95NKgb9+x2TPGTrBL5YigAJsszTiCqIKZhrQnFB oFFSUs2pTl66vymRXZHaLT4EvVHrY8jFBb8O1BtfD2FGAq/YMfWy5m9OCmu1hg9v0YfI 2g0OF3bNM3klBCFCY0l2ckJCn0uh8onpM/BhtyRcSb6Gxc4lsq8WstRZ4/C+9uS4Y8r6 OOwA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="EbljZkA/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y2-20020ae9f402000000b007875617a7easi5071399qkl.438.2024.02.19.08.41.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2024 08:41:08 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="EbljZkA/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rc6gh-0003Qf-SB; Mon, 19 Feb 2024 11:40:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rc6ge-0003AX-H9 for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:40:12 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rc6gc-0003Hk-KF for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:40:12 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-40fd72f7125so37727045e9.1 for ; Mon, 19 Feb 2024 08:40:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708360809; x=1708965609; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G3uRtm+UhgX23rdC9bJKVvQF8N8ZLI8dwwAO65r+PJ0=; b=EbljZkA/eq6Md6EybymS3SA/+562WW6Nrc1XEuDk0qxJ5ah+5/0WqcuXKUjflQ7lZb XHoQ32qg/0TVN975oh7pXAH5RZ1DJzp0tT6GGI9QXh/YpRVL5zwRnPPo+JwHP95JLQOq uS40kT1U66RTGKi/WaGfm7Vhk8OfzkAnPBwEY167R8BsBTuYmpoYY6IDe7ahSBueUtFm AKom226KEziCQC6muTTQ4RzX3DVu35TDtDuP3WjTs1UE9rNUtRCcPatJ+iVTX9Gyqhok zd+UzvjuoTjaDm7t/AqWPRbSspLS7h8CknNSQ9bzQw+2tLesFa/Hic1PYvSG+5rlA0V0 YjlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708360809; x=1708965609; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G3uRtm+UhgX23rdC9bJKVvQF8N8ZLI8dwwAO65r+PJ0=; b=HvDUFuHsBAuDT19ofG+S45nu7su35N/qwXuPfBGgF5ogIFzXiSq578POzobVDn6kVB agrLA80sv3c5m1zKcaWn3JFKndU1xDORQRxdzIS4g0CyIW50gc2ORsxzSd9eu/NG9gem MANoVDpJ33opFqvwG4k1deELgU0zdhdIXs51JOHhmIEBtysp6P9ENBljqbNvK+vJBch9 occ/vTlj/ZaEAS6tQ5QQJpzDVvMZJU5ta9jDv1XAdibT+rnRawWoADi0Vpng00JqIxp8 ObayoXONg8zC2szEImbVOw6wHkWUbm62ZzFl2L5oqdwMMIYG44902sxnYGDZW+df16Iy u0hw== X-Gm-Message-State: AOJu0YyM0BqRADoEozt8XW8ulECEEvb2eDdFWHxlDLeiXAENr6vgDSRE KkFZyleTFD9YjKv7Q3HlruqSpdp5cCQHAEwusxMIxUNKJZLLtNg7XeEoUFU3YGmSy83WS7gKUSI u X-Received: by 2002:a5d:5f47:0:b0:33d:5d4f:a45a with SMTP id cm7-20020a5d5f47000000b0033d5d4fa45amr1881140wrb.22.1708360808807; Mon, 19 Feb 2024 08:40:08 -0800 (PST) Received: from m1x-phil.lan ([176.176.181.220]) by smtp.gmail.com with ESMTPSA id i5-20020a05600011c500b0033cf095b9a2sm10827520wrx.78.2024.02.19.08.40.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 19 Feb 2024 08:40:08 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 10/14] hw/i2c/smbus: Extract QOM ICH9 definitions to 'smbus_ich9.h' Date: Mon, 19 Feb 2024 17:38:50 +0100 Message-ID: <20240219163855.87326-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Expose TYPE_ICH9_SMB_DEVICE to the new "hw/i2c/smbus_ich9.h" header. Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + include/hw/i2c/smbus_ich9.h | 25 +++++++++++++++++++++++++ hw/i2c/smbus_ich9.c | 15 ++------------- 3 files changed, 28 insertions(+), 13 deletions(-) create mode 100644 include/hw/i2c/smbus_ich9.h diff --git a/MAINTAINERS b/MAINTAINERS index 937ebb5c96..b896d953af 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2611,6 +2611,7 @@ F: hw/ide/ich.c F: hw/isa/lpc_ich9.c F: hw/southbridge/ich9.c F: include/hw/acpi/ich9*.h +F: include/hw/i2c/smbus_ich9.h F: include/hw/ide/ahci-pci.h F: include/hw/pci-bridge/ich_dmi_pci.h F: include/hw/southbridge/ich9.h diff --git a/include/hw/i2c/smbus_ich9.h b/include/hw/i2c/smbus_ich9.h new file mode 100644 index 0000000000..d716cbca33 --- /dev/null +++ b/include/hw/i2c/smbus_ich9.h @@ -0,0 +1,25 @@ +/* + * QEMU ICH9 SMBus emulation + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef HW_I2C_SMBUS_ICH9_H +#define HW_I2C_SMBUS_ICH9_H + +#include "qom/object.h" +#include "hw/pci/pci_device.h" +#include "hw/i2c/pm_smbus.h" + +#define TYPE_ICH9_SMB_DEVICE "ICH9-SMB" + +OBJECT_DECLARE_SIMPLE_TYPE(ICH9SMBState, ICH9_SMB_DEVICE) + +struct ICH9SMBState { + PCIDevice dev; + + bool irq_enabled; + + PMSMBus smb; +}; + +#endif diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c index 208f263ac5..3980bca4c5 100644 --- a/hw/i2c/smbus_ich9.c +++ b/hw/i2c/smbus_ich9.c @@ -1,5 +1,5 @@ /* - * ACPI implementation + * QEMU ICH9 SMBus emulation * * Copyright (c) 2006 Fabrice Bellard * Copyright (c) 2009 Isaku Yamahata @@ -22,8 +22,7 @@ #include "qemu/osdep.h" #include "qemu/range.h" -#include "hw/i2c/pm_smbus.h" -#include "hw/pci/pci.h" +#include "hw/i2c/smbus_ich9.h" #include "migration/vmstate.h" #include "qemu/module.h" @@ -31,16 +30,6 @@ #include "qom/object.h" #include "hw/acpi/acpi_aml_interface.h" -OBJECT_DECLARE_SIMPLE_TYPE(ICH9SMBState, ICH9_SMB_DEVICE) - -struct ICH9SMBState { - PCIDevice dev; - - bool irq_enabled; - - PMSMBus smb; -}; - static bool ich9_vmstate_need_smbus(void *opaque, int version_id) { return pm_smbus_vmstate_needed(); From patchwork Mon Feb 19 16:38:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 774096 Delivered-To: patch@linaro.org Received: by 2002:a5d:4943:0:b0:33b:4db1:f5b3 with SMTP id r3csp1252854wrs; Mon, 19 Feb 2024 08:40:32 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXxH78CmGK/cOnbbe6RAdFUpYDSERWmDEHsBEiIneipHYfah5DBTo4tO2fesKcJFEBYxUZ+UmroDV0GvWIj4I66 X-Google-Smtp-Source: AGHT+IEXtlSLdtXz87p0R+V4RoxC7iVaKyRw4QEyZTLeGAohapuLxHs26oAkxPNvGPFcyIaDK19f X-Received: by 2002:a05:622a:164f:b0:42c:5027:f34d with SMTP id y15-20020a05622a164f00b0042c5027f34dmr18008994qtj.66.1708360832008; Mon, 19 Feb 2024 08:40:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1708360831; cv=none; d=google.com; s=arc-20160816; b=NhS4Axtjt1b0tQq9QTOA4jDReAPfjrEecQ9JosUQDMrZbiGFIqolNX1HpZgX/eGwPT 391Hdh3pSSJQlIKp+3ye3GHhjFnvZr5D/XqxpaIVLB+Sm+lOWmwJ17YDbedRrz5KrenW gDTO2vNhQNCqri50dLVIS412xzshh6+GsLuwIvguEhO28H4Ah/YqgjuM9v69PxJLkfPY ajeX++mZGFUoGs8b8saAiqU1xkehSE11Q8sncwielxlP7rPjfn9VR3spen5JlnD/mfoM u5DFGZTStIu9zVU5xRC79Iq9nR5QveQfWQcdoHI4a3PjuQi41kE6E6mmfjTcROUa4INg PzBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wnW3NrES6EgGgUSsi0TQE7HA63k49t1HjgMoJkFxvYI=; fh=GFH0+Nfz+rN0IvTHf71Tn8mJWCh907g2jnPgVcMG7yo=; b=bsy5dRF2SzrPFLUfeQy3OLU/skYuXuVvzeKXhiu1xITe/wYwWiTRtdv/vzBAiyzcm/ U5LrXKw7+tHcV4jw5fEHKw2j2gTk0iHBEZy1G3otmdBRHYgVvHTwVJlZEbE5cbOUusd1 h2fiDL0UYtucFZbFS7zv61nraIGj22fBDmQm/gNpwNWwtVl+vyzeFEzDqOCzPCjuAW/8 KnnQCSXrnx3SvVJngeHKbQJOw6PA+zm8Xbwr1VqKXZKBh4DOnTdPBqrytVejzzL4Oued tRiX61z4pswtHHeDTqCACXu0za05SOhC3FPA3ZHRfUPtIw6MQubu9RnVp07RtFcfGX1S saQg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ISXE2Xv1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t22-20020ac85316000000b0042c67428c3dsi6018705qtn.784.2024.02.19.08.40.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2024 08:40:31 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ISXE2Xv1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rc6go-0004B5-KC; Mon, 19 Feb 2024 11:40:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rc6gm-00040z-RI for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:40:20 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rc6gk-0003Ig-Lz for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:40:20 -0500 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-3394b892691so2544684f8f.1 for ; Mon, 19 Feb 2024 08:40:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708360816; x=1708965616; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wnW3NrES6EgGgUSsi0TQE7HA63k49t1HjgMoJkFxvYI=; b=ISXE2Xv1Hg75yvYpo70bPxGahWsoJyl4n0DUW2AxV/4Ve2uxMTsvLdKE7VXorxITHk eGVhPLYo7irB+p/qmeMFdLJwIr2vHWa7/cf8ynuRhLk/fcWCvlwHYrPHPWrZHhXpnc0K rCx+YcLsFzmjc3btf0FbH/ZO7HCue9nlfdwfd8ArvWCPH+UEVS6nEDf577093cjjsJTE Ks4T5URfHnAkN+sVqEYAW/yEKbixeVgcFnzbogQOemwQ8ao5aWz/+cqNJkWAZRk4lPf7 YQ1fxW3iaTFm3L4vhNO3ARIxOqNynfE4qrvFBIUgLBykVnKgA/IX03d/bS69QIlHr80u 8yzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708360816; x=1708965616; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wnW3NrES6EgGgUSsi0TQE7HA63k49t1HjgMoJkFxvYI=; b=nBCis1vkGLc8t1H9md+ZpWLCdczYIjvd50p/wSs9brbonNpNN0c4Q2dg03VeevXExG IH/36dP0A1WtOwnFu6wCTpbp1K8x6O9qQpuSEGJNPLtyjotwranKW2H01HAJhAywTEhm ASvJl4DziFtS3Zjg1gefdHhWone3BM3UhzxK9SUlaTulo+xJYAq3eR7Mztia7CJBdO9w gM7As/uZ25qL4gRPFuVOY+Rs3YBKicQVIpT1O+ZEbttcqFig36zQ6f7qCqGm7N4vNK0q IvglH3gS/YcavHqjPljsoyOyBORamlPL26BEZOAON2mOYSkfkumFl41RnZDLINbnh6G0 1llQ== X-Gm-Message-State: AOJu0Yx6aIB+6+ljzF7jZH6QcAA5X6sVztyYKO7+TTq6FJQDiyU6eoCk 5RPIzLaP/SURA2OlDy8WgarLCZyGPnMt78bmL07b0/E/9P0WpRUhNpkw4m5ea37D84hT/BK/aAi A X-Received: by 2002:adf:ec4e:0:b0:33d:5472:5751 with SMTP id w14-20020adfec4e000000b0033d54725751mr2195354wrn.10.1708360816209; Mon, 19 Feb 2024 08:40:16 -0800 (PST) Received: from m1x-phil.lan ([176.176.181.220]) by smtp.gmail.com with ESMTPSA id bw2-20020a0560001f8200b003392206c808sm4803778wrb.105.2024.02.19.08.40.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 19 Feb 2024 08:40:15 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 11/14] hw/southbridge/ich9: Add the SMBus function Date: Mon, 19 Feb 2024 17:38:51 +0100 Message-ID: <20240219163855.87326-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instantiate TYPE_ICH9_SMB_DEVICE in TYPE_ICH9_SOUTHBRIDGE. Since the PC machines can disable SMBus (see the PC_MACHINE_SMBUS dynamic property), add the 'smbus-enabled' property to disable it. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/southbridge/ich9.h | 32 -------------------------------- hw/i2c/smbus_ich9.c | 29 ++++++++++++++++++++++++++++- hw/i386/pc_q35.c | 10 ++-------- hw/southbridge/ich9.c | 21 +++++++++++++++++++++ hw/southbridge/Kconfig | 1 + 5 files changed, 52 insertions(+), 41 deletions(-) diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index ac7f9f4ff5..d4b299bf3c 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -173,38 +173,6 @@ struct ICH9LPCState { #define ICH9_APM_ACPI_ENABLE 0x2 #define ICH9_APM_ACPI_DISABLE 0x3 - -/* D31:F3 SMBus controller */ -#define TYPE_ICH9_SMB_DEVICE "ICH9-SMB" - -#define ICH9_A2_SMB_REVISION 0x02 -#define ICH9_SMB_PI 0x00 - -#define ICH9_SMB_SMBMBAR0 0x10 -#define ICH9_SMB_SMBMBAR1 0x14 -#define ICH9_SMB_SMBM_BAR 0 -#define ICH9_SMB_SMBM_SIZE (1 << 8) -#define ICH9_SMB_SMB_BASE 0x20 -#define ICH9_SMB_SMB_BASE_BAR 4 -#define ICH9_SMB_SMB_BASE_SIZE (1 << 5) -#define ICH9_SMB_HOSTC 0x40 -#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3)) -#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2)) -#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1)) -#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0)) - -/* D31:F3 SMBus I/O and memory mapped I/O registers */ -#define ICH9_SMB_DEV 31 -#define ICH9_SMB_FUNC 3 - -#define ICH9_SMB_HST_STS 0x00 -#define ICH9_SMB_HST_CNT 0x02 -#define ICH9_SMB_HST_CMD 0x03 -#define ICH9_SMB_XMIT_SLVA 0x04 -#define ICH9_SMB_HST_D0 0x05 -#define ICH9_SMB_HST_D1 0x06 -#define ICH9_SMB_HOST_BLOCK_DB 0x07 - #define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features" /* bit positions used in fw_cfg SMI feature negotiation */ diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c index 3980bca4c5..2c18278090 100644 --- a/hw/i2c/smbus_ich9.c +++ b/hw/i2c/smbus_ich9.c @@ -26,10 +26,37 @@ #include "migration/vmstate.h" #include "qemu/module.h" -#include "hw/southbridge/ich9.h" #include "qom/object.h" #include "hw/acpi/acpi_aml_interface.h" +/* D31:F3 SMBus controller */ + +#define ICH9_A2_SMB_REVISION 0x02 +#define ICH9_SMB_PI 0x00 + +#define ICH9_SMB_SMBMBAR0 0x10 +#define ICH9_SMB_SMBMBAR1 0x14 +#define ICH9_SMB_SMBM_BAR 0 +#define ICH9_SMB_SMBM_SIZE (1 << 8) +#define ICH9_SMB_SMB_BASE 0x20 +#define ICH9_SMB_SMB_BASE_BAR 4 +#define ICH9_SMB_SMB_BASE_SIZE (1 << 5) +#define ICH9_SMB_HOSTC 0x40 +#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3)) +#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2)) +#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1)) +#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0)) + +/* D31:F3 SMBus I/O and memory mapped I/O registers */ + +#define ICH9_SMB_HST_STS 0x00 +#define ICH9_SMB_HST_CNT 0x02 +#define ICH9_SMB_HST_CMD 0x03 +#define ICH9_SMB_XMIT_SLVA 0x04 +#define ICH9_SMB_HST_D0 0x05 +#define ICH9_SMB_HST_D1 0x06 +#define ICH9_SMB_HOST_BLOCK_DB 0x07 + static bool ich9_vmstate_need_smbus(void *opaque, int version_id) { return pm_smbus_vmstate_needed(); diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 060358d449..7f6ced8a6e 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -236,6 +236,7 @@ static void pc_q35_init(MachineState *machine) OBJECT(host_bus), &error_abort); qdev_prop_set_bit(ich9, "d2p-enabled", false); qdev_prop_set_bit(ich9, "sata-enabled", pcms->sata_enabled); + qdev_prop_set_bit(ich9, "smbus-enabled", pcms->smbus_enabled); qdev_realize_and_unref(ich9, NULL, &error_fatal); /* irq lines */ @@ -309,15 +310,8 @@ static void pc_q35_init(MachineState *machine) } if (pcms->smbus_enabled) { - PCIDevice *smb; - + pcms->smbus = I2C_BUS(qdev_get_child_bus(ich9, "i2c")); /* TODO: Populate SPD eeprom data. */ - smb = pci_create_simple_multifunction(host_bus, - PCI_DEVFN(ICH9_SMB_DEV, - ICH9_SMB_FUNC), - TYPE_ICH9_SMB_DEVICE); - pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c")); - smbus_eeprom_init(pcms->smbus, 8, NULL, 0); } diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c index 233dc1c5d7..4d2c298666 100644 --- a/hw/southbridge/ich9.c +++ b/hw/southbridge/ich9.c @@ -15,9 +15,11 @@ #include "hw/pci-bridge/ich_dmi_pci.h" #include "hw/ide/ahci-pci.h" #include "hw/ide.h" +#include "hw/i2c/smbus_ich9.h" #define ICH9_D2P_DEVFN PCI_DEVFN(30, 0) #define ICH9_SATA1_DEVFN PCI_DEVFN(31, 2) +#define ICH9_SMB_DEVFN PCI_DEVFN(31, 3) #define SATA_PORTS 6 @@ -26,10 +28,12 @@ struct ICH9State { I82801b11Bridge d2p; AHCIPCIState sata0; + ICH9SMBState smb; PCIBus *pci_bus; bool d2p_enabled; bool sata_enabled; + bool smbus_enabled; }; static Property ich9_props[] = { @@ -37,6 +41,7 @@ static Property ich9_props[] = { TYPE_PCIE_BUS, PCIBus *), DEFINE_PROP_BOOL("d2p-enabled", ICH9State, d2p_enabled, true), DEFINE_PROP_BOOL("sata-enabled", ICH9State, sata_enabled, true), + DEFINE_PROP_BOOL("smbus-enabled", ICH9State, smbus_enabled, true), DEFINE_PROP_END_OF_LIST(), }; @@ -79,6 +84,18 @@ static bool ich9_realize_sata(ICH9State *s, Error **errp) return true; } +static bool ich9_realize_smbus(ICH9State *s, Error **errp) +{ + object_initialize_child(OBJECT(s), "smb", &s->smb, TYPE_ICH9_SMB_DEVICE); + qdev_prop_set_int32(DEVICE(&s->smb), "addr", ICH9_SMB_DEVFN); + if (!qdev_realize(DEVICE(&s->smb), BUS(s->pci_bus), errp)) { + return false; + } + object_property_add_alias(OBJECT(s), "i2c", OBJECT(&s->smb), "i2c"); + + return true; +} + static void ich9_init(Object *obj) { } @@ -99,6 +116,10 @@ static void ich9_realize(DeviceState *dev, Error **errp) if (s->sata_enabled && !ich9_realize_sata(s, errp)) { return; } + + if (s->smbus_enabled && !ich9_realize_smbus(s, errp)) { + return; + } } static void ich9_class_init(ObjectClass *klass, void *data) diff --git a/hw/southbridge/Kconfig b/hw/southbridge/Kconfig index f806033d48..03e89a55d1 100644 --- a/hw/southbridge/Kconfig +++ b/hw/southbridge/Kconfig @@ -5,3 +5,4 @@ config ICH9 depends on PCI_EXPRESS imply I82801B11 select AHCI_ICH9 + select ACPI_ICH9 From patchwork Mon Feb 19 16:38:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 774098 Delivered-To: patch@linaro.org Received: by 2002:a5d:4943:0:b0:33b:4db1:f5b3 with SMTP id r3csp1253033wrs; Mon, 19 Feb 2024 08:40:53 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXkweG6OcOFM7TT9p2lj9XbAbFW02fDPYSYie7Y3fmqEi4WEVThMFMoUAv6EAtvH15K9929MQi4cJaV3k6cjAyN X-Google-Smtp-Source: AGHT+IGvWPDkO1/6n516u3kbOs5Bbwj2/66pw4+qz3uJfbw/G7ZxvxKtzQ4D0lFbc0kQNlZtQ9lx X-Received: by 2002:a05:6102:c08:b0:470:29d8:f5db with SMTP id x8-20020a0561020c0800b0047029d8f5dbmr8724121vss.33.1708360852984; Mon, 19 Feb 2024 08:40:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1708360852; cv=none; d=google.com; s=arc-20160816; b=P951gzdH8lxCHqbOuBp0Vbdq5uiOQGPNtNOPXiucprWpk8fn43QsHBdSZa8gi1SHF5 Kt07OTIzDgYAd2UtKmGbJqGFLYdjjz33o40VEuc1CwTYyZzEH1s2N6TEBuSApJrVooO6 DIG5LD6Gyj12pyW3mWNGej+iW3oYi3JxoRfz4cXJRiQqs0rU44DArYk3hvvO45xGRI8R 7MllOPdFqHR0FC0GiugbCQH8kCY2bg7QvesLY3X00MuSg3orgdZc1xbaa6vDVkQQUGi9 W3VzFkhJQvzApjWDFisls3BABjigF6WGmZ+6ZOkLgLhAaPqkGiLkbBjvqhThYJSeouPC DoVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=IWlF+UpmhJ8SFg+x+XwkbZFwwWh6ItdJHO548hO5izE=; fh=GFH0+Nfz+rN0IvTHf71Tn8mJWCh907g2jnPgVcMG7yo=; b=OTMud23fEfAyQiEChpsrRRJ3q8jU7i8kXZ9Piu3v3mArMhxVr2E5oFw6h1u1b0kOq1 IfavpFXnA/B38DfUT0iQj4WqyqbiKgHLQZl9+/CGjVtmUjh/23dK8l7VheoE5/FF8+G3 uB6v5JAu0a8SC5m6YqUiQzNnEzF6zy7nh+Ebqeuv168fH7lfn0fk5ZrZMo8RCkG7JBy4 7GL5hMqplm8Hw/HEvzFxMQNWYq1Tkb3PSh5k/pgR1chLmUbhe8AjbRZPhXRBjXjAjJG/ WrZ/aZXyIcE6lVOHxChmFLLLX+wNfg5xRTlAT4+V12hlatmzcUd8FdkWUfjozWsGs5q5 fKHA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="S/7ee+AV"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id dt46-20020a05620a47ae00b0078756ecb887si5039038qkb.392.2024.02.19.08.40.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2024 08:40:52 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="S/7ee+AV"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rc6gw-0004YS-Tt; Mon, 19 Feb 2024 11:40:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rc6gu-0004SX-WC for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:40:29 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rc6gq-0003KW-Qt for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:40:28 -0500 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-33d509ab80eso495355f8f.3 for ; Mon, 19 Feb 2024 08:40:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708360823; x=1708965623; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IWlF+UpmhJ8SFg+x+XwkbZFwwWh6ItdJHO548hO5izE=; b=S/7ee+AVbOSHWgPQmIqKlfmhtGdZJMq/sVml8xZ8IB5KHtoYg05Ck7ISd13PVFXMBs DeEHO1kufZm/AfGrnXmMRsh2aZh3MMg7kZrDMNj+zzhhgEjlaXuEno5HFX9RGuAB39ve ScLOF61ctqDVwicvqWKRAsQbIrBXlJ6rie+BL94CYhvDDFvTs7ah7zQLaKuX83ehKCec NBfo6H0bGe5XjAOjTKGwufocbLBKrLEbCkSnkIInaZyonLZuO1A2KynztOzQlxkO2bTC LVCrcPHjOKB8qr6ncmpm7QT5nLphdGTHzRnJIe4sBOz9DppSiQfoUCOaz7tzacfTFMYR Mppw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708360823; x=1708965623; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IWlF+UpmhJ8SFg+x+XwkbZFwwWh6ItdJHO548hO5izE=; b=U/1K1UEcZkdac5jEM6W7GXR6w017cIAC+hMrLIyrWLAmphew3EDckkExoPIE1BsFDy kk2Py/GjWeTV/x+miRV8dbAy1Oc5g1BRIb9iLJ38Cz9lla/3NTb5N/QPMH2v9Ea+f5kF zUnUR0dqjsC+x61jVyu+BOzbDGmVMvPL/YF63E3HTv39vvvwekazZLTz2Pta+W4EohT0 eTNxKOwmJ6jMDf96Q0BTHguRkMJn0kR21aTWcGk22CZmOCMH6AQwMHovXBEBURny74b2 FnrElrg/ReuMjKPp+0anEPeThFgN/Zj47aZJ80W94qNEJXnJyT3ZRLxei/3qSCANDHtF GA4A== X-Gm-Message-State: AOJu0YxpGBjL/gA9vOCwvrq2cXCq1qrT5UdyK2Njojq7K541iWpAxssw UouSYLlvhfbxy/QjprqMPokguxUpotCUunAVbY3Em5wjEKZTFuwa+rFBLuUKe56DUIpZQS+shVu h X-Received: by 2002:adf:e6c3:0:b0:33c:dd33:90cb with SMTP id y3-20020adfe6c3000000b0033cdd3390cbmr9110031wrm.14.1708360823077; Mon, 19 Feb 2024 08:40:23 -0800 (PST) Received: from m1x-phil.lan ([176.176.181.220]) by smtp.gmail.com with ESMTPSA id co18-20020a0560000a1200b0033d4c3b0beesm4576863wrb.19.2024.02.19.08.40.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 19 Feb 2024 08:40:22 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 12/14] hw/southbridge/ich9: Add the USB EHCI/UHCI functions Date: Mon, 19 Feb 2024 17:38:52 +0100 Message-ID: <20240219163855.87326-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instantiate EHCI and UHCI in TYPE_ICH9_SOUTHBRIDGE. Since machines can disable USB, add the 'ehci-count' property. Machine can disable USB functions by setting ehci-count=0. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/southbridge/ich9.h | 5 --- hw/i386/pc_q35.c | 62 ++--------------------------------- hw/southbridge/ich9.c | 54 ++++++++++++++++++++++++++++++ hw/southbridge/Kconfig | 2 ++ 4 files changed, 58 insertions(+), 65 deletions(-) diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index d4b299bf3c..7e75496b0b 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -103,11 +103,6 @@ struct ICH9LPCState { #define ICH9_PCIE_DEV 28 #define ICH9_PCIE_FUNC_MAX 6 - -/* D29:F0 USB UHCI Controller #1 */ -#define ICH9_USB_UHCI1_DEV 29 -#define ICH9_USB_UHCI1_FUNC 0 - /* D31:F0 LPC Processor Interface */ #define ICH9_RST_CNT_IOPORT 0xCF9 diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 7f6ced8a6e..e5f5bb0db1 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -50,8 +50,6 @@ #include "hw/ide/ahci-pci.h" #include "hw/intc/ioapic.h" #include "hw/southbridge/ich9.h" -#include "hw/usb.h" -#include "hw/usb/hcd-uhci.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/numa.h" @@ -61,59 +59,6 @@ #include "hw/acpi/acpi.h" #include "target/i386/cpu.h" -struct ehci_companions { - const char *name; - int func; - int port; -}; - -static const struct ehci_companions ich9_1d[] = { - { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 }, - { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 }, - { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 }, -}; - -static const struct ehci_companions ich9_1a[] = { - { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 }, - { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 }, - { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 }, -}; - -static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) -{ - const struct ehci_companions *comp; - PCIDevice *ehci, *uhci; - BusState *usbbus; - const char *name; - int i; - - switch (slot) { - case 0x1d: - name = "ich9-usb-ehci1"; - comp = ich9_1d; - break; - case 0x1a: - name = "ich9-usb-ehci2"; - comp = ich9_1a; - break; - default: - return -1; - } - - ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), name); - pci_realize_and_unref(ehci, bus, &error_fatal); - usbbus = QLIST_FIRST(&ehci->qdev.child_bus); - - for (i = 0; i < 3; i++) { - uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), - comp[i].name); - qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); - qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); - pci_realize_and_unref(uhci, bus, &error_fatal); - } - return 0; -} - /* PC hardware initialisation */ static void pc_q35_init(MachineState *machine) { @@ -237,6 +182,8 @@ static void pc_q35_init(MachineState *machine) qdev_prop_set_bit(ich9, "d2p-enabled", false); qdev_prop_set_bit(ich9, "sata-enabled", pcms->sata_enabled); qdev_prop_set_bit(ich9, "smbus-enabled", pcms->smbus_enabled); + /* Should we create 6 UHCI according to ich9 spec? */ + qdev_prop_set_uint8(ich9, "ehci-count", machine_usb(machine) ? 1 : 0); qdev_realize_and_unref(ich9, NULL, &error_fatal); /* irq lines */ @@ -304,11 +251,6 @@ static void pc_q35_init(MachineState *machine) idebus[1] = qdev_get_child_bus(ich9, "ide.1"); } - if (machine_usb(machine)) { - /* Should we create 6 UHCI according to ich9 spec? */ - ehci_create_ich9_with_companions(host_bus, 0x1d); - } - if (pcms->smbus_enabled) { pcms->smbus = I2C_BUS(qdev_get_child_bus(ich9, "i2c")); /* TODO: Populate SPD eeprom data. */ diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c index 4d2c298666..085d75e569 100644 --- a/hw/southbridge/ich9.c +++ b/hw/southbridge/ich9.c @@ -16,12 +16,18 @@ #include "hw/ide/ahci-pci.h" #include "hw/ide.h" #include "hw/i2c/smbus_ich9.h" +#include "hw/usb.h" +#include "hw/usb/hcd-ehci.h" +#include "hw/usb/hcd-uhci.h" #define ICH9_D2P_DEVFN PCI_DEVFN(30, 0) #define ICH9_SATA1_DEVFN PCI_DEVFN(31, 2) #define ICH9_SMB_DEVFN PCI_DEVFN(31, 3) +#define ICH9_EHCI_FUNC 7 #define SATA_PORTS 6 +#define EHCI_PER_FN 2 +#define UHCI_PER_FN 3 struct ICH9State { DeviceState parent_obj; @@ -29,11 +35,14 @@ struct ICH9State { I82801b11Bridge d2p; AHCIPCIState sata0; ICH9SMBState smb; + EHCIPCIState ehci[EHCI_PER_FN]; + UHCIState uhci[EHCI_PER_FN * UHCI_PER_FN]; PCIBus *pci_bus; bool d2p_enabled; bool sata_enabled; bool smbus_enabled; + uint8_t ehci_count; }; static Property ich9_props[] = { @@ -42,6 +51,7 @@ static Property ich9_props[] = { DEFINE_PROP_BOOL("d2p-enabled", ICH9State, d2p_enabled, true), DEFINE_PROP_BOOL("sata-enabled", ICH9State, sata_enabled, true), DEFINE_PROP_BOOL("smbus-enabled", ICH9State, smbus_enabled, true), + DEFINE_PROP_UINT8("ehci-count", ICH9State, ehci_count, 2), DEFINE_PROP_END_OF_LIST(), }; @@ -96,6 +106,46 @@ static bool ich9_realize_smbus(ICH9State *s, Error **errp) return true; } +static bool ich9_realize_usb(ICH9State *s, Error **errp) +{ + if (!module_object_class_by_name(TYPE_ICH9_USB_UHCI(0)) + || !module_object_class_by_name("ich9-usb-ehci0")) { + error_setg(errp, "USB functions not available in this build"); + return false; + } + for (unsigned e = 0; e < s->ehci_count; e++) { + g_autofree gchar *ename = g_strdup_printf("ich9-usb-ehci%u", e + 1); + EHCIPCIState *ehci = &s->ehci[e]; + const unsigned devid = e ? 0x1a : 0x1d; + BusState *masterbus; + + object_initialize_child(OBJECT(s), "ehci[*]", ehci, ename); + qdev_prop_set_int32(DEVICE(ehci), "addr", PCI_DEVFN(devid, + ICH9_EHCI_FUNC)); + if (!qdev_realize(DEVICE(ehci), BUS(s->pci_bus), errp)) { + return false; + } + masterbus = QLIST_FIRST(&DEVICE(ehci)->child_bus); + + for (unsigned u = 0; u < UHCI_PER_FN; u++) { + unsigned c = UHCI_PER_FN * e + u; + UHCIState *uhci = &s->uhci[c]; + g_autofree gchar *cname = g_strdup_printf("ich9-usb-uhci%u", c + 1); + + object_initialize_child(OBJECT(s), "uhci[*]", uhci, cname); + qdev_prop_set_bit(DEVICE(uhci), "multifunction", true); + qdev_prop_set_int32(DEVICE(uhci), "addr", PCI_DEVFN(devid, u)); + qdev_prop_set_string(DEVICE(uhci), "masterbus", masterbus->name); + qdev_prop_set_uint32(DEVICE(uhci), "firstport", 2 * u); + if (!qdev_realize(DEVICE(uhci), BUS(s->pci_bus), errp)) { + return false; + } + } + } + + return true; +} + static void ich9_init(Object *obj) { } @@ -120,6 +170,10 @@ static void ich9_realize(DeviceState *dev, Error **errp) if (s->smbus_enabled && !ich9_realize_smbus(s, errp)) { return; } + + if (!ich9_realize_usb(s, errp)) { + return; + } } static void ich9_class_init(ObjectClass *klass, void *data) diff --git a/hw/southbridge/Kconfig b/hw/southbridge/Kconfig index 03e89a55d1..31eb125bf7 100644 --- a/hw/southbridge/Kconfig +++ b/hw/southbridge/Kconfig @@ -6,3 +6,5 @@ config ICH9 imply I82801B11 select AHCI_ICH9 select ACPI_ICH9 + imply USB_EHCI_PCI + imply USB_UHCI From patchwork Mon Feb 19 16:38:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 774103 Delivered-To: patch@linaro.org Received: by 2002:a5d:4943:0:b0:33b:4db1:f5b3 with SMTP id r3csp1253281wrs; Mon, 19 Feb 2024 08:41:24 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU63ndKfWBs+DqEjfOJCL8BC1Rlw0JwgfYVv0zMx0UBK07uhs4pKk1y6i9WcylTm+OxSRnnlYnu4CyEYtAz0Rst X-Google-Smtp-Source: AGHT+IGnHEZXffE9CSWKLx8Qjp5vDj1XCzLurJF2veOFDCJNMPiqXXJbnfuSOJvYXt9bodH/Ir1o X-Received: by 2002:a05:620a:4590:b0:787:3519:d27d with SMTP id bp16-20020a05620a459000b007873519d27dmr18588380qkb.36.1708360883958; Mon, 19 Feb 2024 08:41:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1708360883; cv=none; d=google.com; s=arc-20160816; b=M3FLyYCfvVeIX1lRcifZGm9dzdSBDw9mr2GVEAxaMAfiYfx4wt6dV3blN9GfRiQDnc gnGjkSZ3QmpDHgZJXEBzBFMQF+9ZqICeYlWTbqgsEP3xNs7+JDMLCHLCWSUtDlzugm1w mzb41C7YijN11SW/yalvqCg2Kiz/OTZF2uZEmEF0VQ6MSCG/2HAihS2qp111CUZs9TbD BDuPiguveh9O8EbtJMTZDypY3FEzriMF3c81PmmdmVmTs0aAKNtgTk0LMVcoZKAnUfj6 vlWgmoHs8Rl76s+YK9o6Y22kfS5lmd220kr3AbqNt6jNZQU/ziOZ42UoF8vqtG4udDAY eMbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xfCswE87MrfEEdDQPiTzQH8oIwvxhRBQgelgWfBP5LM=; fh=GFH0+Nfz+rN0IvTHf71Tn8mJWCh907g2jnPgVcMG7yo=; b=kkbNHvUCo5jWGycGX3m8qoC60tetDRfypyYZvwUPHOobw5zIK3iaOUSD1xdR1wKpYI OiM7b2MR1gzpyosu8khON0z9Wg6Ir78VBmYwdEIgkfegwn5mBg4AysKFTGFH1WKN6T1P 2QqdralCYEpz9AF1nRinHLTyzviFZjTtQDiD5Rapp4sF9c3uEz8MsNPNIqDNmGJNWyd4 nqtmgdzkfu9JrSI+/9/trBjUG86/ctqa2twMB+C/wWfeyOsUsRj6A1Pfqr8WOl8OGQz/ Ok8eQB9/gCsc6cYLqFtwSXS8rlxHv+ZZN886WK9MTiCtlVH0jCwY12C1mvZzC6Js/Kqr ngUg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Zh5nGvje; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id dw6-20020a05620a600600b00787722a29ecsi882867qkb.163.2024.02.19.08.41.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2024 08:41:23 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Zh5nGvje; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rc6h2-0004ih-Mm; Mon, 19 Feb 2024 11:40:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rc6h0-0004hV-Nc for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:40:34 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rc6gy-0003P9-0Z for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:40:34 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4125cf71eecso14640245e9.1 for ; Mon, 19 Feb 2024 08:40:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708360830; x=1708965630; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xfCswE87MrfEEdDQPiTzQH8oIwvxhRBQgelgWfBP5LM=; b=Zh5nGvjeX2vuCCF8aVGOXnnzOXVqWcn4Z5cpWtf2lDAojYjwz8f02/1gY08QSRhLa4 YoH7NxlERmAMLjt2R78pPEssv0L9MUunJHMtBSQxcHSgA1oyMOafP6qiiEq2mZJxD/lG 7TAwT8d9AvOA9a76Mt6SWW7JjQqLrAx4g2HCQBF5Wl7NW1KEwe/NMntXlUsIpmo7Lp/F N3sxMguQdkIHje9fZmrLCR+M2AZgdq8hQQ+4FIU5vMO5i6TwQRYNp9dph1qxJPaSI7VN Bi8pZ1AR4NfRFJdw9tTUMaAZG23yx2yLuUWe11+qaOb8kl/nleznp7vFqJbXrHvbsPk9 mHKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708360830; x=1708965630; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xfCswE87MrfEEdDQPiTzQH8oIwvxhRBQgelgWfBP5LM=; b=qKYkfQynqBi2LnG0LCy/tLFZqjLcgwE4ZNP3zBv0S69eLaxKBRLmWTWLHy9ocqOE75 wvIH5swnf2JC1Ibjuc/9swjMicUbY8cuff0Tt6dqUTjl6IDXWQx8NhMnE0r1Gin32lPU 71Jb7C8VsNtpeav57DNky/yh9IxdsddjjlspYkTIKTY8axPly/jIjBUXSpiwGhpu21Wv ct4Yp+YWBdajJGfs0TxJoV11eaSsodaCDIgCdoeqrGARASAdfBfg1tqVMhXxgeeHPoy+ LG0e3RyVQEpqQIwHn+R1O9C0NdKam84krK0tb5rmWwLGwSkRRy9t/ymDg7VXTMCRZWSA JvRg== X-Gm-Message-State: AOJu0YybvCGPxMMtiGvLYdX5ZJCZDGZBvCndya74JFjNHKJCw45rtcx9 ah1j8ephTWtYmiZotffDIptrwFGhfsYh92W0vSpneVaQatqv3ncqoUaToXnAysv3B8QZ8ZxzW0b 1 X-Received: by 2002:a05:600c:21d8:b0:411:e398:ca7a with SMTP id x24-20020a05600c21d800b00411e398ca7amr10332822wmj.39.1708360829860; Mon, 19 Feb 2024 08:40:29 -0800 (PST) Received: from m1x-phil.lan ([176.176.181.220]) by smtp.gmail.com with ESMTPSA id n24-20020a7bcbd8000000b004120c134b40sm11683469wmi.22.2024.02.19.08.40.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 19 Feb 2024 08:40:29 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 13/14] hw/southbridge/ich9: Extract LPC definitions to 'hw/isa/ich9_lpc.h' Date: Mon, 19 Feb 2024 17:38:53 +0100 Message-ID: <20240219163855.87326-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Restrict ICH9 LPC/ISA definitions by moving them to the "hw/isa/ich9_lpc.h" header. Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + include/hw/isa/ich9_lpc.h | 166 ++++++++++++++++++++++++++++++++++ include/hw/southbridge/ich9.h | 158 ++------------------------------ hw/acpi/ich9.c | 1 + hw/acpi/ich9_tco.c | 1 + hw/i386/acpi-build.c | 1 + hw/i386/pc_q35.c | 1 + hw/isa/lpc_ich9.c | 34 ++++++- tests/qtest/tco-test.c | 2 +- 9 files changed, 208 insertions(+), 157 deletions(-) create mode 100644 include/hw/isa/ich9_lpc.h diff --git a/MAINTAINERS b/MAINTAINERS index b896d953af..31ddbc565b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2613,6 +2613,7 @@ F: hw/southbridge/ich9.c F: include/hw/acpi/ich9*.h F: include/hw/i2c/smbus_ich9.h F: include/hw/ide/ahci-pci.h +F: include/hw/isa/ich9_lpc.h F: include/hw/pci-bridge/ich_dmi_pci.h F: include/hw/southbridge/ich9.h diff --git a/include/hw/isa/ich9_lpc.h b/include/hw/isa/ich9_lpc.h new file mode 100644 index 0000000000..b64d88b395 --- /dev/null +++ b/include/hw/isa/ich9_lpc.h @@ -0,0 +1,166 @@ +/* + * QEMU ICH9 PCI-to-LPC/ISA bridge emulation + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ISA_ICH9_LPC_H +#define HW_ISA_ICH9_LPC_H + +#include "exec/memory.h" +#include "hw/isa/apm.h" +#include "hw/acpi/ich9.h" +#include "hw/intc/ioapic.h" +#include "hw/pci/pci_device.h" +#include "hw/rtc/mc146818rtc.h" +#include "qemu/notify.h" +#include "qom/object.h" + +#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC" +OBJECT_DECLARE_SIMPLE_TYPE(ICH9LPCState, ICH9_LPC_DEVICE) + +#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */ + +struct ICH9LPCState { + /* ICH9 LPC PCI to ISA bridge */ + PCIDevice d; + + /* (pci device, intx) -> pirq + * In real chipset case, the unused slots are never used + * as ICH9 supports only D25-D31 irq routing. + * On the other hand in qemu case, any slot/function can be populated + * via command line option. + * So fallback interrupt routing for any devices in any slots is necessary. + */ + uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; + + MC146818RtcState rtc; + APMState apm; + ICH9LPCPMRegs pm; + uint32_t sci_level; /* track sci level */ + uint8_t sci_gsi; + + /* 2.24 Pin Straps */ + struct { + bool spkr_hi; + } pin_strap; + + /* 10.1 Chipset Configuration registers(Memory Space) + which is pointed by RCBA */ + uint8_t chip_config[ICH9_CC_SIZE]; + + /* + * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0) + * + * register contents and IO memory region + */ + uint8_t rst_cnt; + MemoryRegion rst_cnt_mem; + + /* SMI feature negotiation via fw_cfg */ + uint64_t smi_host_features; /* guest-invisible, host endian */ + uint8_t smi_host_features_le[8]; /* guest-visible, read-only, little + * endian uint64_t */ + uint8_t smi_guest_features_le[8]; /* guest-visible, read-write, little + * endian uint64_t */ + uint8_t smi_features_ok; /* guest-visible, read-only; selecting it + * triggers feature lockdown */ + uint64_t smi_negotiated_features; /* guest-invisible, host endian */ + + MemoryRegion rcrb_mem; /* root complex register block */ + Notifier machine_ready; + + qemu_irq gsi[IOAPIC_NUM_PINS]; +}; + +#define ICH9_MASK(bit, ms_bit, ls_bit) \ +((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) + +#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */ + +/* ICH9: Chipset Configuration Registers */ +#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1) + +#define ICH9_CC +#define ICH9_CC_D28IP 0x310C +#define ICH9_CC_D28IP_SHIFT 4 +#define ICH9_CC_D28IP_MASK 0xf +#define ICH9_CC_D28IP_DEFAULT 0x00214321 +#define ICH9_CC_D31IR 0x3140 +#define ICH9_CC_D30IR 0x3142 +#define ICH9_CC_D29IR 0x3144 +#define ICH9_CC_D28IR 0x3146 +#define ICH9_CC_D27IR 0x3148 +#define ICH9_CC_D26IR 0x314C +#define ICH9_CC_D25IR 0x3150 +#define ICH9_CC_DIR_DEFAULT 0x3210 +#define ICH9_CC_D30IR_DEFAULT 0x0 +#define ICH9_CC_DIR_SHIFT 4 +#define ICH9_CC_DIR_MASK 0x7 +#define ICH9_CC_OIC 0x31FF +#define ICH9_CC_OIC_AEN 0x1 +#define ICH9_CC_GCS 0x3410 +#define ICH9_CC_GCS_DEFAULT 0x00000020 +#define ICH9_CC_GCS_NO_REBOOT (1 << 5) + +/* D31:F0 LPC Processor Interface */ +#define ICH9_RST_CNT_IOPORT 0xCF9 + +/* D31:F1 LPC controller */ +#define ICH9_A2_LPC "ICH9 A2 LPC" +#define ICH9_A2_LPC_SAVEVM_VERSION 0 + +#define ICH9_A2_LPC_REVISION 0x2 +#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */ + +#define ICH9_LPC_PMBASE 0x40 +#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK ICH9_MASK(32, 15, 7) +#define ICH9_LPC_PMBASE_RTE 0x1 +#define ICH9_LPC_PMBASE_DEFAULT 0x1 + +#define ICH9_LPC_ACPI_CTRL 0x44 +#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80 +#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK ICH9_MASK(8, 2, 0) +#define ICH9_LPC_ACPI_CTRL_9 0x0 +#define ICH9_LPC_ACPI_CTRL_10 0x1 +#define ICH9_LPC_ACPI_CTRL_11 0x2 +#define ICH9_LPC_ACPI_CTRL_20 0x4 +#define ICH9_LPC_ACPI_CTRL_21 0x5 +#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0 + +#define ICH9_LPC_PIRQA_ROUT 0x60 +#define ICH9_LPC_PIRQB_ROUT 0x61 +#define ICH9_LPC_PIRQC_ROUT 0x62 +#define ICH9_LPC_PIRQD_ROUT 0x63 + +#define ICH9_LPC_PIRQE_ROUT 0x68 +#define ICH9_LPC_PIRQF_ROUT 0x69 +#define ICH9_LPC_PIRQG_ROUT 0x6a +#define ICH9_LPC_PIRQH_ROUT 0x6b + +#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80 +#define ICH9_LPC_PIRQ_ROUT_MASK ICH9_MASK(8, 3, 0) +#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80 + +#define ICH9_LPC_GEN_PMCON_1 0xa0 +#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4) +#define ICH9_LPC_GEN_PMCON_2 0xa2 +#define ICH9_LPC_GEN_PMCON_3 0xa4 +#define ICH9_LPC_GEN_PMCON_LOCK 0xa6 + +#define ICH9_LPC_RCBA 0xf0 +#define ICH9_LPC_RCBA_BA_MASK ICH9_MASK(32, 31, 14) +#define ICH9_LPC_RCBA_EN 0x1 +#define ICH9_LPC_RCBA_DEFAULT 0x0 + +#define ICH9_LPC_PIC_NUM_PINS 16 +#define ICH9_LPC_IOAPIC_NUM_PINS 24 + +/* D31:F0 power management I/O registers + offset from the address ICH9_LPC_PMBASE */ + +/* FADT ACPI_ENABLE/ACPI_DISABLE */ +#define ICH9_APM_ACPI_ENABLE 0x2 +#define ICH9_APM_ACPI_DISABLE 0x3 + +#endif diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index 7e75496b0b..d6c3b5ece3 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -1,173 +1,27 @@ +/* + * QEMU Intel ICH9 south bridge emulation + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + #ifndef HW_SOUTHBRIDGE_ICH9_H #define HW_SOUTHBRIDGE_ICH9_H -#include "hw/isa/apm.h" -#include "hw/acpi/ich9.h" -#include "hw/intc/ioapic.h" -#include "hw/pci/pci.h" -#include "hw/pci/pci_device.h" -#include "hw/rtc/mc146818rtc.h" -#include "exec/memory.h" -#include "qemu/notify.h" #include "qom/object.h" #define TYPE_ICH9_SOUTHBRIDGE "ICH9-southbridge" OBJECT_DECLARE_SIMPLE_TYPE(ICH9State, ICH9_SOUTHBRIDGE) -#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */ - -#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC" -OBJECT_DECLARE_SIMPLE_TYPE(ICH9LPCState, ICH9_LPC_DEVICE) - -struct ICH9LPCState { - /* ICH9 LPC PCI to ISA bridge */ - PCIDevice d; - - /* (pci device, intx) -> pirq - * In real chipset case, the unused slots are never used - * as ICH9 supports only D25-D31 irq routing. - * On the other hand in qemu case, any slot/function can be populated - * via command line option. - * So fallback interrupt routing for any devices in any slots is necessary. - */ - uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; - - MC146818RtcState rtc; - APMState apm; - ICH9LPCPMRegs pm; - uint32_t sci_level; /* track sci level */ - uint8_t sci_gsi; - - /* 2.24 Pin Straps */ - struct { - bool spkr_hi; - } pin_strap; - - /* 10.1 Chipset Configuration registers(Memory Space) - which is pointed by RCBA */ - uint8_t chip_config[ICH9_CC_SIZE]; - - /* - * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0) - * - * register contents and IO memory region - */ - uint8_t rst_cnt; - MemoryRegion rst_cnt_mem; - - /* SMI feature negotiation via fw_cfg */ - uint64_t smi_host_features; /* guest-invisible, host endian */ - uint8_t smi_host_features_le[8]; /* guest-visible, read-only, little - * endian uint64_t */ - uint8_t smi_guest_features_le[8]; /* guest-visible, read-write, little - * endian uint64_t */ - uint8_t smi_features_ok; /* guest-visible, read-only; selecting it - * triggers feature lockdown */ - uint64_t smi_negotiated_features; /* guest-invisible, host endian */ - - MemoryRegion rcrb_mem; /* root complex register block */ - Notifier machine_ready; - - qemu_irq gsi[IOAPIC_NUM_PINS]; -}; - -#define ICH9_MASK(bit, ms_bit, ls_bit) \ -((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) - -/* ICH9: Chipset Configuration Registers */ -#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1) - -#define ICH9_CC -#define ICH9_CC_D28IP 0x310C -#define ICH9_CC_D28IP_SHIFT 4 -#define ICH9_CC_D28IP_MASK 0xf -#define ICH9_CC_D28IP_DEFAULT 0x00214321 -#define ICH9_CC_D31IR 0x3140 -#define ICH9_CC_D30IR 0x3142 -#define ICH9_CC_D29IR 0x3144 -#define ICH9_CC_D28IR 0x3146 -#define ICH9_CC_D27IR 0x3148 -#define ICH9_CC_D26IR 0x314C -#define ICH9_CC_D25IR 0x3150 -#define ICH9_CC_DIR_DEFAULT 0x3210 -#define ICH9_CC_D30IR_DEFAULT 0x0 -#define ICH9_CC_DIR_SHIFT 4 -#define ICH9_CC_DIR_MASK 0x7 -#define ICH9_CC_OIC 0x31FF -#define ICH9_CC_OIC_AEN 0x1 -#define ICH9_CC_GCS 0x3410 -#define ICH9_CC_GCS_DEFAULT 0x00000020 -#define ICH9_CC_GCS_NO_REBOOT (1 << 5) - /* D28:F[0-5] */ #define ICH9_PCIE_DEV 28 #define ICH9_PCIE_FUNC_MAX 6 -/* D31:F0 LPC Processor Interface */ -#define ICH9_RST_CNT_IOPORT 0xCF9 - /* D31:F1 LPC controller */ -#define ICH9_A2_LPC "ICH9 A2 LPC" -#define ICH9_A2_LPC_SAVEVM_VERSION 0 - #define ICH9_LPC_DEV 31 #define ICH9_LPC_FUNC 0 -#define ICH9_A2_LPC_REVISION 0x2 -#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */ - -#define ICH9_LPC_PMBASE 0x40 -#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK ICH9_MASK(32, 15, 7) -#define ICH9_LPC_PMBASE_RTE 0x1 -#define ICH9_LPC_PMBASE_DEFAULT 0x1 - -#define ICH9_LPC_ACPI_CTRL 0x44 -#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80 -#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK ICH9_MASK(8, 2, 0) -#define ICH9_LPC_ACPI_CTRL_9 0x0 -#define ICH9_LPC_ACPI_CTRL_10 0x1 -#define ICH9_LPC_ACPI_CTRL_11 0x2 -#define ICH9_LPC_ACPI_CTRL_20 0x4 -#define ICH9_LPC_ACPI_CTRL_21 0x5 -#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0 - -#define ICH9_LPC_PIRQA_ROUT 0x60 -#define ICH9_LPC_PIRQB_ROUT 0x61 -#define ICH9_LPC_PIRQC_ROUT 0x62 -#define ICH9_LPC_PIRQD_ROUT 0x63 - -#define ICH9_LPC_PIRQE_ROUT 0x68 -#define ICH9_LPC_PIRQF_ROUT 0x69 -#define ICH9_LPC_PIRQG_ROUT 0x6a -#define ICH9_LPC_PIRQH_ROUT 0x6b - -#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80 -#define ICH9_LPC_PIRQ_ROUT_MASK ICH9_MASK(8, 3, 0) -#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80 - -#define ICH9_LPC_GEN_PMCON_1 0xa0 -#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4) -#define ICH9_LPC_GEN_PMCON_2 0xa2 -#define ICH9_LPC_GEN_PMCON_3 0xa4 -#define ICH9_LPC_GEN_PMCON_LOCK 0xa6 - -#define ICH9_LPC_RCBA 0xf0 -#define ICH9_LPC_RCBA_BA_MASK ICH9_MASK(32, 31, 14) -#define ICH9_LPC_RCBA_EN 0x1 -#define ICH9_LPC_RCBA_DEFAULT 0x0 - -#define ICH9_LPC_PIC_NUM_PINS 16 -#define ICH9_LPC_IOAPIC_NUM_PINS 24 - #define ICH9_GPIO_GSI "gsi" -/* D31:F0 power management I/O registers - offset from the address ICH9_LPC_PMBASE */ - -/* FADT ACPI_ENABLE/ACPI_DISABLE */ -#define ICH9_APM_ACPI_ENABLE 0x2 -#define ICH9_APM_ACPI_DISABLE 0x3 - #define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features" /* bit positions used in fw_cfg SMI feature negotiation */ diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 660fa6a082..5e293ffb2a 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -37,6 +37,7 @@ #include "hw/acpi/ich9_tco.h" #include "hw/acpi/acpi_dev_interface.h" #include "hw/southbridge/ich9.h" +#include "hw/isa/ich9_lpc.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" diff --git a/hw/acpi/ich9_tco.c b/hw/acpi/ich9_tco.c index dd4aff82e0..7499ec17db 100644 --- a/hw/acpi/ich9_tco.c +++ b/hw/acpi/ich9_tco.c @@ -13,6 +13,7 @@ #include "migration/vmstate.h" #include "hw/acpi/ich9_tco.h" +#include "hw/isa/ich9_lpc.h" #include "trace.h" enum { diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index d3ce96dd9f..34f3f03949 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -56,6 +56,7 @@ /* Supported chipsets: */ #include "hw/southbridge/ich9.h" +#include "hw/isa/ich9_lpc.h" #include "hw/acpi/pcihp.h" #include "hw/i386/fw_cfg.h" #include "hw/i386/pc.h" diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index e5f5bb0db1..573a5a0bc0 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -50,6 +50,7 @@ #include "hw/ide/ahci-pci.h" #include "hw/intc/ioapic.h" #include "hw/southbridge/ich9.h" +#include "hw/isa/ich9_lpc.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/numa.h" diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 70c6e8a093..685ac38c72 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -1,5 +1,5 @@ /* - * QEMU ICH9 Emulation + * QEMU ICH9 LPC PCI-to-ISA bridge Emulation * * Copyright (c) 2006 Fabrice Bellard * Copyright (c) 2009, 2010, 2011 @@ -42,6 +42,7 @@ #include "hw/pci/pci.h" #include "hw/southbridge/ich9.h" #include "hw/i386/pc.h" +#include "hw/isa/ich9_lpc.h" #include "hw/acpi/acpi.h" #include "hw/acpi/ich9.h" #include "hw/pci/pci_bus.h" @@ -54,10 +55,35 @@ #include "hw/acpi/acpi_aml_interface.h" #include "trace.h" -/*****************************************************************************/ -/* ICH9 LPC PCI to ISA bridge */ +#define ICH9_A2_LPC_REVISION 0x2 +#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */ -/* chipset configuration register +/* ICH9: Chipset Configuration Registers */ +#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1) + +#define ICH9_CC +#define ICH9_CC_D28IP 0x310C +#define ICH9_CC_D28IP_SHIFT 4 +#define ICH9_CC_D28IP_MASK 0xf +#define ICH9_CC_D28IP_DEFAULT 0x00214321 +#define ICH9_CC_D31IR 0x3140 +#define ICH9_CC_D30IR 0x3142 +#define ICH9_CC_D29IR 0x3144 +#define ICH9_CC_D28IR 0x3146 +#define ICH9_CC_D27IR 0x3148 +#define ICH9_CC_D26IR 0x314C +#define ICH9_CC_D25IR 0x3150 +#define ICH9_CC_DIR_DEFAULT 0x3210 +#define ICH9_CC_D30IR_DEFAULT 0x0 +#define ICH9_CC_DIR_SHIFT 4 +#define ICH9_CC_DIR_MASK 0x7 +#define ICH9_CC_OIC 0x31FF +#define ICH9_CC_OIC_AEN 0x1 +#define ICH9_CC_GCS 0x3410 +#define ICH9_CC_GCS_DEFAULT 0x00000020 +#define ICH9_CC_GCS_NO_REBOOT (1 << 5) + +/* * to access chipset configuration registers, pci_[sg]et_{byte, word, long} * are used. * Although it's not pci configuration space, it's little endian as Intel. diff --git a/tests/qtest/tco-test.c b/tests/qtest/tco-test.c index 0547d41173..c5974e72bd 100644 --- a/tests/qtest/tco-test.c +++ b/tests/qtest/tco-test.c @@ -14,7 +14,7 @@ #include "libqos/pci-pc.h" #include "qapi/qmp/qdict.h" #include "hw/pci/pci_regs.h" -#include "hw/southbridge/ich9.h" +#include "hw/isa/ich9_lpc.h" #include "hw/acpi/ich9.h" #include "hw/acpi/ich9_tco.h" From patchwork Mon Feb 19 16:38:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 774102 Delivered-To: patch@linaro.org Received: by 2002:a5d:4943:0:b0:33b:4db1:f5b3 with SMTP id r3csp1253208wrs; Mon, 19 Feb 2024 08:41:16 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVKd6ysejdyzoaYrrnouDH3J48gCYAW3wEgS7GjmpL5w3zyLpcQYxDnulOPgN9+OdJ2b6wwdM5VnEW+SAZZaUeW X-Google-Smtp-Source: AGHT+IETLmh8IkLb2NkHVtZgMoXGi6EbIRLdjP/3i6EtsNyX0RAer46TOA0awEY/iY3UOpyYYbRf X-Received: by 2002:a05:6214:440c:b0:68f:2e24:6155 with SMTP id oj12-20020a056214440c00b0068f2e246155mr13464342qvb.11.1708360876186; Mon, 19 Feb 2024 08:41:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1708360876; cv=none; d=google.com; s=arc-20160816; b=CNKBJ2LfkHKqhCpD9qU06qHGLSjXDrV5rxaoV4y/Y56hOZozJ91kA3LeB2e2wE4x4i KybcOnZZ0XZfTXfNVaMfArm+beKqIfgP00ZzfNU98kg2SnoWc4WBzQmrDnZHOs4htcs0 CLOEsoa2G1zLZUzvuNbi2Fz0cntC+desYCgvb78Dnbj3jL9m/9vJMnAvXDTBsWlAWVxX eVZ1Nk53Qiv8Cd8ZrTCQxjGts2ULmYhaTJk7vwRGXB3+wcVnF9lm8OghOMWB88he7Ebt 7CRhp+8Bi65tCj6i8x2rgMFQCs63HXopWnF4eDWvxVlBwSAQ3uoKteB4Ws3zZaihUHXJ YYzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=z3eeC3bMQM+uCMwmyOtFt5MF4rfCj1kFAANhRaPaRfQ=; fh=GFH0+Nfz+rN0IvTHf71Tn8mJWCh907g2jnPgVcMG7yo=; b=FQzXLaLCkOVE9xGb/6pZAw5w8158npCdJya3e7dFtSxaG6PyOyzoggLanhBpx9Junh 4c4tnIKVyhI1RJFhYwNFqjjSAKT0ltkywi7vWPjAuRpa3g69ibzp51Js/mkUPlBPoGs+ 4kfLc9+vYFuhodd7yab+MGtIfB54UKm7jBkIK7KgWRfydv/c61LOm8vWrAj42q1vogS8 rv9qgZr0SpX6UXIVsoHTvhCO1mZ4JZfsg9Ue+uIgkFzAOSpx1MlWqLh/91KQVppxD6ny 3IqAjqDrYQmEtcj0xcmmugIaWt+4g1QTQGOQpVGmpaORzZWtGDhpcbhUe6VKtJG7FQf2 pv8g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JTsYYdWw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q14-20020a056214194e00b0068cb0e2e9aesi6309283qvk.580.2024.02.19.08.41.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2024 08:41:16 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JTsYYdWw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rc6h9-000579-E6; Mon, 19 Feb 2024 11:40:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rc6h7-000504-QJ for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:40:41 -0500 Received: from mail-lj1-x229.google.com ([2a00:1450:4864:20::229]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rc6h5-0003Po-KT for qemu-devel@nongnu.org; Mon, 19 Feb 2024 11:40:41 -0500 Received: by mail-lj1-x229.google.com with SMTP id 38308e7fff4ca-2d2387a5408so19228181fa.3 for ; Mon, 19 Feb 2024 08:40:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708360837; x=1708965637; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=z3eeC3bMQM+uCMwmyOtFt5MF4rfCj1kFAANhRaPaRfQ=; b=JTsYYdWwk1w/XseV5ouXQjcXXViMNXk5D3gIkCy/fnxzCvHjhh6RAOtPa79LkyGbso Pi+6JUneC2fHn1yjJVAhysYbSU7ILhAU/wkgaDtgAdZYwvUKvH6mEszNY8PZh9VS5B2J NHExDuU6bY399TdF7mAMPLxObJf37AehMsKX0eJ5loZ+HWTWzlyN/9BWyKH50RDYJdsg SgeJU1P2IOITtjd3pbl3YLt4SIrzL8zsaGZR/i/jpeP+y2eSPh/MV3RyTPIVp4Q/tnvZ ZBihwGhzyJQMSTeiP+eAMp24G1/A6E27/zm/5eAO+Glf9fGFFMjHEOZhZpJWd9R6g/FJ EqnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708360837; x=1708965637; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z3eeC3bMQM+uCMwmyOtFt5MF4rfCj1kFAANhRaPaRfQ=; b=v32/nyzot9abwaSl/HAnHUAX+x1WtXHdP5O+cGmxsthOYfRHgqI4hVVdfnP5402dDA DbWXBqAvvuyBgm+NIjd3NGwIM45gynlaiOw4C3ma/M4oF7jfiHpYxVpJeNX0ZsVTd6ib ftxTo1ATg2cYV56Jh4MA/1jGI7d1y93NBaNXMNS0+hAkbfOK+l5Hlgip4kVpTn2hKNQb tRUySjrbcC8ChOfLx6wL7sRL7ZouNrSTPxcAAiqWlYRe50itvIX8t6C9AvzutQKpkpxk w/JPD1N5iGh1WlKf0QAAdvgOMba1B+M/CB7y7PH35PYV5//kEoGHh7+g1BPkTlJV239H wwkw== X-Gm-Message-State: AOJu0Yx1PdOf0VGhkbSh+wje39HIUFyY2aV8tR5RxvcLo2XtMTYBgkuk VVD4IDSwPj7oWwstQDskYi624L63XMfizhlqK57PDccsEdLIY+ft5Bc6SL5RDNsrAFSCgijunTg T X-Received: by 2002:a2e:2a84:0:b0:2d2:3b6f:3630 with SMTP id q126-20020a2e2a84000000b002d23b6f3630mr1760945ljq.2.1708360837185; Mon, 19 Feb 2024 08:40:37 -0800 (PST) Received: from m1x-phil.lan ([176.176.181.220]) by smtp.gmail.com with ESMTPSA id bw4-20020a0560001f8400b0033d297c9118sm8300073wrb.24.2024.02.19.08.40.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 19 Feb 2024 08:40:36 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: "Michael S. Tsirkin" , Ani Sinha , Richard Henderson , Igor Mammedov , Mark Cave-Ayland , Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Paolo Bonzini , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 14/14] hw/southbridge/ich9: Add the LPC / ISA bridge function Date: Mon, 19 Feb 2024 17:38:54 +0100 Message-ID: <20240219163855.87326-15-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240219163855.87326-1-philmd@linaro.org> References: <20240219163855.87326-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=philmd@linaro.org; helo=mail-lj1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instantiate TYPE_ICH9_LPC_DEVICE in TYPE_ICH9_SOUTHBRIDGE. Expose the SMM property so the Q35 machine can disable it (depending on the accelerator used). Signed-off-by: Philippe Mathieu-Daudé --- include/hw/southbridge/ich9.h | 4 ---- hw/i386/pc_q35.c | 12 +++--------- hw/isa/lpc_ich9.c | 3 +++ hw/southbridge/ich9.c | 14 ++++++++++++++ hw/i386/Kconfig | 1 - hw/southbridge/Kconfig | 1 + 6 files changed, 21 insertions(+), 14 deletions(-) diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index d6c3b5ece3..a8da4a8665 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -16,10 +16,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(ICH9State, ICH9_SOUTHBRIDGE) #define ICH9_PCIE_DEV 28 #define ICH9_PCIE_FUNC_MAX 6 -/* D31:F1 LPC controller */ -#define ICH9_LPC_DEV 31 -#define ICH9_LPC_FUNC 0 - #define ICH9_GPIO_GSI "gsi" #define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features" diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 573a5a0bc0..0fe43e8e2d 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -50,7 +50,6 @@ #include "hw/ide/ahci-pci.h" #include "hw/intc/ioapic.h" #include "hw/southbridge/ich9.h" -#include "hw/isa/ich9_lpc.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/numa.h" @@ -69,7 +68,6 @@ static void pc_q35_init(MachineState *machine) Object *phb; PCIBus *host_bus; DeviceState *ich9; - PCIDevice *lpc; Object *lpc_obj; DeviceState *lpc_dev; BusState *idebus[2] = { }; @@ -181,6 +179,7 @@ static void pc_q35_init(MachineState *machine) object_property_set_link(OBJECT(ich9), "mch-pcie-bus", OBJECT(host_bus), &error_abort); qdev_prop_set_bit(ich9, "d2p-enabled", false); + qdev_prop_set_bit(ich9, "smm-enabled", x86_machine_is_smm_enabled(x86ms)); qdev_prop_set_bit(ich9, "sata-enabled", pcms->sata_enabled); qdev_prop_set_bit(ich9, "smbus-enabled", pcms->smbus_enabled); /* Should we create 6 UHCI according to ich9 spec? */ @@ -191,13 +190,8 @@ static void pc_q35_init(MachineState *machine) gsi_state = pc_gsi_create(&x86ms->gsi, true); /* create ISA bus */ - lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), - TYPE_ICH9_LPC_DEVICE); - lpc_obj = OBJECT(lpc); - lpc_dev = DEVICE(lpc); - qdev_prop_set_bit(lpc_dev, "smm-enabled", - x86_machine_is_smm_enabled(x86ms)); - pci_realize_and_unref(lpc, host_bus, &error_fatal); + lpc_obj = object_resolve_path_component(OBJECT(ich9), "lpc"); + lpc_dev = DEVICE(lpc_obj); for (i = 0; i < IOAPIC_NUM_PINS; i++) { qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); } diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 685ac38c72..4d7b5c0c64 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -55,6 +55,9 @@ #include "hw/acpi/acpi_aml_interface.h" #include "trace.h" +#define ICH9_LPC_DEV 31 +#define ICH9_LPC_FUNC 0 + #define ICH9_A2_LPC_REVISION 0x2 #define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */ diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c index 085d75e569..57a05b35e1 100644 --- a/hw/southbridge/ich9.c +++ b/hw/southbridge/ich9.c @@ -13,6 +13,7 @@ #include "hw/southbridge/ich9.h" #include "hw/pci/pci.h" #include "hw/pci-bridge/ich_dmi_pci.h" +#include "hw/isa/ich9_lpc.h" #include "hw/ide/ahci-pci.h" #include "hw/ide.h" #include "hw/i2c/smbus_ich9.h" @@ -21,6 +22,7 @@ #include "hw/usb/hcd-uhci.h" #define ICH9_D2P_DEVFN PCI_DEVFN(30, 0) +#define ICH9_LPC_DEVFN PCI_DEVFN(31, 0) #define ICH9_SATA1_DEVFN PCI_DEVFN(31, 2) #define ICH9_SMB_DEVFN PCI_DEVFN(31, 3) #define ICH9_EHCI_FUNC 7 @@ -34,6 +36,7 @@ struct ICH9State { I82801b11Bridge d2p; AHCIPCIState sata0; + ICH9LPCState lpc; ICH9SMBState smb; EHCIPCIState ehci[EHCI_PER_FN]; UHCIState uhci[EHCI_PER_FN * UHCI_PER_FN]; @@ -148,6 +151,13 @@ static bool ich9_realize_usb(ICH9State *s, Error **errp) static void ich9_init(Object *obj) { + ICH9State *s = ICH9_SOUTHBRIDGE(obj); + + object_initialize_child(obj, "lpc", &s->lpc, TYPE_ICH9_LPC_DEVICE); + qdev_prop_set_int32(DEVICE(&s->lpc), "addr", ICH9_LPC_DEVFN); + qdev_prop_set_bit(DEVICE(&s->lpc), "multifunction", true); + object_property_add_alias(obj, "smm-enabled", + OBJECT(&s->lpc), "smm-enabled"); } static void ich9_realize(DeviceState *dev, Error **errp) @@ -163,6 +173,10 @@ static void ich9_realize(DeviceState *dev, Error **errp) return; } + if (!qdev_realize(DEVICE(&s->lpc), BUS(s->pci_bus), errp)) { + return; + } + if (s->sata_enabled && !ich9_realize_sata(s, errp)) { return; } diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index 226d7f6916..eccc834e49 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -100,7 +100,6 @@ config Q35 select PC_ACPI select PCI_EXPRESS_Q35 select ICH9 - select LPC_ICH9 select DIMM select SMBIOS select FW_CFG_DMA diff --git a/hw/southbridge/Kconfig b/hw/southbridge/Kconfig index 31eb125bf7..8ce62b703c 100644 --- a/hw/southbridge/Kconfig +++ b/hw/southbridge/Kconfig @@ -8,3 +8,4 @@ config ICH9 select ACPI_ICH9 imply USB_EHCI_PCI imply USB_UHCI + select LPC_ICH9