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([223.178.209.148]) by smtp.gmail.com with ESMTPSA id f9-20020a170902e98900b001db45855528sm3797059plb.198.2024.02.19.00.41.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Feb 2024 00:41:51 -0800 (PST) From: Sumit Garg To: caleb.connolly@linaro.org, neil.armstrong@linaro.org Cc: u-boot@lists.denx.de, trini@konsulko.com, Sumit Garg Subject: [PATCH] qcom_defconfig: Enable ethernet and I2C support Date: Mon, 19 Feb 2024 14:11:44 +0530 Message-Id: <20240219084144.2881155-1-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean QCS404 supports Synopsys Designware Ethernet QOS IP and we already have the corresponding glue layer present upstream as: drivers/net/dwc_eth_qos_qcom.c. So enable corresponding support. Along with that it is possible for Qualcomm platforms to retrieve MAC address from I2C eeprom present on board. So enable corresponding support as well. Signed-off-by: Sumit Garg --- This patch based upon Caleb's series [1]. [1] https://lore.kernel.org/all/20240215-b4-qcom-common-target-v4-0-ed06355c634a@linaro.org/ configs/qcom_defconfig | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 222db6448aba..cbc612b44bd9 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -26,7 +26,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_CAT=y CONFIG_CMD_BMP=y CONFIG_CMD_LOG=y -# CONFIG_NET is not set CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y CONFIG_CLK_QCOM_QCS404=y @@ -65,3 +64,26 @@ CONFIG_VIDEO_SIMPLE=y CONFIG_HEXDUMP=y # CONFIG_GENERATE_SMBIOS_TABLE is not set CONFIG_LMB_MAX_REGIONS=64 +CONFIG_CMD_DHCP=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_I2C=y +CONFIG_CMD_PING=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_DM_MDIO=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_QCOM=y +CONFIG_RGMII=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_MISC=y +CONFIG_NVMEM=y +CONFIG_DM_I2C=y +CONFIG_I2C_SUPPORT=y +CONFIG_I2C_MUX=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C=y +CONFIG_SYS_I2C_QUP=y +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5