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Thu, 15 Feb 2024 01:20:33 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id l8-20020adfa388000000b0033b66c2d61esm1156435wrb.48.2024.02.15.01.20.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 01:20:32 -0800 (PST) From: Neil Armstrong Date: Thu, 15 Feb 2024 10:20:24 +0100 Subject: [PATCH v2 2/6] dt-bindings: arm-smmu: Document SM8650 GPU SMMU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240215-topic-sm8650-gpu-v2-2-6be0b4bf2e09@linaro.org> References: <20240215-topic-sm8650-gpu-v2-0-6be0b4bf2e09@linaro.org> In-Reply-To: <20240215-topic-sm8650-gpu-v2-0-6be0b4bf2e09@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Document the GPU SMMU found on the SM8650 platform. Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index a4042ae24770..3ad5c850f3bf 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -93,6 +93,7 @@ properties: - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 - qcom,sm8550-smmu-500 + - qcom,sm8650-smmu-500 - const: qcom,adreno-smmu - const: qcom,smmu-500 - const: arm,mmu-500 @@ -508,7 +509,10 @@ allOf: - if: properties: compatible: - const: qcom,sm8550-smmu-500 + contains: + enum: + - qcom,sm8550-smmu-500 + - qcom,sm8650-smmu-500 then: properties: clock-names: @@ -544,7 +548,6 @@ allOf: - qcom,sdx65-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - - qcom,sm8650-smmu-500 - qcom,x1e80100-smmu-500 then: properties: From patchwork Thu Feb 15 09:20:26 2024 Content-Type: text/plain; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add support for the A750 GPU found on the SM8650 platform Unlike the the very close A740 GPU on the SM8550 SoC, the A750 GPU doesn't have an HWCFG block but a separate register set. The A750 GPU info are added under the adreno_is_a750() macro and the ADRENO_7XX_GEN3 family id. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 28 +++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 ++++++++-- 4 files changed, 49 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 8c4900444b2c..325881d8ff08 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -842,6 +842,8 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) */ if (adreno_is_a740(adreno_gpu)) chipid_min = 2; + else if (adreno_is_a750(adreno_gpu)) + chipid_min = 9; else return -EINVAL; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c9c55e2ea584..475b601a48ee 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -961,7 +961,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) unsigned int i; u32 val, clock_cntl_on, cgc_mode; - if (!adreno_gpu->info->hwcg) + if (!(adreno_gpu->info->hwcg || adreno_is_a7xx(adreno_gpu))) return; if (adreno_is_a630(adreno_gpu)) @@ -982,6 +982,25 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) state ? 0x5555 : 0); } + if (!adreno_gpu->info->hwcg) { + gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1); + gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0); + + if (state) { + gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1); + + if (gpu_poll_timeout(gpu, REG_A7XX_RBBM_CGC_P2S_STATUS, val, + val & A7XX_RBBM_CGC_P2S_STATUS_TXDONE, 1, 10)) { + dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n"); + return; + } + + gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0); + } + + return; + } + val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); /* Don't re-program the registers if they are already correct */ @@ -1239,7 +1258,9 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) count = ARRAY_SIZE(a660_protect); count_max = 48; BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48); - } else if (adreno_is_a730(adreno_gpu) || adreno_is_a740(adreno_gpu)) { + } else if (adreno_is_a730(adreno_gpu) || + adreno_is_a740(adreno_gpu) || + adreno_is_a750(adreno_gpu)) { regs = a730_protect; count = ARRAY_SIZE(a730_protect); count_max = 48; @@ -2880,7 +2901,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) /* gpu->info only gets assigned in adreno_gpu_init() */ is_a7xx = config->info->family == ADRENO_7XX_GEN1 || - config->info->family == ADRENO_7XX_GEN2; + config->info->family == ADRENO_7XX_GEN2 || + config->info->family == ADRENO_7XX_GEN3; a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 2ce7d7b1690d..e2582c91d7e7 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -522,6 +522,20 @@ static const struct adreno_info gpulist[] = { .zapfw = "a740_zap.mdt", .hwcg = a740_hwcg, .address_space_size = SZ_16G, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ + .family = ADRENO_7XX_GEN3, + .fw = { + [ADRENO_FW_SQE] = "gen70900_sqe.fw", + [ADRENO_FW_GMU] = "gmu_gen70900.bin", + }, + .gmem = 3 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "gen70900_zap.mbn", + .address_space_size = SZ_16G, }, }; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index bc14df96feb0..9e9415df2cea 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -48,6 +48,7 @@ enum adreno_family { ADRENO_6XX_GEN4, /* a660 family */ ADRENO_7XX_GEN1, /* a730 family */ ADRENO_7XX_GEN2, /* a740 family */ + ADRENO_7XX_GEN3, /* a750 family */ }; #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) @@ -423,12 +424,17 @@ static inline int adreno_is_a740(struct adreno_gpu *gpu) return gpu->info->chip_ids[0] == 0x43050a01; } -/* Placeholder to make future diffs smaller */ +static inline int adreno_is_a750(struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x43051401; +} + static inline int adreno_is_a740_family(struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; - return gpu->info->family == ADRENO_7XX_GEN2; + return gpu->info->family == ADRENO_7XX_GEN2 || + gpu->info->family == ADRENO_7XX_GEN3; } static inline int adreno_is_a7xx(struct adreno_gpu *gpu) From patchwork Thu Feb 15 09:20:28 2024 Content-Type: text/plain; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add path of the GPU firmware for the SM8650-QRD board Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index b07cac2e5bc8..dc91f0bf4b8c 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -766,6 +766,14 @@ &ipa { status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8650/gen70900_zap.mbn"; + }; +}; + &lpass_tlmm { spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio21";