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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2024 14:42:01.9732 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fab5a440-4000-439c-2c37-08dc2d6b1b29 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB50.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5287 During the initialization sensors may take some time to respond. Hence, increase the sensor command timeouts in order to obtain status responses within a maximum timeout. Co-developed-by: Akshata MukundShetty Signed-off-by: Akshata MukundShetty Signed-off-by: Basavaraj Natikar --- drivers/hid/amd-sfh-hid/amd_sfh_pcie.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c b/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c index 2530fa98b568..8a4cd793d021 100644 --- a/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c +++ b/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c @@ -39,11 +39,11 @@ static int amd_sfh_wait_response_v2(struct amd_mp2_dev *mp2, u8 sid, u32 sensor_ { union cmd_response cmd_resp; - /* Get response with status within a max of 1600 ms timeout */ + /* Get response with status within a max of 10 seconds timeout */ if (!readl_poll_timeout(mp2->mmio + AMD_P2C_MSG(0), cmd_resp.resp, (cmd_resp.response_v2.response == sensor_sts && cmd_resp.response_v2.status == 0 && (sid == 0xff || - cmd_resp.response_v2.sensor_id == sid)), 500, 1600000)) + cmd_resp.response_v2.sensor_id == sid)), 500, 10000000)) return cmd_resp.response_v2.response; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2024 14:42:07.2493 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 50981e3e-5f54-4bae-da9a-08dc2d6b1e6a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7826 HPD sensor data is not populating properly because of wrong order of HPD sensor structure elements. So update the order of structure elements to match the HPD sensor data received from the firmware. Fixes: 24a31ea94922 ("HID: amd_sfh: Add initial support for HPD sensor") Co-developed-by: Akshata MukundShetty Signed-off-by: Akshata MukundShetty Signed-off-by: Basavaraj Natikar --- drivers/hid/amd-sfh-hid/amd_sfh_pcie.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_pcie.h b/drivers/hid/amd-sfh-hid/amd_sfh_pcie.h index 70add75fc506..05e400a4a83e 100644 --- a/drivers/hid/amd-sfh-hid/amd_sfh_pcie.h +++ b/drivers/hid/amd-sfh-hid/amd_sfh_pcie.h @@ -90,10 +90,10 @@ enum mem_use_type { struct hpd_status { union { struct { - u32 human_presence_report : 4; - u32 human_presence_actual : 4; - u32 probablity : 8; u32 object_distance : 16; + u32 probablity : 8; + u32 human_presence_actual : 4; + u32 human_presence_report : 4; } shpd; u32 val; }; From patchwork Wed Feb 14 14:41:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Basavaraj Natikar X-Patchwork-Id: 772740 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2055.outbound.protection.outlook.com [40.107.92.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4536E5A7A4 for ; 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Wed, 14 Feb 2024 08:42:03 -0600 From: Basavaraj Natikar To: , , CC: , Basavaraj Natikar Subject: [PATCH 3/5] HID: amd_sfh: Avoid disabling the interrupt Date: Wed, 14 Feb 2024 20:11:42 +0530 Message-ID: <20240214144144.682750-4-Basavaraj.Natikar@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240214144144.682750-1-Basavaraj.Natikar@amd.com> References: <20240214144144.682750-1-Basavaraj.Natikar@amd.com> Precedence: bulk X-Mailing-List: linux-input@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989E6:EE_|BL1PR12MB5287:EE_ X-MS-Office365-Filtering-Correlation-Id: 91b604c3-4a9c-4abb-2a98-08dc2d6b2000 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /eufgdJc+NDUftea06K9U/KZ4X7bFoONJLM2RuJrjyxU6RmaKaY7uLAMmBcTjlJS6HoPCH5kXc1I8u6K1vQUcHohhzUQsu7XzkisM4WkENLZJjKIb0g/vLCa/v0wMAiqXq9VaiQ789nmrRTRVGukk+hkyRwEJfDSBmO9+ftbEVSM3ukNM10aIj8aweehq7Jb5COa1wFyKqhz39eV/yELFWjeWWGDAYE4esX56SuqE3fZemBCJk4QFxgV/Mb9eR3wbjeTLNF1vc0aIu0pBNT09XS0Z8zs/HeOoXJ+EEc1opbmY28EKHvhFNB5gGAn/o1wrOMbS/Re+dZUjqXFOFNoce6vweHqUJQgKHLLcRi1i57rB4JjjQO9vC7BzUoBNowWmEAlWmYIobU0ZaophcaB8SLtnCAorZU2u5AfQY7FWqhvb6dBs6g4SnwB6+2lVXfwUjT/BJNWTzSrfRLsp0o6LDDa+YxV6w0T7pWEgcIFj1vMLxYbtokKbxNB2QiZQk93mVh24IQRvmbbV6yzYNxbhrzsqcPcQcrl0K0hobtAGLl1kG3RF24+j8LhuSBVa/GxTd8p6DSBpztKrpkmyiis/g== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Hence avoid disabling the interrupt for that particular model. Link: https://bugzilla.kernel.org/show_bug.cgi?id=218104 Fixes: b300667b33b2 ("HID: amd_sfh: Disable the interrupt for all command") Co-developed-by: Akshata MukundShetty Signed-off-by: Akshata MukundShetty Signed-off-by: Basavaraj Natikar --- drivers/hid/amd-sfh-hid/amd_sfh_pcie.c | 30 +++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c b/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c index 8a4cd793d021..8c1809c7d1f7 100644 --- a/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c +++ b/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c @@ -35,6 +35,8 @@ static int sensor_mask_override = -1; module_param_named(sensor_mask, sensor_mask_override, int, 0444); MODULE_PARM_DESC(sensor_mask, "override the detected sensors mask"); +static bool intr_disable = true; + static int amd_sfh_wait_response_v2(struct amd_mp2_dev *mp2, u8 sid, u32 sensor_sts) { union cmd_response cmd_resp; @@ -55,7 +57,7 @@ static void amd_start_sensor_v2(struct amd_mp2_dev *privdata, struct amd_mp2_sen cmd_base.ul = 0; cmd_base.cmd_v2.cmd_id = ENABLE_SENSOR; - cmd_base.cmd_v2.intr_disable = 1; + cmd_base.cmd_v2.intr_disable = intr_disable; cmd_base.cmd_v2.period = info.period; cmd_base.cmd_v2.sensor_id = info.sensor_idx; cmd_base.cmd_v2.length = 16; @@ -73,7 +75,7 @@ static void amd_stop_sensor_v2(struct amd_mp2_dev *privdata, u16 sensor_idx) cmd_base.ul = 0; cmd_base.cmd_v2.cmd_id = DISABLE_SENSOR; - cmd_base.cmd_v2.intr_disable = 1; + cmd_base.cmd_v2.intr_disable = intr_disable; cmd_base.cmd_v2.period = 0; cmd_base.cmd_v2.sensor_id = sensor_idx; cmd_base.cmd_v2.length = 16; @@ -87,7 +89,7 @@ static void amd_stop_all_sensor_v2(struct amd_mp2_dev *privdata) union sfh_cmd_base cmd_base; cmd_base.cmd_v2.cmd_id = STOP_ALL_SENSORS; - cmd_base.cmd_v2.intr_disable = 1; + cmd_base.cmd_v2.intr_disable = intr_disable; cmd_base.cmd_v2.period = 0; cmd_base.cmd_v2.sensor_id = 0; @@ -292,6 +294,26 @@ int amd_sfh_irq_init(struct amd_mp2_dev *privdata) return 0; } +static int mp2_disable_intr(const struct dmi_system_id *id) +{ + intr_disable = false; + return 0; +} + +static const struct dmi_system_id dmi_sfh_table[] = { + { + /* + * https://bugzilla.kernel.org/show_bug.cgi?id=218104 + */ + .callback = mp2_disable_intr, + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "HP"), + DMI_MATCH(DMI_PRODUCT_NAME, "HP ProBook x360 435 G7"), + }, + }, + {} +}; + static const struct dmi_system_id dmi_nodevs[] = { { /* @@ -315,6 +337,8 @@ static int amd_mp2_pci_probe(struct pci_dev *pdev, const struct pci_device_id *i if (dmi_first_match(dmi_nodevs)) return -ENODEV; + dmi_check_system(dmi_sfh_table); + privdata = devm_kzalloc(&pdev->dev, sizeof(*privdata), GFP_KERNEL); if (!privdata) return -ENOMEM; From patchwork Wed Feb 14 14:41:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Basavaraj Natikar X-Patchwork-Id: 772739 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2063.outbound.protection.outlook.com [40.107.93.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53DC85A0FB for ; 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Wed, 14 Feb 2024 08:42:05 -0600 From: Basavaraj Natikar To: , , CC: , Basavaraj Natikar Subject: [PATCH 4/5] HID: amd_sfh: Improve boot time when SFH is available Date: Wed, 14 Feb 2024 20:11:43 +0530 Message-ID: <20240214144144.682750-5-Basavaraj.Natikar@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240214144144.682750-1-Basavaraj.Natikar@amd.com> References: <20240214144144.682750-1-Basavaraj.Natikar@amd.com> Precedence: bulk X-Mailing-List: linux-input@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989E6:EE_|CH3PR12MB8330:EE_ X-MS-Office365-Filtering-Correlation-Id: 7671bc7b-8226-46cb-223f-08dc2d6b20ba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HZnNGx54gyHcoBl+3h12k9/xR9mAaO+5duU5X9Wgfn65sOxtKTKklLhHJ6c9uVcZfEBCbxI31+YG75NXTYo+vxgYTqdN7Yff2PrAeX57UayIVWwy5U4r3DI1sRLAz6w5jnBxtrmfTv3bYpY3vo1iWgTcuqvsGfmbS9EZU6PwB4244D/5UELRV9vnXnGiSFooFMf0r6SDNbEz45KyLJE71L4wKWu3X+/lpMDU1BfZb0mK8seNHYT9we167+83Jsk7cDq9QIA4c5WoFVknAj82/gM5un20SwKFRrim3SBO3Ofp4eLkO3D3e3CLFETySg/vxwvp7qFGZpquH7pFgb0P7Hhyl64xMKYQxGOwfRabsTCKiqvcdERYZBnLXekYWzzv0cCclj4veWsNpcvA7ydKgdg65n3sICq6jPWzX/5jpifRrm8BPZm9tQFUAbC1qgDpsEPepVe+X0IsPKzv/fyxqM5Pudn49B5cAXvfOcy8oEGqZPEs6uyN9IJz6+0bktdqtkw7zGfmpvhm5+uEs0B/kkd7QjaSYstXjUdL43zHsC7rP3zsZUamsPpGc9RGg6F5WaedZBYewOX390cL2nCOl6EYdhCXIrhfXAUN6IxmuWw= X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Hence split and defer initialization code to improve SFH module load time and boot time of the system when SFH is available. Signed-off-by: Basavaraj Natikar --- drivers/hid/amd-sfh-hid/amd_sfh_common.h | 2 + drivers/hid/amd-sfh-hid/amd_sfh_pcie.c | 75 ++++++++++++++++++++---- 2 files changed, 64 insertions(+), 13 deletions(-) diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_common.h b/drivers/hid/amd-sfh-hid/amd_sfh_common.h index a1950bc6e6ce..ef5551c1eec5 100644 --- a/drivers/hid/amd-sfh-hid/amd_sfh_common.h +++ b/drivers/hid/amd-sfh-hid/amd_sfh_common.h @@ -53,6 +53,8 @@ struct amd_mp2_dev { /* mp2 active control status */ u32 mp2_acs; struct sfh_dev_status dev_en; + struct work_struct work; + u8 init_done; }; struct amd_mp2_ops { diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c b/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c index 8c1809c7d1f7..495ec1179ee5 100644 --- a/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c +++ b/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -329,6 +330,48 @@ static const struct dmi_system_id dmi_nodevs[] = { { } }; +static void sfh1_1_init_work(struct work_struct *work) +{ + struct amd_mp2_dev *mp2 = container_of(work, struct amd_mp2_dev, work); + struct pci_dev *pdev = mp2->pdev; + int rc; + + rc = mp2->sfh1_1_ops->init(mp2); + if (rc) { + dev_err(&pdev->dev, "sfh1_1_init failed err %d\n", rc); + return; + } + + amd_sfh_clear_intr(mp2); + mp2->init_done = 1; +} + +static void sfh_init_work(struct work_struct *work) +{ + struct amd_mp2_dev *mp2 = container_of(work, struct amd_mp2_dev, work); + struct pci_dev *pdev = mp2->pdev; + int rc; + + rc = amd_sfh_hid_client_init(mp2); + if (rc) { + amd_sfh_clear_intr(mp2); + dev_err(&pdev->dev, "amd_sfh_hid_client_init failed err %d\n", rc); + return; + } + + amd_sfh_clear_intr(mp2); + mp2->init_done = 1; +} + +static void amd_sfh_remove(struct pci_dev *pdev) +{ + struct amd_mp2_dev *mp2 = pci_get_drvdata(pdev); + + flush_work(&mp2->work); + if (mp2->init_done) + mp2->mp2_ops->remove(mp2); +} + static int amd_mp2_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct amd_mp2_dev *privdata; @@ -367,10 +410,12 @@ static int amd_mp2_pci_probe(struct pci_dev *pdev, const struct pci_device_id *i privdata->sfh1_1_ops = (const struct amd_sfh1_1_ops *)id->driver_data; if (privdata->sfh1_1_ops) { - rc = privdata->sfh1_1_ops->init(privdata); + rc = devm_work_autocancel(&pdev->dev, &privdata->work, sfh1_1_init_work); if (rc) return rc; - goto init_done; + + schedule_work(&privdata->work); + return 0; } mp2_select_ops(privdata); @@ -381,33 +426,34 @@ static int amd_mp2_pci_probe(struct pci_dev *pdev, const struct pci_device_id *i return rc; } - rc = amd_sfh_hid_client_init(privdata); + rc = devm_work_autocancel(&pdev->dev, &privdata->work, sfh_init_work); if (rc) { amd_sfh_clear_intr(privdata); - if (rc != -EOPNOTSUPP) - dev_err(&pdev->dev, "amd_sfh_hid_client_init failed\n"); return rc; } -init_done: - amd_sfh_clear_intr(privdata); - - return devm_add_action_or_reset(&pdev->dev, privdata->mp2_ops->remove, privdata); + schedule_work(&privdata->work); + return 0; } static void amd_sfh_shutdown(struct pci_dev *pdev) { struct amd_mp2_dev *mp2 = pci_get_drvdata(pdev); - if (mp2 && mp2->mp2_ops) - mp2->mp2_ops->stop_all(mp2); + if (mp2) { + flush_work(&mp2->work); + if (mp2->init_done) + mp2->mp2_ops->stop_all(mp2); + } } static int __maybe_unused amd_mp2_pci_resume(struct device *dev) { struct amd_mp2_dev *mp2 = dev_get_drvdata(dev); - mp2->mp2_ops->resume(mp2); + flush_work(&mp2->work); + if (mp2->init_done) + mp2->mp2_ops->resume(mp2); return 0; } @@ -416,7 +462,9 @@ static int __maybe_unused amd_mp2_pci_suspend(struct device *dev) { struct amd_mp2_dev *mp2 = dev_get_drvdata(dev); - mp2->mp2_ops->suspend(mp2); + flush_work(&mp2->work); + if (mp2->init_done) + mp2->mp2_ops->suspend(mp2); return 0; } @@ -438,6 +486,7 @@ static struct pci_driver amd_mp2_pci_driver = { .probe = amd_mp2_pci_probe, .driver.pm = &amd_mp2_pm_ops, .shutdown = amd_sfh_shutdown, + .remove = amd_sfh_remove, }; module_pci_driver(amd_mp2_pci_driver); From patchwork Wed Feb 14 14:41:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Basavaraj Natikar X-Patchwork-Id: 773525 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2065.outbound.protection.outlook.com [40.107.93.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EF215644D for ; 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Wed, 14 Feb 2024 08:42:07 -0600 From: Basavaraj Natikar To: , , CC: , Basavaraj Natikar Subject: [PATCH 5/5] HID: amd_sfh: Extend MP2 register access to SFH Date: Wed, 14 Feb 2024 20:11:44 +0530 Message-ID: <20240214144144.682750-6-Basavaraj.Natikar@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240214144144.682750-1-Basavaraj.Natikar@amd.com> References: <20240214144144.682750-1-Basavaraj.Natikar@amd.com> Precedence: bulk X-Mailing-List: linux-input@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989E6:EE_|CY8PR12MB7122:EE_ X-MS-Office365-Filtering-Correlation-Id: 33204825-7f5e-4b8c-2f7c-08dc2d6b2149 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bz+ufrjiBMCs64+ZQpcDT+hDqvD3RFWFldMN5EMg9/N8vjrrd7MmUf19p0W8uA7MRY/Y0E7/0a2389fszsHzObNqRBElovMXS2rSa3ACpxEkERCIgjA8AE9v6DLSa90yGJeMRqJFIPYHWctBr2DhUkLbz/Qo1kP1z1AM93R/OPnpMQwzf+GH/oEQKU+ZB4Ue1WY6s70fu72Ain/aH432t+Fx9vrwJ+PUzs0IeNb+semHZp2mjEZMuenRPV5RY3BquNmJuq5rFbDtXT/Eg8UvAhYx+2I0SZcLjEou8StBUis/rAj3iPGsz9fwlClzMdZa83rYwjSyTYdIFA2hw6K6O5W6VEUbpkEBKq7+VYOQj8+yp4RezoJbZfrD/rBFgdbN2Ao1oRdtOSBT7E/dVLn7rMxC+Lks3VMv9Z9W9+HDBtNqIHBu61keRG5SCvdKqMa7zJmHCQOWTnc3oljKqtW6EmIb1cHMIJxW8PrHr0IFUYWcVIwL7UItUVf/o4uTG7d44BRy3AToyI7zTr9dTZtWR44O7a1eMQQEQqxlWIa+7Zn+pldJnkA4V7o/TT206dRa4M24oYxAVQSWzKZokCT4drgkI2rmd3zKOn/oHH4ieto= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(376002)(346002)(136003)(39860400002)(396003)(230922051799003)(64100799003)(186009)(1800799012)(451199024)(82310400011)(40470700004)(36840700001)(46966006)(2906002)(41300700001)(6666004)(36756003)(7696005)(2616005)(26005)(1076003)(478600001)(81166007)(16526019)(82740400003)(86362001)(8676002)(83380400001)(356005)(426003)(8936002)(336012)(5660300002)(4326008)(110136005)(54906003)(70586007)(316002)(70206006); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2024 14:42:12.1400 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 33204825-7f5e-4b8c-2f7c-08dc2d6b2149 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7122 Various MP2 register sets are supported by newer processors. Therefore, extend MP2 register access to SFH. Signed-off-by: Basavaraj Natikar --- drivers/hid/amd-sfh-hid/amd_sfh_common.h | 14 ++++++++++++++ drivers/hid/amd-sfh-hid/amd_sfh_pcie.c | 9 ++++++--- drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_desc.c | 2 +- drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_init.c | 4 ++-- drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.c | 10 +++++----- 5 files changed, 28 insertions(+), 11 deletions(-) diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_common.h b/drivers/hid/amd-sfh-hid/amd_sfh_common.h index ef5551c1eec5..e5620d7db569 100644 --- a/drivers/hid/amd-sfh-hid/amd_sfh_common.h +++ b/drivers/hid/amd-sfh-hid/amd_sfh_common.h @@ -19,6 +19,9 @@ #define AMD_C2P_MSG(regno) (0x10500 + ((regno) * 4)) #define AMD_P2C_MSG(regno) (0x10680 + ((regno) * 4)) +#define AMD_C2P_MSG_V1(regno) (0x10900 + ((regno) * 4)) +#define AMD_P2C_MSG_V1(regno) (0x10500 + ((regno) * 4)) + #define SENSOR_ENABLED 4 #define SENSOR_DISABLED 5 @@ -55,6 +58,7 @@ struct amd_mp2_dev { struct sfh_dev_status dev_en; struct work_struct work; u8 init_done; + u8 rver; }; struct amd_mp2_ops { @@ -81,4 +85,14 @@ void amd_sfh_clear_intr_v2(struct amd_mp2_dev *privdata); int amd_sfh_irq_init_v2(struct amd_mp2_dev *privdata); void amd_sfh_clear_intr(struct amd_mp2_dev *privdata); int amd_sfh_irq_init(struct amd_mp2_dev *privdata); + +static inline u64 amd_get_c2p_val(struct amd_mp2_dev *mp2, u32 idx) +{ + return mp2->rver == 1 ? AMD_C2P_MSG_V1(idx) : AMD_C2P_MSG(idx); +} + +static inline u64 amd_get_p2c_val(struct amd_mp2_dev *mp2, u32 idx) +{ + return mp2->rver == 1 ? AMD_P2C_MSG_V1(idx) : AMD_P2C_MSG(idx); +} #endif diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c b/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c index 495ec1179ee5..9e97c26c4482 100644 --- a/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c +++ b/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c @@ -99,9 +99,9 @@ static void amd_stop_all_sensor_v2(struct amd_mp2_dev *privdata) void amd_sfh_clear_intr_v2(struct amd_mp2_dev *privdata) { - if (readl(privdata->mmio + AMD_P2C_MSG(4))) { - writel(0, privdata->mmio + AMD_P2C_MSG(4)); - writel(0xf, privdata->mmio + AMD_P2C_MSG(5)); + if (readl(privdata->mmio + amd_get_p2c_val(privdata, 4))) { + writel(0, privdata->mmio + amd_get_p2c_val(privdata, 4)); + writel(0xf, privdata->mmio + amd_get_p2c_val(privdata, 5)); } } @@ -410,6 +410,9 @@ static int amd_mp2_pci_probe(struct pci_dev *pdev, const struct pci_device_id *i privdata->sfh1_1_ops = (const struct amd_sfh1_1_ops *)id->driver_data; if (privdata->sfh1_1_ops) { + if (boot_cpu_data.x86 >= 0x1A) + privdata->rver = 1; + rc = devm_work_autocancel(&pdev->dev, &privdata->work, sfh1_1_init_work); if (rc) return rc; diff --git a/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_desc.c b/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_desc.c index 33fbdde8aff0..c8916afefa62 100644 --- a/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_desc.c +++ b/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_desc.c @@ -251,7 +251,7 @@ static u8 get_input_rep(u8 current_index, int sensor_idx, int report_id, break; case HPD_IDX: get_common_inputs(&hpd_input.common_property, report_id); - hpdstatus.val = readl(mp2->mmio + AMD_C2P_MSG(4)); + hpdstatus.val = readl(mp2->mmio + amd_get_c2p_val(mp2, 4)); hpd_input.human_presence = hpdstatus.shpd.presence; report_size = sizeof(hpd_input); memcpy(input_report, &hpd_input, sizeof(hpd_input)); diff --git a/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_init.c b/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_init.c index 9dbe6f4cb294..5b24d5f63701 100644 --- a/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_init.c +++ b/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_init.c @@ -172,7 +172,7 @@ static int amd_sfh1_1_hid_client_init(struct amd_mp2_dev *privdata) if (rc) goto cleanup; - writel(0, privdata->mmio + AMD_P2C_MSG(0)); + writel(0, privdata->mmio + amd_get_p2c_val(privdata, 0)); mp2_ops->start(privdata, info); status = amd_sfh_wait_for_response (privdata, cl_data->sensor_idx[i], ENABLE_SENSOR); @@ -298,7 +298,7 @@ static void amd_sfh_set_ops(struct amd_mp2_dev *mp2) int amd_sfh1_1_init(struct amd_mp2_dev *mp2) { - u32 phy_base = readl(mp2->mmio + AMD_C2P_MSG(22)); + u32 phy_base = readl(mp2->mmio + amd_get_c2p_val(mp2, 22)); struct device *dev = &mp2->pdev->dev; struct sfh_base_info binfo; int rc; diff --git a/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.c b/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.c index ae36312bc236..2de2668a0277 100644 --- a/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.c +++ b/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.c @@ -20,7 +20,7 @@ static int amd_sfh_wait_response(struct amd_mp2_dev *mp2, u8 sid, u32 cmd_id) struct sfh_cmd_response cmd_resp; /* Get response with status within a max of 10000 ms timeout */ - if (!readl_poll_timeout(mp2->mmio + AMD_P2C_MSG(0), cmd_resp.resp, + if (!readl_poll_timeout(mp2->mmio + amd_get_p2c_val(mp2, 0), cmd_resp.resp, (cmd_resp.response.response == 0 && cmd_resp.response.cmd_id == cmd_id && (sid == 0xff || cmd_resp.response.sensor_id == sid)), 500, 10000000)) @@ -39,7 +39,7 @@ static void amd_start_sensor(struct amd_mp2_dev *privdata, struct amd_mp2_sensor cmd_base.cmd.sub_cmd_value = 1; cmd_base.cmd.sensor_id = info.sensor_idx; - writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG(0)); + writel(cmd_base.ul, privdata->mmio + amd_get_c2p_val(privdata, 0)); } static void amd_stop_sensor(struct amd_mp2_dev *privdata, u16 sensor_idx) @@ -52,8 +52,8 @@ static void amd_stop_sensor(struct amd_mp2_dev *privdata, u16 sensor_idx) cmd_base.cmd.sub_cmd_value = 1; cmd_base.cmd.sensor_id = sensor_idx; - writeq(0x0, privdata->mmio + AMD_C2P_MSG(1)); - writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG(0)); + writeq(0x0, privdata->mmio + amd_get_c2p_val(privdata, 1)); + writel(cmd_base.ul, privdata->mmio + amd_get_c2p_val(privdata, 0)); } static void amd_stop_all_sensor(struct amd_mp2_dev *privdata) @@ -66,7 +66,7 @@ static void amd_stop_all_sensor(struct amd_mp2_dev *privdata) /* 0xf indicates all sensors */ cmd_base.cmd.sensor_id = 0xf; - writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG(0)); + writel(cmd_base.ul, privdata->mmio + amd_get_c2p_val(privdata, 0)); } static struct amd_mp2_ops amd_sfh_ops = {