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Fri, 09 Feb 2024 13:50:34 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 09 Feb 2024 23:50:31 +0200 Subject: [PATCH 1/8] dt-bindings: ufs: qcom,ufs: add second RX lane on MSM8996 platform Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240209-msm8996-fix-ufs-v1-1-107b52e57420@linaro.org> References: <20240209-msm8996-fix-ufs-v1-0-107b52e57420@linaro.org> In-Reply-To: <20240209-msm8996-fix-ufs-v1-0-107b52e57420@linaro.org> To: Manivannan Sadhasivam , Bjorn Andersson , Konrad Dybcio , "James E.J. Bottomley" , "Martin K. Petersen" , Nitin Rawat , Can Guo , Naveen Kumar Goud Arepalli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Alim Akhtar , Avri Altman , Bart Van Assche , Andy Gross Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1529; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=zXQTB0UTbLqKL0nxwT+xbYvoKu354PiK4225HNhdxm8=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlxp4ndlknkuTjzr3YIUwDh2PR22rrOETju3Aes xxGv6YOUdGJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZcaeJwAKCRCLPIo+Aiko 1f3yB/42hjMD4zHwA5aBzdnkKQvx+zi1nWnB61HhTZp/FugvwIPPdsPLpLz8BIaZKjmTsUhVvmC Jfhr2ctqhCPbiRB1JJ6UEYTD9WIWLlaDCM6pEtRxqu0wc0HFUZaoYpbA6KR0SAOTI0ENv93WQpM ixbdwIAUM2JIVTBVXHBcYAOZgZYJ5bQnj9ySI7C347lsi7Svjy/niwTzFCIjdNRguf15DLmbOAl q2o9eP22t/AR/gdSlbJPXk0hKsZwlW+2CFQvj+3k6+RPn5XV2uagTaIjFnHC3HoFrZ5STpkcGAm FKaKmmaMwoqntvRNPs6BjP44Wexd8qSgTvo3647WzqvqLmMR X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Describe the second RX lane used by the UFS controller on MSM8996 platform. Fixes: 462c5c0aa798 ("dt-bindings: ufs: qcom,ufs: convert to dtschema") Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index 10c146424baa..f1de3244b473 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -43,11 +43,11 @@ properties: clocks: minItems: 8 - maxItems: 11 + maxItems: 12 clock-names: minItems: 8 - maxItems: 11 + maxItems: 12 dma-coherent: true @@ -188,8 +188,8 @@ allOf: then: properties: clocks: - minItems: 11 - maxItems: 11 + minItems: 12 + maxItems: 12 clock-names: items: - const: core_clk_src @@ -203,6 +203,7 @@ allOf: - const: ref_clk - const: tx_lane0_sync_clk - const: rx_lane0_sync_clk + - const: rx_lane1_sync_clk reg: minItems: 1 maxItems: 1 @@ -257,7 +258,7 @@ allOf: maxItems: 2 clocks: minItems: 8 - maxItems: 11 + maxItems: 12 unevaluatedProperties: false From patchwork Fri Feb 9 21:50:32 2024 Content-Type: text/plain; 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Bottomley" , "Martin K. Petersen" , Nitin Rawat , Can Guo , Naveen Kumar Goud Arepalli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Alim Akhtar , Avri Altman , Bart Van Assche , Andy Gross Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1292; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=sny/m9wJ9i9gQI3uK7sG9rC2WxbHvJ9BZkJpg0lVtPU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlxp4oF/udIPmh25v9YaVBGF8zomk/oAgu82oWc 4qjt3F9Vo+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZcaeKAAKCRCLPIo+Aiko 1fqJB/9MX9MZSLldZwM1esOwZZgWaY816oeEp0Kz6LtZi4kAPH483880Np+n7VHQz00nlQTGwMa IGHIxyL0OV132G+to0mZ68vDXrPlIiecUxo5fUADw5Dl6QIyp0cLW8ewj91Rzp3b4fI3TM8HOBC Y87B+sdiwznm3ZENyUcd89xkUaILfIO5xpMsd0aweNTjiwTbpNgG0AufCvU8WldZgMF+rwwd5A0 VlzGssDcpOiEWB4+4Jg6GfS95/0XgKn5tmhDyX+LFrPOKR17CTJ7f6r1DQOFQgmuO0BaP3e9uqE mCjM+v3umfKHqUMCWfOFKaVLnzbDXn00pzmPmeXTh823Fean X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The MSM8996 DT doesn't provide frequency limits for the core_clk_unipro clock, which results in miscalculation of the cycles_in_1us value. Provide the backwards-compatible default to support existing MSM8996 DT files. Fixes: b4e13e1ae95e ("scsi: ufs: qcom: Add multiple frequency support for MAX_CORE_CLK_1US_CYCLES") Cc: Nitin Rawat Signed-off-by: Dmitry Baryshkov --- drivers/ufs/host/ufs-qcom.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 0aeaee1c564c..79f8cb377710 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1210,8 +1210,10 @@ static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up) list_for_each_entry(clki, head, list) { if (!IS_ERR_OR_NULL(clki->clk) && - !strcmp(clki->name, "core_clk_unipro")) { - if (is_scale_up) + !strcmp(clki->name, "core_clk_unipro")) { + if (!clki->max_freq) + cycles_in_1us = 150; /* default for backwards compatibility */ + else if (is_scale_up) cycles_in_1us = ceil(clki->max_freq, (1000 * 1000)); else cycles_in_1us = ceil(clk_get_rate(clki->clk), (1000 * 1000)); From patchwork Fri Feb 9 21:50:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 771996 Received: from mail-lj1-f169.google.com (mail-lj1-f169.google.com [209.85.208.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1683364AE for ; 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Bottomley" , "Martin K. Petersen" , Nitin Rawat , Can Guo , Naveen Kumar Goud Arepalli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Alim Akhtar , Avri Altman , Bart Van Assche , Andy Gross Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1096; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=lme1RrLHypMhP1IKVUdYE5epWMb2CFcPlYghOxVFbxc=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlxp4om9AdF+KEigHcO+gUHEp2estUthJn4ZfFk q7hdNIxcl2JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZcaeKAAKCRCLPIo+Aiko 1cy7B/9BYW+GCvAnSvNFR1zqowRnTsJW8Hgvg4UjhOn3GEZQENNcrEPOzR7lDotXiX24M2vG4kC cx+8fXE+L2O2oZzO364S5sB6HCOeGE2W4JjltbYtuiJNs16EAEA9TG53RZqeioYt6MsuB8tHx+2 py+Evqoeh4luSLKnh9aSipQt0cpLt19Qv2V9gsUEzeW816ZSPv+kPshVl5sCqYDyi85eptD5Jbj 4LJKW5CoZUq1fTio58YFg72J5Y3mTwhbbOZgmxk+bfdyVqhH7k2su/W3jAR/C/OI0NZ05wlEYsU r5j1qxsLPULLZiOl4kYz9zbxrovBjJ3HBPGUiiaeK/dGr+qu X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Since the commit b4e13e1ae95e ("scsi: ufs: qcom: Add multiple frequency support for MAX_CORE_CLK_1US_CYCLES") the Qualcomm UFS driver uses core_clk_unipro values from frequency table to calculate cycles_in_1us. The DT file for MSM8996 passed 0 HZ frequencies there, resulting in broken UFS support on that platform. Fix the corresponding clock values in the frequency table. Suggested-by: Nitin Rawat Fixes: 57fc67ef0d35 ("arm64: dts: qcom: msm8996: Add ufs related nodes") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index f6b6fdc12f44..80d83e01bb4d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2077,7 +2077,7 @@ ufshc: ufshc@624000 { <0 0>, <0 0>, <150000000 300000000>, - <0 0>, + <75000000 150000000>, <0 0>, <0 0>, <0 0>, From patchwork Fri Feb 9 21:50:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 771995 Received: from mail-lj1-f180.google.com (mail-lj1-f180.google.com [209.85.208.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97AF536AE3 for ; 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Bottomley" , "Martin K. Petersen" , Nitin Rawat , Can Guo , Naveen Kumar Goud Arepalli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Alim Akhtar , Avri Altman , Bart Van Assche , Andy Gross Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=975; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Yu/LzOcQdCwZAyJpUXbklqudqrQ3EIxx4vsAwegkqbc=; b=owEBbAGT/pANAwAKAYs8ij4CKSjVAcsmYgBlxp4oPisjdMAjttGDKMVPpDmlZqu7GPwM7Nd5H MqTPgqlgz6JATIEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZcaeKAAKCRCLPIo+Aiko 1ciFB/ib4ZE+Qk5EBi+qpqjvxVXZjDd/Haa7IBdbqcSY5lkPH3lhVep03A1QtYcGtCzQACbKlmD TUaijeU5T2l4Kjz3OvlvinaAVUsWpdkSBDVFHmHQl5k3uVGlblvu4+KEvOono83JMIh7LAEOUOl gzZlWSGN9ovjd0+ZeVnlRncNq59y6bBmA26c9/+nhmnlndYuGuliry/311qFBz5i/eo5dNNn2qN ud51qCkweLTgkYzlGWIFGbGn+n97eIfSdwkDoaUSiXhfqaHepjX7Uvahc7R//LZ2sua04lxcnxq 4jOaUSk7dnBPb/Bo+5YoMyF4vhO6itXVz24wcbUta8xjI50= X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Follow the example of other platforms and specify core_clk frequencies in the frequency table in addition to the core_clk_src frequencies. The driver should be setting the leaf frequency instead of some interim clock freq. Suggested-by: Nitin Rawat Fixes: 57fc67ef0d35 ("arm64: dts: qcom: msm8996: Add ufs related nodes") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 80d83e01bb4d..401c6cce9fec 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2072,7 +2072,7 @@ ufshc: ufshc@624000 { <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; freq-table-hz = <100000000 200000000>, - <0 0>, + <100000000 200000000>, <0 0>, <0 0>, <0 0>, From patchwork Fri Feb 9 21:50:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 771508 Received: from mail-lj1-f176.google.com (mail-lj1-f176.google.com [209.85.208.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 234192110B for ; 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Bottomley" , "Martin K. Petersen" , Nitin Rawat , Can Guo , Naveen Kumar Goud Arepalli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Alim Akhtar , Avri Altman , Bart Van Assche , Andy Gross Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1349; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=qFaDb3+HsDF2bsx5hIZxH6UqlzjoVIko72glK0fFo+4=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlxp4ocXormBCjJV1YQU2TLy5kWlu8cty5tBadG rGlQyyYLwqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZcaeKAAKCRCLPIo+Aiko 1ZRpB/9W0blSBVKtdWzVaBEZ2OFl6Afuo/pny8EhwnN2UU+znkCUmxSShEiVqvj48eH2pJ77T3R A6lUeYVgjf/P+ofMLm6lFKjPP/1hSYh24Jj+3fqYFKK/9eqRLQ4lBJh9zk6xY9LUyhaCWGpVAzm dk67C0bPRsYr5BPdDAPysn+cxIqtXLs1AQL0RtwjjUWCcC+Yuzg3XPX9o8Fr2gm1lQqrDhSUAdU dsdVEnwLXs02SU243fSyFwt14NHHIFFS0ln8+MP7xFasMbDeB37vzGLqt1pCMlKGhpwoegV65/z DxAmOQFcGCOLf7HeXMy0O9wEx23H5VE1CYE+MkBTyYtvTkl7 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Describe the second RX lane used by the UFS controller on MSM8996 platform. Fixes: 462c5c0aa798 ("dt-bindings: ufs: qcom,ufs: convert to dtschema") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 401c6cce9fec..4472bbc7f058 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2057,7 +2057,8 @@ ufshc: ufshc@624000 { "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", - "rx_lane0_sync_clk"; + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; clocks = <&gcc UFS_AXI_CLK_SRC>, <&gcc GCC_UFS_AXI_CLK>, @@ -2069,7 +2070,8 @@ ufshc: ufshc@624000 { <&gcc GCC_UFS_ICE_CORE_CLK>, <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; + <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; freq-table-hz = <100000000 200000000>, <100000000 200000000>, @@ -2081,6 +2083,7 @@ ufshc: ufshc@624000 { <0 0>, <0 0>, <0 0>, + <0 0>, <0 0>; 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Fri, 09 Feb 2024 13:50:38 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 09 Feb 2024 23:50:36 +0200 Subject: [PATCH 6/8] arm64: dts: qcom: msm8996: set GCC_UFS_ICE_CORE_CLK freq directly Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240209-msm8996-fix-ufs-v1-6-107b52e57420@linaro.org> References: <20240209-msm8996-fix-ufs-v1-0-107b52e57420@linaro.org> In-Reply-To: <20240209-msm8996-fix-ufs-v1-0-107b52e57420@linaro.org> To: Manivannan Sadhasivam , Bjorn Andersson , Konrad Dybcio , "James E.J. Bottomley" , "Martin K. Petersen" , Nitin Rawat , Can Guo , Naveen Kumar Goud Arepalli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Alim Akhtar , Avri Altman , Bart Van Assche , Andy Gross Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=802; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=+sh35SiDz43Be9QOkvS4z1KDQSnZwszEyuZbCIKMEwo=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlxp4oYG5Gd0OLzMKalzNm4aoxG8kTBWMSGbKft HyDO5hljnCJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZcaeKAAKCRCLPIo+Aiko 1cmaCACmMi2HsX2bWSlLj5IRSe+5MEXfaRuiFjOAT/2ir+d4T1PLWQiYxEahuMih72XpyBlAiFA KbwPolTPR+mkf1F6hzsuEIP1knqgyNSY+qZURaaDmtzxuE/L6V0Be0yiIxbm8o9A8haIUcG9Q9h i/xWtLy/qwvniGoNcGPvxGZ7n9R487U5mYxjAJAiL/25v92OU5D8ZZU1uMb1FBtIH8XpJmQ/tt2 KjGvhOt1QHBv/xDScsOgs9OZFq0EbQiLGi0hh8oIufzS6F1kBChkLx3mU7GBM0i/KGpzY0t8YNR wLn7oWamLR1eRcEH/s7201keyP32knOPU8Xg9ECZErrVUkRc X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Instead of setting the frequency of the interim UFS_ICE_CORE_CLK_SRC clokc, set the freency of the leaf GCC_UFS_ICE_CORE_CLK clock directly. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 4472bbc7f058..6c847fdff192 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2078,9 +2078,9 @@ ufshc: ufshc@624000 { <0 0>, <0 0>, <0 0>, - <150000000 300000000>, - <75000000 150000000>, <0 0>, + <75000000 150000000>, + <150000000 300000000>, <0 0>, <0 0>, <0 0>, From patchwork Fri Feb 9 21:50:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 771994 Received: from mail-lj1-f178.google.com (mail-lj1-f178.google.com [209.85.208.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DFCB3770D for ; Fri, 9 Feb 2024 21:50:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Bottomley" , "Martin K. Petersen" , Nitin Rawat , Can Guo , Naveen Kumar Goud Arepalli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Alim Akhtar , Avri Altman , Bart Van Assche , Andy Gross Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1605; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=bl2Y26bAQOrF7Fx/WmrM2EjdC+b87dw5MwVD4zAMJ9M=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlxp4o6+ge7Ga9YGQOCLnWjLlEkJGho/D8fvUuQ Aqrb6MMCH+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZcaeKAAKCRCLPIo+Aiko 1ZJLCACXqw6fod0tdRakwnJftPOdGZeXy681leZj+s6dUQsa169uzUXrRvEvFQloADwOQqIbXNk VUdBVkAb/XFahK6KcHkJkm/gbTgZc4eQ4+PPyI7bvq4iPG8SD8+DhwN2SVlFhQ+85/3t56b/ZuW Fpw5quFC1JgywN1NdxQgdmOi2679ROlQjarkbYCmS+ml5wWde61ACWpqLWYyKHBksOzCXMsPYnM DIzAlqdvEB9xR4jahxlZHcRzdFTvfksPFNtevMwdJLKfk4ljGg/b4Jlp9HbCKXyF2lRDpyHkdSp pOV/F292IMoZ62bT0+oqAS6d/IEpMpnHBrclgXSQHSe3JZul X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A There is no need to mention and/or to touch in any way the intermediate (source) clocks. Drop them from MSM8996 UFSHCD schema, making it follow the example lead by all other platforms. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index f1de3244b473..e835f12c75ca 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -43,11 +43,11 @@ properties: clocks: minItems: 8 - maxItems: 12 + maxItems: 10 clock-names: minItems: 8 - maxItems: 12 + maxItems: 10 dma-coherent: true @@ -188,16 +188,14 @@ allOf: then: properties: clocks: - minItems: 12 - maxItems: 12 + minItems: 10 + maxItems: 10 clock-names: items: - - const: core_clk_src - const: core_clk - const: bus_clk - const: bus_aggr_clk - const: iface_clk - - const: core_clk_unipro_src - const: core_clk_unipro - const: core_clk_ice - const: ref_clk @@ -258,7 +256,7 @@ allOf: maxItems: 2 clocks: minItems: 8 - maxItems: 12 + maxItems: 10 unevaluatedProperties: false From patchwork Fri Feb 9 21:50:38 2024 Content-Type: text/plain; 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Fri, 09 Feb 2024 13:50:40 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 09 Feb 2024 23:50:38 +0200 Subject: [PATCH 8/8] arm64: dts: qcom: msm8996: drop source clock entries from the UFS node Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240209-msm8996-fix-ufs-v1-8-107b52e57420@linaro.org> References: <20240209-msm8996-fix-ufs-v1-0-107b52e57420@linaro.org> In-Reply-To: <20240209-msm8996-fix-ufs-v1-0-107b52e57420@linaro.org> To: Manivannan Sadhasivam , Bjorn Andersson , Konrad Dybcio , "James E.J. Bottomley" , "Martin K. Petersen" , Nitin Rawat , Can Guo , Naveen Kumar Goud Arepalli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Alim Akhtar , Avri Altman , Bart Van Assche , Andy Gross Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1516; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=74MCy96nF03W7EAJTz2PT10B7QEkB+SqtG1CDRc9HX8=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ+qxeZoc8focG91fuD+QiwgTVXfYLbhfe8ah0En9E7Tdd 2eHs5zqZDRmYWDkYpAVU2TxKWiZGrMpOezDjqn1MINYmUCmMHBxCsBFvNj/cJSpqqwrZ7xzo1w2 50q+6cGaxe6ChiynXr6PiT62e3qM/wze1yInZWtf1PqcsdIU5fM/ofFlR4fKI2u5Ezeudm3yZv8 9zT3cWGjew1ePOyZwrPvq0lhk65xpU6jq92/nLoHa6rRpB+YWh3FpWC6xYav1PqK0UmjTO+X0zE 7eP4IP2gLfcpsVXrPP1r/cECD1TruuoPXrNnWGyS5CzefP3jBveK3K2nth1SRZ14nXohancVaue RHBE7fp1YxH+6MCn/Y0dCeer5rCcOno49g8n2zpedfN57y9fz3LpmCV+cmVnPcMLpsy7JtWeD+6 9nbjxxjWdUf9yudybkl7sDN3zn7+n++8UpRyo7YF5JYDAA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A There is no need to mention and/or to touch in any way the intermediate (source) clocks. Drop them from MSM8996 UFSHCD schema, making it follow the example lead by all other platforms. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 6c847fdff192..fc44979d7902 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2047,12 +2047,10 @@ ufshc: ufshc@624000 { power-domains = <&gcc UFS_GDSC>; clock-names = - "core_clk_src", "core_clk", "bus_clk", "bus_aggr_clk", "iface_clk", - "core_clk_unipro_src", "core_clk_unipro", "core_clk_ice", "ref_clk", @@ -2060,12 +2058,10 @@ ufshc: ufshc@624000 { "rx_lane0_sync_clk", "rx_lane1_sync_clk"; clocks = - <&gcc UFS_AXI_CLK_SRC>, <&gcc GCC_UFS_AXI_CLK>, <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, <&gcc GCC_AGGRE2_UFS_AXI_CLK>, <&gcc GCC_UFS_AHB_CLK>, - <&gcc UFS_ICE_CORE_CLK_SRC>, <&gcc GCC_UFS_UNIPRO_CORE_CLK>, <&gcc GCC_UFS_ICE_CORE_CLK>, <&rpmcc RPM_SMD_LN_BB_CLK>, @@ -2074,8 +2070,6 @@ ufshc: ufshc@624000 { <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; freq-table-hz = <100000000 200000000>, - <100000000 200000000>, - <0 0>, <0 0>, <0 0>, <0 0>,