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envelope-from=philmd@linaro.org; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org DisasContext::saar boolean is never set, so this code is not reachable. Remove it. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/sysemu_helper.h.inc | 5 --- target/mips/tcg/sysemu/cp0_helper.c | 55 ----------------------------- target/mips/tcg/translate.c | 42 ---------------------- 3 files changed, 102 deletions(-) diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_helper.h.inc index f163af1eac..78f7272208 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -31,8 +31,6 @@ DEF_HELPER_1(mftc0_tcschedule, tl, env) DEF_HELPER_1(mfc0_tcschefback, tl, env) DEF_HELPER_1(mftc0_tcschefback, tl, env) DEF_HELPER_1(mfc0_count, tl, env) -DEF_HELPER_1(mfc0_saar, tl, env) -DEF_HELPER_1(mfhc0_saar, tl, env) DEF_HELPER_1(mftc0_entryhi, tl, env) DEF_HELPER_1(mftc0_status, tl, env) DEF_HELPER_1(mftc0_cause, tl, env) @@ -57,7 +55,6 @@ DEF_HELPER_1(dmfc0_lladdr, tl, env) DEF_HELPER_1(dmfc0_maar, tl, env) DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) DEF_HELPER_2(dmfc0_watchhi, tl, env, i32) -DEF_HELPER_1(dmfc0_saar, tl, env) #endif /* TARGET_MIPS64 */ DEF_HELPER_2(mtc0_index, void, env, tl) @@ -104,8 +101,6 @@ DEF_HELPER_2(mtc0_hwrena, void, env, tl) DEF_HELPER_2(mtc0_pwctl, void, env, tl) DEF_HELPER_2(mtc0_count, void, env, tl) DEF_HELPER_2(mtc0_saari, void, env, tl) -DEF_HELPER_2(mtc0_saar, void, env, tl) -DEF_HELPER_2(mthc0_saar, void, env, tl) DEF_HELPER_2(mtc0_entryhi, void, env, tl) DEF_HELPER_2(mttc0_entryhi, void, env, tl) DEF_HELPER_2(mtc0_compare, void, env, tl) diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c index 62f6fb4bf6..f8883a3515 100644 --- a/target/mips/tcg/sysemu/cp0_helper.c +++ b/target/mips/tcg/sysemu/cp0_helper.c @@ -371,22 +371,6 @@ target_ulong helper_mfc0_count(CPUMIPSState *env) return (int32_t)cpu_mips_get_count(env); } -target_ulong helper_mfc0_saar(CPUMIPSState *env) -{ - if ((env->CP0_SAARI & 0x3f) < 2) { - return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f]; - } - return 0; -} - -target_ulong helper_mfhc0_saar(CPUMIPSState *env) -{ - if ((env->CP0_SAARI & 0x3f) < 2) { - return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32; - } - return 0; -} - target_ulong helper_mftc0_entryhi(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); @@ -514,13 +498,6 @@ target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel) return env->CP0_WatchHi[sel]; } -target_ulong helper_dmfc0_saar(CPUMIPSState *env) -{ - if ((env->CP0_SAARI & 0x3f) < 2) { - return env->CP0_SAAR[env->CP0_SAARI & 0x3f]; - } - return 0; -} #endif /* TARGET_MIPS64 */ void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) @@ -1108,38 +1085,6 @@ void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1) } } -void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t target = env->CP0_SAARI & 0x3f; - if (target < 2) { - env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL; - switch (target) { - case 0: - if (env->itu) { - itc_reconfigure(env->itu); - } - break; - } - } -} - -void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t target = env->CP0_SAARI & 0x3f; - if (target < 2) { - env->CP0_SAAR[target] = - (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) | - (env->CP0_SAAR[target] & 0x00000000ffffffffULL); - switch (target) { - case 0: - if (env->itu) { - itc_reconfigure(env->itu); - } - break; - } - } -} - void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) { target_ulong old, val, mask; diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 12094cc1e7..173b19a090 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -5151,17 +5151,6 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CP0_REGISTER_09: - switch (sel) { - case CP0_REG09__SAAR: - CP0_CHECK(ctx->saar); - gen_helper_mfhc0_saar(arg, tcg_env); - register_name = "SAAR"; - break; - default: - goto cp0_unimplemented; - } - break; case CP0_REGISTER_17: switch (sel) { case CP0_REG17__LLADDR: @@ -5252,17 +5241,6 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CP0_REGISTER_09: - switch (sel) { - case CP0_REG09__SAAR: - CP0_CHECK(ctx->saar); - gen_helper_mthc0_saar(tcg_env, arg); - register_name = "SAAR"; - break; - default: - goto cp0_unimplemented; - } - break; case CP0_REGISTER_17: switch (sel) { case CP0_REG17__LLADDR: @@ -5680,11 +5658,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); register_name = "SAARI"; break; - case CP0_REG09__SAAR: - CP0_CHECK(ctx->saar); - gen_helper_mfc0_saar(arg, tcg_env); - register_name = "SAAR"; - break; default: goto cp0_unimplemented; } @@ -6406,11 +6379,6 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_helper_mtc0_saari(tcg_env, arg); register_name = "SAARI"; break; - case CP0_REG09__SAAR: - CP0_CHECK(ctx->saar); - gen_helper_mtc0_saar(tcg_env, arg); - register_name = "SAAR"; - break; default: goto cp0_unimplemented; } @@ -7180,11 +7148,6 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); register_name = "SAARI"; break; - case CP0_REG09__SAAR: - CP0_CHECK(ctx->saar); - gen_helper_dmfc0_saar(arg, tcg_env); - register_name = "SAAR"; - break; default: goto cp0_unimplemented; } @@ -7892,11 +7855,6 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_helper_mtc0_saari(tcg_env, arg); register_name = "SAARI"; break; - case CP0_REG09__SAAR: - CP0_CHECK(ctx->saar); - gen_helper_mtc0_saar(tcg_env, arg); - register_name = "SAAR"; - break; default: goto cp0_unimplemented; } From patchwork Fri Feb 9 09:05:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 771302 Delivered-To: patch@linaro.org Received: by 2002:adf:9dca:0:b0:33b:4db1:f5b3 with SMTP id q10csp749643wre; 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envelope-from=philmd@linaro.org; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Previous commit removed the MT*C0(SAAR) helpers which were the only calls to itc_reconfigure() out of hw/, we can reduce its scope and declare it statically. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/misc/mips_itu.h | 2 -- hw/misc/mips_itu.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index 5caed6cc36..3a7330ac07 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -79,6 +79,4 @@ struct MIPSITUState { /* Get ITC Configuration Tag memory region. */ MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu); -void itc_reconfigure(struct MIPSITUState *tag); - #endif /* MIPS_ITU_H */ diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 37aea0e737..db1220f8e0 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -86,7 +86,7 @@ static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size) return tag->ITCAddressMap[index]; } -void itc_reconfigure(MIPSITUState *tag) +static void itc_reconfigure(MIPSITUState *tag) { uint64_t *am = &tag->ITCAddressMap[0]; MemoryRegion *mr = &tag->storage_io; From patchwork Fri Feb 9 09:05:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 771304 Delivered-To: patch@linaro.org Received: by 2002:adf:9dca:0:b0:33b:4db1:f5b3 with SMTP id q10csp749912wre; Fri, 9 Feb 2024 01:06:51 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXLguVRVdtGF1Y72F5jLgEoab8YUdQnL9gwn0mBzAg33z61fao8+AWMJVf+++byzF2p9ogXoPK+o2Q9KObSajjh X-Google-Smtp-Source: AGHT+IFvqS6Kgp+ndwfwgsdN/+LBxxOdxn5SdXm/ydisPOx0cLkZmK8ObW6xCbHZ3IHgcBPBrRCN X-Received: by 2002:a0c:b549:0:b0:68c:9649:df96 with SMTP id w9-20020a0cb549000000b0068c9649df96mr437224qvd.12.1707469611757; Fri, 09 Feb 2024 01:06:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1707469611; cv=none; d=google.com; s=arc-20160816; b=DN9E5QqExGHOY4kC6tUsXjdM3lujX9awNE047q7rdEnnu2P5lzWsFnXfsnozKflz6l 3wSLDq4l6wr8QdbfTfz3zzP1EJIpLk7IpZNYnB2WeHm+BpY72UHQ+5BYjrF19ONKHRg3 +/wSedUpYHXlQOtQwvXPmq/ywVQiNY3pIAVk496CqDQ0aUPHZ4Ki7ebk0wd3Gmg9dr6F CdlKw/4qho8jh8Q+KehqT2iQbRTVJh2tLcf6LvD8DZTVncCBlEHtvaNC1wgHPNjJOs0C /QGReld7VFrxexX6MZowEag8kRktd06/plzjmpBNsHdYYAkLTYmdIukt6drrNXqLQDBu fggQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=HTBcOkyf9XYobNj1mcoJBJIN9decb6okix3YTMtoBGI=; fh=C/n9JOzwF46TH1Bn3VQcZncL+mekiQQEthqoCOe4fuQ=; b=l4wp25zR1tEEA2diZPo7JfmD+P9B3UcT3Al4tJ18r90Q5HiZP/sxSKdZ8Q3a5vAfS+ T801Y1CAOrGZU2wM3Hfnz/nyuzYzSr+89ga2ukT0jO8ZOXhTVj3y5uw/t4jaN2oPDlFB qSP+N0MqR6M8i3g4UqlOj2wWCU+4AB6HirVTvMxGcz6IJMzt7xEop9xRPYgCSdqxMNtE P/okHvC9BF4woApegYJ1LM/EouYZEgN6nge+JWFbPGZ4wB2B9QPw6OqeBVn0+byEyi9V FBXOpuf9h7Ty81aRIi6h6ZEKBAxZpfhnRSq01R3GM8H6vSjRrfF/0A3C6AXxPk3R5RiP RutQ==; darn=linaro.org ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hFScsn7B; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=1; AJvYcCWrCO6YqcjCh+U+f5rD7MTPIkKm899bLNPREI53uLH2MrJ/kfvVP/aFRZW+JHQtFlJ6Tf0NrJ5eSZ1Rseo7R5Vi Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.h | 1 - hw/mips/cps.c | 1 - 2 files changed, 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index ef26fe03c7..6ec2ff4b97 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1184,7 +1184,6 @@ typedef struct CPUArchState { #if !defined(CONFIG_USER_ONLY) CPUMIPSTLBContext *tlb; void *irq[8]; - struct MIPSITUState *itu; MemoryRegion *itc_tag; /* ITC Configuration Tags */ /* Loongson IOCSR memory */ diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 4f12e23ab5..988ceaa0b9 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -96,7 +96,6 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) itu_present = true; /* Attach ITC Tag to the VP */ env->itc_tag = mips_itu_get_tag_region(&s->itu); - env->itu = &s->itu; } qemu_register_reset(main_cpu_reset, cpu); } From patchwork Fri Feb 9 09:05:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 771306 Delivered-To: patch@linaro.org Received: by 2002:adf:9dca:0:b0:33b:4db1:f5b3 with SMTP id q10csp749925wre; Fri, 9 Feb 2024 01:06:54 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXH5bMMA2gm9RIOyjL5ssqHQtiJV519HyUaDwqqQQfeALpIbdc+cjjzGCVVFc+snPqoXESfu92B4H4WQJbsHRAZ X-Google-Smtp-Source: AGHT+IHtHq3GCFt4Yza+qM5NPwnKvonIDE+X+NsCwm1w+GATK/c/ggpdHmC5D0gEbtVktHZVKRpG X-Received: by 2002:a05:620a:21d5:b0:783:20c4:663f with SMTP id h21-20020a05620a21d500b0078320c4663fmr950820qka.67.1707469614130; Fri, 09 Feb 2024 01:06:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1707469614; cv=none; d=google.com; s=arc-20160816; b=WJHcabdXKRVpfNR4/ZKWgerBf182JOoS134Vq8Ixa+fbWirSmsSR3IXP6Cxtz50GHW B7cr80fU+US4ZKAwuMukOt5PIKBF5SC1OVbGNuTFx+K3gt14o3wkRGdDPJr+bRYWM3N0 +kJalVHsNNmlKiA7BiBQXg+JQka7Cnp/whnaAvhqwfxeLvnnrgUpgMGXSmRCWG4Gtrtl 191kLd0q0i2IDoSVhT02WoX2LqH5PERkArcaB1ioJ4UD7bRi05IUAl4mUOHulaxhdIym pr0R7Nbil3VMedi4I2l9om3b4awWrlSxrf+3sorOLMjfwy2XMzBYMWBV49wMaZl6sTK4 Q/0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vBAiggojLFMqRRiAH15aXDVwluwADGNW6uYXJNwpeRo=; fh=00lx5aYMpLgJtYqrnqQyGam3owncuRVv/sEJjw/Q5bg=; b=C7SnngAXZI9UOBhCwE863sSjH6cWYa7DeESg02yV0/JZ+TQ9JHzUI+u3nJv7k1Pyfm d/k+SdhTLIFA0RW2th2/09cYfB/LPgrQ7CR/uHRdz/A2lzRz3Z9c0OZ5pDbiBOsL8rGH uR+IoowetKAuEn7gj5Fj1YyZVS71qSa47C8NYhz6G6HAFEmi1bBInDXb3ddJdEUNaNmL Iyl6pyJEOHHBUXyBxkdOU+kXLyHjvUHG7J18jQ0qmPSEBeU95cpu/ApXxwRUFNgKpA43 RZXp0bWVlib9QpplbzC4oFM7YU3VNOqDQC09p7ztnXsQSvYIVOslYhDnFu6bMTemnWAE GrIA==; darn=linaro.org ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cHdsujh+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=1; AJvYcCUS/PziQ+wxRUw8O3JBChT2tbMLqMhaHUWRS+51GdrWIQ5n24HwyxHbQOUcjMBydQa6EtNrpaRMZprYU9jn/ztk Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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envelope-from=philmd@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This field is never set, so remove the unreachable code. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.h | 1 - hw/misc/mips_itu.c | 6 ------ 2 files changed, 7 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 6ec2ff4b97..3b93591f7e 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1174,7 +1174,6 @@ typedef struct CPUArchState { uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ uint64_t insn_flags; /* Supported instruction set */ - int saarp; /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index db1220f8e0..d259a88d22 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -516,7 +516,6 @@ static void mips_itu_init(Object *obj) static void mips_itu_realize(DeviceState *dev, Error **errp) { MIPSITUState *s = MIPS_ITU(dev); - CPUMIPSState *env; if (s->num_fifo > ITC_FIFO_NUM_MAX) { error_setg(errp, "Exceed maximum number of FIFO cells: %d", @@ -533,11 +532,6 @@ static void mips_itu_realize(DeviceState *dev, Error **errp) return; } - env = &MIPS_CPU(s->cpu0)->env; - if (env->saarp) { - s->saar = env->CP0_SAAR; - } - s->cell = g_new(ITCStorageCell, get_num_cells(s)); } From patchwork Fri Feb 9 09:05:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 771313 Delivered-To: patch@linaro.org Received: by 2002:adf:9dca:0:b0:33b:4db1:f5b3 with SMTP id q10csp750142wre; Fri, 9 Feb 2024 01:07:28 -0800 (PST) X-Google-Smtp-Source: AGHT+IHfXwa/v2rUO7CTthl1daZvaamg+Vrt4XXypp0P6lLEVFGoSAvRnQNv38gwnB2re/mLUsUJ X-Received: by 2002:a1f:df84:0:b0:4c0:23a8:df2a with SMTP id w126-20020a1fdf84000000b004c023a8df2amr798127vkg.10.1707469648591; Fri, 09 Feb 2024 01:07:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1707469648; cv=none; d=google.com; s=arc-20160816; b=TjHwRWI/767rPHtgtA1fM4tgmVB6jQpSku4/mFgxBxE1bzRAMWxIrtjY9H7cGof0KW QEFRWVlAuC2BzrAIf/SBBPl4Q39b+GFa5nOUFXS8kFwsM97M2uTEdMpvhwV0IM4KGG/2 quUZh8xrpApmAZImPZuUAQX9NPQ/aNPfwPaQlz5DbC83HYkXxeMFHTgOK31X1m4IBahq MXIfJJ6sqz36hzK03dRfKK38FEm6xQzVa7PJoALfeLNTinSxr+AcAxMOLXwTbcqpPe4u iwesv+J9WTUy9VvOCeKQt3+06nRG+byfXWsZBTUuzSdwvBDYMroG3Sy0+x3NssKtJvDZ FoBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Qpf2BCRR7hPdbIWz71eTijHKC+DHO0kimrwlNqyg5K8=; fh=IA2AIxR9wkIbXe5P9jfS/INudHWsdPFjAjBn7p8O+1E=; b=vd3OWFUwHvfoCoIP4fRswmRn4OjoKGxBdZCXzvyYzEs5th2nWlvvj/mm4kvSrS1ckM XkO77JUPmb0SINslCSwf1E2TDDSVcs23IIcaiO4fzdmahB55f354YVJYlUy2V/4MEEgu fYNAT3ddwLufrguHKiZuMK/LZVp18V4yN6igWSVQIN2j5wo2HphA8atyWulJk1MuQFU/ p8WWScy/EuS293IHWcCMP84cJqsbc5uhdllet/rihas0UqDR3LhxEeuNH7WaUTYirbhG 3eQmJsKAzoDPTnXfbxEcmVsyPrFcfoYIe87u0EWyjr8KTDZf9qtfGwQkNLBHzXJibgMK g59g==; darn=linaro.org ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XcOz3sHw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=1; AJvYcCWGRy18e3EOvqc5OsqcOZY9sp3W0LzkITcWmUWqzTVic2X7NwO6Gzp8qa/nRhAB99n0HC0wtz2IZgM8kgaS0L/T Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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envelope-from=philmd@linaro.org; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since previous commit the MIPSITUState::cpu0 field is not used anymore. Remove it. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/misc/mips_itu.h | 1 - hw/mips/cps.c | 2 -- hw/misc/mips_itu.c | 5 ----- 3 files changed, 8 deletions(-) diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index 3a7330ac07..de7400c1fe 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -73,7 +73,6 @@ struct MIPSITUState { /* SAAR */ uint64_t *saar; - ArchCPU *cpu0; }; /* Get ITC Configuration Tag memory region. */ diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 988ceaa0b9..07b73b0a1f 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -103,8 +103,6 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) /* Inter-Thread Communication Unit */ if (itu_present) { object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU); - object_property_set_link(OBJECT(&s->itu), "cpu[0]", - OBJECT(first_cpu), &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16, &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16, diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index d259a88d22..9705efeafe 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -527,10 +527,6 @@ static void mips_itu_realize(DeviceState *dev, Error **errp) s->num_semaphores); return; } - if (!s->cpu0) { - error_setg(errp, "Missing 'cpu[0]' property"); - return; - } s->cell = g_new(ITCStorageCell, get_num_cells(s)); } @@ -558,7 +554,6 @@ static Property mips_itu_properties[] = { ITC_FIFO_NUM_MAX), DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores, ITC_SEMAPH_NUM_MAX), - DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, ArchCPU *), DEFINE_PROP_END_OF_LIST(), }; From patchwork Fri Feb 9 09:05:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 771307 Delivered-To: patch@linaro.org Received: by 2002:adf:9dca:0:b0:33b:4db1:f5b3 with SMTP id q10csp749968wre; Fri, 9 Feb 2024 01:07:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IFuSWy+S+DKwanXSFOqDepZWjce0vQ9qi6Kzrs1k1m3gQ49jux8dJwwaRas2lebe6oRbPWl X-Received: by 2002:ac8:5c0d:0:b0:42c:51e1:9b15 with SMTP id i13-20020ac85c0d000000b0042c51e19b15mr1196970qti.14.1707469622821; Fri, 09 Feb 2024 01:07:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1707469622; cv=none; d=google.com; s=arc-20160816; b=j12nnRxzOeuYE+XvSQG1jXS3bKDuWSEQPr8w/QsEqVzKJEOFUkJSit7nxTd+q60W+z Cat53izlTUc8dYYXFFGsrQO6JfAUM6j5dMCoVVe+dJ8DF81SdCA8CslCPkErQUoweUIl EU9s6FEDb239Hil3bVvXe5Uts/YMxr+ZGsNpAyunoHbFFIDjo/ZAho8EqSBaBgU7Z1tH 8KEgahw9CpXxEwB/NrCGbm/K3VYdwolEWKa39lcTtxssYssZuSASVL3JC5RlkPYnE8px L+Kh9+kwIV1y++s0zuFri0jSiBdw3Qg2Pj56Yq6uP4vgnjCxbcNF0kTppMq3oYohCUb6 C13A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ahGl576821/GPhzoaU/l92B3Gi9UsGeCtBiy/M2bP2c=; fh=dMwjZAYe5EARx7/Rw+0an66BmxFhm+UdfqrI8Wwe6EY=; b=hyUoQ24iHP9FPupsM8XbLotmoiCc39gOW2GN3nFPzjWQWyD2fSfbXHP8qeEdXpzDSt zXD2Wp01rADXAJAYNbizeSH5EgLFw0UTAr/ucZdGluuudBHLP2n1kLRroGBng6xDA84E PrMtWF7XkfMl+2Ha4G1pKcIYBNvsNXFUvqcPDKVMj5hnu60/QsCnnnxkB1Ic/zpNc9y9 pqG2X5medlGamuRbJv7gy2OlMsowXx0hbwipmrDcZ9p+3HncV8tD9fEubEakpdgPKoTI sioAiTsPzcvxzkIKut9e+HvHRAXT5Zgx6lfs7ZFHrWF3zVnfTzqdO7f31EBbxQ2R2fx2 Je7w==; darn=linaro.org ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zRAabjQh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=1; AJvYcCVEqycdT51x0fr8xJbTbsnL5hb+AW9xLbIvLUb1T8HOc5RzOacD+FuyByfmMRNZtJdaVJzfJakHWQio+HDpXTqa Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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envelope-from=philmd@linaro.org; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This field is not set. Remove it along with the dead code it was guarding. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/misc/mips_itu.h | 3 --- hw/misc/mips_itu.c | 22 +++------------------- 2 files changed, 3 insertions(+), 22 deletions(-) diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index de7400c1fe..27c9a1090d 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -70,9 +70,6 @@ struct MIPSITUState { /* ITU Control Register */ uint64_t icr0; - - /* SAAR */ - uint64_t *saar; }; /* Get ITC Configuration Tag memory region. */ diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 9705efeafe..f8acfb3ee2 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -94,12 +94,6 @@ static void itc_reconfigure(MIPSITUState *tag) uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK); bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0; - if (tag->saar) { - address = (tag->saar[0] & 0xFFFFFFFFE000ULL) << 4; - size = 1ULL << ((tag->saar[0] >> 1) & 0x1f); - is_enabled = tag->saar[0] & 1; - } - memory_region_transaction_begin(); if (!(size & (size - 1))) { memory_region_set_size(mr, size); @@ -158,12 +152,7 @@ static inline ITCView get_itc_view(hwaddr addr) static inline int get_cell_stride_shift(const MIPSITUState *s) { /* Minimum interval (for EntryGain = 0) is 128 B */ - if (s->saar) { - return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) & - ITC_ICR0_BLK_GRAIN_MASK); - } else { - return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); - } + return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); } static inline ITCStorageCell *get_cell(MIPSITUState *s, @@ -535,15 +524,10 @@ static void mips_itu_reset(DeviceState *dev) { MIPSITUState *s = MIPS_ITU(dev); - if (s->saar) { - s->saar[0] = 0x11 << 1; - s->icr0 = get_num_cells(s) << ITC_ICR0_CELL_NUM; - } else { - s->ITCAddressMap[0] = 0; - s->ITCAddressMap[1] = + s->ITCAddressMap[0] = 0; + s->ITCAddressMap[1] = ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) | (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS); - } itc_reconfigure(s); itc_reset_cells(s); From patchwork Fri Feb 9 09:05:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 771309 Delivered-To: patch@linaro.org Received: by 2002:adf:9dca:0:b0:33b:4db1:f5b3 with SMTP id q10csp749995wre; Fri, 9 Feb 2024 01:07:08 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVXrN9ztTvAUYrk7X01gDDMY5k2ZsQ9JeeYIummIZoNxTqScHTkYBBo3wfB1eUsXd07TdgBYRV2EVA9i2dQebKg X-Google-Smtp-Source: AGHT+IELwvdieznli6feJl0KTA6IHpL34ZhhtFtL2DnhUPldUOCdseSXjuyA/xlJ1saCaMPBEOhx X-Received: by 2002:a05:6102:cc8:b0:46d:6587:4bf0 with SMTP id g8-20020a0561020cc800b0046d65874bf0mr710079vst.20.1707469628173; Fri, 09 Feb 2024 01:07:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1707469628; cv=none; d=google.com; s=arc-20160816; b=dAeTvam3+n48p1ZVSWoo3B5KNBVAsfmGG6Q91VDKKjjUMe0I3q4Zd/x0AnyufieAct fYxfRrf6D78wiy+i8mFftHqgAgY8pZ0ZnP+fUUVJNAVSAZJr7OQrZof7ePL9YPNstfeM jRVcSCVlPqXcXzW4d3wtuRL1VG77U+GWs+qi5BkueXLUgCtNgH/Dn32dt/PACM5DgOXf yK7FwZ/8SsgjuZKcse5gzwb7oCNwKeuyMfPOdHH4zpmWPEd36hCs3f0lmFaZHEx4Awkz PNdHqcOg3uI5m6lVFscYJRSzArxvLH+iUcBH1IMDt8ydRvytCrVnWf0dyzunJ7f0/yXd 1JOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=y81PALGbwlj4LEixOoZpqNxmKjEUvcPM6tG+ojj/Tqo=; fh=pdLzg/PlLkz3bcH/NzyBBjV37d3H+RllWbNGZwbA9bw=; b=GSOV1wS5EwFZTg6LV6J2O/OuFAARd81I5mAWmyGIg9un4+SKftaOabo4Rt3J16wqAP +L0WdRNq6rvVztqB02D8eIUmD3L+EZdb5mTC8nlM42apkMD3cCwvLpGmWD7E0wF03WxQ kiuAXlP8Q0xbmm5bM2gp4gYXmFCbWpcWv0/fpSVFMyQ7XvR8eoekhDNbZTWZyFrW5w+P NOY9M4TAGEoNuG3yuNb7STYagvYKjqpU+EQYUQt7xr0RdoIQS6qMNkC9RCe6e+qtrzvM HpFZhsKWe3SNXwCg0TkLGXbK1o8H/UQJz6X+Y8Q7rFomrgmDslZKeAd8PN5xRDMRUF0i R/2Q==; darn=linaro.org ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mZMa+xlH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=1; AJvYcCWV4PjuTptSWnTe+znzsozz6vtv0oT/0z5Ea13AQIN+3JRmneiOyZWYt8X0Gsn2Zf14Z6ssZ4HHqlS/MtkzgVcT Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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envelope-from=philmd@linaro.org; helo=mail-lf1-x130.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Remove the unused CP0_SAAR[2] registers. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.h | 1 - target/mips/sysemu/machine.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3b93591f7e..e621196ae1 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -749,7 +749,6 @@ typedef struct CPUArchState { int32_t CP0_Count; uint32_t CP0_SAARI; #define CP0SAARI_TARGET 0 /* 5..0 */ - uint64_t CP0_SAAR[2]; #define CP0SAAR_BASE 12 /* 43..12 */ #define CP0SAAR_SIZE 1 /* 5..1 */ #define CP0SAAR_EN 0 diff --git a/target/mips/sysemu/machine.c b/target/mips/sysemu/machine.c index 218f4c3a67..6d1299a89e 100644 --- a/target/mips/sysemu/machine.c +++ b/target/mips/sysemu/machine.c @@ -282,7 +282,7 @@ const VMStateDescription vmstate_mips_cpu = { VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU), VMSTATE_INT32(env.CP0_Count, MIPSCPU), VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU), - VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2), + VMSTATE_UNUSED(2 * sizeof(uint64_t)), /* was CP0_SAAR[2] */ VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU), VMSTATE_INT32(env.CP0_Compare, MIPSCPU), VMSTATE_INT32(env.CP0_Status, MIPSCPU), From patchwork Fri Feb 9 09:05:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 771308 Delivered-To: patch@linaro.org Received: by 2002:adf:9dca:0:b0:33b:4db1:f5b3 with SMTP id q10csp749982wre; Fri, 9 Feb 2024 01:07:06 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXKry6Ax0R+hA3s9AafXzpCiDlSlrhqR9JHRcEViJB/Un6TjGg2WdGSfE7u0ieKK+wg4OdKCoaOy2iDzsYG1a2n X-Google-Smtp-Source: AGHT+IH+t6q0/zRHEI6M+tkcY8ZPhyfwzhCvVArV41UqpoLb5eNmJ4s/7RGVIr2PdPS+IWJBZNXK X-Received: by 2002:a0c:e08d:0:b0:68c:7672:1830 with SMTP id l13-20020a0ce08d000000b0068c76721830mr1030847qvk.22.1707469626330; Fri, 09 Feb 2024 01:07:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1707469626; cv=none; d=google.com; s=arc-20160816; b=pB+Y2Og3KT42gDU830+xDs4QTMdmQICyDPihQzZCCQpW3sBdt2W4fjSUEMV48NGqHS GjdOzAM6TOjLqk8gaPPi3xJ9EGU0XHvajP0cCkQaiyBibHqusjTus2Fn1dIZoEg3uTlE hHwLX+IlUVL+44xTNiBU1sIzttKbnoWOlF8nXZX2dKHn64QPepkizfxqUdbvTty8zvvf q9GPSj0LEqOP68rG7yDk1fysw1blHRhTe7GpsishxOITLlz8+Blo4nBNDPslhi65xff3 3l+ZxOw2K2XvT058ceQltzZEMTK7KoeiqlwrIuGPTqJ6FcD9veDzz9ap6kcI5OtrZGKo uHkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nKmjKPYaXqxtBmNfQKEzaMf5GSszmv9atx7nueaYzHE=; fh=/Zm7KjJoMUiUUk51qlB9ZRu2RwqdRunGCM+NxQIb/Ws=; b=pwXlB82MXaFL8pb40oX5aQAMNe7HQhTDMG5EC+3CNRG/C290cH/brfQKR6pJylXGBn +jdxJTT8EGoD5X5Y4uJZmnwvlrgE1lajMyhFkUeRNjKua1fLO77kg/MxhwVCmaKBBjlb IZ1o8+bhAPCRmKhZWoK3e8A36mMLOcxUtOm/l4K2eKJx3oY2OG93IHFNnj0JQoTdD9Kq dKChB+SwelItJe4zKL/TOi2XqV9zWSp8uW09jtFsMFXO3Of6p6I8YpjH9PE/UEGcoAze SRmqNRhG+dGwxVvMkh5KzuHLikfRSVvtVj/W2H2oEnduAq3OaCF1dPIGqJAiTV6sZ9SB P1CA==; darn=linaro.org ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zwCjor+m; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=1; AJvYcCX+RyX/XgXwW/UXoTqFrF/NX5S/QX7WQozqaYoLY83tuwUgGegXMlhzkblX5MGz4EGNqNqQG03GYY9dBfu2dpsX Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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envelope-from=philmd@linaro.org; helo=mail-lj1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org DisasContext::saar boolean is never set, so this code is not reachable. Remove it. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/sysemu_helper.h.inc | 1 - target/mips/tcg/sysemu/cp0_helper.c | 8 -------- target/mips/tcg/translate.c | 20 -------------------- 3 files changed, 29 deletions(-) diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_helper.h.inc index 78f7272208..1861d538de 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -100,7 +100,6 @@ DEF_HELPER_2(mtc0_srsconf4, void, env, tl) DEF_HELPER_2(mtc0_hwrena, void, env, tl) DEF_HELPER_2(mtc0_pwctl, void, env, tl) DEF_HELPER_2(mtc0_count, void, env, tl) -DEF_HELPER_2(mtc0_saari, void, env, tl) DEF_HELPER_2(mtc0_entryhi, void, env, tl) DEF_HELPER_2(mttc0_entryhi, void, env, tl) DEF_HELPER_2(mtc0_compare, void, env, tl) diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c index f8883a3515..ded6c78e9a 100644 --- a/target/mips/tcg/sysemu/cp0_helper.c +++ b/target/mips/tcg/sysemu/cp0_helper.c @@ -1077,14 +1077,6 @@ void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1) cpu_mips_store_count(env, arg1); } -void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t target = arg1 & 0x3f; - if (target <= 1) { - env->CP0_SAARI = target; - } -} - void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) { target_ulong old, val, mask; diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 173b19a090..3ba2101647 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -5653,11 +5653,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) ctx->base.is_jmp = DISAS_EXIT; register_name = "Count"; break; - case CP0_REG09__SAARI: - CP0_CHECK(ctx->saar); - gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); - register_name = "SAARI"; - break; default: goto cp0_unimplemented; } @@ -6374,11 +6369,6 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_helper_mtc0_count(tcg_env, arg); register_name = "Count"; break; - case CP0_REG09__SAARI: - CP0_CHECK(ctx->saar); - gen_helper_mtc0_saari(tcg_env, arg); - register_name = "SAARI"; - break; default: goto cp0_unimplemented; } @@ -7143,11 +7133,6 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) ctx->base.is_jmp = DISAS_EXIT; register_name = "Count"; break; - case CP0_REG09__SAARI: - CP0_CHECK(ctx->saar); - gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); - register_name = "SAARI"; - break; default: goto cp0_unimplemented; } @@ -7850,11 +7835,6 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_helper_mtc0_count(tcg_env, arg); register_name = "Count"; break; - case CP0_REG09__SAARI: - CP0_CHECK(ctx->saar); - gen_helper_mtc0_saari(tcg_env, arg); - register_name = "SAARI"; - break; default: goto cp0_unimplemented; } From patchwork Fri Feb 9 09:05:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 771303 Delivered-To: patch@linaro.org Received: by 2002:adf:9dca:0:b0:33b:4db1:f5b3 with SMTP id q10csp749838wre; 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envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Remove the unused CP0_SAARI register. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.h | 1 - target/mips/sysemu/machine.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index e621196ae1..c65e5fa162 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -747,7 +747,6 @@ typedef struct CPUArchState { * CP0 Register 9 */ int32_t CP0_Count; - uint32_t CP0_SAARI; #define CP0SAARI_TARGET 0 /* 5..0 */ #define CP0SAAR_BASE 12 /* 43..12 */ #define CP0SAAR_SIZE 1 /* 5..1 */ diff --git a/target/mips/sysemu/machine.c b/target/mips/sysemu/machine.c index 6d1299a89e..213fd637fc 100644 --- a/target/mips/sysemu/machine.c +++ b/target/mips/sysemu/machine.c @@ -281,7 +281,7 @@ const VMStateDescription vmstate_mips_cpu = { VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU), VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU), VMSTATE_INT32(env.CP0_Count, MIPSCPU), - VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU), + VMSTATE_UNUSED(sizeof(uint32_t)), /* was CP0_SAARI */ VMSTATE_UNUSED(2 * sizeof(uint64_t)), /* was CP0_SAAR[2] */ VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU), VMSTATE_INT32(env.CP0_Compare, MIPSCPU), From patchwork Fri Feb 9 09:05:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 771312 Delivered-To: patch@linaro.org Received: by 2002:adf:9dca:0:b0:33b:4db1:f5b3 with SMTP id q10csp750113wre; Fri, 9 Feb 2024 01:07:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IHtFzvt2W9HeU2eGQ+5cKz8Omb1XHaTtRfwH+5tFr0X0UmfMvAkRRQwgQNNjbQSKnLqt4fv X-Received: by 2002:a05:6808:1456:b0:3bf:da3a:cf15 with SMTP id x22-20020a056808145600b003bfda3acf15mr1072768oiv.40.1707469645274; Fri, 09 Feb 2024 01:07:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1707469645; cv=none; d=google.com; s=arc-20160816; b=xx4axDtBL15i+oNQLwQNBeEMKOcelClzCZDK1Lpe2I+4pVuhS3VyxTVtxhaXTzut7K SPZxwapfLXuGemXkswiupy2kSEsu+6pKWS83iCbMKXURVn+zG/By5k/IiM1717Im3zey tK1qTlEF9JE+6Qmr/jLDUspLMvp4E/siobxgsvxjv+ZBrnjUdHYQSjbjcHfI/LIlkvAl qykBsJ82pEzUBtPQ0hgMoJcBRfCIE9wVbRbW6K5Kmd7uSOwNmGFjYTi7MXcyIdro6WIO 2l7XTTVHk2mtumtfYSkC4tWZwd6jwJagP0tVvbCjnNv1eE8Y70ASUVvJ0NakWPM/cIxo 8yvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cbHg54FPHaJAybTU864EBj6Jitha7wqkJSQ/7bQlzd8=; fh=0zal1Yq1a1STGMCQiHkm6xnAr4pMwQQCh9OYf8mYiEs=; b=BsStykNCs/e2YBu5y53vB4O5RkZNEAuXNCt1lQKt9HxW5atHAOhEoPeYL6oS7CT0/4 01+9p15bxJMqwdMtDy2hROL4xP5e3jBwOYKeARQXh7r3t4/zbbtO15xKNvYqOamjgsUt 86TfqF/ng86Wau3AV44RPHeM+b/jMV0y59v4xwMUcCg23w6RhSjno+1Pk/U2Hd/I+inT TexjSCEg7NhMdnHqBv1PHTLq3uuOyhNVnIRonIY8ONWH2Gf+/2FUhuE0zxcxszoTHHWU piXd7lDn5baFYazltHLyj5W9boRyTIITpGVhBxG2Z2bWMj4CjOBwrEoO3pxWaLly9vba iKDQ==; darn=linaro.org ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hanzaiZp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=1; AJvYcCXyOdiLSvIjphi8t6cgy1NDJ1jL5O8ptBtYEOxmNOY9pprQ71ItO6ptax/noTnj1PBtdUEFkWLLHhj+yEI7VVb4 Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org DisasContext::saar is not used, remove it. Reported-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 93a78b8121..2b6646b339 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -49,7 +49,6 @@ typedef struct DisasContext { bool mrp; bool nan2008; bool abs2008; - bool saar; bool mi; int gi; } DisasContext; From patchwork Fri Feb 9 09:05:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 771311 Delivered-To: patch@linaro.org Received: by 2002:adf:9dca:0:b0:33b:4db1:f5b3 with SMTP id q10csp750102wre; Fri, 9 Feb 2024 01:07:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IHJZKTXu3PoQ7nfvBLvg5jDu9tMS0UbNN0NxDFkXlw35Z6pykzWx5gDNbRvNfQzQsv7XojK X-Received: by 2002:a05:620a:40d6:b0:785:b921:40a0 with SMTP id g22-20020a05620a40d600b00785b92140a0mr646812qko.17.1707469643100; Fri, 09 Feb 2024 01:07:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1707469643; cv=none; d=google.com; s=arc-20160816; b=YKlWKHKO9HRAldL85eWbAdx2r9OukPuBMvFOmkWrJuMsaT5GZdspMs7ZM0SQiMsPYo pSFYILj7+H4+EUCRrPzSlLV7SybgiAv2ACkha705aopaiR6SZtQ+rPx4hINldRHDWKlj HMHNj0qQeMQIIF+tg4tMbrCFEhURDO1CPpHgNgLtQK60947uue06hNv/fjlV0hHLy187 Z3Gk7dPdkPfIpJGPDnma26B5P7FqJF4/NWBVAld9g3SNIl2V9mvznIW0oKSR+XSe7eYR byvH6/PJdw0imEk8jIm/+7WnLXbeuMhNQ/nDb3tF1qYLFn2vWI9Cm755LkWXgKGT2i0O ETKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yoZvEPhif8MxqPqYvi0f+lZWa93ax0j+gUCJerzTQQw=; fh=JwQZGt6gKSWmVs6IcYv/ESPt1X9AlNLrrbfTwiVvwVY=; b=oz4TD6X7LolvsFf5I5JdEAVB5/g8SJiB7qNWh4eqrnhsZOOuUegj6Ij3vQrOo0i1a2 fTxy3MFh5tnCZFvr4Mr/aYVWD0qcaKamwjWv2WzqS5VwlVZBkIjHhjruOYcf4lpwmIBW r1jz+9uCfRxc7w1Kul0SVUqm1JiQx7kJ3ZJ9bTEs7u1IaxQbpVa5BeByZz5+NG3b4fNI xSeDaD1PxBFFCzFeHqrkxzM+GXDo4s4laavxIA4xpKIkxmGOB/7mxg16Dz9uLcPbCZf8 C9DWm/3cGHcbWpRNSk6cNkkWFjhQkRWXZlHJlTE1MvZSUboqw79Iv/rPt6tLCG+Xvwhh KnVw==; darn=linaro.org ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="L/DsYVm/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=1; AJvYcCWX2EugSQ8ogx2BMQt1zmtBU1/QhFoUdkh10HKrPKMZfGVuoiLacsFYMEeeS7nkpt9ZTHNL87fm7jU74KMqcis/ Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org I6500 support is incomplete as it lacks SAAR (Special Address Access Register) and DSPRAM (Data Scratch Pad RAM) features. Signed-off-by: Philippe Mathieu-Daudé --- docs/about/removed-features.rst | 5 +++++ tests/qtest/machine-none-test.c | 2 +- target/mips/cpu-defs.c.inc | 40 --------------------------------- 3 files changed, 6 insertions(+), 41 deletions(-) diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst index 54081a6c19..d61b4c92dd 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -727,6 +727,11 @@ x86 ``Icelake-Client`` CPU (removed in 7.1) There isn't ever Icelake Client CPU, it is some wrong and imaginary one. Use ``Icelake-Server`` instead. +MIPS I6500 CPU (removed in 9.0) +''''''''''''''''''''''''''''''' + +The I6500 support was never fully contributed. + System accelerators ------------------- diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-test.c index 31cc0bfb01..b653a0dd5c 100644 --- a/tests/qtest/machine-none-test.c +++ b/tests/qtest/machine-none-test.c @@ -37,7 +37,7 @@ static struct arch2cpu cpus_map[] = { { "mips", "4Kc" }, { "mipsel", "I7200" }, { "mips64", "20Kc" }, - { "mips64el", "I6500" }, + { "mips64el", "I6400" }, { "nios2", "FIXME" }, { "or1k", "or1200" }, { "ppc", "604" }, diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index fbf787d8ce..ce2c01cbfa 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -778,46 +778,6 @@ const mips_def_t mips_defs[] = .insn_flags = CPU_MIPS64R6, .mmu_type = MMU_TYPE_R4000, }, - { - .name = "I6500", - .CP0_PRid = 0x1B000, - .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | - (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) | - (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) | - (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | - (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | - (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | - (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), - .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | - (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), - .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) | - (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI), - .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | - (1 << CP0C5_FRE) | (1 << CP0C5_UFE), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 0, - .SYNCI_Step = 64, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x30D8FFFF, - .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | - (1U << CP0PG_RIE), - .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), - .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), - .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | - (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | - (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV), - .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), - .CP1_fcr31_rw_bitmask = 0x0103FFFF, - .MSAIR = 0x03 << MSAIR_ProcID, - .SEGBITS = 48, - .PABITS = 48, - .insn_flags = CPU_MIPS64R6, - .mmu_type = MMU_TYPE_R4000, - }, { .name = "Loongson-2E", .CP0_PRid = 0x6302,