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Wysocki" , Len Brown , Paul Walmsley , Palmer Dabbelt , Albert Ou , Viresh Kumar , Conor Dooley , Andrew Jones , Atish Kumar Patra , Anup Patel , Sunil V L Subject: [PATCH v1 -next 1/3] ACPI: RISC-V: Add CPPC driver Date: Thu, 8 Feb 2024 09:14:12 +0530 Message-Id: <20240208034414.22579-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208034414.22579-1-sunilvl@ventanamicro.com> References: <20240208034414.22579-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add cpufreq driver based on ACPI CPPC for RISC-V. The driver uses either SBI CPPC interfaces or the CSRs to access the CPPC registers as defined by the RISC-V FFH spec. Signed-off-by: Sunil V L --- drivers/acpi/riscv/Makefile | 1 + drivers/acpi/riscv/cppc.c | 157 ++++++++++++++++++++++++++++++++++++ 2 files changed, 158 insertions(+) create mode 100644 drivers/acpi/riscv/cppc.c diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile index 7309d92dd477..86b0925f612d 100644 --- a/drivers/acpi/riscv/Makefile +++ b/drivers/acpi/riscv/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y += rhct.o obj-$(CONFIG_ACPI_PROCESSOR_IDLE) += cpuidle.o +obj-$(CONFIG_ACPI_CPPC_LIB) += cppc.o diff --git a/drivers/acpi/riscv/cppc.c b/drivers/acpi/riscv/cppc.c new file mode 100644 index 000000000000..4cdff387deff --- /dev/null +++ b/drivers/acpi/riscv/cppc.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Implement CPPC FFH helper routines for RISC-V. + * + * Copyright (C) 2024 Ventana Micro Systems Inc. + */ + +#include +#include +#include + +#define SBI_EXT_CPPC 0x43505043 + +/* CPPC interfaces defined in SBI spec */ +#define SBI_CPPC_PROBE 0x0 +#define SBI_CPPC_READ 0x1 +#define SBI_CPPC_READ_HI 0x2 +#define SBI_CPPC_WRITE 0x3 + +/* RISC-V FFH definitions from RISC-V FFH spec */ +#define FFH_CPPC_TYPE(r) (((r) & GENMASK_ULL(63, 60)) >> 60) +#define FFH_CPPC_SBI_REG(r) ((r) & GENMASK(31, 0)) +#define FFH_CPPC_CSR_NUM(r) ((r) & GENMASK(11, 0)) + +#define FFH_CPPC_SBI 0x1 +#define FFH_CPPC_CSR 0x2 + +struct sbi_cppc_data { + u64 val; + u32 reg; + struct sbiret ret; +}; + +static bool cppc_ext_present; + +static int __init sbi_cppc_init(void) +{ + if (sbi_spec_version >= sbi_mk_version(2, 0) && + sbi_probe_extension(SBI_EXT_CPPC) > 0) { + pr_info("SBI CPPC extension detected\n"); + cppc_ext_present = true; + } else { + pr_info("SBI CPPC extension NOT detected!!\n"); + cppc_ext_present = false; + } + + return 0; +} +device_initcall(sbi_cppc_init); + +static void sbi_cppc_read(void *read_data) +{ + struct sbi_cppc_data *data = (struct sbi_cppc_data *)read_data; + + data->ret = sbi_ecall(SBI_EXT_CPPC, SBI_CPPC_READ, + data->reg, 0, 0, 0, 0, 0); +} + +static void sbi_cppc_write(void *write_data) +{ + struct sbi_cppc_data *data = (struct sbi_cppc_data *)write_data; + + data->ret = sbi_ecall(SBI_EXT_CPPC, SBI_CPPC_WRITE, + data->reg, data->val, 0, 0, 0, 0); +} + +static void cppc_ffh_csr_read(void *read_data) +{ + struct sbi_cppc_data *data = (struct sbi_cppc_data *)read_data; + + switch (data->reg) { + /* Support only TIME CSR for now */ + case CSR_TIME: + data->ret.value = csr_read(CSR_TIME); + data->ret.error = 0; + break; + default: + data->ret.error = -EINVAL; + break; + } +} + +static void cppc_ffh_csr_write(void *write_data) +{ + struct sbi_cppc_data *data = (struct sbi_cppc_data *)write_data; + + data->ret.error = -EINVAL; +} + +/* + * Refer to drivers/acpi/cppc_acpi.c for the description of the functions + * below. + */ +bool cpc_ffh_supported(void) +{ + return true; +} + +int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val) +{ + struct sbi_cppc_data data; + + if (WARN_ON_ONCE(irqs_disabled())) + return -EPERM; + + if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_SBI) { + if (!cppc_ext_present) + return -EINVAL; + + data.reg = FFH_CPPC_SBI_REG(reg->address); + + smp_call_function_single(cpu, sbi_cppc_read, &data, 1); + + *val = data.ret.value; + + return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0; + } else if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_CSR) { + data.reg = FFH_CPPC_CSR_NUM(reg->address); + + smp_call_function_single(cpu, cppc_ffh_csr_read, &data, 1); + + *val = data.ret.value; + + return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0; + } + + return -EINVAL; +} + +int cpc_write_ffh(int cpu, struct cpc_reg *reg, u64 val) +{ + struct sbi_cppc_data data; + + if (WARN_ON_ONCE(irqs_disabled())) + return -EPERM; + + if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_SBI) { + if (!cppc_ext_present) + return -EINVAL; + + data.reg = FFH_CPPC_SBI_REG(reg->address); + data.val = val; + + smp_call_function_single(cpu, sbi_cppc_write, &data, 1); + + return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0; + } else if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_CSR) { + data.reg = FFH_CPPC_CSR_NUM(reg->address); + data.val = val; + + smp_call_function_single(cpu, cppc_ffh_csr_write, &data, 1); + + return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0; + } + + return -EINVAL; +} From patchwork Thu Feb 8 03:44:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 770923 Received: from mail-oa1-f49.google.com (mail-oa1-f49.google.com [209.85.160.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E4072E3F1 for ; Thu, 8 Feb 2024 03:44:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707363879; cv=none; b=LEdqf7xI7N4FzTqUhr/3Cr9W/gxGzPUaDNrb+14gmKQW5uRYer0L4/cYXflE6vgnQJsDz0xAG6yUfFR9csvAdyeT45ArolfOumUJ97FZ36lYXNN2HoAYR3v62Vt8wwTGGab3szIyT05ap29JqCh9efYV+iGLjDa/+CD+VYvrbO4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707363879; c=relaxed/simple; bh=g0fx2hA5H7XGXKhInZLiSKn01bgcxRTeVThP7ASvphc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=KBHqwlHo3hXKz15seOolWcQ30w/wEUHHFWL8F1mwz/VrOWvpBoWrD2Ko7Agy+alLuSRaRnl1iYsj/bkTkAoh096L2jU5PoEph3HdS3BrVhh/Iu49dOyFvyV6zU8+Vsp9mpXeZ9WaB+n+M0lHwEXYrqzU8NCdWphgdGZfCbG5/ng= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=D6lzucUR; arc=none smtp.client-ip=209.85.160.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="D6lzucUR" Received: by mail-oa1-f49.google.com with SMTP id 586e51a60fabf-219122781a3so803904fac.0 for ; Wed, 07 Feb 2024 19:44:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1707363877; x=1707968677; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yizVqarSWst4aU/Dh5XxoRIOdJJxEsR3ATXXBPWi+lw=; b=D6lzucURy+G58YW49NY9DjKm15fcUNvgkHS6CPHWXsc+eF+Yyx0R8Vr3RN4qmjPvSS RBCrJtbOaedOoKtym1BDD4nzsw5qKUyhMthXTWF6WjgsW0tw9qsXUBE3J09tBzy+XqKN 1UPJPRnP+g+zKEzFS2t2us43tsWBcyCArIt9HlW7Nuf4R3fWmVGqQR8/4lDKeKfh5Vpm m8l8+q+A0f+MzcInNiWUW+ck7KEgSnnCxftqQWYGt6CHS1a25xnAnsH9yOfNs8AJ5co6 hXZKLu8vghzVMbG1gV7dXJKPPnm2bRch4w1MsyKnPFRgqzneWHJdf3/MSVgqwU0eALjj yZhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707363877; x=1707968677; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yizVqarSWst4aU/Dh5XxoRIOdJJxEsR3ATXXBPWi+lw=; b=ZtN4DB+8OMpx9NxPSOecqu6HXVWwjZHL0hoCdBU5A0A4sRwk3blc8IXvagVvegoHE+ IMtneRB182Sb40tb5kdqMd30GPVlITLQEntrLcfV3l8wzRrOOUsk2dilDXOEDHqGtkLR N9hnqbcMpkBG0c3iEOdpjo44WP28AmKIaPUl8DaWg//d5h5I9EMUEYorYFQrlqzWMJUS 8DyQwcn292e3x+jZkE0QLu4Z0+B6sNeD/Bf4guFwdBOSd+PSR/cXpej5eoi8j+iGXGmF /nMawlwTAPLoZtFgu3zs1JPGeZU0ue2HMAwN/onReBbJDMPKxrUKdTK3M+BlFgNrYZqt 7BIA== X-Forwarded-Encrypted: i=1; AJvYcCX8+vtPs2B0lq4dTqJb1FOSru8dlW/+wT3F/tDoerefHKHph+tsbKO6BKsFvO1r3PoOQDAEWS46Ln0gDjfa8ra3hPWgm9bReZkoIg== X-Gm-Message-State: AOJu0YwSKGQhjKdwAM7kGC9s7Q9xhqteySovVhkJnbHxMIzQ9oyrCfTp RrbZdugp361v14eQZuxlrZeIKpFxYviDnidNvlX27DSsap7z6SG0L8G+LbwwxXr3zb0iOJtMRgA Ia/g= X-Google-Smtp-Source: AGHT+IFOtpxyVrCmmf5j/9YheBJxdbKCH0Y2umngPfrW1aFy9KUJdJOkdmzNUcIURse5wbX8fsh1xQ== X-Received: by 2002:a05:6870:1681:b0:214:269d:785a with SMTP id j1-20020a056870168100b00214269d785amr8743371oae.53.1707363877181; Wed, 07 Feb 2024 19:44:37 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCWn8ZEOAjgnL+Jx4yBkYXCD5ALrkdT7ucfJBWU9DaGB2ywmBZjUnJW6ow7WqR3G5rX3vuzL+eJ3RulTStUSDcL6jTeGuOk3FAVNlVnC0cHJTRByIsx6ubfO/gOQZMro5pxY51D8WO++N/TlH4xtf6GZXlM9Gf918L6ENzgiQLyRny4viixyAPlBjxsHJhUAv0Piws3gr0ZQW9i59dTiUNVeyppZzrAk8QVeI7WGKSJifX9yCAMtJHGbo2VLVAojonpd6MgisF8Z5E9IzHJzW+dhkdwmd6QYg2A//29RZOG1h2iccMu5ipJIdI53iunhTFmAoqliiCsh1GE/HZw/by+qJK5lNPuWPMAa9JRdOt13fgFESIsvB0mUnrVa5rAciBlKP7ZYVbJlNXcTyUUa13pQUuEXUArgsWwcCT2jalgwb9YH2imqeDU0D76YTcY2hNgj0KYf Received: from sunil-laptop.dc1.ventanamicro.com ([106.51.83.242]) by smtp.gmail.com with ESMTPSA id g10-20020a056830160a00b006ddbfc37c87sm443595otr.49.2024.02.07.19.44.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Feb 2024 19:44:36 -0800 (PST) From: Sunil V L To: linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: "Rafael J . Wysocki" , Len Brown , Paul Walmsley , Palmer Dabbelt , Albert Ou , Viresh Kumar , Conor Dooley , Andrew Jones , Atish Kumar Patra , Anup Patel , Sunil V L Subject: [PATCH v1 -next 2/3] cpufreq: Move CPPC configs to common Kconfig and add RISC-V Date: Thu, 8 Feb 2024 09:14:13 +0530 Message-Id: <20240208034414.22579-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208034414.22579-1-sunilvl@ventanamicro.com> References: <20240208034414.22579-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 CPPC related config options are currently defined only in ARM specific file. However, they are required for RISC-V as well. Instead of creating a new Kconfig.riscv file and duplicating them, move them to the common Kconfig file and enable RISC-V too. Signed-off-by: Sunil V L --- drivers/cpufreq/Kconfig | 29 +++++++++++++++++++++++++++++ drivers/cpufreq/Kconfig.arm | 26 -------------------------- 2 files changed, 29 insertions(+), 26 deletions(-) diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig index 35efb53d5492..94e55c40970a 100644 --- a/drivers/cpufreq/Kconfig +++ b/drivers/cpufreq/Kconfig @@ -302,4 +302,33 @@ config QORIQ_CPUFREQ which are capable of changing the CPU's frequency dynamically. endif + +config ACPI_CPPC_CPUFREQ + tristate "CPUFreq driver based on the ACPI CPPC spec" + depends on ACPI_PROCESSOR + depends on ARM || ARM64 || RISCV + select ACPI_CPPC_LIB + help + This adds a CPUFreq driver which uses CPPC methods + as described in the ACPIv5.1 spec. CPPC stands for + Collaborative Processor Performance Controls. It + is based on an abstract continuous scale of CPU + performance values which allows the remote power + processor to flexibly optimize for power and + performance. CPPC relies on power management firmware + support for its operation. + + If in doubt, say N. + +config ACPI_CPPC_CPUFREQ_FIE + bool "Frequency Invariance support for CPPC cpufreq driver" + depends on ACPI_CPPC_CPUFREQ && GENERIC_ARCH_TOPOLOGY + depends on ARM || ARM64 || RISCV + default y + help + This extends frequency invariance support in the CPPC cpufreq driver, + by using CPPC delivered and reference performance counters. + + If in doubt, say N. + endmenu diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index f911606897b8..987b3d900a89 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -3,32 +3,6 @@ # ARM CPU Frequency scaling drivers # -config ACPI_CPPC_CPUFREQ - tristate "CPUFreq driver based on the ACPI CPPC spec" - depends on ACPI_PROCESSOR - select ACPI_CPPC_LIB - help - This adds a CPUFreq driver which uses CPPC methods - as described in the ACPIv5.1 spec. CPPC stands for - Collaborative Processor Performance Controls. It - is based on an abstract continuous scale of CPU - performance values which allows the remote power - processor to flexibly optimize for power and - performance. CPPC relies on power management firmware - support for its operation. - - If in doubt, say N. - -config ACPI_CPPC_CPUFREQ_FIE - bool "Frequency Invariance support for CPPC cpufreq driver" - depends on ACPI_CPPC_CPUFREQ && GENERIC_ARCH_TOPOLOGY - default y - help - This extends frequency invariance support in the CPPC cpufreq driver, - by using CPPC delivered and reference performance counters. - - If in doubt, say N. - config ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM tristate "Allwinner nvmem based SUN50I CPUFreq driver" depends on ARCH_SUNXI From patchwork Thu Feb 8 03:44:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 771580 Received: from mail-oa1-f46.google.com (mail-oa1-f46.google.com [209.85.160.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43A422E83F for ; Thu, 8 Feb 2024 03:44:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wysocki" , Len Brown , Paul Walmsley , Palmer Dabbelt , Albert Ou , Viresh Kumar , Conor Dooley , Andrew Jones , Atish Kumar Patra , Anup Patel , Sunil V L Subject: [PATCH v1 -next 3/3] RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ Date: Thu, 8 Feb 2024 09:14:14 +0530 Message-Id: <20240208034414.22579-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208034414.22579-1-sunilvl@ventanamicro.com> References: <20240208034414.22579-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 CONFIG_ACPI_CPPC_CPUFREQ is required to enable CPPC for RISC-V. Signed-off-by: Sunil V L --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index eaf34e871e30..2988ecd3eb4d 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -44,6 +44,7 @@ CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m CONFIG_CPUFREQ_DT=y +CONFIG_ACPI_CPPC_CPUFREQ=m CONFIG_VIRTUALIZATION=y CONFIG_KVM=m CONFIG_ACPI=y